system.h 8.7 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357
  1. /*
  2. * This file is subject to the terms and conditions of the GNU General Public
  3. * License. See the file "COPYING" in the main directory of this archive
  4. * for more details.
  5. *
  6. * Copyright (C) 1994, 95, 96, 97, 98, 99, 2003, 06 by Ralf Baechle
  7. * Copyright (C) 1996 by Paul M. Antoine
  8. * Copyright (C) 1999 Silicon Graphics
  9. * Kevin D. Kissell, kevink@mips.org and Carsten Langgaard, carstenl@mips.com
  10. * Copyright (C) 2000 MIPS Technologies, Inc.
  11. */
  12. #ifndef _ASM_SYSTEM_H
  13. #define _ASM_SYSTEM_H
  14. #include <linux/types.h>
  15. #include <linux/irqflags.h>
  16. #include <asm/addrspace.h>
  17. #include <asm/barrier.h>
  18. #include <asm/cpu-features.h>
  19. #include <asm/dsp.h>
  20. #include <asm/ptrace.h>
  21. #include <asm/war.h>
  22. /*
  23. * switch_to(n) should switch tasks to task nr n, first
  24. * checking that n isn't the current task, in which case it does nothing.
  25. */
  26. extern asmlinkage void *resume(void *last, void *next, void *next_ti);
  27. struct task_struct;
  28. #ifdef CONFIG_MIPS_MT_FPAFF
  29. /*
  30. * Handle the scheduler resume end of FPU affinity management. We do this
  31. * inline to try to keep the overhead down. If we have been forced to run on
  32. * a "CPU" with an FPU because of a previous high level of FP computation,
  33. * but did not actually use the FPU during the most recent time-slice (CU1
  34. * isn't set), we undo the restriction on cpus_allowed.
  35. *
  36. * We're not calling set_cpus_allowed() here, because we have no need to
  37. * force prompt migration - we're already switching the current CPU to a
  38. * different thread.
  39. */
  40. #define switch_to(prev,next,last) \
  41. do { \
  42. if (cpu_has_fpu && \
  43. (prev->thread.mflags & MF_FPUBOUND) && \
  44. (!(KSTK_STATUS(prev) & ST0_CU1))) { \
  45. prev->thread.mflags &= ~MF_FPUBOUND; \
  46. prev->cpus_allowed = prev->thread.user_cpus_allowed; \
  47. } \
  48. if (cpu_has_dsp) \
  49. __save_dsp(prev); \
  50. next->thread.emulated_fp = 0; \
  51. (last) = resume(prev, next, next->thread_info); \
  52. if (cpu_has_dsp) \
  53. __restore_dsp(current); \
  54. } while(0)
  55. #else
  56. #define switch_to(prev,next,last) \
  57. do { \
  58. if (cpu_has_dsp) \
  59. __save_dsp(prev); \
  60. (last) = resume(prev, next, task_thread_info(next)); \
  61. if (cpu_has_dsp) \
  62. __restore_dsp(current); \
  63. } while(0)
  64. #endif
  65. /*
  66. * On SMP systems, when the scheduler does migration-cost autodetection,
  67. * it needs a way to flush as much of the CPU's caches as possible.
  68. *
  69. * TODO: fill this in!
  70. */
  71. static inline void sched_cacheflush(void)
  72. {
  73. }
  74. static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
  75. {
  76. __u32 retval;
  77. if (cpu_has_llsc && R10000_LLSC_WAR) {
  78. unsigned long dummy;
  79. __asm__ __volatile__(
  80. " .set mips3 \n"
  81. "1: ll %0, %3 # xchg_u32 \n"
  82. " .set mips0 \n"
  83. " move %2, %z4 \n"
  84. " .set mips3 \n"
  85. " sc %2, %1 \n"
  86. " beqzl %2, 1b \n"
  87. " .set mips0 \n"
  88. : "=&r" (retval), "=m" (*m), "=&r" (dummy)
  89. : "R" (*m), "Jr" (val)
  90. : "memory");
  91. } else if (cpu_has_llsc) {
  92. unsigned long dummy;
  93. __asm__ __volatile__(
  94. " .set mips3 \n"
  95. "1: ll %0, %3 # xchg_u32 \n"
  96. " .set mips0 \n"
  97. " move %2, %z4 \n"
  98. " .set mips3 \n"
  99. " sc %2, %1 \n"
  100. " beqz %2, 1b \n"
  101. " .set mips0 \n"
  102. : "=&r" (retval), "=m" (*m), "=&r" (dummy)
  103. : "R" (*m), "Jr" (val)
  104. : "memory");
  105. } else {
  106. unsigned long flags;
  107. local_irq_save(flags);
  108. retval = *m;
  109. *m = val;
  110. local_irq_restore(flags); /* implies memory barrier */
  111. }
  112. smp_mb();
  113. return retval;
  114. }
  115. #ifdef CONFIG_64BIT
  116. static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val)
  117. {
  118. __u64 retval;
  119. if (cpu_has_llsc && R10000_LLSC_WAR) {
  120. unsigned long dummy;
  121. __asm__ __volatile__(
  122. " .set mips3 \n"
  123. "1: lld %0, %3 # xchg_u64 \n"
  124. " move %2, %z4 \n"
  125. " scd %2, %1 \n"
  126. " beqzl %2, 1b \n"
  127. " .set mips0 \n"
  128. : "=&r" (retval), "=m" (*m), "=&r" (dummy)
  129. : "R" (*m), "Jr" (val)
  130. : "memory");
  131. } else if (cpu_has_llsc) {
  132. unsigned long dummy;
  133. __asm__ __volatile__(
  134. " .set mips3 \n"
  135. "1: lld %0, %3 # xchg_u64 \n"
  136. " move %2, %z4 \n"
  137. " scd %2, %1 \n"
  138. " beqz %2, 1b \n"
  139. " .set mips0 \n"
  140. : "=&r" (retval), "=m" (*m), "=&r" (dummy)
  141. : "R" (*m), "Jr" (val)
  142. : "memory");
  143. } else {
  144. unsigned long flags;
  145. local_irq_save(flags);
  146. retval = *m;
  147. *m = val;
  148. local_irq_restore(flags); /* implies memory barrier */
  149. }
  150. smp_mb();
  151. return retval;
  152. }
  153. #else
  154. extern __u64 __xchg_u64_unsupported_on_32bit_kernels(volatile __u64 * m, __u64 val);
  155. #define __xchg_u64 __xchg_u64_unsupported_on_32bit_kernels
  156. #endif
  157. /* This function doesn't exist, so you'll get a linker error
  158. if something tries to do an invalid xchg(). */
  159. extern void __xchg_called_with_bad_pointer(void);
  160. static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
  161. {
  162. switch (size) {
  163. case 4:
  164. return __xchg_u32(ptr, x);
  165. case 8:
  166. return __xchg_u64(ptr, x);
  167. }
  168. __xchg_called_with_bad_pointer();
  169. return x;
  170. }
  171. #define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
  172. #define tas(ptr) (xchg((ptr),1))
  173. #define __HAVE_ARCH_CMPXCHG 1
  174. static inline unsigned long __cmpxchg_u32(volatile int * m, unsigned long old,
  175. unsigned long new)
  176. {
  177. __u32 retval;
  178. if (cpu_has_llsc && R10000_LLSC_WAR) {
  179. __asm__ __volatile__(
  180. " .set push \n"
  181. " .set noat \n"
  182. " .set mips3 \n"
  183. "1: ll %0, %2 # __cmpxchg_u32 \n"
  184. " bne %0, %z3, 2f \n"
  185. " .set mips0 \n"
  186. " move $1, %z4 \n"
  187. " .set mips3 \n"
  188. " sc $1, %1 \n"
  189. " beqzl $1, 1b \n"
  190. "2: \n"
  191. " .set pop \n"
  192. : "=&r" (retval), "=R" (*m)
  193. : "R" (*m), "Jr" (old), "Jr" (new)
  194. : "memory");
  195. } else if (cpu_has_llsc) {
  196. __asm__ __volatile__(
  197. " .set push \n"
  198. " .set noat \n"
  199. " .set mips3 \n"
  200. "1: ll %0, %2 # __cmpxchg_u32 \n"
  201. " bne %0, %z3, 2f \n"
  202. " .set mips0 \n"
  203. " move $1, %z4 \n"
  204. " .set mips3 \n"
  205. " sc $1, %1 \n"
  206. " beqz $1, 1b \n"
  207. "2: \n"
  208. " .set pop \n"
  209. : "=&r" (retval), "=R" (*m)
  210. : "R" (*m), "Jr" (old), "Jr" (new)
  211. : "memory");
  212. } else {
  213. unsigned long flags;
  214. local_irq_save(flags);
  215. retval = *m;
  216. if (retval == old)
  217. *m = new;
  218. local_irq_restore(flags); /* implies memory barrier */
  219. }
  220. smp_mb();
  221. return retval;
  222. }
  223. #ifdef CONFIG_64BIT
  224. static inline unsigned long __cmpxchg_u64(volatile int * m, unsigned long old,
  225. unsigned long new)
  226. {
  227. __u64 retval;
  228. if (cpu_has_llsc && R10000_LLSC_WAR) {
  229. __asm__ __volatile__(
  230. " .set push \n"
  231. " .set noat \n"
  232. " .set mips3 \n"
  233. "1: lld %0, %2 # __cmpxchg_u64 \n"
  234. " bne %0, %z3, 2f \n"
  235. " move $1, %z4 \n"
  236. " scd $1, %1 \n"
  237. " beqzl $1, 1b \n"
  238. "2: \n"
  239. " .set pop \n"
  240. : "=&r" (retval), "=R" (*m)
  241. : "R" (*m), "Jr" (old), "Jr" (new)
  242. : "memory");
  243. } else if (cpu_has_llsc) {
  244. __asm__ __volatile__(
  245. " .set push \n"
  246. " .set noat \n"
  247. " .set mips3 \n"
  248. "1: lld %0, %2 # __cmpxchg_u64 \n"
  249. " bne %0, %z3, 2f \n"
  250. " move $1, %z4 \n"
  251. " scd $1, %1 \n"
  252. " beqz $1, 1b \n"
  253. "2: \n"
  254. " .set pop \n"
  255. : "=&r" (retval), "=R" (*m)
  256. : "R" (*m), "Jr" (old), "Jr" (new)
  257. : "memory");
  258. } else {
  259. unsigned long flags;
  260. local_irq_save(flags);
  261. retval = *m;
  262. if (retval == old)
  263. *m = new;
  264. local_irq_restore(flags); /* implies memory barrier */
  265. }
  266. smp_mb();
  267. return retval;
  268. }
  269. #else
  270. extern unsigned long __cmpxchg_u64_unsupported_on_32bit_kernels(
  271. volatile int * m, unsigned long old, unsigned long new);
  272. #define __cmpxchg_u64 __cmpxchg_u64_unsupported_on_32bit_kernels
  273. #endif
  274. /* This function doesn't exist, so you'll get a linker error
  275. if something tries to do an invalid cmpxchg(). */
  276. extern void __cmpxchg_called_with_bad_pointer(void);
  277. static inline unsigned long __cmpxchg(volatile void * ptr, unsigned long old,
  278. unsigned long new, int size)
  279. {
  280. switch (size) {
  281. case 4:
  282. return __cmpxchg_u32(ptr, old, new);
  283. case 8:
  284. return __cmpxchg_u64(ptr, old, new);
  285. }
  286. __cmpxchg_called_with_bad_pointer();
  287. return old;
  288. }
  289. #define cmpxchg(ptr,old,new) ((__typeof__(*(ptr)))__cmpxchg((ptr), (unsigned long)(old), (unsigned long)(new),sizeof(*(ptr))))
  290. extern void set_handler (unsigned long offset, void *addr, unsigned long len);
  291. extern void set_uncached_handler (unsigned long offset, void *addr, unsigned long len);
  292. extern void *set_vi_handler (int n, void *addr);
  293. extern void *set_except_vector(int n, void *addr);
  294. extern unsigned long ebase;
  295. extern void per_cpu_trap_init(void);
  296. extern NORET_TYPE void die(const char *, struct pt_regs *);
  297. static inline void die_if_kernel(const char *str, struct pt_regs *regs)
  298. {
  299. if (unlikely(!user_mode(regs)))
  300. die(str, regs);
  301. }
  302. extern int stop_a_enabled;
  303. /*
  304. * See include/asm-ia64/system.h; prevents deadlock on SMP
  305. * systems.
  306. */
  307. #define __ARCH_WANT_UNLOCKED_CTXSW
  308. #define arch_align_stack(x) (x)
  309. #endif /* _ASM_SYSTEM_H */