mx2x.h 9.8 KB

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  1. /*
  2. * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
  3. * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
  4. *
  5. * This contains hardware definitions that are common between i.MX21 and
  6. * i.MX27.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License
  10. * as published by the Free Software Foundation; either version 2
  11. * of the License, or (at your option) any later version.
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  20. * MA 02110-1301, USA.
  21. */
  22. #ifndef __MACH_MX2x_H__
  23. #define __MACH_MX2x_H__
  24. /* The following addresses are common between i.MX21 and i.MX27 */
  25. /* Register offsets */
  26. #define MX2x_AIPI_BASE_ADDR 0x10000000
  27. #define MX2x_AIPI_SIZE SZ_1M
  28. #define MX2x_DMA_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x01000)
  29. #define MX2x_WDOG_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x02000)
  30. #define MX2x_GPT1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x03000)
  31. #define MX2x_GPT2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x04000)
  32. #define MX2x_GPT3_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x05000)
  33. #define MX2x_PWM_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x06000)
  34. #define MX2x_RTC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x07000)
  35. #define MX2x_KPP_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x08000)
  36. #define MX2x_OWIRE_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x09000)
  37. #define MX2x_UART1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0a000)
  38. #define MX2x_UART2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0b000)
  39. #define MX2x_UART3_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0c000)
  40. #define MX2x_UART4_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0d000)
  41. #define MX2x_CSPI1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0e000)
  42. #define MX2x_CSPI2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0f000)
  43. #define MX2x_SSI1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x10000)
  44. #define MX2x_SSI2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x11000)
  45. #define MX2x_I2C_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x12000)
  46. #define MX2x_SDHC1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x13000)
  47. #define MX2x_SDHC2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x14000)
  48. #define MX2x_GPIO_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x15000)
  49. #define MX2x_AUDMUX_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x16000)
  50. #define MX2x_CSPI3_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x17000)
  51. #define MX2x_LCDC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x21000)
  52. #define MX2x_SLCDC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x22000)
  53. #define MX2x_USBOTG_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x24000)
  54. #define MX2x_EMMA_PP_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x26000)
  55. #define MX2x_EMMA_PRP_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x26400)
  56. #define MX2x_CCM_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x27000)
  57. #define MX2x_SYSCTRL_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x27800)
  58. #define MX2x_JAM_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x3e000)
  59. #define MX2x_MAX_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x3f000)
  60. #define MX2x_AVIC_BASE_ADDR 0x10040000
  61. #define MX2x_SAHB1_BASE_ADDR 0x80000000
  62. #define MX2x_SAHB1_SIZE SZ_1M
  63. #define MX2x_CSI_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x0000)
  64. /* fixed interrupt numbers */
  65. #define MX2x_INT_CSPI3 6
  66. #define MX2x_INT_GPIO 8
  67. #define MX2x_INT_SDHC2 10
  68. #define MX2x_INT_SDHC1 11
  69. #define MX2x_INT_I2C 12
  70. #define MX2x_INT_SSI2 13
  71. #define MX2x_INT_SSI1 14
  72. #define MX2x_INT_CSPI2 15
  73. #define MX2x_INT_CSPI1 16
  74. #define MX2x_INT_UART4 17
  75. #define MX2x_INT_UART3 18
  76. #define MX2x_INT_UART2 19
  77. #define MX2x_INT_UART1 20
  78. #define MX2x_INT_KPP 21
  79. #define MX2x_INT_RTC 22
  80. #define MX2x_INT_PWM 23
  81. #define MX2x_INT_GPT3 24
  82. #define MX2x_INT_GPT2 25
  83. #define MX2x_INT_GPT1 26
  84. #define MX2x_INT_WDOG 27
  85. #define MX2x_INT_PCMCIA 28
  86. #define MX2x_INT_NANDFC 29
  87. #define MX2x_INT_CSI 31
  88. #define MX2x_INT_DMACH0 32
  89. #define MX2x_INT_DMACH1 33
  90. #define MX2x_INT_DMACH2 34
  91. #define MX2x_INT_DMACH3 35
  92. #define MX2x_INT_DMACH4 36
  93. #define MX2x_INT_DMACH5 37
  94. #define MX2x_INT_DMACH6 38
  95. #define MX2x_INT_DMACH7 39
  96. #define MX2x_INT_DMACH8 40
  97. #define MX2x_INT_DMACH9 41
  98. #define MX2x_INT_DMACH10 42
  99. #define MX2x_INT_DMACH11 43
  100. #define MX2x_INT_DMACH12 44
  101. #define MX2x_INT_DMACH13 45
  102. #define MX2x_INT_DMACH14 46
  103. #define MX2x_INT_DMACH15 47
  104. #define MX2x_INT_EMMAPRP 51
  105. #define MX2x_INT_EMMAPP 52
  106. #define MX2x_INT_SLCDC 60
  107. #define MX2x_INT_LCDC 61
  108. /* fixed DMA request numbers */
  109. #define MX2x_DMA_REQ_CSPI3_RX 1
  110. #define MX2x_DMA_REQ_CSPI3_TX 2
  111. #define MX2x_DMA_REQ_EXT 3
  112. #define MX2x_DMA_REQ_SDHC2 6
  113. #define MX2x_DMA_REQ_SDHC1 7
  114. #define MX2x_DMA_REQ_SSI2_RX0 8
  115. #define MX2x_DMA_REQ_SSI2_TX0 9
  116. #define MX2x_DMA_REQ_SSI2_RX1 10
  117. #define MX2x_DMA_REQ_SSI2_TX1 11
  118. #define MX2x_DMA_REQ_SSI1_RX0 12
  119. #define MX2x_DMA_REQ_SSI1_TX0 13
  120. #define MX2x_DMA_REQ_SSI1_RX1 14
  121. #define MX2x_DMA_REQ_SSI1_TX1 15
  122. #define MX2x_DMA_REQ_CSPI2_RX 16
  123. #define MX2x_DMA_REQ_CSPI2_TX 17
  124. #define MX2x_DMA_REQ_CSPI1_RX 18
  125. #define MX2x_DMA_REQ_CSPI1_TX 19
  126. #define MX2x_DMA_REQ_UART4_RX 20
  127. #define MX2x_DMA_REQ_UART4_TX 21
  128. #define MX2x_DMA_REQ_UART3_RX 22
  129. #define MX2x_DMA_REQ_UART3_TX 23
  130. #define MX2x_DMA_REQ_UART2_RX 24
  131. #define MX2x_DMA_REQ_UART2_TX 25
  132. #define MX2x_DMA_REQ_UART1_RX 26
  133. #define MX2x_DMA_REQ_UART1_TX 27
  134. #define MX2x_DMA_REQ_CSI_STAT 30
  135. #define MX2x_DMA_REQ_CSI_RX 31
  136. #ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
  137. /* these should go away */
  138. #define AIPI_BASE_ADDR MX2x_AIPI_BASE_ADDR
  139. #define AIPI_SIZE MX2x_AIPI_SIZE
  140. #define DMA_BASE_ADDR MX2x_DMA_BASE_ADDR
  141. #define WDOG_BASE_ADDR MX2x_WDOG_BASE_ADDR
  142. #define GPT1_BASE_ADDR MX2x_GPT1_BASE_ADDR
  143. #define GPT2_BASE_ADDR MX2x_GPT2_BASE_ADDR
  144. #define GPT3_BASE_ADDR MX2x_GPT3_BASE_ADDR
  145. #define PWM_BASE_ADDR MX2x_PWM_BASE_ADDR
  146. #define RTC_BASE_ADDR MX2x_RTC_BASE_ADDR
  147. #define KPP_BASE_ADDR MX2x_KPP_BASE_ADDR
  148. #define OWIRE_BASE_ADDR MX2x_OWIRE_BASE_ADDR
  149. #define UART1_BASE_ADDR MX2x_UART1_BASE_ADDR
  150. #define UART2_BASE_ADDR MX2x_UART2_BASE_ADDR
  151. #define UART3_BASE_ADDR MX2x_UART3_BASE_ADDR
  152. #define UART4_BASE_ADDR MX2x_UART4_BASE_ADDR
  153. #define CSPI1_BASE_ADDR MX2x_CSPI1_BASE_ADDR
  154. #define CSPI2_BASE_ADDR MX2x_CSPI2_BASE_ADDR
  155. #define SSI1_BASE_ADDR MX2x_SSI1_BASE_ADDR
  156. #define SSI2_BASE_ADDR MX2x_SSI2_BASE_ADDR
  157. #define I2C_BASE_ADDR MX2x_I2C_BASE_ADDR
  158. #define SDHC1_BASE_ADDR MX2x_SDHC1_BASE_ADDR
  159. #define SDHC2_BASE_ADDR MX2x_SDHC2_BASE_ADDR
  160. #define GPIO_BASE_ADDR MX2x_GPIO_BASE_ADDR
  161. #define AUDMUX_BASE_ADDR MX2x_AUDMUX_BASE_ADDR
  162. #define CSPI3_BASE_ADDR MX2x_CSPI3_BASE_ADDR
  163. #define LCDC_BASE_ADDR MX2x_LCDC_BASE_ADDR
  164. #define SLCDC_BASE_ADDR MX2x_SLCDC_BASE_ADDR
  165. #define USBOTG_BASE_ADDR MX2x_USBOTG_BASE_ADDR
  166. #define EMMA_PP_BASE_ADDR MX2x_EMMA_PP_BASE_ADDR
  167. #define EMMA_PRP_BASE_ADDR MX2x_EMMA_PRP_BASE_ADDR
  168. #define CCM_BASE_ADDR MX2x_CCM_BASE_ADDR
  169. #define SYSCTRL_BASE_ADDR MX2x_SYSCTRL_BASE_ADDR
  170. #define JAM_BASE_ADDR MX2x_JAM_BASE_ADDR
  171. #define MAX_BASE_ADDR MX2x_MAX_BASE_ADDR
  172. #define AVIC_BASE_ADDR MX2x_AVIC_BASE_ADDR
  173. #define SAHB1_BASE_ADDR MX2x_SAHB1_BASE_ADDR
  174. #define SAHB1_SIZE MX2x_SAHB1_SIZE
  175. #define CSI_BASE_ADDR MX2x_CSI_BASE_ADDR
  176. #define MXC_INT_CSPI3 MX2x_INT_CSPI3
  177. #define MXC_INT_GPIO MX2x_INT_GPIO
  178. #define MXC_INT_SDHC2 MX2x_INT_SDHC2
  179. #define MXC_INT_SDHC1 MX2x_INT_SDHC1
  180. #define MXC_INT_I2C MX2x_INT_I2C
  181. #define MXC_INT_SSI2 MX2x_INT_SSI2
  182. #define MXC_INT_SSI1 MX2x_INT_SSI1
  183. #define MXC_INT_CSPI2 MX2x_INT_CSPI2
  184. #define MXC_INT_CSPI1 MX2x_INT_CSPI1
  185. #define MXC_INT_UART4 MX2x_INT_UART4
  186. #define MXC_INT_UART3 MX2x_INT_UART3
  187. #define MXC_INT_UART2 MX2x_INT_UART2
  188. #define MXC_INT_UART1 MX2x_INT_UART1
  189. #define MXC_INT_KPP MX2x_INT_KPP
  190. #define MXC_INT_RTC MX2x_INT_RTC
  191. #define MXC_INT_PWM MX2x_INT_PWM
  192. #define MXC_INT_GPT3 MX2x_INT_GPT3
  193. #define MXC_INT_GPT2 MX2x_INT_GPT2
  194. #define MXC_INT_GPT1 MX2x_INT_GPT1
  195. #define MXC_INT_WDOG MX2x_INT_WDOG
  196. #define MXC_INT_PCMCIA MX2x_INT_PCMCIA
  197. #define MXC_INT_NANDFC MX2x_INT_NANDFC
  198. #define MXC_INT_CSI MX2x_INT_CSI
  199. #define MXC_INT_DMACH0 MX2x_INT_DMACH0
  200. #define MXC_INT_DMACH1 MX2x_INT_DMACH1
  201. #define MXC_INT_DMACH2 MX2x_INT_DMACH2
  202. #define MXC_INT_DMACH3 MX2x_INT_DMACH3
  203. #define MXC_INT_DMACH4 MX2x_INT_DMACH4
  204. #define MXC_INT_DMACH5 MX2x_INT_DMACH5
  205. #define MXC_INT_DMACH6 MX2x_INT_DMACH6
  206. #define MXC_INT_DMACH7 MX2x_INT_DMACH7
  207. #define MXC_INT_DMACH8 MX2x_INT_DMACH8
  208. #define MXC_INT_DMACH9 MX2x_INT_DMACH9
  209. #define MXC_INT_DMACH10 MX2x_INT_DMACH10
  210. #define MXC_INT_DMACH11 MX2x_INT_DMACH11
  211. #define MXC_INT_DMACH12 MX2x_INT_DMACH12
  212. #define MXC_INT_DMACH13 MX2x_INT_DMACH13
  213. #define MXC_INT_DMACH14 MX2x_INT_DMACH14
  214. #define MXC_INT_DMACH15 MX2x_INT_DMACH15
  215. #define MXC_INT_EMMAPRP MX2x_INT_EMMAPRP
  216. #define MXC_INT_EMMAPP MX2x_INT_EMMAPP
  217. #define MXC_INT_SLCDC MX2x_INT_SLCDC
  218. #define MXC_INT_LCDC MX2x_INT_LCDC
  219. #define DMA_REQ_CSPI3_RX MX2x_DMA_REQ_CSPI3_RX
  220. #define DMA_REQ_CSPI3_TX MX2x_DMA_REQ_CSPI3_TX
  221. #define DMA_REQ_EXT MX2x_DMA_REQ_EXT
  222. #define DMA_REQ_SDHC2 MX2x_DMA_REQ_SDHC2
  223. #define DMA_REQ_SDHC1 MX2x_DMA_REQ_SDHC1
  224. #define DMA_REQ_SSI2_RX0 MX2x_DMA_REQ_SSI2_RX0
  225. #define DMA_REQ_SSI2_TX0 MX2x_DMA_REQ_SSI2_TX0
  226. #define DMA_REQ_SSI2_RX1 MX2x_DMA_REQ_SSI2_RX1
  227. #define DMA_REQ_SSI2_TX1 MX2x_DMA_REQ_SSI2_TX1
  228. #define DMA_REQ_SSI1_RX0 MX2x_DMA_REQ_SSI1_RX0
  229. #define DMA_REQ_SSI1_TX0 MX2x_DMA_REQ_SSI1_TX0
  230. #define DMA_REQ_SSI1_RX1 MX2x_DMA_REQ_SSI1_RX1
  231. #define DMA_REQ_SSI1_TX1 MX2x_DMA_REQ_SSI1_TX1
  232. #define DMA_REQ_CSPI2_RX MX2x_DMA_REQ_CSPI2_RX
  233. #define DMA_REQ_CSPI2_TX MX2x_DMA_REQ_CSPI2_TX
  234. #define DMA_REQ_CSPI1_RX MX2x_DMA_REQ_CSPI1_RX
  235. #define DMA_REQ_CSPI1_TX MX2x_DMA_REQ_CSPI1_TX
  236. #define DMA_REQ_UART4_RX MX2x_DMA_REQ_UART4_RX
  237. #define DMA_REQ_UART4_TX MX2x_DMA_REQ_UART4_TX
  238. #define DMA_REQ_UART3_RX MX2x_DMA_REQ_UART3_RX
  239. #define DMA_REQ_UART3_TX MX2x_DMA_REQ_UART3_TX
  240. #define DMA_REQ_UART2_RX MX2x_DMA_REQ_UART2_RX
  241. #define DMA_REQ_UART2_TX MX2x_DMA_REQ_UART2_TX
  242. #define DMA_REQ_UART1_RX MX2x_DMA_REQ_UART1_RX
  243. #define DMA_REQ_UART1_TX MX2x_DMA_REQ_UART1_TX
  244. #define DMA_REQ_CSI_STAT MX2x_DMA_REQ_CSI_STAT
  245. #define DMA_REQ_CSI_RX MX2x_DMA_REQ_CSI_RX
  246. #endif
  247. #endif /* ifndef __MACH_MX2x_H__ */