mx25.h 2.9 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586
  1. #ifndef __MACH_MX25_H__
  2. #define __MACH_MX25_H__
  3. #define MX25_AIPS1_BASE_ADDR 0x43f00000
  4. #define MX25_AIPS1_SIZE SZ_1M
  5. #define MX25_AIPS2_BASE_ADDR 0x53f00000
  6. #define MX25_AIPS2_SIZE SZ_1M
  7. #define MX25_AVIC_BASE_ADDR 0x68000000
  8. #define MX25_AVIC_SIZE SZ_1M
  9. #define MX25_I2C1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x80000)
  10. #define MX25_I2C3_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x84000)
  11. #define MX25_CAN1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x88000)
  12. #define MX25_CAN2_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x8c000)
  13. #define MX25_I2C2_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x98000)
  14. #define MX25_CSPI1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xa4000)
  15. #define MX25_IOMUXC_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xac000)
  16. #define MX25_CRM_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x80000)
  17. #define MX25_GPT1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x90000)
  18. #define MX25_GPIO4_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x9c000)
  19. #define MX25_GPIO3_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa4000)
  20. #define MX25_GPIO1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xcc000)
  21. #define MX25_GPIO2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xd0000)
  22. #define MX25_WDOG_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xdc000)
  23. #define MX25_UART1_BASE_ADDR 0x43f90000
  24. #define MX25_UART2_BASE_ADDR 0x43f94000
  25. #define MX25_AUDMUX_BASE_ADDR 0x43fb0000
  26. #define MX25_UART3_BASE_ADDR 0x5000c000
  27. #define MX25_UART4_BASE_ADDR 0x50008000
  28. #define MX25_UART5_BASE_ADDR 0x5002c000
  29. #define MX25_CSPI3_BASE_ADDR 0x50004000
  30. #define MX25_CSPI2_BASE_ADDR 0x50010000
  31. #define MX25_FEC_BASE_ADDR 0x50038000
  32. #define MX25_SSI2_BASE_ADDR 0x50014000
  33. #define MX25_SSI1_BASE_ADDR 0x50034000
  34. #define MX25_NFC_BASE_ADDR 0xbb000000
  35. #define MX25_DRYICE_BASE_ADDR 0x53ffc000
  36. #define MX25_ESDHC1_BASE_ADDR 0x53fb4000
  37. #define MX25_ESDHC2_BASE_ADDR 0x53fb8000
  38. #define MX25_LCDC_BASE_ADDR 0x53fbc000
  39. #define MX25_KPP_BASE_ADDR 0x43fa8000
  40. #define MX25_SDMA_BASE_ADDR 0x53fd4000
  41. #define MX25_OTG_BASE_ADDR 0x53ff4000
  42. #define MX25_CSI_BASE_ADDR 0x53ff8000
  43. #define MX25_IO_P2V(x) IMX_IO_P2V(x)
  44. #define MX25_IO_ADDRESS(x) IOMEM(MX25_IO_P2V(x))
  45. #define MX25_INT_CSPI3 0
  46. #define MX25_INT_I2C1 3
  47. #define MX25_INT_I2C2 4
  48. #define MX25_INT_UART4 5
  49. #define MX25_INT_ESDHC2 8
  50. #define MX25_INT_ESDHC1 9
  51. #define MX25_INT_I2C3 10
  52. #define MX25_INT_SSI2 11
  53. #define MX25_INT_SSI1 12
  54. #define MX25_INT_CSPI2 13
  55. #define MX25_INT_CSPI1 14
  56. #define MX25_INT_CSI 17
  57. #define MX25_INT_UART3 18
  58. #define MX25_INT_KPP 24
  59. #define MX25_INT_DRYICE 25
  60. #define MX25_INT_UART2 32
  61. #define MX25_INT_NFC 33
  62. #define MX25_INT_SDMA 34
  63. #define MX25_INT_LCDC 39
  64. #define MX25_INT_UART5 40
  65. #define MX25_INT_CAN1 43
  66. #define MX25_INT_CAN2 44
  67. #define MX25_INT_UART1 45
  68. #define MX25_INT_FEC 57
  69. #define MX25_DMA_REQ_SSI2_RX1 22
  70. #define MX25_DMA_REQ_SSI2_TX1 23
  71. #define MX25_DMA_REQ_SSI2_RX0 24
  72. #define MX25_DMA_REQ_SSI2_TX0 25
  73. #define MX25_DMA_REQ_SSI1_RX1 26
  74. #define MX25_DMA_REQ_SSI1_TX1 27
  75. #define MX25_DMA_REQ_SSI1_RX0 28
  76. #define MX25_DMA_REQ_SSI1_TX0 29
  77. #endif /* ifndef __MACH_MX25_H__ */