s2io.c 216 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914191519161917191819191920192119221923192419251926192719281929193019311932193319341935193619371938193919401941194219431944194519461947194819491950195119521953195419551956195719581959196019611962196319641965196619671968196919701971197219731974197519761977197819791980198119821983198419851986198719881989199019911992199319941995199619971998199920002001200220032004200520062007200820092010201120122013201420152016201720182019202020212022202320242025202620272028202920302031203220332034203520362037203820392040204120422043204420452046204720482049205020512052205320542055205620572058205920602061206220632064206520662067206820692070207120722073207420752076207720782079208020812082208320842085208620872088208920902091209220932094209520962097209820992100210121022103210421052106210721082109211021112112211321142115211621172118211921202121212221232124212521262127212821292130213121322133213421352136213721382139214021412142214321442145214621472148214921502151215221532154215521562157215821592160216121622163216421652166216721682169217021712172217321742175217621772178217921802181218221832184218521862187218821892190219121922193219421952196219721982199220022012202220322042205220622072208220922102211221222132214221522162217221822192220222122222223222422252226222722282229223022312232223322342235223622372238223922402241224222432244224522462247224822492250225122522253225422552256225722582259226022612262226322642265226622672268226922702271227222732274227522762277227822792280228122822283228422852286228722882289229022912292229322942295229622972298229923002301230223032304230523062307230823092310231123122313231423152316231723182319232023212322232323242325232623272328232923302331233223332334233523362337233823392340234123422343234423452346234723482349235023512352235323542355235623572358235923602361236223632364236523662367236823692370237123722373237423752376237723782379238023812382238323842385238623872388238923902391239223932394239523962397239823992400240124022403240424052406240724082409241024112412241324142415241624172418241924202421242224232424242524262427242824292430243124322433243424352436243724382439244024412442244324442445244624472448244924502451245224532454245524562457245824592460246124622463246424652466246724682469247024712472247324742475247624772478247924802481248224832484248524862487248824892490249124922493249424952496249724982499250025012502250325042505250625072508250925102511251225132514251525162517251825192520252125222523252425252526252725282529253025312532253325342535253625372538253925402541254225432544254525462547254825492550255125522553255425552556255725582559256025612562256325642565256625672568256925702571257225732574257525762577257825792580258125822583258425852586258725882589259025912592259325942595259625972598259926002601260226032604260526062607260826092610261126122613261426152616261726182619262026212622262326242625262626272628262926302631263226332634263526362637263826392640264126422643264426452646264726482649265026512652265326542655265626572658265926602661266226632664266526662667266826692670267126722673267426752676267726782679268026812682268326842685268626872688268926902691269226932694269526962697269826992700270127022703270427052706270727082709271027112712271327142715271627172718271927202721272227232724272527262727272827292730273127322733273427352736273727382739274027412742274327442745274627472748274927502751275227532754275527562757275827592760276127622763276427652766276727682769277027712772277327742775277627772778277927802781278227832784278527862787278827892790279127922793279427952796279727982799280028012802280328042805280628072808280928102811281228132814281528162817281828192820282128222823282428252826282728282829283028312832283328342835283628372838283928402841284228432844284528462847284828492850285128522853285428552856285728582859286028612862286328642865286628672868286928702871287228732874287528762877287828792880288128822883288428852886288728882889289028912892289328942895289628972898289929002901290229032904290529062907290829092910291129122913291429152916291729182919292029212922292329242925292629272928292929302931293229332934293529362937293829392940294129422943294429452946294729482949295029512952295329542955295629572958295929602961296229632964296529662967296829692970297129722973297429752976297729782979298029812982298329842985298629872988298929902991299229932994299529962997299829993000300130023003300430053006300730083009301030113012301330143015301630173018301930203021302230233024302530263027302830293030303130323033303430353036303730383039304030413042304330443045304630473048304930503051305230533054305530563057305830593060306130623063306430653066306730683069307030713072307330743075307630773078307930803081308230833084308530863087308830893090309130923093309430953096309730983099310031013102310331043105310631073108310931103111311231133114311531163117311831193120312131223123312431253126312731283129313031313132313331343135313631373138313931403141314231433144314531463147314831493150315131523153315431553156315731583159316031613162316331643165316631673168316931703171317231733174317531763177317831793180318131823183318431853186318731883189319031913192319331943195319631973198319932003201320232033204320532063207320832093210321132123213321432153216321732183219322032213222322332243225322632273228322932303231323232333234323532363237323832393240324132423243324432453246324732483249325032513252325332543255325632573258325932603261326232633264326532663267326832693270327132723273327432753276327732783279328032813282328332843285328632873288328932903291329232933294329532963297329832993300330133023303330433053306330733083309331033113312331333143315331633173318331933203321332233233324332533263327332833293330333133323333333433353336333733383339334033413342334333443345334633473348334933503351335233533354335533563357335833593360336133623363336433653366336733683369337033713372337333743375337633773378337933803381338233833384338533863387338833893390339133923393339433953396339733983399340034013402340334043405340634073408340934103411341234133414341534163417341834193420342134223423342434253426342734283429343034313432343334343435343634373438343934403441344234433444344534463447344834493450345134523453345434553456345734583459346034613462346334643465346634673468346934703471347234733474347534763477347834793480348134823483348434853486348734883489349034913492349334943495349634973498349935003501350235033504350535063507350835093510351135123513351435153516351735183519352035213522352335243525352635273528352935303531353235333534353535363537353835393540354135423543354435453546354735483549355035513552355335543555355635573558355935603561356235633564356535663567356835693570357135723573357435753576357735783579358035813582358335843585358635873588358935903591359235933594359535963597359835993600360136023603360436053606360736083609361036113612361336143615361636173618361936203621362236233624362536263627362836293630363136323633363436353636363736383639364036413642364336443645364636473648364936503651365236533654365536563657365836593660366136623663366436653666366736683669367036713672367336743675367636773678367936803681368236833684368536863687368836893690369136923693369436953696369736983699370037013702370337043705370637073708370937103711371237133714371537163717371837193720372137223723372437253726372737283729373037313732373337343735373637373738373937403741374237433744374537463747374837493750375137523753375437553756375737583759376037613762376337643765376637673768376937703771377237733774377537763777377837793780378137823783378437853786378737883789379037913792379337943795379637973798379938003801380238033804380538063807380838093810381138123813381438153816381738183819382038213822382338243825382638273828382938303831383238333834383538363837383838393840384138423843384438453846384738483849385038513852385338543855385638573858385938603861386238633864386538663867386838693870387138723873387438753876387738783879388038813882388338843885388638873888388938903891389238933894389538963897389838993900390139023903390439053906390739083909391039113912391339143915391639173918391939203921392239233924392539263927392839293930393139323933393439353936393739383939394039413942394339443945394639473948394939503951395239533954395539563957395839593960396139623963396439653966396739683969397039713972397339743975397639773978397939803981398239833984398539863987398839893990399139923993399439953996399739983999400040014002400340044005400640074008400940104011401240134014401540164017401840194020402140224023402440254026402740284029403040314032403340344035403640374038403940404041404240434044404540464047404840494050405140524053405440554056405740584059406040614062406340644065406640674068406940704071407240734074407540764077407840794080408140824083408440854086408740884089409040914092409340944095409640974098409941004101410241034104410541064107410841094110411141124113411441154116411741184119412041214122412341244125412641274128412941304131413241334134413541364137413841394140414141424143414441454146414741484149415041514152415341544155415641574158415941604161416241634164416541664167416841694170417141724173417441754176417741784179418041814182418341844185418641874188418941904191419241934194419541964197419841994200420142024203420442054206420742084209421042114212421342144215421642174218421942204221422242234224422542264227422842294230423142324233423442354236423742384239424042414242424342444245424642474248424942504251425242534254425542564257425842594260426142624263426442654266426742684269427042714272427342744275427642774278427942804281428242834284428542864287428842894290429142924293429442954296429742984299430043014302430343044305430643074308430943104311431243134314431543164317431843194320432143224323432443254326432743284329433043314332433343344335433643374338433943404341434243434344434543464347434843494350435143524353435443554356435743584359436043614362436343644365436643674368436943704371437243734374437543764377437843794380438143824383438443854386438743884389439043914392439343944395439643974398439944004401440244034404440544064407440844094410441144124413441444154416441744184419442044214422442344244425442644274428442944304431443244334434443544364437443844394440444144424443444444454446444744484449445044514452445344544455445644574458445944604461446244634464446544664467446844694470447144724473447444754476447744784479448044814482448344844485448644874488448944904491449244934494449544964497449844994500450145024503450445054506450745084509451045114512451345144515451645174518451945204521452245234524452545264527452845294530453145324533453445354536453745384539454045414542454345444545454645474548454945504551455245534554455545564557455845594560456145624563456445654566456745684569457045714572457345744575457645774578457945804581458245834584458545864587458845894590459145924593459445954596459745984599460046014602460346044605460646074608460946104611461246134614461546164617461846194620462146224623462446254626462746284629463046314632463346344635463646374638463946404641464246434644464546464647464846494650465146524653465446554656465746584659466046614662466346644665466646674668466946704671467246734674467546764677467846794680468146824683468446854686468746884689469046914692469346944695469646974698469947004701470247034704470547064707470847094710471147124713471447154716471747184719472047214722472347244725472647274728472947304731473247334734473547364737473847394740474147424743474447454746474747484749475047514752475347544755475647574758475947604761476247634764476547664767476847694770477147724773477447754776477747784779478047814782478347844785478647874788478947904791479247934794479547964797479847994800480148024803480448054806480748084809481048114812481348144815481648174818481948204821482248234824482548264827482848294830483148324833483448354836483748384839484048414842484348444845484648474848484948504851485248534854485548564857485848594860486148624863486448654866486748684869487048714872487348744875487648774878487948804881488248834884488548864887488848894890489148924893489448954896489748984899490049014902490349044905490649074908490949104911491249134914491549164917491849194920492149224923492449254926492749284929493049314932493349344935493649374938493949404941494249434944494549464947494849494950495149524953495449554956495749584959496049614962496349644965496649674968496949704971497249734974497549764977497849794980498149824983498449854986498749884989499049914992499349944995499649974998499950005001500250035004500550065007500850095010501150125013501450155016501750185019502050215022502350245025502650275028502950305031503250335034503550365037503850395040504150425043504450455046504750485049505050515052505350545055505650575058505950605061506250635064506550665067506850695070507150725073507450755076507750785079508050815082508350845085508650875088508950905091509250935094509550965097509850995100510151025103510451055106510751085109511051115112511351145115511651175118511951205121512251235124512551265127512851295130513151325133513451355136513751385139514051415142514351445145514651475148514951505151515251535154515551565157515851595160516151625163516451655166516751685169517051715172517351745175517651775178517951805181518251835184518551865187518851895190519151925193519451955196519751985199520052015202520352045205520652075208520952105211521252135214521552165217521852195220522152225223522452255226522752285229523052315232523352345235523652375238523952405241524252435244524552465247524852495250525152525253525452555256525752585259526052615262526352645265526652675268526952705271527252735274527552765277527852795280528152825283528452855286528752885289529052915292529352945295529652975298529953005301530253035304530553065307530853095310531153125313531453155316531753185319532053215322532353245325532653275328532953305331533253335334533553365337533853395340534153425343534453455346534753485349535053515352535353545355535653575358535953605361536253635364536553665367536853695370537153725373537453755376537753785379538053815382538353845385538653875388538953905391539253935394539553965397539853995400540154025403540454055406540754085409541054115412541354145415541654175418541954205421542254235424542554265427542854295430543154325433543454355436543754385439544054415442544354445445544654475448544954505451545254535454545554565457545854595460546154625463546454655466546754685469547054715472547354745475547654775478547954805481548254835484548554865487548854895490549154925493549454955496549754985499550055015502550355045505550655075508550955105511551255135514551555165517551855195520552155225523552455255526552755285529553055315532553355345535553655375538553955405541554255435544554555465547554855495550555155525553555455555556555755585559556055615562556355645565556655675568556955705571557255735574557555765577557855795580558155825583558455855586558755885589559055915592559355945595559655975598559956005601560256035604560556065607560856095610561156125613561456155616561756185619562056215622562356245625562656275628562956305631563256335634563556365637563856395640564156425643564456455646564756485649565056515652565356545655565656575658565956605661566256635664566556665667566856695670567156725673567456755676567756785679568056815682568356845685568656875688568956905691569256935694569556965697569856995700570157025703570457055706570757085709571057115712571357145715571657175718571957205721572257235724572557265727572857295730573157325733573457355736573757385739574057415742574357445745574657475748574957505751575257535754575557565757575857595760576157625763576457655766576757685769577057715772577357745775577657775778577957805781578257835784578557865787578857895790579157925793579457955796579757985799580058015802580358045805580658075808580958105811581258135814581558165817581858195820582158225823582458255826582758285829583058315832583358345835583658375838583958405841584258435844584558465847584858495850585158525853585458555856585758585859586058615862586358645865586658675868586958705871587258735874587558765877587858795880588158825883588458855886588758885889589058915892589358945895589658975898589959005901590259035904590559065907590859095910591159125913591459155916591759185919592059215922592359245925592659275928592959305931593259335934593559365937593859395940594159425943594459455946594759485949595059515952595359545955595659575958595959605961596259635964596559665967596859695970597159725973597459755976597759785979598059815982598359845985598659875988598959905991599259935994599559965997599859996000600160026003600460056006600760086009601060116012601360146015601660176018601960206021602260236024602560266027602860296030603160326033603460356036603760386039604060416042604360446045604660476048604960506051605260536054605560566057605860596060606160626063606460656066606760686069607060716072607360746075607660776078607960806081608260836084608560866087608860896090609160926093609460956096609760986099610061016102610361046105610661076108610961106111611261136114611561166117611861196120612161226123612461256126612761286129613061316132613361346135613661376138613961406141614261436144614561466147614861496150615161526153615461556156615761586159616061616162616361646165616661676168616961706171617261736174617561766177617861796180618161826183618461856186618761886189619061916192619361946195619661976198619962006201620262036204620562066207620862096210621162126213621462156216621762186219622062216222622362246225622662276228622962306231623262336234623562366237623862396240624162426243624462456246624762486249625062516252625362546255625662576258625962606261626262636264626562666267626862696270627162726273627462756276627762786279628062816282628362846285628662876288628962906291629262936294629562966297629862996300630163026303630463056306630763086309631063116312631363146315631663176318631963206321632263236324632563266327632863296330633163326333633463356336633763386339634063416342634363446345634663476348634963506351635263536354635563566357635863596360636163626363636463656366636763686369637063716372637363746375637663776378637963806381638263836384638563866387638863896390639163926393639463956396639763986399640064016402640364046405640664076408640964106411641264136414641564166417641864196420642164226423642464256426642764286429643064316432643364346435643664376438643964406441644264436444644564466447644864496450645164526453645464556456645764586459646064616462646364646465646664676468646964706471647264736474647564766477647864796480648164826483648464856486648764886489649064916492649364946495649664976498649965006501650265036504650565066507650865096510651165126513651465156516651765186519652065216522652365246525652665276528652965306531653265336534653565366537653865396540654165426543654465456546654765486549655065516552655365546555655665576558655965606561656265636564656565666567656865696570657165726573657465756576657765786579658065816582658365846585658665876588658965906591659265936594659565966597659865996600660166026603660466056606660766086609661066116612661366146615661666176618661966206621662266236624662566266627662866296630663166326633663466356636663766386639664066416642664366446645664666476648664966506651665266536654665566566657665866596660666166626663666466656666666766686669667066716672667366746675667666776678667966806681668266836684668566866687668866896690669166926693669466956696669766986699670067016702670367046705670667076708670967106711671267136714671567166717671867196720672167226723672467256726672767286729673067316732673367346735673667376738673967406741674267436744674567466747674867496750675167526753675467556756675767586759676067616762676367646765676667676768676967706771677267736774677567766777677867796780678167826783678467856786678767886789679067916792679367946795679667976798679968006801680268036804680568066807680868096810681168126813681468156816681768186819682068216822682368246825682668276828682968306831683268336834683568366837683868396840684168426843684468456846684768486849685068516852685368546855685668576858685968606861686268636864686568666867686868696870687168726873687468756876687768786879688068816882688368846885688668876888688968906891689268936894689568966897689868996900690169026903690469056906690769086909691069116912691369146915691669176918691969206921692269236924692569266927692869296930693169326933693469356936693769386939694069416942694369446945694669476948694969506951695269536954695569566957695869596960696169626963696469656966696769686969697069716972697369746975697669776978697969806981698269836984698569866987698869896990699169926993699469956996699769986999700070017002700370047005700670077008700970107011701270137014701570167017701870197020702170227023702470257026702770287029703070317032703370347035703670377038703970407041704270437044704570467047704870497050705170527053705470557056705770587059706070617062706370647065706670677068706970707071707270737074707570767077707870797080708170827083708470857086708770887089709070917092709370947095709670977098709971007101710271037104710571067107710871097110711171127113711471157116711771187119712071217122712371247125712671277128712971307131713271337134713571367137713871397140714171427143714471457146714771487149715071517152715371547155715671577158715971607161716271637164716571667167716871697170717171727173717471757176717771787179718071817182718371847185718671877188718971907191719271937194719571967197719871997200720172027203720472057206720772087209721072117212721372147215721672177218721972207221722272237224722572267227722872297230723172327233723472357236723772387239724072417242724372447245724672477248724972507251725272537254725572567257725872597260726172627263726472657266726772687269727072717272727372747275727672777278727972807281728272837284728572867287728872897290729172927293729472957296729772987299730073017302730373047305730673077308730973107311731273137314731573167317731873197320732173227323732473257326732773287329733073317332733373347335733673377338733973407341734273437344734573467347734873497350735173527353735473557356735773587359736073617362736373647365736673677368736973707371737273737374737573767377737873797380738173827383738473857386738773887389739073917392739373947395739673977398739974007401740274037404740574067407740874097410741174127413741474157416741774187419742074217422742374247425742674277428742974307431743274337434743574367437743874397440744174427443744474457446744774487449745074517452745374547455745674577458745974607461746274637464746574667467746874697470747174727473747474757476747774787479748074817482748374847485748674877488748974907491749274937494749574967497749874997500750175027503750475057506750775087509751075117512751375147515751675177518751975207521752275237524752575267527752875297530753175327533753475357536753775387539754075417542754375447545754675477548754975507551755275537554755575567557755875597560756175627563756475657566756775687569757075717572757375747575757675777578757975807581758275837584758575867587758875897590759175927593759475957596759775987599760076017602760376047605760676077608760976107611761276137614761576167617761876197620762176227623762476257626762776287629763076317632763376347635763676377638763976407641764276437644764576467647764876497650765176527653765476557656765776587659766076617662766376647665766676677668766976707671
  1. /************************************************************************
  2. * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
  3. * Copyright(c) 2002-2005 Neterion Inc.
  4. * This software may be used and distributed according to the terms of
  5. * the GNU General Public License (GPL), incorporated herein by reference.
  6. * Drivers based on or derived from this code fall under the GPL and must
  7. * retain the authorship, copyright and license notice. This file is not
  8. * a complete program and may only be used when the entire operating
  9. * system is licensed under the GPL.
  10. * See the file COPYING in this distribution for more information.
  11. *
  12. * Credits:
  13. * Jeff Garzik : For pointing out the improper error condition
  14. * check in the s2io_xmit routine and also some
  15. * issues in the Tx watch dog function. Also for
  16. * patiently answering all those innumerable
  17. * questions regaring the 2.6 porting issues.
  18. * Stephen Hemminger : Providing proper 2.6 porting mechanism for some
  19. * macros available only in 2.6 Kernel.
  20. * Francois Romieu : For pointing out all code part that were
  21. * deprecated and also styling related comments.
  22. * Grant Grundler : For helping me get rid of some Architecture
  23. * dependent code.
  24. * Christopher Hellwig : Some more 2.6 specific issues in the driver.
  25. *
  26. * The module loadable parameters that are supported by the driver and a brief
  27. * explaination of all the variables.
  28. *
  29. * rx_ring_num : This can be used to program the number of receive rings used
  30. * in the driver.
  31. * rx_ring_sz: This defines the number of receive blocks each ring can have.
  32. * This is also an array of size 8.
  33. * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
  34. * values are 1, 2 and 3.
  35. * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
  36. * tx_fifo_len: This too is an array of 8. Each element defines the number of
  37. * Tx descriptors that can be associated with each corresponding FIFO.
  38. * intr_type: This defines the type of interrupt. The values can be 0(INTA),
  39. * 1(MSI), 2(MSI_X). Default value is '0(INTA)'
  40. * lro: Specifies whether to enable Large Receive Offload (LRO) or not.
  41. * Possible values '1' for enable '0' for disable. Default is '0'
  42. * lro_max_pkts: This parameter defines maximum number of packets can be
  43. * aggregated as a single large packet
  44. * napi: This parameter used to enable/disable NAPI (polling Rx)
  45. * Possible values '1' for enable and '0' for disable. Default is '1'
  46. * ufo: This parameter used to enable/disable UDP Fragmentation Offload(UFO)
  47. * Possible values '1' for enable and '0' for disable. Default is '0'
  48. * vlan_tag_strip: This can be used to enable or disable vlan stripping.
  49. * Possible values '1' for enable , '0' for disable.
  50. * Default is '2' - which means disable in promisc mode
  51. * and enable in non-promiscuous mode.
  52. ************************************************************************/
  53. #include <linux/module.h>
  54. #include <linux/types.h>
  55. #include <linux/errno.h>
  56. #include <linux/ioport.h>
  57. #include <linux/pci.h>
  58. #include <linux/dma-mapping.h>
  59. #include <linux/kernel.h>
  60. #include <linux/netdevice.h>
  61. #include <linux/etherdevice.h>
  62. #include <linux/skbuff.h>
  63. #include <linux/init.h>
  64. #include <linux/delay.h>
  65. #include <linux/stddef.h>
  66. #include <linux/ioctl.h>
  67. #include <linux/timex.h>
  68. #include <linux/ethtool.h>
  69. #include <linux/workqueue.h>
  70. #include <linux/if_vlan.h>
  71. #include <linux/ip.h>
  72. #include <linux/tcp.h>
  73. #include <net/tcp.h>
  74. #include <asm/system.h>
  75. #include <asm/uaccess.h>
  76. #include <asm/io.h>
  77. #include <asm/div64.h>
  78. #include <asm/irq.h>
  79. /* local include */
  80. #include "s2io.h"
  81. #include "s2io-regs.h"
  82. #define DRV_VERSION "2.0.16.1"
  83. /* S2io Driver name & version. */
  84. static char s2io_driver_name[] = "Neterion";
  85. static char s2io_driver_version[] = DRV_VERSION;
  86. static int rxd_size[4] = {32,48,48,64};
  87. static int rxd_count[4] = {127,85,85,63};
  88. static inline int RXD_IS_UP2DT(struct RxD_t *rxdp)
  89. {
  90. int ret;
  91. ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
  92. (GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK));
  93. return ret;
  94. }
  95. /*
  96. * Cards with following subsystem_id have a link state indication
  97. * problem, 600B, 600C, 600D, 640B, 640C and 640D.
  98. * macro below identifies these cards given the subsystem_id.
  99. */
  100. #define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \
  101. (dev_type == XFRAME_I_DEVICE) ? \
  102. ((((subid >= 0x600B) && (subid <= 0x600D)) || \
  103. ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
  104. #define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
  105. ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
  106. #define TASKLET_IN_USE test_and_set_bit(0, (&sp->tasklet_status))
  107. #define PANIC 1
  108. #define LOW 2
  109. static inline int rx_buffer_level(struct s2io_nic * sp, int rxb_size, int ring)
  110. {
  111. struct mac_info *mac_control;
  112. mac_control = &sp->mac_control;
  113. if (rxb_size <= rxd_count[sp->rxd_mode])
  114. return PANIC;
  115. else if ((mac_control->rings[ring].pkt_cnt - rxb_size) > 16)
  116. return LOW;
  117. return 0;
  118. }
  119. /* Ethtool related variables and Macros. */
  120. static char s2io_gstrings[][ETH_GSTRING_LEN] = {
  121. "Register test\t(offline)",
  122. "Eeprom test\t(offline)",
  123. "Link test\t(online)",
  124. "RLDRAM test\t(offline)",
  125. "BIST Test\t(offline)"
  126. };
  127. static char ethtool_stats_keys[][ETH_GSTRING_LEN] = {
  128. {"tmac_frms"},
  129. {"tmac_data_octets"},
  130. {"tmac_drop_frms"},
  131. {"tmac_mcst_frms"},
  132. {"tmac_bcst_frms"},
  133. {"tmac_pause_ctrl_frms"},
  134. {"tmac_ttl_octets"},
  135. {"tmac_ucst_frms"},
  136. {"tmac_nucst_frms"},
  137. {"tmac_any_err_frms"},
  138. {"tmac_ttl_less_fb_octets"},
  139. {"tmac_vld_ip_octets"},
  140. {"tmac_vld_ip"},
  141. {"tmac_drop_ip"},
  142. {"tmac_icmp"},
  143. {"tmac_rst_tcp"},
  144. {"tmac_tcp"},
  145. {"tmac_udp"},
  146. {"rmac_vld_frms"},
  147. {"rmac_data_octets"},
  148. {"rmac_fcs_err_frms"},
  149. {"rmac_drop_frms"},
  150. {"rmac_vld_mcst_frms"},
  151. {"rmac_vld_bcst_frms"},
  152. {"rmac_in_rng_len_err_frms"},
  153. {"rmac_out_rng_len_err_frms"},
  154. {"rmac_long_frms"},
  155. {"rmac_pause_ctrl_frms"},
  156. {"rmac_unsup_ctrl_frms"},
  157. {"rmac_ttl_octets"},
  158. {"rmac_accepted_ucst_frms"},
  159. {"rmac_accepted_nucst_frms"},
  160. {"rmac_discarded_frms"},
  161. {"rmac_drop_events"},
  162. {"rmac_ttl_less_fb_octets"},
  163. {"rmac_ttl_frms"},
  164. {"rmac_usized_frms"},
  165. {"rmac_osized_frms"},
  166. {"rmac_frag_frms"},
  167. {"rmac_jabber_frms"},
  168. {"rmac_ttl_64_frms"},
  169. {"rmac_ttl_65_127_frms"},
  170. {"rmac_ttl_128_255_frms"},
  171. {"rmac_ttl_256_511_frms"},
  172. {"rmac_ttl_512_1023_frms"},
  173. {"rmac_ttl_1024_1518_frms"},
  174. {"rmac_ip"},
  175. {"rmac_ip_octets"},
  176. {"rmac_hdr_err_ip"},
  177. {"rmac_drop_ip"},
  178. {"rmac_icmp"},
  179. {"rmac_tcp"},
  180. {"rmac_udp"},
  181. {"rmac_err_drp_udp"},
  182. {"rmac_xgmii_err_sym"},
  183. {"rmac_frms_q0"},
  184. {"rmac_frms_q1"},
  185. {"rmac_frms_q2"},
  186. {"rmac_frms_q3"},
  187. {"rmac_frms_q4"},
  188. {"rmac_frms_q5"},
  189. {"rmac_frms_q6"},
  190. {"rmac_frms_q7"},
  191. {"rmac_full_q0"},
  192. {"rmac_full_q1"},
  193. {"rmac_full_q2"},
  194. {"rmac_full_q3"},
  195. {"rmac_full_q4"},
  196. {"rmac_full_q5"},
  197. {"rmac_full_q6"},
  198. {"rmac_full_q7"},
  199. {"rmac_pause_cnt"},
  200. {"rmac_xgmii_data_err_cnt"},
  201. {"rmac_xgmii_ctrl_err_cnt"},
  202. {"rmac_accepted_ip"},
  203. {"rmac_err_tcp"},
  204. {"rd_req_cnt"},
  205. {"new_rd_req_cnt"},
  206. {"new_rd_req_rtry_cnt"},
  207. {"rd_rtry_cnt"},
  208. {"wr_rtry_rd_ack_cnt"},
  209. {"wr_req_cnt"},
  210. {"new_wr_req_cnt"},
  211. {"new_wr_req_rtry_cnt"},
  212. {"wr_rtry_cnt"},
  213. {"wr_disc_cnt"},
  214. {"rd_rtry_wr_ack_cnt"},
  215. {"txp_wr_cnt"},
  216. {"txd_rd_cnt"},
  217. {"txd_wr_cnt"},
  218. {"rxd_rd_cnt"},
  219. {"rxd_wr_cnt"},
  220. {"txf_rd_cnt"},
  221. {"rxf_wr_cnt"},
  222. {"rmac_ttl_1519_4095_frms"},
  223. {"rmac_ttl_4096_8191_frms"},
  224. {"rmac_ttl_8192_max_frms"},
  225. {"rmac_ttl_gt_max_frms"},
  226. {"rmac_osized_alt_frms"},
  227. {"rmac_jabber_alt_frms"},
  228. {"rmac_gt_max_alt_frms"},
  229. {"rmac_vlan_frms"},
  230. {"rmac_len_discard"},
  231. {"rmac_fcs_discard"},
  232. {"rmac_pf_discard"},
  233. {"rmac_da_discard"},
  234. {"rmac_red_discard"},
  235. {"rmac_rts_discard"},
  236. {"rmac_ingm_full_discard"},
  237. {"link_fault_cnt"},
  238. {"\n DRIVER STATISTICS"},
  239. {"single_bit_ecc_errs"},
  240. {"double_bit_ecc_errs"},
  241. {"parity_err_cnt"},
  242. {"serious_err_cnt"},
  243. {"soft_reset_cnt"},
  244. {"fifo_full_cnt"},
  245. {"ring_full_cnt"},
  246. ("alarm_transceiver_temp_high"),
  247. ("alarm_transceiver_temp_low"),
  248. ("alarm_laser_bias_current_high"),
  249. ("alarm_laser_bias_current_low"),
  250. ("alarm_laser_output_power_high"),
  251. ("alarm_laser_output_power_low"),
  252. ("warn_transceiver_temp_high"),
  253. ("warn_transceiver_temp_low"),
  254. ("warn_laser_bias_current_high"),
  255. ("warn_laser_bias_current_low"),
  256. ("warn_laser_output_power_high"),
  257. ("warn_laser_output_power_low"),
  258. ("lro_aggregated_pkts"),
  259. ("lro_flush_both_count"),
  260. ("lro_out_of_sequence_pkts"),
  261. ("lro_flush_due_to_max_pkts"),
  262. ("lro_avg_aggr_pkts"),
  263. };
  264. #define S2IO_STAT_LEN sizeof(ethtool_stats_keys)/ ETH_GSTRING_LEN
  265. #define S2IO_STAT_STRINGS_LEN S2IO_STAT_LEN * ETH_GSTRING_LEN
  266. #define S2IO_TEST_LEN sizeof(s2io_gstrings) / ETH_GSTRING_LEN
  267. #define S2IO_STRINGS_LEN S2IO_TEST_LEN * ETH_GSTRING_LEN
  268. #define S2IO_TIMER_CONF(timer, handle, arg, exp) \
  269. init_timer(&timer); \
  270. timer.function = handle; \
  271. timer.data = (unsigned long) arg; \
  272. mod_timer(&timer, (jiffies + exp)) \
  273. /* Add the vlan */
  274. static void s2io_vlan_rx_register(struct net_device *dev,
  275. struct vlan_group *grp)
  276. {
  277. struct s2io_nic *nic = dev->priv;
  278. unsigned long flags;
  279. spin_lock_irqsave(&nic->tx_lock, flags);
  280. nic->vlgrp = grp;
  281. spin_unlock_irqrestore(&nic->tx_lock, flags);
  282. }
  283. /* A flag indicating whether 'RX_PA_CFG_STRIP_VLAN_TAG' bit is set or not */
  284. int vlan_strip_flag;
  285. /* Unregister the vlan */
  286. static void s2io_vlan_rx_kill_vid(struct net_device *dev, unsigned long vid)
  287. {
  288. struct s2io_nic *nic = dev->priv;
  289. unsigned long flags;
  290. spin_lock_irqsave(&nic->tx_lock, flags);
  291. if (nic->vlgrp)
  292. nic->vlgrp->vlan_devices[vid] = NULL;
  293. spin_unlock_irqrestore(&nic->tx_lock, flags);
  294. }
  295. /*
  296. * Constants to be programmed into the Xena's registers, to configure
  297. * the XAUI.
  298. */
  299. #define END_SIGN 0x0
  300. static const u64 herc_act_dtx_cfg[] = {
  301. /* Set address */
  302. 0x8000051536750000ULL, 0x80000515367500E0ULL,
  303. /* Write data */
  304. 0x8000051536750004ULL, 0x80000515367500E4ULL,
  305. /* Set address */
  306. 0x80010515003F0000ULL, 0x80010515003F00E0ULL,
  307. /* Write data */
  308. 0x80010515003F0004ULL, 0x80010515003F00E4ULL,
  309. /* Set address */
  310. 0x801205150D440000ULL, 0x801205150D4400E0ULL,
  311. /* Write data */
  312. 0x801205150D440004ULL, 0x801205150D4400E4ULL,
  313. /* Set address */
  314. 0x80020515F2100000ULL, 0x80020515F21000E0ULL,
  315. /* Write data */
  316. 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
  317. /* Done */
  318. END_SIGN
  319. };
  320. static const u64 xena_dtx_cfg[] = {
  321. /* Set address */
  322. 0x8000051500000000ULL, 0x80000515000000E0ULL,
  323. /* Write data */
  324. 0x80000515D9350004ULL, 0x80000515D93500E4ULL,
  325. /* Set address */
  326. 0x8001051500000000ULL, 0x80010515000000E0ULL,
  327. /* Write data */
  328. 0x80010515001E0004ULL, 0x80010515001E00E4ULL,
  329. /* Set address */
  330. 0x8002051500000000ULL, 0x80020515000000E0ULL,
  331. /* Write data */
  332. 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
  333. END_SIGN
  334. };
  335. /*
  336. * Constants for Fixing the MacAddress problem seen mostly on
  337. * Alpha machines.
  338. */
  339. static const u64 fix_mac[] = {
  340. 0x0060000000000000ULL, 0x0060600000000000ULL,
  341. 0x0040600000000000ULL, 0x0000600000000000ULL,
  342. 0x0020600000000000ULL, 0x0060600000000000ULL,
  343. 0x0020600000000000ULL, 0x0060600000000000ULL,
  344. 0x0020600000000000ULL, 0x0060600000000000ULL,
  345. 0x0020600000000000ULL, 0x0060600000000000ULL,
  346. 0x0020600000000000ULL, 0x0060600000000000ULL,
  347. 0x0020600000000000ULL, 0x0060600000000000ULL,
  348. 0x0020600000000000ULL, 0x0060600000000000ULL,
  349. 0x0020600000000000ULL, 0x0060600000000000ULL,
  350. 0x0020600000000000ULL, 0x0060600000000000ULL,
  351. 0x0020600000000000ULL, 0x0060600000000000ULL,
  352. 0x0020600000000000ULL, 0x0000600000000000ULL,
  353. 0x0040600000000000ULL, 0x0060600000000000ULL,
  354. END_SIGN
  355. };
  356. MODULE_AUTHOR("Raghavendra Koushik <raghavendra.koushik@neterion.com>");
  357. MODULE_LICENSE("GPL");
  358. MODULE_VERSION(DRV_VERSION);
  359. /* Module Loadable parameters. */
  360. S2IO_PARM_INT(tx_fifo_num, 1);
  361. S2IO_PARM_INT(rx_ring_num, 1);
  362. S2IO_PARM_INT(rx_ring_mode, 1);
  363. S2IO_PARM_INT(use_continuous_tx_intrs, 1);
  364. S2IO_PARM_INT(rmac_pause_time, 0x100);
  365. S2IO_PARM_INT(mc_pause_threshold_q0q3, 187);
  366. S2IO_PARM_INT(mc_pause_threshold_q4q7, 187);
  367. S2IO_PARM_INT(shared_splits, 0);
  368. S2IO_PARM_INT(tmac_util_period, 5);
  369. S2IO_PARM_INT(rmac_util_period, 5);
  370. S2IO_PARM_INT(bimodal, 0);
  371. S2IO_PARM_INT(l3l4hdr_size, 128);
  372. /* Frequency of Rx desc syncs expressed as power of 2 */
  373. S2IO_PARM_INT(rxsync_frequency, 3);
  374. /* Interrupt type. Values can be 0(INTA), 1(MSI), 2(MSI_X) */
  375. S2IO_PARM_INT(intr_type, 0);
  376. /* Large receive offload feature */
  377. S2IO_PARM_INT(lro, 0);
  378. /* Max pkts to be aggregated by LRO at one time. If not specified,
  379. * aggregation happens until we hit max IP pkt size(64K)
  380. */
  381. S2IO_PARM_INT(lro_max_pkts, 0xFFFF);
  382. S2IO_PARM_INT(indicate_max_pkts, 0);
  383. S2IO_PARM_INT(napi, 1);
  384. S2IO_PARM_INT(ufo, 0);
  385. S2IO_PARM_INT(vlan_tag_strip, NO_STRIP_IN_PROMISC);
  386. static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
  387. {DEFAULT_FIFO_0_LEN, [1 ...(MAX_TX_FIFOS - 1)] = DEFAULT_FIFO_1_7_LEN};
  388. static unsigned int rx_ring_sz[MAX_RX_RINGS] =
  389. {[0 ...(MAX_RX_RINGS - 1)] = SMALL_BLK_CNT};
  390. static unsigned int rts_frm_len[MAX_RX_RINGS] =
  391. {[0 ...(MAX_RX_RINGS - 1)] = 0 };
  392. module_param_array(tx_fifo_len, uint, NULL, 0);
  393. module_param_array(rx_ring_sz, uint, NULL, 0);
  394. module_param_array(rts_frm_len, uint, NULL, 0);
  395. /*
  396. * S2IO device table.
  397. * This table lists all the devices that this driver supports.
  398. */
  399. static struct pci_device_id s2io_tbl[] __devinitdata = {
  400. {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
  401. PCI_ANY_ID, PCI_ANY_ID},
  402. {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
  403. PCI_ANY_ID, PCI_ANY_ID},
  404. {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN,
  405. PCI_ANY_ID, PCI_ANY_ID},
  406. {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI,
  407. PCI_ANY_ID, PCI_ANY_ID},
  408. {0,}
  409. };
  410. MODULE_DEVICE_TABLE(pci, s2io_tbl);
  411. static struct pci_driver s2io_driver = {
  412. .name = "S2IO",
  413. .id_table = s2io_tbl,
  414. .probe = s2io_init_nic,
  415. .remove = __devexit_p(s2io_rem_nic),
  416. };
  417. /* A simplifier macro used both by init and free shared_mem Fns(). */
  418. #define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
  419. /**
  420. * init_shared_mem - Allocation and Initialization of Memory
  421. * @nic: Device private variable.
  422. * Description: The function allocates all the memory areas shared
  423. * between the NIC and the driver. This includes Tx descriptors,
  424. * Rx descriptors and the statistics block.
  425. */
  426. static int init_shared_mem(struct s2io_nic *nic)
  427. {
  428. u32 size;
  429. void *tmp_v_addr, *tmp_v_addr_next;
  430. dma_addr_t tmp_p_addr, tmp_p_addr_next;
  431. struct RxD_block *pre_rxd_blk = NULL;
  432. int i, j, blk_cnt;
  433. int lst_size, lst_per_page;
  434. struct net_device *dev = nic->dev;
  435. unsigned long tmp;
  436. struct buffAdd *ba;
  437. struct mac_info *mac_control;
  438. struct config_param *config;
  439. mac_control = &nic->mac_control;
  440. config = &nic->config;
  441. /* Allocation and initialization of TXDLs in FIOFs */
  442. size = 0;
  443. for (i = 0; i < config->tx_fifo_num; i++) {
  444. size += config->tx_cfg[i].fifo_len;
  445. }
  446. if (size > MAX_AVAILABLE_TXDS) {
  447. DBG_PRINT(ERR_DBG, "s2io: Requested TxDs too high, ");
  448. DBG_PRINT(ERR_DBG, "Requested: %d, max supported: 8192\n", size);
  449. return -EINVAL;
  450. }
  451. lst_size = (sizeof(struct TxD) * config->max_txds);
  452. lst_per_page = PAGE_SIZE / lst_size;
  453. for (i = 0; i < config->tx_fifo_num; i++) {
  454. int fifo_len = config->tx_cfg[i].fifo_len;
  455. int list_holder_size = fifo_len * sizeof(struct list_info_hold);
  456. mac_control->fifos[i].list_info = kmalloc(list_holder_size,
  457. GFP_KERNEL);
  458. if (!mac_control->fifos[i].list_info) {
  459. DBG_PRINT(ERR_DBG,
  460. "Malloc failed for list_info\n");
  461. return -ENOMEM;
  462. }
  463. memset(mac_control->fifos[i].list_info, 0, list_holder_size);
  464. }
  465. for (i = 0; i < config->tx_fifo_num; i++) {
  466. int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
  467. lst_per_page);
  468. mac_control->fifos[i].tx_curr_put_info.offset = 0;
  469. mac_control->fifos[i].tx_curr_put_info.fifo_len =
  470. config->tx_cfg[i].fifo_len - 1;
  471. mac_control->fifos[i].tx_curr_get_info.offset = 0;
  472. mac_control->fifos[i].tx_curr_get_info.fifo_len =
  473. config->tx_cfg[i].fifo_len - 1;
  474. mac_control->fifos[i].fifo_no = i;
  475. mac_control->fifos[i].nic = nic;
  476. mac_control->fifos[i].max_txds = MAX_SKB_FRAGS + 2;
  477. for (j = 0; j < page_num; j++) {
  478. int k = 0;
  479. dma_addr_t tmp_p;
  480. void *tmp_v;
  481. tmp_v = pci_alloc_consistent(nic->pdev,
  482. PAGE_SIZE, &tmp_p);
  483. if (!tmp_v) {
  484. DBG_PRINT(ERR_DBG,
  485. "pci_alloc_consistent ");
  486. DBG_PRINT(ERR_DBG, "failed for TxDL\n");
  487. return -ENOMEM;
  488. }
  489. /* If we got a zero DMA address(can happen on
  490. * certain platforms like PPC), reallocate.
  491. * Store virtual address of page we don't want,
  492. * to be freed later.
  493. */
  494. if (!tmp_p) {
  495. mac_control->zerodma_virt_addr = tmp_v;
  496. DBG_PRINT(INIT_DBG,
  497. "%s: Zero DMA address for TxDL. ", dev->name);
  498. DBG_PRINT(INIT_DBG,
  499. "Virtual address %p\n", tmp_v);
  500. tmp_v = pci_alloc_consistent(nic->pdev,
  501. PAGE_SIZE, &tmp_p);
  502. if (!tmp_v) {
  503. DBG_PRINT(ERR_DBG,
  504. "pci_alloc_consistent ");
  505. DBG_PRINT(ERR_DBG, "failed for TxDL\n");
  506. return -ENOMEM;
  507. }
  508. }
  509. while (k < lst_per_page) {
  510. int l = (j * lst_per_page) + k;
  511. if (l == config->tx_cfg[i].fifo_len)
  512. break;
  513. mac_control->fifos[i].list_info[l].list_virt_addr =
  514. tmp_v + (k * lst_size);
  515. mac_control->fifos[i].list_info[l].list_phy_addr =
  516. tmp_p + (k * lst_size);
  517. k++;
  518. }
  519. }
  520. }
  521. nic->ufo_in_band_v = kcalloc(size, sizeof(u64), GFP_KERNEL);
  522. if (!nic->ufo_in_band_v)
  523. return -ENOMEM;
  524. /* Allocation and initialization of RXDs in Rings */
  525. size = 0;
  526. for (i = 0; i < config->rx_ring_num; i++) {
  527. if (config->rx_cfg[i].num_rxd %
  528. (rxd_count[nic->rxd_mode] + 1)) {
  529. DBG_PRINT(ERR_DBG, "%s: RxD count of ", dev->name);
  530. DBG_PRINT(ERR_DBG, "Ring%d is not a multiple of ",
  531. i);
  532. DBG_PRINT(ERR_DBG, "RxDs per Block");
  533. return FAILURE;
  534. }
  535. size += config->rx_cfg[i].num_rxd;
  536. mac_control->rings[i].block_count =
  537. config->rx_cfg[i].num_rxd /
  538. (rxd_count[nic->rxd_mode] + 1 );
  539. mac_control->rings[i].pkt_cnt = config->rx_cfg[i].num_rxd -
  540. mac_control->rings[i].block_count;
  541. }
  542. if (nic->rxd_mode == RXD_MODE_1)
  543. size = (size * (sizeof(struct RxD1)));
  544. else
  545. size = (size * (sizeof(struct RxD3)));
  546. for (i = 0; i < config->rx_ring_num; i++) {
  547. mac_control->rings[i].rx_curr_get_info.block_index = 0;
  548. mac_control->rings[i].rx_curr_get_info.offset = 0;
  549. mac_control->rings[i].rx_curr_get_info.ring_len =
  550. config->rx_cfg[i].num_rxd - 1;
  551. mac_control->rings[i].rx_curr_put_info.block_index = 0;
  552. mac_control->rings[i].rx_curr_put_info.offset = 0;
  553. mac_control->rings[i].rx_curr_put_info.ring_len =
  554. config->rx_cfg[i].num_rxd - 1;
  555. mac_control->rings[i].nic = nic;
  556. mac_control->rings[i].ring_no = i;
  557. blk_cnt = config->rx_cfg[i].num_rxd /
  558. (rxd_count[nic->rxd_mode] + 1);
  559. /* Allocating all the Rx blocks */
  560. for (j = 0; j < blk_cnt; j++) {
  561. struct rx_block_info *rx_blocks;
  562. int l;
  563. rx_blocks = &mac_control->rings[i].rx_blocks[j];
  564. size = SIZE_OF_BLOCK; //size is always page size
  565. tmp_v_addr = pci_alloc_consistent(nic->pdev, size,
  566. &tmp_p_addr);
  567. if (tmp_v_addr == NULL) {
  568. /*
  569. * In case of failure, free_shared_mem()
  570. * is called, which should free any
  571. * memory that was alloced till the
  572. * failure happened.
  573. */
  574. rx_blocks->block_virt_addr = tmp_v_addr;
  575. return -ENOMEM;
  576. }
  577. memset(tmp_v_addr, 0, size);
  578. rx_blocks->block_virt_addr = tmp_v_addr;
  579. rx_blocks->block_dma_addr = tmp_p_addr;
  580. rx_blocks->rxds = kmalloc(sizeof(struct rxd_info)*
  581. rxd_count[nic->rxd_mode],
  582. GFP_KERNEL);
  583. if (!rx_blocks->rxds)
  584. return -ENOMEM;
  585. for (l=0; l<rxd_count[nic->rxd_mode];l++) {
  586. rx_blocks->rxds[l].virt_addr =
  587. rx_blocks->block_virt_addr +
  588. (rxd_size[nic->rxd_mode] * l);
  589. rx_blocks->rxds[l].dma_addr =
  590. rx_blocks->block_dma_addr +
  591. (rxd_size[nic->rxd_mode] * l);
  592. }
  593. }
  594. /* Interlinking all Rx Blocks */
  595. for (j = 0; j < blk_cnt; j++) {
  596. tmp_v_addr =
  597. mac_control->rings[i].rx_blocks[j].block_virt_addr;
  598. tmp_v_addr_next =
  599. mac_control->rings[i].rx_blocks[(j + 1) %
  600. blk_cnt].block_virt_addr;
  601. tmp_p_addr =
  602. mac_control->rings[i].rx_blocks[j].block_dma_addr;
  603. tmp_p_addr_next =
  604. mac_control->rings[i].rx_blocks[(j + 1) %
  605. blk_cnt].block_dma_addr;
  606. pre_rxd_blk = (struct RxD_block *) tmp_v_addr;
  607. pre_rxd_blk->reserved_2_pNext_RxD_block =
  608. (unsigned long) tmp_v_addr_next;
  609. pre_rxd_blk->pNext_RxD_Blk_physical =
  610. (u64) tmp_p_addr_next;
  611. }
  612. }
  613. if (nic->rxd_mode >= RXD_MODE_3A) {
  614. /*
  615. * Allocation of Storages for buffer addresses in 2BUFF mode
  616. * and the buffers as well.
  617. */
  618. for (i = 0; i < config->rx_ring_num; i++) {
  619. blk_cnt = config->rx_cfg[i].num_rxd /
  620. (rxd_count[nic->rxd_mode]+ 1);
  621. mac_control->rings[i].ba =
  622. kmalloc((sizeof(struct buffAdd *) * blk_cnt),
  623. GFP_KERNEL);
  624. if (!mac_control->rings[i].ba)
  625. return -ENOMEM;
  626. for (j = 0; j < blk_cnt; j++) {
  627. int k = 0;
  628. mac_control->rings[i].ba[j] =
  629. kmalloc((sizeof(struct buffAdd) *
  630. (rxd_count[nic->rxd_mode] + 1)),
  631. GFP_KERNEL);
  632. if (!mac_control->rings[i].ba[j])
  633. return -ENOMEM;
  634. while (k != rxd_count[nic->rxd_mode]) {
  635. ba = &mac_control->rings[i].ba[j][k];
  636. ba->ba_0_org = (void *) kmalloc
  637. (BUF0_LEN + ALIGN_SIZE, GFP_KERNEL);
  638. if (!ba->ba_0_org)
  639. return -ENOMEM;
  640. tmp = (unsigned long)ba->ba_0_org;
  641. tmp += ALIGN_SIZE;
  642. tmp &= ~((unsigned long) ALIGN_SIZE);
  643. ba->ba_0 = (void *) tmp;
  644. ba->ba_1_org = (void *) kmalloc
  645. (BUF1_LEN + ALIGN_SIZE, GFP_KERNEL);
  646. if (!ba->ba_1_org)
  647. return -ENOMEM;
  648. tmp = (unsigned long) ba->ba_1_org;
  649. tmp += ALIGN_SIZE;
  650. tmp &= ~((unsigned long) ALIGN_SIZE);
  651. ba->ba_1 = (void *) tmp;
  652. k++;
  653. }
  654. }
  655. }
  656. }
  657. /* Allocation and initialization of Statistics block */
  658. size = sizeof(struct stat_block);
  659. mac_control->stats_mem = pci_alloc_consistent
  660. (nic->pdev, size, &mac_control->stats_mem_phy);
  661. if (!mac_control->stats_mem) {
  662. /*
  663. * In case of failure, free_shared_mem() is called, which
  664. * should free any memory that was alloced till the
  665. * failure happened.
  666. */
  667. return -ENOMEM;
  668. }
  669. mac_control->stats_mem_sz = size;
  670. tmp_v_addr = mac_control->stats_mem;
  671. mac_control->stats_info = (struct stat_block *) tmp_v_addr;
  672. memset(tmp_v_addr, 0, size);
  673. DBG_PRINT(INIT_DBG, "%s:Ring Mem PHY: 0x%llx\n", dev->name,
  674. (unsigned long long) tmp_p_addr);
  675. return SUCCESS;
  676. }
  677. /**
  678. * free_shared_mem - Free the allocated Memory
  679. * @nic: Device private variable.
  680. * Description: This function is to free all memory locations allocated by
  681. * the init_shared_mem() function and return it to the kernel.
  682. */
  683. static void free_shared_mem(struct s2io_nic *nic)
  684. {
  685. int i, j, blk_cnt, size;
  686. void *tmp_v_addr;
  687. dma_addr_t tmp_p_addr;
  688. struct mac_info *mac_control;
  689. struct config_param *config;
  690. int lst_size, lst_per_page;
  691. struct net_device *dev = nic->dev;
  692. if (!nic)
  693. return;
  694. mac_control = &nic->mac_control;
  695. config = &nic->config;
  696. lst_size = (sizeof(struct TxD) * config->max_txds);
  697. lst_per_page = PAGE_SIZE / lst_size;
  698. for (i = 0; i < config->tx_fifo_num; i++) {
  699. int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
  700. lst_per_page);
  701. for (j = 0; j < page_num; j++) {
  702. int mem_blks = (j * lst_per_page);
  703. if (!mac_control->fifos[i].list_info)
  704. return;
  705. if (!mac_control->fifos[i].list_info[mem_blks].
  706. list_virt_addr)
  707. break;
  708. pci_free_consistent(nic->pdev, PAGE_SIZE,
  709. mac_control->fifos[i].
  710. list_info[mem_blks].
  711. list_virt_addr,
  712. mac_control->fifos[i].
  713. list_info[mem_blks].
  714. list_phy_addr);
  715. }
  716. /* If we got a zero DMA address during allocation,
  717. * free the page now
  718. */
  719. if (mac_control->zerodma_virt_addr) {
  720. pci_free_consistent(nic->pdev, PAGE_SIZE,
  721. mac_control->zerodma_virt_addr,
  722. (dma_addr_t)0);
  723. DBG_PRINT(INIT_DBG,
  724. "%s: Freeing TxDL with zero DMA addr. ",
  725. dev->name);
  726. DBG_PRINT(INIT_DBG, "Virtual address %p\n",
  727. mac_control->zerodma_virt_addr);
  728. }
  729. kfree(mac_control->fifos[i].list_info);
  730. }
  731. size = SIZE_OF_BLOCK;
  732. for (i = 0; i < config->rx_ring_num; i++) {
  733. blk_cnt = mac_control->rings[i].block_count;
  734. for (j = 0; j < blk_cnt; j++) {
  735. tmp_v_addr = mac_control->rings[i].rx_blocks[j].
  736. block_virt_addr;
  737. tmp_p_addr = mac_control->rings[i].rx_blocks[j].
  738. block_dma_addr;
  739. if (tmp_v_addr == NULL)
  740. break;
  741. pci_free_consistent(nic->pdev, size,
  742. tmp_v_addr, tmp_p_addr);
  743. kfree(mac_control->rings[i].rx_blocks[j].rxds);
  744. }
  745. }
  746. if (nic->rxd_mode >= RXD_MODE_3A) {
  747. /* Freeing buffer storage addresses in 2BUFF mode. */
  748. for (i = 0; i < config->rx_ring_num; i++) {
  749. blk_cnt = config->rx_cfg[i].num_rxd /
  750. (rxd_count[nic->rxd_mode] + 1);
  751. for (j = 0; j < blk_cnt; j++) {
  752. int k = 0;
  753. if (!mac_control->rings[i].ba[j])
  754. continue;
  755. while (k != rxd_count[nic->rxd_mode]) {
  756. struct buffAdd *ba =
  757. &mac_control->rings[i].ba[j][k];
  758. kfree(ba->ba_0_org);
  759. kfree(ba->ba_1_org);
  760. k++;
  761. }
  762. kfree(mac_control->rings[i].ba[j]);
  763. }
  764. kfree(mac_control->rings[i].ba);
  765. }
  766. }
  767. if (mac_control->stats_mem) {
  768. pci_free_consistent(nic->pdev,
  769. mac_control->stats_mem_sz,
  770. mac_control->stats_mem,
  771. mac_control->stats_mem_phy);
  772. }
  773. if (nic->ufo_in_band_v)
  774. kfree(nic->ufo_in_band_v);
  775. }
  776. /**
  777. * s2io_verify_pci_mode -
  778. */
  779. static int s2io_verify_pci_mode(struct s2io_nic *nic)
  780. {
  781. struct XENA_dev_config __iomem *bar0 = nic->bar0;
  782. register u64 val64 = 0;
  783. int mode;
  784. val64 = readq(&bar0->pci_mode);
  785. mode = (u8)GET_PCI_MODE(val64);
  786. if ( val64 & PCI_MODE_UNKNOWN_MODE)
  787. return -1; /* Unknown PCI mode */
  788. return mode;
  789. }
  790. #define NEC_VENID 0x1033
  791. #define NEC_DEVID 0x0125
  792. static int s2io_on_nec_bridge(struct pci_dev *s2io_pdev)
  793. {
  794. struct pci_dev *tdev = NULL;
  795. while ((tdev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, tdev)) != NULL) {
  796. if (tdev->vendor == NEC_VENID && tdev->device == NEC_DEVID) {
  797. if (tdev->bus == s2io_pdev->bus->parent)
  798. pci_dev_put(tdev);
  799. return 1;
  800. }
  801. }
  802. return 0;
  803. }
  804. static int bus_speed[8] = {33, 133, 133, 200, 266, 133, 200, 266};
  805. /**
  806. * s2io_print_pci_mode -
  807. */
  808. static int s2io_print_pci_mode(struct s2io_nic *nic)
  809. {
  810. struct XENA_dev_config __iomem *bar0 = nic->bar0;
  811. register u64 val64 = 0;
  812. int mode;
  813. struct config_param *config = &nic->config;
  814. val64 = readq(&bar0->pci_mode);
  815. mode = (u8)GET_PCI_MODE(val64);
  816. if ( val64 & PCI_MODE_UNKNOWN_MODE)
  817. return -1; /* Unknown PCI mode */
  818. config->bus_speed = bus_speed[mode];
  819. if (s2io_on_nec_bridge(nic->pdev)) {
  820. DBG_PRINT(ERR_DBG, "%s: Device is on PCI-E bus\n",
  821. nic->dev->name);
  822. return mode;
  823. }
  824. if (val64 & PCI_MODE_32_BITS) {
  825. DBG_PRINT(ERR_DBG, "%s: Device is on 32 bit ", nic->dev->name);
  826. } else {
  827. DBG_PRINT(ERR_DBG, "%s: Device is on 64 bit ", nic->dev->name);
  828. }
  829. switch(mode) {
  830. case PCI_MODE_PCI_33:
  831. DBG_PRINT(ERR_DBG, "33MHz PCI bus\n");
  832. break;
  833. case PCI_MODE_PCI_66:
  834. DBG_PRINT(ERR_DBG, "66MHz PCI bus\n");
  835. break;
  836. case PCI_MODE_PCIX_M1_66:
  837. DBG_PRINT(ERR_DBG, "66MHz PCIX(M1) bus\n");
  838. break;
  839. case PCI_MODE_PCIX_M1_100:
  840. DBG_PRINT(ERR_DBG, "100MHz PCIX(M1) bus\n");
  841. break;
  842. case PCI_MODE_PCIX_M1_133:
  843. DBG_PRINT(ERR_DBG, "133MHz PCIX(M1) bus\n");
  844. break;
  845. case PCI_MODE_PCIX_M2_66:
  846. DBG_PRINT(ERR_DBG, "133MHz PCIX(M2) bus\n");
  847. break;
  848. case PCI_MODE_PCIX_M2_100:
  849. DBG_PRINT(ERR_DBG, "200MHz PCIX(M2) bus\n");
  850. break;
  851. case PCI_MODE_PCIX_M2_133:
  852. DBG_PRINT(ERR_DBG, "266MHz PCIX(M2) bus\n");
  853. break;
  854. default:
  855. return -1; /* Unsupported bus speed */
  856. }
  857. return mode;
  858. }
  859. /**
  860. * init_nic - Initialization of hardware
  861. * @nic: device peivate variable
  862. * Description: The function sequentially configures every block
  863. * of the H/W from their reset values.
  864. * Return Value: SUCCESS on success and
  865. * '-1' on failure (endian settings incorrect).
  866. */
  867. static int init_nic(struct s2io_nic *nic)
  868. {
  869. struct XENA_dev_config __iomem *bar0 = nic->bar0;
  870. struct net_device *dev = nic->dev;
  871. register u64 val64 = 0;
  872. void __iomem *add;
  873. u32 time;
  874. int i, j;
  875. struct mac_info *mac_control;
  876. struct config_param *config;
  877. int dtx_cnt = 0;
  878. unsigned long long mem_share;
  879. int mem_size;
  880. mac_control = &nic->mac_control;
  881. config = &nic->config;
  882. /* to set the swapper controle on the card */
  883. if(s2io_set_swapper(nic)) {
  884. DBG_PRINT(ERR_DBG,"ERROR: Setting Swapper failed\n");
  885. return -1;
  886. }
  887. /*
  888. * Herc requires EOI to be removed from reset before XGXS, so..
  889. */
  890. if (nic->device_type & XFRAME_II_DEVICE) {
  891. val64 = 0xA500000000ULL;
  892. writeq(val64, &bar0->sw_reset);
  893. msleep(500);
  894. val64 = readq(&bar0->sw_reset);
  895. }
  896. /* Remove XGXS from reset state */
  897. val64 = 0;
  898. writeq(val64, &bar0->sw_reset);
  899. msleep(500);
  900. val64 = readq(&bar0->sw_reset);
  901. /* Enable Receiving broadcasts */
  902. add = &bar0->mac_cfg;
  903. val64 = readq(&bar0->mac_cfg);
  904. val64 |= MAC_RMAC_BCAST_ENABLE;
  905. writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
  906. writel((u32) val64, add);
  907. writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
  908. writel((u32) (val64 >> 32), (add + 4));
  909. /* Read registers in all blocks */
  910. val64 = readq(&bar0->mac_int_mask);
  911. val64 = readq(&bar0->mc_int_mask);
  912. val64 = readq(&bar0->xgxs_int_mask);
  913. /* Set MTU */
  914. val64 = dev->mtu;
  915. writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
  916. if (nic->device_type & XFRAME_II_DEVICE) {
  917. while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
  918. SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
  919. &bar0->dtx_control, UF);
  920. if (dtx_cnt & 0x1)
  921. msleep(1); /* Necessary!! */
  922. dtx_cnt++;
  923. }
  924. } else {
  925. while (xena_dtx_cfg[dtx_cnt] != END_SIGN) {
  926. SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
  927. &bar0->dtx_control, UF);
  928. val64 = readq(&bar0->dtx_control);
  929. dtx_cnt++;
  930. }
  931. }
  932. /* Tx DMA Initialization */
  933. val64 = 0;
  934. writeq(val64, &bar0->tx_fifo_partition_0);
  935. writeq(val64, &bar0->tx_fifo_partition_1);
  936. writeq(val64, &bar0->tx_fifo_partition_2);
  937. writeq(val64, &bar0->tx_fifo_partition_3);
  938. for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
  939. val64 |=
  940. vBIT(config->tx_cfg[i].fifo_len - 1, ((i * 32) + 19),
  941. 13) | vBIT(config->tx_cfg[i].fifo_priority,
  942. ((i * 32) + 5), 3);
  943. if (i == (config->tx_fifo_num - 1)) {
  944. if (i % 2 == 0)
  945. i++;
  946. }
  947. switch (i) {
  948. case 1:
  949. writeq(val64, &bar0->tx_fifo_partition_0);
  950. val64 = 0;
  951. break;
  952. case 3:
  953. writeq(val64, &bar0->tx_fifo_partition_1);
  954. val64 = 0;
  955. break;
  956. case 5:
  957. writeq(val64, &bar0->tx_fifo_partition_2);
  958. val64 = 0;
  959. break;
  960. case 7:
  961. writeq(val64, &bar0->tx_fifo_partition_3);
  962. break;
  963. }
  964. }
  965. /*
  966. * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
  967. * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
  968. */
  969. if ((nic->device_type == XFRAME_I_DEVICE) &&
  970. (get_xena_rev_id(nic->pdev) < 4))
  971. writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
  972. val64 = readq(&bar0->tx_fifo_partition_0);
  973. DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
  974. &bar0->tx_fifo_partition_0, (unsigned long long) val64);
  975. /*
  976. * Initialization of Tx_PA_CONFIG register to ignore packet
  977. * integrity checking.
  978. */
  979. val64 = readq(&bar0->tx_pa_cfg);
  980. val64 |= TX_PA_CFG_IGNORE_FRM_ERR | TX_PA_CFG_IGNORE_SNAP_OUI |
  981. TX_PA_CFG_IGNORE_LLC_CTRL | TX_PA_CFG_IGNORE_L2_ERR;
  982. writeq(val64, &bar0->tx_pa_cfg);
  983. /* Rx DMA intialization. */
  984. val64 = 0;
  985. for (i = 0; i < config->rx_ring_num; i++) {
  986. val64 |=
  987. vBIT(config->rx_cfg[i].ring_priority, (5 + (i * 8)),
  988. 3);
  989. }
  990. writeq(val64, &bar0->rx_queue_priority);
  991. /*
  992. * Allocating equal share of memory to all the
  993. * configured Rings.
  994. */
  995. val64 = 0;
  996. if (nic->device_type & XFRAME_II_DEVICE)
  997. mem_size = 32;
  998. else
  999. mem_size = 64;
  1000. for (i = 0; i < config->rx_ring_num; i++) {
  1001. switch (i) {
  1002. case 0:
  1003. mem_share = (mem_size / config->rx_ring_num +
  1004. mem_size % config->rx_ring_num);
  1005. val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
  1006. continue;
  1007. case 1:
  1008. mem_share = (mem_size / config->rx_ring_num);
  1009. val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
  1010. continue;
  1011. case 2:
  1012. mem_share = (mem_size / config->rx_ring_num);
  1013. val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
  1014. continue;
  1015. case 3:
  1016. mem_share = (mem_size / config->rx_ring_num);
  1017. val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
  1018. continue;
  1019. case 4:
  1020. mem_share = (mem_size / config->rx_ring_num);
  1021. val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
  1022. continue;
  1023. case 5:
  1024. mem_share = (mem_size / config->rx_ring_num);
  1025. val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
  1026. continue;
  1027. case 6:
  1028. mem_share = (mem_size / config->rx_ring_num);
  1029. val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
  1030. continue;
  1031. case 7:
  1032. mem_share = (mem_size / config->rx_ring_num);
  1033. val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
  1034. continue;
  1035. }
  1036. }
  1037. writeq(val64, &bar0->rx_queue_cfg);
  1038. /*
  1039. * Filling Tx round robin registers
  1040. * as per the number of FIFOs
  1041. */
  1042. switch (config->tx_fifo_num) {
  1043. case 1:
  1044. val64 = 0x0000000000000000ULL;
  1045. writeq(val64, &bar0->tx_w_round_robin_0);
  1046. writeq(val64, &bar0->tx_w_round_robin_1);
  1047. writeq(val64, &bar0->tx_w_round_robin_2);
  1048. writeq(val64, &bar0->tx_w_round_robin_3);
  1049. writeq(val64, &bar0->tx_w_round_robin_4);
  1050. break;
  1051. case 2:
  1052. val64 = 0x0000010000010000ULL;
  1053. writeq(val64, &bar0->tx_w_round_robin_0);
  1054. val64 = 0x0100000100000100ULL;
  1055. writeq(val64, &bar0->tx_w_round_robin_1);
  1056. val64 = 0x0001000001000001ULL;
  1057. writeq(val64, &bar0->tx_w_round_robin_2);
  1058. val64 = 0x0000010000010000ULL;
  1059. writeq(val64, &bar0->tx_w_round_robin_3);
  1060. val64 = 0x0100000000000000ULL;
  1061. writeq(val64, &bar0->tx_w_round_robin_4);
  1062. break;
  1063. case 3:
  1064. val64 = 0x0001000102000001ULL;
  1065. writeq(val64, &bar0->tx_w_round_robin_0);
  1066. val64 = 0x0001020000010001ULL;
  1067. writeq(val64, &bar0->tx_w_round_robin_1);
  1068. val64 = 0x0200000100010200ULL;
  1069. writeq(val64, &bar0->tx_w_round_robin_2);
  1070. val64 = 0x0001000102000001ULL;
  1071. writeq(val64, &bar0->tx_w_round_robin_3);
  1072. val64 = 0x0001020000000000ULL;
  1073. writeq(val64, &bar0->tx_w_round_robin_4);
  1074. break;
  1075. case 4:
  1076. val64 = 0x0001020300010200ULL;
  1077. writeq(val64, &bar0->tx_w_round_robin_0);
  1078. val64 = 0x0100000102030001ULL;
  1079. writeq(val64, &bar0->tx_w_round_robin_1);
  1080. val64 = 0x0200010000010203ULL;
  1081. writeq(val64, &bar0->tx_w_round_robin_2);
  1082. val64 = 0x0001020001000001ULL;
  1083. writeq(val64, &bar0->tx_w_round_robin_3);
  1084. val64 = 0x0203000100000000ULL;
  1085. writeq(val64, &bar0->tx_w_round_robin_4);
  1086. break;
  1087. case 5:
  1088. val64 = 0x0001000203000102ULL;
  1089. writeq(val64, &bar0->tx_w_round_robin_0);
  1090. val64 = 0x0001020001030004ULL;
  1091. writeq(val64, &bar0->tx_w_round_robin_1);
  1092. val64 = 0x0001000203000102ULL;
  1093. writeq(val64, &bar0->tx_w_round_robin_2);
  1094. val64 = 0x0001020001030004ULL;
  1095. writeq(val64, &bar0->tx_w_round_robin_3);
  1096. val64 = 0x0001000000000000ULL;
  1097. writeq(val64, &bar0->tx_w_round_robin_4);
  1098. break;
  1099. case 6:
  1100. val64 = 0x0001020304000102ULL;
  1101. writeq(val64, &bar0->tx_w_round_robin_0);
  1102. val64 = 0x0304050001020001ULL;
  1103. writeq(val64, &bar0->tx_w_round_robin_1);
  1104. val64 = 0x0203000100000102ULL;
  1105. writeq(val64, &bar0->tx_w_round_robin_2);
  1106. val64 = 0x0304000102030405ULL;
  1107. writeq(val64, &bar0->tx_w_round_robin_3);
  1108. val64 = 0x0001000200000000ULL;
  1109. writeq(val64, &bar0->tx_w_round_robin_4);
  1110. break;
  1111. case 7:
  1112. val64 = 0x0001020001020300ULL;
  1113. writeq(val64, &bar0->tx_w_round_robin_0);
  1114. val64 = 0x0102030400010203ULL;
  1115. writeq(val64, &bar0->tx_w_round_robin_1);
  1116. val64 = 0x0405060001020001ULL;
  1117. writeq(val64, &bar0->tx_w_round_robin_2);
  1118. val64 = 0x0304050000010200ULL;
  1119. writeq(val64, &bar0->tx_w_round_robin_3);
  1120. val64 = 0x0102030000000000ULL;
  1121. writeq(val64, &bar0->tx_w_round_robin_4);
  1122. break;
  1123. case 8:
  1124. val64 = 0x0001020300040105ULL;
  1125. writeq(val64, &bar0->tx_w_round_robin_0);
  1126. val64 = 0x0200030106000204ULL;
  1127. writeq(val64, &bar0->tx_w_round_robin_1);
  1128. val64 = 0x0103000502010007ULL;
  1129. writeq(val64, &bar0->tx_w_round_robin_2);
  1130. val64 = 0x0304010002060500ULL;
  1131. writeq(val64, &bar0->tx_w_round_robin_3);
  1132. val64 = 0x0103020400000000ULL;
  1133. writeq(val64, &bar0->tx_w_round_robin_4);
  1134. break;
  1135. }
  1136. /* Enable all configured Tx FIFO partitions */
  1137. val64 = readq(&bar0->tx_fifo_partition_0);
  1138. val64 |= (TX_FIFO_PARTITION_EN);
  1139. writeq(val64, &bar0->tx_fifo_partition_0);
  1140. /* Filling the Rx round robin registers as per the
  1141. * number of Rings and steering based on QoS.
  1142. */
  1143. switch (config->rx_ring_num) {
  1144. case 1:
  1145. val64 = 0x8080808080808080ULL;
  1146. writeq(val64, &bar0->rts_qos_steering);
  1147. break;
  1148. case 2:
  1149. val64 = 0x0000010000010000ULL;
  1150. writeq(val64, &bar0->rx_w_round_robin_0);
  1151. val64 = 0x0100000100000100ULL;
  1152. writeq(val64, &bar0->rx_w_round_robin_1);
  1153. val64 = 0x0001000001000001ULL;
  1154. writeq(val64, &bar0->rx_w_round_robin_2);
  1155. val64 = 0x0000010000010000ULL;
  1156. writeq(val64, &bar0->rx_w_round_robin_3);
  1157. val64 = 0x0100000000000000ULL;
  1158. writeq(val64, &bar0->rx_w_round_robin_4);
  1159. val64 = 0x8080808040404040ULL;
  1160. writeq(val64, &bar0->rts_qos_steering);
  1161. break;
  1162. case 3:
  1163. val64 = 0x0001000102000001ULL;
  1164. writeq(val64, &bar0->rx_w_round_robin_0);
  1165. val64 = 0x0001020000010001ULL;
  1166. writeq(val64, &bar0->rx_w_round_robin_1);
  1167. val64 = 0x0200000100010200ULL;
  1168. writeq(val64, &bar0->rx_w_round_robin_2);
  1169. val64 = 0x0001000102000001ULL;
  1170. writeq(val64, &bar0->rx_w_round_robin_3);
  1171. val64 = 0x0001020000000000ULL;
  1172. writeq(val64, &bar0->rx_w_round_robin_4);
  1173. val64 = 0x8080804040402020ULL;
  1174. writeq(val64, &bar0->rts_qos_steering);
  1175. break;
  1176. case 4:
  1177. val64 = 0x0001020300010200ULL;
  1178. writeq(val64, &bar0->rx_w_round_robin_0);
  1179. val64 = 0x0100000102030001ULL;
  1180. writeq(val64, &bar0->rx_w_round_robin_1);
  1181. val64 = 0x0200010000010203ULL;
  1182. writeq(val64, &bar0->rx_w_round_robin_2);
  1183. val64 = 0x0001020001000001ULL;
  1184. writeq(val64, &bar0->rx_w_round_robin_3);
  1185. val64 = 0x0203000100000000ULL;
  1186. writeq(val64, &bar0->rx_w_round_robin_4);
  1187. val64 = 0x8080404020201010ULL;
  1188. writeq(val64, &bar0->rts_qos_steering);
  1189. break;
  1190. case 5:
  1191. val64 = 0x0001000203000102ULL;
  1192. writeq(val64, &bar0->rx_w_round_robin_0);
  1193. val64 = 0x0001020001030004ULL;
  1194. writeq(val64, &bar0->rx_w_round_robin_1);
  1195. val64 = 0x0001000203000102ULL;
  1196. writeq(val64, &bar0->rx_w_round_robin_2);
  1197. val64 = 0x0001020001030004ULL;
  1198. writeq(val64, &bar0->rx_w_round_robin_3);
  1199. val64 = 0x0001000000000000ULL;
  1200. writeq(val64, &bar0->rx_w_round_robin_4);
  1201. val64 = 0x8080404020201008ULL;
  1202. writeq(val64, &bar0->rts_qos_steering);
  1203. break;
  1204. case 6:
  1205. val64 = 0x0001020304000102ULL;
  1206. writeq(val64, &bar0->rx_w_round_robin_0);
  1207. val64 = 0x0304050001020001ULL;
  1208. writeq(val64, &bar0->rx_w_round_robin_1);
  1209. val64 = 0x0203000100000102ULL;
  1210. writeq(val64, &bar0->rx_w_round_robin_2);
  1211. val64 = 0x0304000102030405ULL;
  1212. writeq(val64, &bar0->rx_w_round_robin_3);
  1213. val64 = 0x0001000200000000ULL;
  1214. writeq(val64, &bar0->rx_w_round_robin_4);
  1215. val64 = 0x8080404020100804ULL;
  1216. writeq(val64, &bar0->rts_qos_steering);
  1217. break;
  1218. case 7:
  1219. val64 = 0x0001020001020300ULL;
  1220. writeq(val64, &bar0->rx_w_round_robin_0);
  1221. val64 = 0x0102030400010203ULL;
  1222. writeq(val64, &bar0->rx_w_round_robin_1);
  1223. val64 = 0x0405060001020001ULL;
  1224. writeq(val64, &bar0->rx_w_round_robin_2);
  1225. val64 = 0x0304050000010200ULL;
  1226. writeq(val64, &bar0->rx_w_round_robin_3);
  1227. val64 = 0x0102030000000000ULL;
  1228. writeq(val64, &bar0->rx_w_round_robin_4);
  1229. val64 = 0x8080402010080402ULL;
  1230. writeq(val64, &bar0->rts_qos_steering);
  1231. break;
  1232. case 8:
  1233. val64 = 0x0001020300040105ULL;
  1234. writeq(val64, &bar0->rx_w_round_robin_0);
  1235. val64 = 0x0200030106000204ULL;
  1236. writeq(val64, &bar0->rx_w_round_robin_1);
  1237. val64 = 0x0103000502010007ULL;
  1238. writeq(val64, &bar0->rx_w_round_robin_2);
  1239. val64 = 0x0304010002060500ULL;
  1240. writeq(val64, &bar0->rx_w_round_robin_3);
  1241. val64 = 0x0103020400000000ULL;
  1242. writeq(val64, &bar0->rx_w_round_robin_4);
  1243. val64 = 0x8040201008040201ULL;
  1244. writeq(val64, &bar0->rts_qos_steering);
  1245. break;
  1246. }
  1247. /* UDP Fix */
  1248. val64 = 0;
  1249. for (i = 0; i < 8; i++)
  1250. writeq(val64, &bar0->rts_frm_len_n[i]);
  1251. /* Set the default rts frame length for the rings configured */
  1252. val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22);
  1253. for (i = 0 ; i < config->rx_ring_num ; i++)
  1254. writeq(val64, &bar0->rts_frm_len_n[i]);
  1255. /* Set the frame length for the configured rings
  1256. * desired by the user
  1257. */
  1258. for (i = 0; i < config->rx_ring_num; i++) {
  1259. /* If rts_frm_len[i] == 0 then it is assumed that user not
  1260. * specified frame length steering.
  1261. * If the user provides the frame length then program
  1262. * the rts_frm_len register for those values or else
  1263. * leave it as it is.
  1264. */
  1265. if (rts_frm_len[i] != 0) {
  1266. writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]),
  1267. &bar0->rts_frm_len_n[i]);
  1268. }
  1269. }
  1270. /* Disable differentiated services steering logic */
  1271. for (i = 0; i < 64; i++) {
  1272. if (rts_ds_steer(nic, i, 0) == FAILURE) {
  1273. DBG_PRINT(ERR_DBG, "%s: failed rts ds steering",
  1274. dev->name);
  1275. DBG_PRINT(ERR_DBG, "set on codepoint %d\n", i);
  1276. return FAILURE;
  1277. }
  1278. }
  1279. /* Program statistics memory */
  1280. writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
  1281. if (nic->device_type == XFRAME_II_DEVICE) {
  1282. val64 = STAT_BC(0x320);
  1283. writeq(val64, &bar0->stat_byte_cnt);
  1284. }
  1285. /*
  1286. * Initializing the sampling rate for the device to calculate the
  1287. * bandwidth utilization.
  1288. */
  1289. val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) |
  1290. MAC_RX_LINK_UTIL_VAL(rmac_util_period);
  1291. writeq(val64, &bar0->mac_link_util);
  1292. /*
  1293. * Initializing the Transmit and Receive Traffic Interrupt
  1294. * Scheme.
  1295. */
  1296. /*
  1297. * TTI Initialization. Default Tx timer gets us about
  1298. * 250 interrupts per sec. Continuous interrupts are enabled
  1299. * by default.
  1300. */
  1301. if (nic->device_type == XFRAME_II_DEVICE) {
  1302. int count = (nic->config.bus_speed * 125)/2;
  1303. val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
  1304. } else {
  1305. val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
  1306. }
  1307. val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
  1308. TTI_DATA1_MEM_TX_URNG_B(0x10) |
  1309. TTI_DATA1_MEM_TX_URNG_C(0x30) | TTI_DATA1_MEM_TX_TIMER_AC_EN;
  1310. if (use_continuous_tx_intrs)
  1311. val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;
  1312. writeq(val64, &bar0->tti_data1_mem);
  1313. val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
  1314. TTI_DATA2_MEM_TX_UFC_B(0x20) |
  1315. TTI_DATA2_MEM_TX_UFC_C(0x40) | TTI_DATA2_MEM_TX_UFC_D(0x80);
  1316. writeq(val64, &bar0->tti_data2_mem);
  1317. val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD;
  1318. writeq(val64, &bar0->tti_command_mem);
  1319. /*
  1320. * Once the operation completes, the Strobe bit of the command
  1321. * register will be reset. We poll for this particular condition
  1322. * We wait for a maximum of 500ms for the operation to complete,
  1323. * if it's not complete by then we return error.
  1324. */
  1325. time = 0;
  1326. while (TRUE) {
  1327. val64 = readq(&bar0->tti_command_mem);
  1328. if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) {
  1329. break;
  1330. }
  1331. if (time > 10) {
  1332. DBG_PRINT(ERR_DBG, "%s: TTI init Failed\n",
  1333. dev->name);
  1334. return -1;
  1335. }
  1336. msleep(50);
  1337. time++;
  1338. }
  1339. if (nic->config.bimodal) {
  1340. int k = 0;
  1341. for (k = 0; k < config->rx_ring_num; k++) {
  1342. val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD;
  1343. val64 |= TTI_CMD_MEM_OFFSET(0x38+k);
  1344. writeq(val64, &bar0->tti_command_mem);
  1345. /*
  1346. * Once the operation completes, the Strobe bit of the command
  1347. * register will be reset. We poll for this particular condition
  1348. * We wait for a maximum of 500ms for the operation to complete,
  1349. * if it's not complete by then we return error.
  1350. */
  1351. time = 0;
  1352. while (TRUE) {
  1353. val64 = readq(&bar0->tti_command_mem);
  1354. if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) {
  1355. break;
  1356. }
  1357. if (time > 10) {
  1358. DBG_PRINT(ERR_DBG,
  1359. "%s: TTI init Failed\n",
  1360. dev->name);
  1361. return -1;
  1362. }
  1363. time++;
  1364. msleep(50);
  1365. }
  1366. }
  1367. } else {
  1368. /* RTI Initialization */
  1369. if (nic->device_type == XFRAME_II_DEVICE) {
  1370. /*
  1371. * Programmed to generate Apprx 500 Intrs per
  1372. * second
  1373. */
  1374. int count = (nic->config.bus_speed * 125)/4;
  1375. val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
  1376. } else {
  1377. val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
  1378. }
  1379. val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
  1380. RTI_DATA1_MEM_RX_URNG_B(0x10) |
  1381. RTI_DATA1_MEM_RX_URNG_C(0x30) | RTI_DATA1_MEM_RX_TIMER_AC_EN;
  1382. writeq(val64, &bar0->rti_data1_mem);
  1383. val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
  1384. RTI_DATA2_MEM_RX_UFC_B(0x2) ;
  1385. if (nic->intr_type == MSI_X)
  1386. val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) | \
  1387. RTI_DATA2_MEM_RX_UFC_D(0x40));
  1388. else
  1389. val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) | \
  1390. RTI_DATA2_MEM_RX_UFC_D(0x80));
  1391. writeq(val64, &bar0->rti_data2_mem);
  1392. for (i = 0; i < config->rx_ring_num; i++) {
  1393. val64 = RTI_CMD_MEM_WE | RTI_CMD_MEM_STROBE_NEW_CMD
  1394. | RTI_CMD_MEM_OFFSET(i);
  1395. writeq(val64, &bar0->rti_command_mem);
  1396. /*
  1397. * Once the operation completes, the Strobe bit of the
  1398. * command register will be reset. We poll for this
  1399. * particular condition. We wait for a maximum of 500ms
  1400. * for the operation to complete, if it's not complete
  1401. * by then we return error.
  1402. */
  1403. time = 0;
  1404. while (TRUE) {
  1405. val64 = readq(&bar0->rti_command_mem);
  1406. if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD)) {
  1407. break;
  1408. }
  1409. if (time > 10) {
  1410. DBG_PRINT(ERR_DBG, "%s: RTI init Failed\n",
  1411. dev->name);
  1412. return -1;
  1413. }
  1414. time++;
  1415. msleep(50);
  1416. }
  1417. }
  1418. }
  1419. /*
  1420. * Initializing proper values as Pause threshold into all
  1421. * the 8 Queues on Rx side.
  1422. */
  1423. writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
  1424. writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
  1425. /* Disable RMAC PAD STRIPPING */
  1426. add = &bar0->mac_cfg;
  1427. val64 = readq(&bar0->mac_cfg);
  1428. val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
  1429. writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
  1430. writel((u32) (val64), add);
  1431. writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
  1432. writel((u32) (val64 >> 32), (add + 4));
  1433. val64 = readq(&bar0->mac_cfg);
  1434. /* Enable FCS stripping by adapter */
  1435. add = &bar0->mac_cfg;
  1436. val64 = readq(&bar0->mac_cfg);
  1437. val64 |= MAC_CFG_RMAC_STRIP_FCS;
  1438. if (nic->device_type == XFRAME_II_DEVICE)
  1439. writeq(val64, &bar0->mac_cfg);
  1440. else {
  1441. writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
  1442. writel((u32) (val64), add);
  1443. writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
  1444. writel((u32) (val64 >> 32), (add + 4));
  1445. }
  1446. /*
  1447. * Set the time value to be inserted in the pause frame
  1448. * generated by xena.
  1449. */
  1450. val64 = readq(&bar0->rmac_pause_cfg);
  1451. val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff));
  1452. val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
  1453. writeq(val64, &bar0->rmac_pause_cfg);
  1454. /*
  1455. * Set the Threshold Limit for Generating the pause frame
  1456. * If the amount of data in any Queue exceeds ratio of
  1457. * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
  1458. * pause frame is generated
  1459. */
  1460. val64 = 0;
  1461. for (i = 0; i < 4; i++) {
  1462. val64 |=
  1463. (((u64) 0xFF00 | nic->mac_control.
  1464. mc_pause_threshold_q0q3)
  1465. << (i * 2 * 8));
  1466. }
  1467. writeq(val64, &bar0->mc_pause_thresh_q0q3);
  1468. val64 = 0;
  1469. for (i = 0; i < 4; i++) {
  1470. val64 |=
  1471. (((u64) 0xFF00 | nic->mac_control.
  1472. mc_pause_threshold_q4q7)
  1473. << (i * 2 * 8));
  1474. }
  1475. writeq(val64, &bar0->mc_pause_thresh_q4q7);
  1476. /*
  1477. * TxDMA will stop Read request if the number of read split has
  1478. * exceeded the limit pointed by shared_splits
  1479. */
  1480. val64 = readq(&bar0->pic_control);
  1481. val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
  1482. writeq(val64, &bar0->pic_control);
  1483. if (nic->config.bus_speed == 266) {
  1484. writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN, &bar0->txreqtimeout);
  1485. writeq(0x0, &bar0->read_retry_delay);
  1486. writeq(0x0, &bar0->write_retry_delay);
  1487. }
  1488. /*
  1489. * Programming the Herc to split every write transaction
  1490. * that does not start on an ADB to reduce disconnects.
  1491. */
  1492. if (nic->device_type == XFRAME_II_DEVICE) {
  1493. val64 = FAULT_BEHAVIOUR | EXT_REQ_EN |
  1494. MISC_LINK_STABILITY_PRD(3);
  1495. writeq(val64, &bar0->misc_control);
  1496. val64 = readq(&bar0->pic_control2);
  1497. val64 &= ~(BIT(13)|BIT(14)|BIT(15));
  1498. writeq(val64, &bar0->pic_control2);
  1499. }
  1500. if (strstr(nic->product_name, "CX4")) {
  1501. val64 = TMAC_AVG_IPG(0x17);
  1502. writeq(val64, &bar0->tmac_avg_ipg);
  1503. }
  1504. return SUCCESS;
  1505. }
  1506. #define LINK_UP_DOWN_INTERRUPT 1
  1507. #define MAC_RMAC_ERR_TIMER 2
  1508. static int s2io_link_fault_indication(struct s2io_nic *nic)
  1509. {
  1510. if (nic->intr_type != INTA)
  1511. return MAC_RMAC_ERR_TIMER;
  1512. if (nic->device_type == XFRAME_II_DEVICE)
  1513. return LINK_UP_DOWN_INTERRUPT;
  1514. else
  1515. return MAC_RMAC_ERR_TIMER;
  1516. }
  1517. /**
  1518. * en_dis_able_nic_intrs - Enable or Disable the interrupts
  1519. * @nic: device private variable,
  1520. * @mask: A mask indicating which Intr block must be modified and,
  1521. * @flag: A flag indicating whether to enable or disable the Intrs.
  1522. * Description: This function will either disable or enable the interrupts
  1523. * depending on the flag argument. The mask argument can be used to
  1524. * enable/disable any Intr block.
  1525. * Return Value: NONE.
  1526. */
  1527. static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
  1528. {
  1529. struct XENA_dev_config __iomem *bar0 = nic->bar0;
  1530. register u64 val64 = 0, temp64 = 0;
  1531. /* Top level interrupt classification */
  1532. /* PIC Interrupts */
  1533. if ((mask & (TX_PIC_INTR | RX_PIC_INTR))) {
  1534. /* Enable PIC Intrs in the general intr mask register */
  1535. val64 = TXPIC_INT_M;
  1536. if (flag == ENABLE_INTRS) {
  1537. temp64 = readq(&bar0->general_int_mask);
  1538. temp64 &= ~((u64) val64);
  1539. writeq(temp64, &bar0->general_int_mask);
  1540. /*
  1541. * If Hercules adapter enable GPIO otherwise
  1542. * disable all PCIX, Flash, MDIO, IIC and GPIO
  1543. * interrupts for now.
  1544. * TODO
  1545. */
  1546. if (s2io_link_fault_indication(nic) ==
  1547. LINK_UP_DOWN_INTERRUPT ) {
  1548. temp64 = readq(&bar0->pic_int_mask);
  1549. temp64 &= ~((u64) PIC_INT_GPIO);
  1550. writeq(temp64, &bar0->pic_int_mask);
  1551. temp64 = readq(&bar0->gpio_int_mask);
  1552. temp64 &= ~((u64) GPIO_INT_MASK_LINK_UP);
  1553. writeq(temp64, &bar0->gpio_int_mask);
  1554. } else {
  1555. writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
  1556. }
  1557. /*
  1558. * No MSI Support is available presently, so TTI and
  1559. * RTI interrupts are also disabled.
  1560. */
  1561. } else if (flag == DISABLE_INTRS) {
  1562. /*
  1563. * Disable PIC Intrs in the general
  1564. * intr mask register
  1565. */
  1566. writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
  1567. temp64 = readq(&bar0->general_int_mask);
  1568. val64 |= temp64;
  1569. writeq(val64, &bar0->general_int_mask);
  1570. }
  1571. }
  1572. /* MAC Interrupts */
  1573. /* Enabling/Disabling MAC interrupts */
  1574. if (mask & (TX_MAC_INTR | RX_MAC_INTR)) {
  1575. val64 = TXMAC_INT_M | RXMAC_INT_M;
  1576. if (flag == ENABLE_INTRS) {
  1577. temp64 = readq(&bar0->general_int_mask);
  1578. temp64 &= ~((u64) val64);
  1579. writeq(temp64, &bar0->general_int_mask);
  1580. /*
  1581. * All MAC block error interrupts are disabled for now
  1582. * TODO
  1583. */
  1584. } else if (flag == DISABLE_INTRS) {
  1585. /*
  1586. * Disable MAC Intrs in the general intr mask register
  1587. */
  1588. writeq(DISABLE_ALL_INTRS, &bar0->mac_int_mask);
  1589. writeq(DISABLE_ALL_INTRS,
  1590. &bar0->mac_rmac_err_mask);
  1591. temp64 = readq(&bar0->general_int_mask);
  1592. val64 |= temp64;
  1593. writeq(val64, &bar0->general_int_mask);
  1594. }
  1595. }
  1596. /* Tx traffic interrupts */
  1597. if (mask & TX_TRAFFIC_INTR) {
  1598. val64 = TXTRAFFIC_INT_M;
  1599. if (flag == ENABLE_INTRS) {
  1600. temp64 = readq(&bar0->general_int_mask);
  1601. temp64 &= ~((u64) val64);
  1602. writeq(temp64, &bar0->general_int_mask);
  1603. /*
  1604. * Enable all the Tx side interrupts
  1605. * writing 0 Enables all 64 TX interrupt levels
  1606. */
  1607. writeq(0x0, &bar0->tx_traffic_mask);
  1608. } else if (flag == DISABLE_INTRS) {
  1609. /*
  1610. * Disable Tx Traffic Intrs in the general intr mask
  1611. * register.
  1612. */
  1613. writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
  1614. temp64 = readq(&bar0->general_int_mask);
  1615. val64 |= temp64;
  1616. writeq(val64, &bar0->general_int_mask);
  1617. }
  1618. }
  1619. /* Rx traffic interrupts */
  1620. if (mask & RX_TRAFFIC_INTR) {
  1621. val64 = RXTRAFFIC_INT_M;
  1622. if (flag == ENABLE_INTRS) {
  1623. temp64 = readq(&bar0->general_int_mask);
  1624. temp64 &= ~((u64) val64);
  1625. writeq(temp64, &bar0->general_int_mask);
  1626. /* writing 0 Enables all 8 RX interrupt levels */
  1627. writeq(0x0, &bar0->rx_traffic_mask);
  1628. } else if (flag == DISABLE_INTRS) {
  1629. /*
  1630. * Disable Rx Traffic Intrs in the general intr mask
  1631. * register.
  1632. */
  1633. writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
  1634. temp64 = readq(&bar0->general_int_mask);
  1635. val64 |= temp64;
  1636. writeq(val64, &bar0->general_int_mask);
  1637. }
  1638. }
  1639. }
  1640. /**
  1641. * verify_pcc_quiescent- Checks for PCC quiescent state
  1642. * Return: 1 If PCC is quiescence
  1643. * 0 If PCC is not quiescence
  1644. */
  1645. static int verify_pcc_quiescent(struct s2io_nic *sp, int flag)
  1646. {
  1647. int ret = 0, herc;
  1648. struct XENA_dev_config __iomem *bar0 = sp->bar0;
  1649. u64 val64 = readq(&bar0->adapter_status);
  1650. herc = (sp->device_type == XFRAME_II_DEVICE);
  1651. if (flag == FALSE) {
  1652. if ((!herc && (get_xena_rev_id(sp->pdev) >= 4)) || herc) {
  1653. if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE))
  1654. ret = 1;
  1655. } else {
  1656. if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
  1657. ret = 1;
  1658. }
  1659. } else {
  1660. if ((!herc && (get_xena_rev_id(sp->pdev) >= 4)) || herc) {
  1661. if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
  1662. ADAPTER_STATUS_RMAC_PCC_IDLE))
  1663. ret = 1;
  1664. } else {
  1665. if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) ==
  1666. ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
  1667. ret = 1;
  1668. }
  1669. }
  1670. return ret;
  1671. }
  1672. /**
  1673. * verify_xena_quiescence - Checks whether the H/W is ready
  1674. * Description: Returns whether the H/W is ready to go or not. Depending
  1675. * on whether adapter enable bit was written or not the comparison
  1676. * differs and the calling function passes the input argument flag to
  1677. * indicate this.
  1678. * Return: 1 If xena is quiescence
  1679. * 0 If Xena is not quiescence
  1680. */
  1681. static int verify_xena_quiescence(struct s2io_nic *sp)
  1682. {
  1683. int mode;
  1684. struct XENA_dev_config __iomem *bar0 = sp->bar0;
  1685. u64 val64 = readq(&bar0->adapter_status);
  1686. mode = s2io_verify_pci_mode(sp);
  1687. if (!(val64 & ADAPTER_STATUS_TDMA_READY)) {
  1688. DBG_PRINT(ERR_DBG, "%s", "TDMA is not ready!");
  1689. return 0;
  1690. }
  1691. if (!(val64 & ADAPTER_STATUS_RDMA_READY)) {
  1692. DBG_PRINT(ERR_DBG, "%s", "RDMA is not ready!");
  1693. return 0;
  1694. }
  1695. if (!(val64 & ADAPTER_STATUS_PFC_READY)) {
  1696. DBG_PRINT(ERR_DBG, "%s", "PFC is not ready!");
  1697. return 0;
  1698. }
  1699. if (!(val64 & ADAPTER_STATUS_TMAC_BUF_EMPTY)) {
  1700. DBG_PRINT(ERR_DBG, "%s", "TMAC BUF is not empty!");
  1701. return 0;
  1702. }
  1703. if (!(val64 & ADAPTER_STATUS_PIC_QUIESCENT)) {
  1704. DBG_PRINT(ERR_DBG, "%s", "PIC is not QUIESCENT!");
  1705. return 0;
  1706. }
  1707. if (!(val64 & ADAPTER_STATUS_MC_DRAM_READY)) {
  1708. DBG_PRINT(ERR_DBG, "%s", "MC_DRAM is not ready!");
  1709. return 0;
  1710. }
  1711. if (!(val64 & ADAPTER_STATUS_MC_QUEUES_READY)) {
  1712. DBG_PRINT(ERR_DBG, "%s", "MC_QUEUES is not ready!");
  1713. return 0;
  1714. }
  1715. if (!(val64 & ADAPTER_STATUS_M_PLL_LOCK)) {
  1716. DBG_PRINT(ERR_DBG, "%s", "M_PLL is not locked!");
  1717. return 0;
  1718. }
  1719. /*
  1720. * In PCI 33 mode, the P_PLL is not used, and therefore,
  1721. * the the P_PLL_LOCK bit in the adapter_status register will
  1722. * not be asserted.
  1723. */
  1724. if (!(val64 & ADAPTER_STATUS_P_PLL_LOCK) &&
  1725. sp->device_type == XFRAME_II_DEVICE && mode !=
  1726. PCI_MODE_PCI_33) {
  1727. DBG_PRINT(ERR_DBG, "%s", "P_PLL is not locked!");
  1728. return 0;
  1729. }
  1730. if (!((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
  1731. ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
  1732. DBG_PRINT(ERR_DBG, "%s", "RC_PRC is not QUIESCENT!");
  1733. return 0;
  1734. }
  1735. return 1;
  1736. }
  1737. /**
  1738. * fix_mac_address - Fix for Mac addr problem on Alpha platforms
  1739. * @sp: Pointer to device specifc structure
  1740. * Description :
  1741. * New procedure to clear mac address reading problems on Alpha platforms
  1742. *
  1743. */
  1744. static void fix_mac_address(struct s2io_nic * sp)
  1745. {
  1746. struct XENA_dev_config __iomem *bar0 = sp->bar0;
  1747. u64 val64;
  1748. int i = 0;
  1749. while (fix_mac[i] != END_SIGN) {
  1750. writeq(fix_mac[i++], &bar0->gpio_control);
  1751. udelay(10);
  1752. val64 = readq(&bar0->gpio_control);
  1753. }
  1754. }
  1755. /**
  1756. * start_nic - Turns the device on
  1757. * @nic : device private variable.
  1758. * Description:
  1759. * This function actually turns the device on. Before this function is
  1760. * called,all Registers are configured from their reset states
  1761. * and shared memory is allocated but the NIC is still quiescent. On
  1762. * calling this function, the device interrupts are cleared and the NIC is
  1763. * literally switched on by writing into the adapter control register.
  1764. * Return Value:
  1765. * SUCCESS on success and -1 on failure.
  1766. */
  1767. static int start_nic(struct s2io_nic *nic)
  1768. {
  1769. struct XENA_dev_config __iomem *bar0 = nic->bar0;
  1770. struct net_device *dev = nic->dev;
  1771. register u64 val64 = 0;
  1772. u16 subid, i;
  1773. struct mac_info *mac_control;
  1774. struct config_param *config;
  1775. mac_control = &nic->mac_control;
  1776. config = &nic->config;
  1777. /* PRC Initialization and configuration */
  1778. for (i = 0; i < config->rx_ring_num; i++) {
  1779. writeq((u64) mac_control->rings[i].rx_blocks[0].block_dma_addr,
  1780. &bar0->prc_rxd0_n[i]);
  1781. val64 = readq(&bar0->prc_ctrl_n[i]);
  1782. if (nic->config.bimodal)
  1783. val64 |= PRC_CTRL_BIMODAL_INTERRUPT;
  1784. if (nic->rxd_mode == RXD_MODE_1)
  1785. val64 |= PRC_CTRL_RC_ENABLED;
  1786. else
  1787. val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3;
  1788. if (nic->device_type == XFRAME_II_DEVICE)
  1789. val64 |= PRC_CTRL_GROUP_READS;
  1790. val64 &= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
  1791. val64 |= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000);
  1792. writeq(val64, &bar0->prc_ctrl_n[i]);
  1793. }
  1794. if (nic->rxd_mode == RXD_MODE_3B) {
  1795. /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
  1796. val64 = readq(&bar0->rx_pa_cfg);
  1797. val64 |= RX_PA_CFG_IGNORE_L2_ERR;
  1798. writeq(val64, &bar0->rx_pa_cfg);
  1799. }
  1800. if (vlan_tag_strip == 0) {
  1801. val64 = readq(&bar0->rx_pa_cfg);
  1802. val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
  1803. writeq(val64, &bar0->rx_pa_cfg);
  1804. vlan_strip_flag = 0;
  1805. }
  1806. /*
  1807. * Enabling MC-RLDRAM. After enabling the device, we timeout
  1808. * for around 100ms, which is approximately the time required
  1809. * for the device to be ready for operation.
  1810. */
  1811. val64 = readq(&bar0->mc_rldram_mrs);
  1812. val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;
  1813. SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
  1814. val64 = readq(&bar0->mc_rldram_mrs);
  1815. msleep(100); /* Delay by around 100 ms. */
  1816. /* Enabling ECC Protection. */
  1817. val64 = readq(&bar0->adapter_control);
  1818. val64 &= ~ADAPTER_ECC_EN;
  1819. writeq(val64, &bar0->adapter_control);
  1820. /*
  1821. * Clearing any possible Link state change interrupts that
  1822. * could have popped up just before Enabling the card.
  1823. */
  1824. val64 = readq(&bar0->mac_rmac_err_reg);
  1825. if (val64)
  1826. writeq(val64, &bar0->mac_rmac_err_reg);
  1827. /*
  1828. * Verify if the device is ready to be enabled, if so enable
  1829. * it.
  1830. */
  1831. val64 = readq(&bar0->adapter_status);
  1832. if (!verify_xena_quiescence(nic)) {
  1833. DBG_PRINT(ERR_DBG, "%s: device is not ready, ", dev->name);
  1834. DBG_PRINT(ERR_DBG, "Adapter status reads: 0x%llx\n",
  1835. (unsigned long long) val64);
  1836. return FAILURE;
  1837. }
  1838. /*
  1839. * With some switches, link might be already up at this point.
  1840. * Because of this weird behavior, when we enable laser,
  1841. * we may not get link. We need to handle this. We cannot
  1842. * figure out which switch is misbehaving. So we are forced to
  1843. * make a global change.
  1844. */
  1845. /* Enabling Laser. */
  1846. val64 = readq(&bar0->adapter_control);
  1847. val64 |= ADAPTER_EOI_TX_ON;
  1848. writeq(val64, &bar0->adapter_control);
  1849. if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
  1850. /*
  1851. * Dont see link state interrupts initally on some switches,
  1852. * so directly scheduling the link state task here.
  1853. */
  1854. schedule_work(&nic->set_link_task);
  1855. }
  1856. /* SXE-002: Initialize link and activity LED */
  1857. subid = nic->pdev->subsystem_device;
  1858. if (((subid & 0xFF) >= 0x07) &&
  1859. (nic->device_type == XFRAME_I_DEVICE)) {
  1860. val64 = readq(&bar0->gpio_control);
  1861. val64 |= 0x0000800000000000ULL;
  1862. writeq(val64, &bar0->gpio_control);
  1863. val64 = 0x0411040400000000ULL;
  1864. writeq(val64, (void __iomem *)bar0 + 0x2700);
  1865. }
  1866. return SUCCESS;
  1867. }
  1868. /**
  1869. * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb
  1870. */
  1871. static struct sk_buff *s2io_txdl_getskb(struct fifo_info *fifo_data, struct \
  1872. TxD *txdlp, int get_off)
  1873. {
  1874. struct s2io_nic *nic = fifo_data->nic;
  1875. struct sk_buff *skb;
  1876. struct TxD *txds;
  1877. u16 j, frg_cnt;
  1878. txds = txdlp;
  1879. if (txds->Host_Control == (u64)(long)nic->ufo_in_band_v) {
  1880. pci_unmap_single(nic->pdev, (dma_addr_t)
  1881. txds->Buffer_Pointer, sizeof(u64),
  1882. PCI_DMA_TODEVICE);
  1883. txds++;
  1884. }
  1885. skb = (struct sk_buff *) ((unsigned long)
  1886. txds->Host_Control);
  1887. if (!skb) {
  1888. memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
  1889. return NULL;
  1890. }
  1891. pci_unmap_single(nic->pdev, (dma_addr_t)
  1892. txds->Buffer_Pointer,
  1893. skb->len - skb->data_len,
  1894. PCI_DMA_TODEVICE);
  1895. frg_cnt = skb_shinfo(skb)->nr_frags;
  1896. if (frg_cnt) {
  1897. txds++;
  1898. for (j = 0; j < frg_cnt; j++, txds++) {
  1899. skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
  1900. if (!txds->Buffer_Pointer)
  1901. break;
  1902. pci_unmap_page(nic->pdev, (dma_addr_t)
  1903. txds->Buffer_Pointer,
  1904. frag->size, PCI_DMA_TODEVICE);
  1905. }
  1906. }
  1907. memset(txdlp,0, (sizeof(struct TxD) * fifo_data->max_txds));
  1908. return(skb);
  1909. }
  1910. /**
  1911. * free_tx_buffers - Free all queued Tx buffers
  1912. * @nic : device private variable.
  1913. * Description:
  1914. * Free all queued Tx buffers.
  1915. * Return Value: void
  1916. */
  1917. static void free_tx_buffers(struct s2io_nic *nic)
  1918. {
  1919. struct net_device *dev = nic->dev;
  1920. struct sk_buff *skb;
  1921. struct TxD *txdp;
  1922. int i, j;
  1923. struct mac_info *mac_control;
  1924. struct config_param *config;
  1925. int cnt = 0;
  1926. mac_control = &nic->mac_control;
  1927. config = &nic->config;
  1928. for (i = 0; i < config->tx_fifo_num; i++) {
  1929. for (j = 0; j < config->tx_cfg[i].fifo_len - 1; j++) {
  1930. txdp = (struct TxD *) mac_control->fifos[i].list_info[j].
  1931. list_virt_addr;
  1932. skb = s2io_txdl_getskb(&mac_control->fifos[i], txdp, j);
  1933. if (skb) {
  1934. dev_kfree_skb(skb);
  1935. cnt++;
  1936. }
  1937. }
  1938. DBG_PRINT(INTR_DBG,
  1939. "%s:forcibly freeing %d skbs on FIFO%d\n",
  1940. dev->name, cnt, i);
  1941. mac_control->fifos[i].tx_curr_get_info.offset = 0;
  1942. mac_control->fifos[i].tx_curr_put_info.offset = 0;
  1943. }
  1944. }
  1945. /**
  1946. * stop_nic - To stop the nic
  1947. * @nic ; device private variable.
  1948. * Description:
  1949. * This function does exactly the opposite of what the start_nic()
  1950. * function does. This function is called to stop the device.
  1951. * Return Value:
  1952. * void.
  1953. */
  1954. static void stop_nic(struct s2io_nic *nic)
  1955. {
  1956. struct XENA_dev_config __iomem *bar0 = nic->bar0;
  1957. register u64 val64 = 0;
  1958. u16 interruptible;
  1959. struct mac_info *mac_control;
  1960. struct config_param *config;
  1961. mac_control = &nic->mac_control;
  1962. config = &nic->config;
  1963. /* Disable all interrupts */
  1964. interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
  1965. interruptible |= TX_PIC_INTR | RX_PIC_INTR;
  1966. interruptible |= TX_MAC_INTR | RX_MAC_INTR;
  1967. en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
  1968. /* Clearing Adapter_En bit of ADAPTER_CONTROL Register */
  1969. val64 = readq(&bar0->adapter_control);
  1970. val64 &= ~(ADAPTER_CNTL_EN);
  1971. writeq(val64, &bar0->adapter_control);
  1972. }
  1973. static int fill_rxd_3buf(struct s2io_nic *nic, struct RxD_t *rxdp, struct \
  1974. sk_buff *skb)
  1975. {
  1976. struct net_device *dev = nic->dev;
  1977. struct sk_buff *frag_list;
  1978. void *tmp;
  1979. /* Buffer-1 receives L3/L4 headers */
  1980. ((struct RxD3*)rxdp)->Buffer1_ptr = pci_map_single
  1981. (nic->pdev, skb->data, l3l4hdr_size + 4,
  1982. PCI_DMA_FROMDEVICE);
  1983. /* skb_shinfo(skb)->frag_list will have L4 data payload */
  1984. skb_shinfo(skb)->frag_list = dev_alloc_skb(dev->mtu + ALIGN_SIZE);
  1985. if (skb_shinfo(skb)->frag_list == NULL) {
  1986. DBG_PRINT(ERR_DBG, "%s: dev_alloc_skb failed\n ", dev->name);
  1987. return -ENOMEM ;
  1988. }
  1989. frag_list = skb_shinfo(skb)->frag_list;
  1990. skb->truesize += frag_list->truesize;
  1991. frag_list->next = NULL;
  1992. tmp = (void *)ALIGN((long)frag_list->data, ALIGN_SIZE + 1);
  1993. frag_list->data = tmp;
  1994. frag_list->tail = tmp;
  1995. /* Buffer-2 receives L4 data payload */
  1996. ((struct RxD3*)rxdp)->Buffer2_ptr = pci_map_single(nic->pdev,
  1997. frag_list->data, dev->mtu,
  1998. PCI_DMA_FROMDEVICE);
  1999. rxdp->Control_2 |= SET_BUFFER1_SIZE_3(l3l4hdr_size + 4);
  2000. rxdp->Control_2 |= SET_BUFFER2_SIZE_3(dev->mtu);
  2001. return SUCCESS;
  2002. }
  2003. /**
  2004. * fill_rx_buffers - Allocates the Rx side skbs
  2005. * @nic: device private variable
  2006. * @ring_no: ring number
  2007. * Description:
  2008. * The function allocates Rx side skbs and puts the physical
  2009. * address of these buffers into the RxD buffer pointers, so that the NIC
  2010. * can DMA the received frame into these locations.
  2011. * The NIC supports 3 receive modes, viz
  2012. * 1. single buffer,
  2013. * 2. three buffer and
  2014. * 3. Five buffer modes.
  2015. * Each mode defines how many fragments the received frame will be split
  2016. * up into by the NIC. The frame is split into L3 header, L4 Header,
  2017. * L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
  2018. * is split into 3 fragments. As of now only single buffer mode is
  2019. * supported.
  2020. * Return Value:
  2021. * SUCCESS on success or an appropriate -ve value on failure.
  2022. */
  2023. static int fill_rx_buffers(struct s2io_nic *nic, int ring_no)
  2024. {
  2025. struct net_device *dev = nic->dev;
  2026. struct sk_buff *skb;
  2027. struct RxD_t *rxdp;
  2028. int off, off1, size, block_no, block_no1;
  2029. u32 alloc_tab = 0;
  2030. u32 alloc_cnt;
  2031. struct mac_info *mac_control;
  2032. struct config_param *config;
  2033. u64 tmp;
  2034. struct buffAdd *ba;
  2035. unsigned long flags;
  2036. struct RxD_t *first_rxdp = NULL;
  2037. mac_control = &nic->mac_control;
  2038. config = &nic->config;
  2039. alloc_cnt = mac_control->rings[ring_no].pkt_cnt -
  2040. atomic_read(&nic->rx_bufs_left[ring_no]);
  2041. block_no1 = mac_control->rings[ring_no].rx_curr_get_info.block_index;
  2042. off1 = mac_control->rings[ring_no].rx_curr_get_info.offset;
  2043. while (alloc_tab < alloc_cnt) {
  2044. block_no = mac_control->rings[ring_no].rx_curr_put_info.
  2045. block_index;
  2046. off = mac_control->rings[ring_no].rx_curr_put_info.offset;
  2047. rxdp = mac_control->rings[ring_no].
  2048. rx_blocks[block_no].rxds[off].virt_addr;
  2049. if ((block_no == block_no1) && (off == off1) &&
  2050. (rxdp->Host_Control)) {
  2051. DBG_PRINT(INTR_DBG, "%s: Get and Put",
  2052. dev->name);
  2053. DBG_PRINT(INTR_DBG, " info equated\n");
  2054. goto end;
  2055. }
  2056. if (off && (off == rxd_count[nic->rxd_mode])) {
  2057. mac_control->rings[ring_no].rx_curr_put_info.
  2058. block_index++;
  2059. if (mac_control->rings[ring_no].rx_curr_put_info.
  2060. block_index == mac_control->rings[ring_no].
  2061. block_count)
  2062. mac_control->rings[ring_no].rx_curr_put_info.
  2063. block_index = 0;
  2064. block_no = mac_control->rings[ring_no].
  2065. rx_curr_put_info.block_index;
  2066. if (off == rxd_count[nic->rxd_mode])
  2067. off = 0;
  2068. mac_control->rings[ring_no].rx_curr_put_info.
  2069. offset = off;
  2070. rxdp = mac_control->rings[ring_no].
  2071. rx_blocks[block_no].block_virt_addr;
  2072. DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
  2073. dev->name, rxdp);
  2074. }
  2075. if(!napi) {
  2076. spin_lock_irqsave(&nic->put_lock, flags);
  2077. mac_control->rings[ring_no].put_pos =
  2078. (block_no * (rxd_count[nic->rxd_mode] + 1)) + off;
  2079. spin_unlock_irqrestore(&nic->put_lock, flags);
  2080. } else {
  2081. mac_control->rings[ring_no].put_pos =
  2082. (block_no * (rxd_count[nic->rxd_mode] + 1)) + off;
  2083. }
  2084. if ((rxdp->Control_1 & RXD_OWN_XENA) &&
  2085. ((nic->rxd_mode >= RXD_MODE_3A) &&
  2086. (rxdp->Control_2 & BIT(0)))) {
  2087. mac_control->rings[ring_no].rx_curr_put_info.
  2088. offset = off;
  2089. goto end;
  2090. }
  2091. /* calculate size of skb based on ring mode */
  2092. size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
  2093. HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
  2094. if (nic->rxd_mode == RXD_MODE_1)
  2095. size += NET_IP_ALIGN;
  2096. else if (nic->rxd_mode == RXD_MODE_3B)
  2097. size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
  2098. else
  2099. size = l3l4hdr_size + ALIGN_SIZE + BUF0_LEN + 4;
  2100. /* allocate skb */
  2101. skb = dev_alloc_skb(size);
  2102. if(!skb) {
  2103. DBG_PRINT(ERR_DBG, "%s: Out of ", dev->name);
  2104. DBG_PRINT(ERR_DBG, "memory to allocate SKBs\n");
  2105. if (first_rxdp) {
  2106. wmb();
  2107. first_rxdp->Control_1 |= RXD_OWN_XENA;
  2108. }
  2109. return -ENOMEM ;
  2110. }
  2111. if (nic->rxd_mode == RXD_MODE_1) {
  2112. /* 1 buffer mode - normal operation mode */
  2113. memset(rxdp, 0, sizeof(struct RxD1));
  2114. skb_reserve(skb, NET_IP_ALIGN);
  2115. ((struct RxD1*)rxdp)->Buffer0_ptr = pci_map_single
  2116. (nic->pdev, skb->data, size - NET_IP_ALIGN,
  2117. PCI_DMA_FROMDEVICE);
  2118. rxdp->Control_2 = SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
  2119. } else if (nic->rxd_mode >= RXD_MODE_3A) {
  2120. /*
  2121. * 2 or 3 buffer mode -
  2122. * Both 2 buffer mode and 3 buffer mode provides 128
  2123. * byte aligned receive buffers.
  2124. *
  2125. * 3 buffer mode provides header separation where in
  2126. * skb->data will have L3/L4 headers where as
  2127. * skb_shinfo(skb)->frag_list will have the L4 data
  2128. * payload
  2129. */
  2130. memset(rxdp, 0, sizeof(struct RxD3));
  2131. ba = &mac_control->rings[ring_no].ba[block_no][off];
  2132. skb_reserve(skb, BUF0_LEN);
  2133. tmp = (u64)(unsigned long) skb->data;
  2134. tmp += ALIGN_SIZE;
  2135. tmp &= ~ALIGN_SIZE;
  2136. skb->data = (void *) (unsigned long)tmp;
  2137. skb->tail = (void *) (unsigned long)tmp;
  2138. if (!(((struct RxD3*)rxdp)->Buffer0_ptr))
  2139. ((struct RxD3*)rxdp)->Buffer0_ptr =
  2140. pci_map_single(nic->pdev, ba->ba_0, BUF0_LEN,
  2141. PCI_DMA_FROMDEVICE);
  2142. else
  2143. pci_dma_sync_single_for_device(nic->pdev,
  2144. (dma_addr_t) ((struct RxD3*)rxdp)->Buffer0_ptr,
  2145. BUF0_LEN, PCI_DMA_FROMDEVICE);
  2146. rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
  2147. if (nic->rxd_mode == RXD_MODE_3B) {
  2148. /* Two buffer mode */
  2149. /*
  2150. * Buffer2 will have L3/L4 header plus
  2151. * L4 payload
  2152. */
  2153. ((struct RxD3*)rxdp)->Buffer2_ptr = pci_map_single
  2154. (nic->pdev, skb->data, dev->mtu + 4,
  2155. PCI_DMA_FROMDEVICE);
  2156. /* Buffer-1 will be dummy buffer. Not used */
  2157. if (!(((struct RxD3*)rxdp)->Buffer1_ptr)) {
  2158. ((struct RxD3*)rxdp)->Buffer1_ptr =
  2159. pci_map_single(nic->pdev,
  2160. ba->ba_1, BUF1_LEN,
  2161. PCI_DMA_FROMDEVICE);
  2162. }
  2163. rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
  2164. rxdp->Control_2 |= SET_BUFFER2_SIZE_3
  2165. (dev->mtu + 4);
  2166. } else {
  2167. /* 3 buffer mode */
  2168. if (fill_rxd_3buf(nic, rxdp, skb) == -ENOMEM) {
  2169. dev_kfree_skb_irq(skb);
  2170. if (first_rxdp) {
  2171. wmb();
  2172. first_rxdp->Control_1 |=
  2173. RXD_OWN_XENA;
  2174. }
  2175. return -ENOMEM ;
  2176. }
  2177. }
  2178. rxdp->Control_2 |= BIT(0);
  2179. }
  2180. rxdp->Host_Control = (unsigned long) (skb);
  2181. if (alloc_tab & ((1 << rxsync_frequency) - 1))
  2182. rxdp->Control_1 |= RXD_OWN_XENA;
  2183. off++;
  2184. if (off == (rxd_count[nic->rxd_mode] + 1))
  2185. off = 0;
  2186. mac_control->rings[ring_no].rx_curr_put_info.offset = off;
  2187. rxdp->Control_2 |= SET_RXD_MARKER;
  2188. if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {
  2189. if (first_rxdp) {
  2190. wmb();
  2191. first_rxdp->Control_1 |= RXD_OWN_XENA;
  2192. }
  2193. first_rxdp = rxdp;
  2194. }
  2195. atomic_inc(&nic->rx_bufs_left[ring_no]);
  2196. alloc_tab++;
  2197. }
  2198. end:
  2199. /* Transfer ownership of first descriptor to adapter just before
  2200. * exiting. Before that, use memory barrier so that ownership
  2201. * and other fields are seen by adapter correctly.
  2202. */
  2203. if (first_rxdp) {
  2204. wmb();
  2205. first_rxdp->Control_1 |= RXD_OWN_XENA;
  2206. }
  2207. return SUCCESS;
  2208. }
  2209. static void free_rxd_blk(struct s2io_nic *sp, int ring_no, int blk)
  2210. {
  2211. struct net_device *dev = sp->dev;
  2212. int j;
  2213. struct sk_buff *skb;
  2214. struct RxD_t *rxdp;
  2215. struct mac_info *mac_control;
  2216. struct buffAdd *ba;
  2217. mac_control = &sp->mac_control;
  2218. for (j = 0 ; j < rxd_count[sp->rxd_mode]; j++) {
  2219. rxdp = mac_control->rings[ring_no].
  2220. rx_blocks[blk].rxds[j].virt_addr;
  2221. skb = (struct sk_buff *)
  2222. ((unsigned long) rxdp->Host_Control);
  2223. if (!skb) {
  2224. continue;
  2225. }
  2226. if (sp->rxd_mode == RXD_MODE_1) {
  2227. pci_unmap_single(sp->pdev, (dma_addr_t)
  2228. ((struct RxD1*)rxdp)->Buffer0_ptr,
  2229. dev->mtu +
  2230. HEADER_ETHERNET_II_802_3_SIZE
  2231. + HEADER_802_2_SIZE +
  2232. HEADER_SNAP_SIZE,
  2233. PCI_DMA_FROMDEVICE);
  2234. memset(rxdp, 0, sizeof(struct RxD1));
  2235. } else if(sp->rxd_mode == RXD_MODE_3B) {
  2236. ba = &mac_control->rings[ring_no].
  2237. ba[blk][j];
  2238. pci_unmap_single(sp->pdev, (dma_addr_t)
  2239. ((struct RxD3*)rxdp)->Buffer0_ptr,
  2240. BUF0_LEN,
  2241. PCI_DMA_FROMDEVICE);
  2242. pci_unmap_single(sp->pdev, (dma_addr_t)
  2243. ((struct RxD3*)rxdp)->Buffer1_ptr,
  2244. BUF1_LEN,
  2245. PCI_DMA_FROMDEVICE);
  2246. pci_unmap_single(sp->pdev, (dma_addr_t)
  2247. ((struct RxD3*)rxdp)->Buffer2_ptr,
  2248. dev->mtu + 4,
  2249. PCI_DMA_FROMDEVICE);
  2250. memset(rxdp, 0, sizeof(struct RxD3));
  2251. } else {
  2252. pci_unmap_single(sp->pdev, (dma_addr_t)
  2253. ((struct RxD3*)rxdp)->Buffer0_ptr, BUF0_LEN,
  2254. PCI_DMA_FROMDEVICE);
  2255. pci_unmap_single(sp->pdev, (dma_addr_t)
  2256. ((struct RxD3*)rxdp)->Buffer1_ptr,
  2257. l3l4hdr_size + 4,
  2258. PCI_DMA_FROMDEVICE);
  2259. pci_unmap_single(sp->pdev, (dma_addr_t)
  2260. ((struct RxD3*)rxdp)->Buffer2_ptr, dev->mtu,
  2261. PCI_DMA_FROMDEVICE);
  2262. memset(rxdp, 0, sizeof(struct RxD3));
  2263. }
  2264. dev_kfree_skb(skb);
  2265. atomic_dec(&sp->rx_bufs_left[ring_no]);
  2266. }
  2267. }
  2268. /**
  2269. * free_rx_buffers - Frees all Rx buffers
  2270. * @sp: device private variable.
  2271. * Description:
  2272. * This function will free all Rx buffers allocated by host.
  2273. * Return Value:
  2274. * NONE.
  2275. */
  2276. static void free_rx_buffers(struct s2io_nic *sp)
  2277. {
  2278. struct net_device *dev = sp->dev;
  2279. int i, blk = 0, buf_cnt = 0;
  2280. struct mac_info *mac_control;
  2281. struct config_param *config;
  2282. mac_control = &sp->mac_control;
  2283. config = &sp->config;
  2284. for (i = 0; i < config->rx_ring_num; i++) {
  2285. for (blk = 0; blk < rx_ring_sz[i]; blk++)
  2286. free_rxd_blk(sp,i,blk);
  2287. mac_control->rings[i].rx_curr_put_info.block_index = 0;
  2288. mac_control->rings[i].rx_curr_get_info.block_index = 0;
  2289. mac_control->rings[i].rx_curr_put_info.offset = 0;
  2290. mac_control->rings[i].rx_curr_get_info.offset = 0;
  2291. atomic_set(&sp->rx_bufs_left[i], 0);
  2292. DBG_PRINT(INIT_DBG, "%s:Freed 0x%x Rx Buffers on ring%d\n",
  2293. dev->name, buf_cnt, i);
  2294. }
  2295. }
  2296. /**
  2297. * s2io_poll - Rx interrupt handler for NAPI support
  2298. * @dev : pointer to the device structure.
  2299. * @budget : The number of packets that were budgeted to be processed
  2300. * during one pass through the 'Poll" function.
  2301. * Description:
  2302. * Comes into picture only if NAPI support has been incorporated. It does
  2303. * the same thing that rx_intr_handler does, but not in a interrupt context
  2304. * also It will process only a given number of packets.
  2305. * Return value:
  2306. * 0 on success and 1 if there are No Rx packets to be processed.
  2307. */
  2308. static int s2io_poll(struct net_device *dev, int *budget)
  2309. {
  2310. struct s2io_nic *nic = dev->priv;
  2311. int pkt_cnt = 0, org_pkts_to_process;
  2312. struct mac_info *mac_control;
  2313. struct config_param *config;
  2314. struct XENA_dev_config __iomem *bar0 = nic->bar0;
  2315. int i;
  2316. atomic_inc(&nic->isr_cnt);
  2317. mac_control = &nic->mac_control;
  2318. config = &nic->config;
  2319. nic->pkts_to_process = *budget;
  2320. if (nic->pkts_to_process > dev->quota)
  2321. nic->pkts_to_process = dev->quota;
  2322. org_pkts_to_process = nic->pkts_to_process;
  2323. writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
  2324. readl(&bar0->rx_traffic_int);
  2325. for (i = 0; i < config->rx_ring_num; i++) {
  2326. rx_intr_handler(&mac_control->rings[i]);
  2327. pkt_cnt = org_pkts_to_process - nic->pkts_to_process;
  2328. if (!nic->pkts_to_process) {
  2329. /* Quota for the current iteration has been met */
  2330. goto no_rx;
  2331. }
  2332. }
  2333. if (!pkt_cnt)
  2334. pkt_cnt = 1;
  2335. dev->quota -= pkt_cnt;
  2336. *budget -= pkt_cnt;
  2337. netif_rx_complete(dev);
  2338. for (i = 0; i < config->rx_ring_num; i++) {
  2339. if (fill_rx_buffers(nic, i) == -ENOMEM) {
  2340. DBG_PRINT(ERR_DBG, "%s:Out of memory", dev->name);
  2341. DBG_PRINT(ERR_DBG, " in Rx Poll!!\n");
  2342. break;
  2343. }
  2344. }
  2345. /* Re enable the Rx interrupts. */
  2346. writeq(0x0, &bar0->rx_traffic_mask);
  2347. readl(&bar0->rx_traffic_mask);
  2348. atomic_dec(&nic->isr_cnt);
  2349. return 0;
  2350. no_rx:
  2351. dev->quota -= pkt_cnt;
  2352. *budget -= pkt_cnt;
  2353. for (i = 0; i < config->rx_ring_num; i++) {
  2354. if (fill_rx_buffers(nic, i) == -ENOMEM) {
  2355. DBG_PRINT(ERR_DBG, "%s:Out of memory", dev->name);
  2356. DBG_PRINT(ERR_DBG, " in Rx Poll!!\n");
  2357. break;
  2358. }
  2359. }
  2360. atomic_dec(&nic->isr_cnt);
  2361. return 1;
  2362. }
  2363. #ifdef CONFIG_NET_POLL_CONTROLLER
  2364. /**
  2365. * s2io_netpoll - netpoll event handler entry point
  2366. * @dev : pointer to the device structure.
  2367. * Description:
  2368. * This function will be called by upper layer to check for events on the
  2369. * interface in situations where interrupts are disabled. It is used for
  2370. * specific in-kernel networking tasks, such as remote consoles and kernel
  2371. * debugging over the network (example netdump in RedHat).
  2372. */
  2373. static void s2io_netpoll(struct net_device *dev)
  2374. {
  2375. struct s2io_nic *nic = dev->priv;
  2376. struct mac_info *mac_control;
  2377. struct config_param *config;
  2378. struct XENA_dev_config __iomem *bar0 = nic->bar0;
  2379. u64 val64 = 0xFFFFFFFFFFFFFFFFULL;
  2380. int i;
  2381. disable_irq(dev->irq);
  2382. atomic_inc(&nic->isr_cnt);
  2383. mac_control = &nic->mac_control;
  2384. config = &nic->config;
  2385. writeq(val64, &bar0->rx_traffic_int);
  2386. writeq(val64, &bar0->tx_traffic_int);
  2387. /* we need to free up the transmitted skbufs or else netpoll will
  2388. * run out of skbs and will fail and eventually netpoll application such
  2389. * as netdump will fail.
  2390. */
  2391. for (i = 0; i < config->tx_fifo_num; i++)
  2392. tx_intr_handler(&mac_control->fifos[i]);
  2393. /* check for received packet and indicate up to network */
  2394. for (i = 0; i < config->rx_ring_num; i++)
  2395. rx_intr_handler(&mac_control->rings[i]);
  2396. for (i = 0; i < config->rx_ring_num; i++) {
  2397. if (fill_rx_buffers(nic, i) == -ENOMEM) {
  2398. DBG_PRINT(ERR_DBG, "%s:Out of memory", dev->name);
  2399. DBG_PRINT(ERR_DBG, " in Rx Netpoll!!\n");
  2400. break;
  2401. }
  2402. }
  2403. atomic_dec(&nic->isr_cnt);
  2404. enable_irq(dev->irq);
  2405. return;
  2406. }
  2407. #endif
  2408. /**
  2409. * rx_intr_handler - Rx interrupt handler
  2410. * @nic: device private variable.
  2411. * Description:
  2412. * If the interrupt is because of a received frame or if the
  2413. * receive ring contains fresh as yet un-processed frames,this function is
  2414. * called. It picks out the RxD at which place the last Rx processing had
  2415. * stopped and sends the skb to the OSM's Rx handler and then increments
  2416. * the offset.
  2417. * Return Value:
  2418. * NONE.
  2419. */
  2420. static void rx_intr_handler(struct ring_info *ring_data)
  2421. {
  2422. struct s2io_nic *nic = ring_data->nic;
  2423. struct net_device *dev = (struct net_device *) nic->dev;
  2424. int get_block, put_block, put_offset;
  2425. struct rx_curr_get_info get_info, put_info;
  2426. struct RxD_t *rxdp;
  2427. struct sk_buff *skb;
  2428. int pkt_cnt = 0;
  2429. int i;
  2430. spin_lock(&nic->rx_lock);
  2431. if (atomic_read(&nic->card_state) == CARD_DOWN) {
  2432. DBG_PRINT(INTR_DBG, "%s: %s going down for reset\n",
  2433. __FUNCTION__, dev->name);
  2434. spin_unlock(&nic->rx_lock);
  2435. return;
  2436. }
  2437. get_info = ring_data->rx_curr_get_info;
  2438. get_block = get_info.block_index;
  2439. memcpy(&put_info, &ring_data->rx_curr_put_info, sizeof(put_info));
  2440. put_block = put_info.block_index;
  2441. rxdp = ring_data->rx_blocks[get_block].rxds[get_info.offset].virt_addr;
  2442. if (!napi) {
  2443. spin_lock(&nic->put_lock);
  2444. put_offset = ring_data->put_pos;
  2445. spin_unlock(&nic->put_lock);
  2446. } else
  2447. put_offset = ring_data->put_pos;
  2448. while (RXD_IS_UP2DT(rxdp)) {
  2449. /*
  2450. * If your are next to put index then it's
  2451. * FIFO full condition
  2452. */
  2453. if ((get_block == put_block) &&
  2454. (get_info.offset + 1) == put_info.offset) {
  2455. DBG_PRINT(INTR_DBG, "%s: Ring Full\n",dev->name);
  2456. break;
  2457. }
  2458. skb = (struct sk_buff *) ((unsigned long)rxdp->Host_Control);
  2459. if (skb == NULL) {
  2460. DBG_PRINT(ERR_DBG, "%s: The skb is ",
  2461. dev->name);
  2462. DBG_PRINT(ERR_DBG, "Null in Rx Intr\n");
  2463. spin_unlock(&nic->rx_lock);
  2464. return;
  2465. }
  2466. if (nic->rxd_mode == RXD_MODE_1) {
  2467. pci_unmap_single(nic->pdev, (dma_addr_t)
  2468. ((struct RxD1*)rxdp)->Buffer0_ptr,
  2469. dev->mtu +
  2470. HEADER_ETHERNET_II_802_3_SIZE +
  2471. HEADER_802_2_SIZE +
  2472. HEADER_SNAP_SIZE,
  2473. PCI_DMA_FROMDEVICE);
  2474. } else if (nic->rxd_mode == RXD_MODE_3B) {
  2475. pci_dma_sync_single_for_cpu(nic->pdev, (dma_addr_t)
  2476. ((struct RxD3*)rxdp)->Buffer0_ptr,
  2477. BUF0_LEN, PCI_DMA_FROMDEVICE);
  2478. pci_unmap_single(nic->pdev, (dma_addr_t)
  2479. ((struct RxD3*)rxdp)->Buffer2_ptr,
  2480. dev->mtu + 4,
  2481. PCI_DMA_FROMDEVICE);
  2482. } else {
  2483. pci_dma_sync_single_for_cpu(nic->pdev, (dma_addr_t)
  2484. ((struct RxD3*)rxdp)->Buffer0_ptr, BUF0_LEN,
  2485. PCI_DMA_FROMDEVICE);
  2486. pci_unmap_single(nic->pdev, (dma_addr_t)
  2487. ((struct RxD3*)rxdp)->Buffer1_ptr,
  2488. l3l4hdr_size + 4,
  2489. PCI_DMA_FROMDEVICE);
  2490. pci_unmap_single(nic->pdev, (dma_addr_t)
  2491. ((struct RxD3*)rxdp)->Buffer2_ptr,
  2492. dev->mtu, PCI_DMA_FROMDEVICE);
  2493. }
  2494. prefetch(skb->data);
  2495. rx_osm_handler(ring_data, rxdp);
  2496. get_info.offset++;
  2497. ring_data->rx_curr_get_info.offset = get_info.offset;
  2498. rxdp = ring_data->rx_blocks[get_block].
  2499. rxds[get_info.offset].virt_addr;
  2500. if (get_info.offset == rxd_count[nic->rxd_mode]) {
  2501. get_info.offset = 0;
  2502. ring_data->rx_curr_get_info.offset = get_info.offset;
  2503. get_block++;
  2504. if (get_block == ring_data->block_count)
  2505. get_block = 0;
  2506. ring_data->rx_curr_get_info.block_index = get_block;
  2507. rxdp = ring_data->rx_blocks[get_block].block_virt_addr;
  2508. }
  2509. nic->pkts_to_process -= 1;
  2510. if ((napi) && (!nic->pkts_to_process))
  2511. break;
  2512. pkt_cnt++;
  2513. if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
  2514. break;
  2515. }
  2516. if (nic->lro) {
  2517. /* Clear all LRO sessions before exiting */
  2518. for (i=0; i<MAX_LRO_SESSIONS; i++) {
  2519. struct lro *lro = &nic->lro0_n[i];
  2520. if (lro->in_use) {
  2521. update_L3L4_header(nic, lro);
  2522. queue_rx_frame(lro->parent);
  2523. clear_lro_session(lro);
  2524. }
  2525. }
  2526. }
  2527. spin_unlock(&nic->rx_lock);
  2528. }
  2529. /**
  2530. * tx_intr_handler - Transmit interrupt handler
  2531. * @nic : device private variable
  2532. * Description:
  2533. * If an interrupt was raised to indicate DMA complete of the
  2534. * Tx packet, this function is called. It identifies the last TxD
  2535. * whose buffer was freed and frees all skbs whose data have already
  2536. * DMA'ed into the NICs internal memory.
  2537. * Return Value:
  2538. * NONE
  2539. */
  2540. static void tx_intr_handler(struct fifo_info *fifo_data)
  2541. {
  2542. struct s2io_nic *nic = fifo_data->nic;
  2543. struct net_device *dev = (struct net_device *) nic->dev;
  2544. struct tx_curr_get_info get_info, put_info;
  2545. struct sk_buff *skb;
  2546. struct TxD *txdlp;
  2547. get_info = fifo_data->tx_curr_get_info;
  2548. memcpy(&put_info, &fifo_data->tx_curr_put_info, sizeof(put_info));
  2549. txdlp = (struct TxD *) fifo_data->list_info[get_info.offset].
  2550. list_virt_addr;
  2551. while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
  2552. (get_info.offset != put_info.offset) &&
  2553. (txdlp->Host_Control)) {
  2554. /* Check for TxD errors */
  2555. if (txdlp->Control_1 & TXD_T_CODE) {
  2556. unsigned long long err;
  2557. err = txdlp->Control_1 & TXD_T_CODE;
  2558. if (err & 0x1) {
  2559. nic->mac_control.stats_info->sw_stat.
  2560. parity_err_cnt++;
  2561. }
  2562. if ((err >> 48) == 0xA) {
  2563. DBG_PRINT(TX_DBG, "TxD returned due \
  2564. to loss of link\n");
  2565. }
  2566. else {
  2567. DBG_PRINT(ERR_DBG, "***TxD error %llx\n", err);
  2568. }
  2569. }
  2570. skb = s2io_txdl_getskb(fifo_data, txdlp, get_info.offset);
  2571. if (skb == NULL) {
  2572. DBG_PRINT(ERR_DBG, "%s: Null skb ",
  2573. __FUNCTION__);
  2574. DBG_PRINT(ERR_DBG, "in Tx Free Intr\n");
  2575. return;
  2576. }
  2577. /* Updating the statistics block */
  2578. nic->stats.tx_bytes += skb->len;
  2579. dev_kfree_skb_irq(skb);
  2580. get_info.offset++;
  2581. if (get_info.offset == get_info.fifo_len + 1)
  2582. get_info.offset = 0;
  2583. txdlp = (struct TxD *) fifo_data->list_info
  2584. [get_info.offset].list_virt_addr;
  2585. fifo_data->tx_curr_get_info.offset =
  2586. get_info.offset;
  2587. }
  2588. spin_lock(&nic->tx_lock);
  2589. if (netif_queue_stopped(dev))
  2590. netif_wake_queue(dev);
  2591. spin_unlock(&nic->tx_lock);
  2592. }
  2593. /**
  2594. * s2io_mdio_write - Function to write in to MDIO registers
  2595. * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
  2596. * @addr : address value
  2597. * @value : data value
  2598. * @dev : pointer to net_device structure
  2599. * Description:
  2600. * This function is used to write values to the MDIO registers
  2601. * NONE
  2602. */
  2603. static void s2io_mdio_write(u32 mmd_type, u64 addr, u16 value, struct net_device *dev)
  2604. {
  2605. u64 val64 = 0x0;
  2606. struct s2io_nic *sp = dev->priv;
  2607. struct XENA_dev_config __iomem *bar0 = sp->bar0;
  2608. //address transaction
  2609. val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
  2610. | MDIO_MMD_DEV_ADDR(mmd_type)
  2611. | MDIO_MMS_PRT_ADDR(0x0);
  2612. writeq(val64, &bar0->mdio_control);
  2613. val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
  2614. writeq(val64, &bar0->mdio_control);
  2615. udelay(100);
  2616. //Data transaction
  2617. val64 = 0x0;
  2618. val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
  2619. | MDIO_MMD_DEV_ADDR(mmd_type)
  2620. | MDIO_MMS_PRT_ADDR(0x0)
  2621. | MDIO_MDIO_DATA(value)
  2622. | MDIO_OP(MDIO_OP_WRITE_TRANS);
  2623. writeq(val64, &bar0->mdio_control);
  2624. val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
  2625. writeq(val64, &bar0->mdio_control);
  2626. udelay(100);
  2627. val64 = 0x0;
  2628. val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
  2629. | MDIO_MMD_DEV_ADDR(mmd_type)
  2630. | MDIO_MMS_PRT_ADDR(0x0)
  2631. | MDIO_OP(MDIO_OP_READ_TRANS);
  2632. writeq(val64, &bar0->mdio_control);
  2633. val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
  2634. writeq(val64, &bar0->mdio_control);
  2635. udelay(100);
  2636. }
  2637. /**
  2638. * s2io_mdio_read - Function to write in to MDIO registers
  2639. * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
  2640. * @addr : address value
  2641. * @dev : pointer to net_device structure
  2642. * Description:
  2643. * This function is used to read values to the MDIO registers
  2644. * NONE
  2645. */
  2646. static u64 s2io_mdio_read(u32 mmd_type, u64 addr, struct net_device *dev)
  2647. {
  2648. u64 val64 = 0x0;
  2649. u64 rval64 = 0x0;
  2650. struct s2io_nic *sp = dev->priv;
  2651. struct XENA_dev_config __iomem *bar0 = sp->bar0;
  2652. /* address transaction */
  2653. val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
  2654. | MDIO_MMD_DEV_ADDR(mmd_type)
  2655. | MDIO_MMS_PRT_ADDR(0x0);
  2656. writeq(val64, &bar0->mdio_control);
  2657. val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
  2658. writeq(val64, &bar0->mdio_control);
  2659. udelay(100);
  2660. /* Data transaction */
  2661. val64 = 0x0;
  2662. val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
  2663. | MDIO_MMD_DEV_ADDR(mmd_type)
  2664. | MDIO_MMS_PRT_ADDR(0x0)
  2665. | MDIO_OP(MDIO_OP_READ_TRANS);
  2666. writeq(val64, &bar0->mdio_control);
  2667. val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
  2668. writeq(val64, &bar0->mdio_control);
  2669. udelay(100);
  2670. /* Read the value from regs */
  2671. rval64 = readq(&bar0->mdio_control);
  2672. rval64 = rval64 & 0xFFFF0000;
  2673. rval64 = rval64 >> 16;
  2674. return rval64;
  2675. }
  2676. /**
  2677. * s2io_chk_xpak_counter - Function to check the status of the xpak counters
  2678. * @counter : couter value to be updated
  2679. * @flag : flag to indicate the status
  2680. * @type : counter type
  2681. * Description:
  2682. * This function is to check the status of the xpak counters value
  2683. * NONE
  2684. */
  2685. static void s2io_chk_xpak_counter(u64 *counter, u64 * regs_stat, u32 index, u16 flag, u16 type)
  2686. {
  2687. u64 mask = 0x3;
  2688. u64 val64;
  2689. int i;
  2690. for(i = 0; i <index; i++)
  2691. mask = mask << 0x2;
  2692. if(flag > 0)
  2693. {
  2694. *counter = *counter + 1;
  2695. val64 = *regs_stat & mask;
  2696. val64 = val64 >> (index * 0x2);
  2697. val64 = val64 + 1;
  2698. if(val64 == 3)
  2699. {
  2700. switch(type)
  2701. {
  2702. case 1:
  2703. DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
  2704. "service. Excessive temperatures may "
  2705. "result in premature transceiver "
  2706. "failure \n");
  2707. break;
  2708. case 2:
  2709. DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
  2710. "service Excessive bias currents may "
  2711. "indicate imminent laser diode "
  2712. "failure \n");
  2713. break;
  2714. case 3:
  2715. DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
  2716. "service Excessive laser output "
  2717. "power may saturate far-end "
  2718. "receiver\n");
  2719. break;
  2720. default:
  2721. DBG_PRINT(ERR_DBG, "Incorrect XPAK Alarm "
  2722. "type \n");
  2723. }
  2724. val64 = 0x0;
  2725. }
  2726. val64 = val64 << (index * 0x2);
  2727. *regs_stat = (*regs_stat & (~mask)) | (val64);
  2728. } else {
  2729. *regs_stat = *regs_stat & (~mask);
  2730. }
  2731. }
  2732. /**
  2733. * s2io_updt_xpak_counter - Function to update the xpak counters
  2734. * @dev : pointer to net_device struct
  2735. * Description:
  2736. * This function is to upate the status of the xpak counters value
  2737. * NONE
  2738. */
  2739. static void s2io_updt_xpak_counter(struct net_device *dev)
  2740. {
  2741. u16 flag = 0x0;
  2742. u16 type = 0x0;
  2743. u16 val16 = 0x0;
  2744. u64 val64 = 0x0;
  2745. u64 addr = 0x0;
  2746. struct s2io_nic *sp = dev->priv;
  2747. struct stat_block *stat_info = sp->mac_control.stats_info;
  2748. /* Check the communication with the MDIO slave */
  2749. addr = 0x0000;
  2750. val64 = 0x0;
  2751. val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
  2752. if((val64 == 0xFFFF) || (val64 == 0x0000))
  2753. {
  2754. DBG_PRINT(ERR_DBG, "ERR: MDIO slave access failed - "
  2755. "Returned %llx\n", (unsigned long long)val64);
  2756. return;
  2757. }
  2758. /* Check for the expecte value of 2040 at PMA address 0x0000 */
  2759. if(val64 != 0x2040)
  2760. {
  2761. DBG_PRINT(ERR_DBG, "Incorrect value at PMA address 0x0000 - ");
  2762. DBG_PRINT(ERR_DBG, "Returned: %llx- Expected: 0x2040\n",
  2763. (unsigned long long)val64);
  2764. return;
  2765. }
  2766. /* Loading the DOM register to MDIO register */
  2767. addr = 0xA100;
  2768. s2io_mdio_write(MDIO_MMD_PMA_DEV_ADDR, addr, val16, dev);
  2769. val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
  2770. /* Reading the Alarm flags */
  2771. addr = 0xA070;
  2772. val64 = 0x0;
  2773. val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
  2774. flag = CHECKBIT(val64, 0x7);
  2775. type = 1;
  2776. s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_transceiver_temp_high,
  2777. &stat_info->xpak_stat.xpak_regs_stat,
  2778. 0x0, flag, type);
  2779. if(CHECKBIT(val64, 0x6))
  2780. stat_info->xpak_stat.alarm_transceiver_temp_low++;
  2781. flag = CHECKBIT(val64, 0x3);
  2782. type = 2;
  2783. s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_bias_current_high,
  2784. &stat_info->xpak_stat.xpak_regs_stat,
  2785. 0x2, flag, type);
  2786. if(CHECKBIT(val64, 0x2))
  2787. stat_info->xpak_stat.alarm_laser_bias_current_low++;
  2788. flag = CHECKBIT(val64, 0x1);
  2789. type = 3;
  2790. s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_output_power_high,
  2791. &stat_info->xpak_stat.xpak_regs_stat,
  2792. 0x4, flag, type);
  2793. if(CHECKBIT(val64, 0x0))
  2794. stat_info->xpak_stat.alarm_laser_output_power_low++;
  2795. /* Reading the Warning flags */
  2796. addr = 0xA074;
  2797. val64 = 0x0;
  2798. val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
  2799. if(CHECKBIT(val64, 0x7))
  2800. stat_info->xpak_stat.warn_transceiver_temp_high++;
  2801. if(CHECKBIT(val64, 0x6))
  2802. stat_info->xpak_stat.warn_transceiver_temp_low++;
  2803. if(CHECKBIT(val64, 0x3))
  2804. stat_info->xpak_stat.warn_laser_bias_current_high++;
  2805. if(CHECKBIT(val64, 0x2))
  2806. stat_info->xpak_stat.warn_laser_bias_current_low++;
  2807. if(CHECKBIT(val64, 0x1))
  2808. stat_info->xpak_stat.warn_laser_output_power_high++;
  2809. if(CHECKBIT(val64, 0x0))
  2810. stat_info->xpak_stat.warn_laser_output_power_low++;
  2811. }
  2812. /**
  2813. * alarm_intr_handler - Alarm Interrrupt handler
  2814. * @nic: device private variable
  2815. * Description: If the interrupt was neither because of Rx packet or Tx
  2816. * complete, this function is called. If the interrupt was to indicate
  2817. * a loss of link, the OSM link status handler is invoked for any other
  2818. * alarm interrupt the block that raised the interrupt is displayed
  2819. * and a H/W reset is issued.
  2820. * Return Value:
  2821. * NONE
  2822. */
  2823. static void alarm_intr_handler(struct s2io_nic *nic)
  2824. {
  2825. struct net_device *dev = (struct net_device *) nic->dev;
  2826. struct XENA_dev_config __iomem *bar0 = nic->bar0;
  2827. register u64 val64 = 0, err_reg = 0;
  2828. u64 cnt;
  2829. int i;
  2830. if (atomic_read(&nic->card_state) == CARD_DOWN)
  2831. return;
  2832. nic->mac_control.stats_info->sw_stat.ring_full_cnt = 0;
  2833. /* Handling the XPAK counters update */
  2834. if(nic->mac_control.stats_info->xpak_stat.xpak_timer_count < 72000) {
  2835. /* waiting for an hour */
  2836. nic->mac_control.stats_info->xpak_stat.xpak_timer_count++;
  2837. } else {
  2838. s2io_updt_xpak_counter(dev);
  2839. /* reset the count to zero */
  2840. nic->mac_control.stats_info->xpak_stat.xpak_timer_count = 0;
  2841. }
  2842. /* Handling link status change error Intr */
  2843. if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
  2844. err_reg = readq(&bar0->mac_rmac_err_reg);
  2845. writeq(err_reg, &bar0->mac_rmac_err_reg);
  2846. if (err_reg & RMAC_LINK_STATE_CHANGE_INT) {
  2847. schedule_work(&nic->set_link_task);
  2848. }
  2849. }
  2850. /* Handling Ecc errors */
  2851. val64 = readq(&bar0->mc_err_reg);
  2852. writeq(val64, &bar0->mc_err_reg);
  2853. if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) {
  2854. if (val64 & MC_ERR_REG_ECC_ALL_DBL) {
  2855. nic->mac_control.stats_info->sw_stat.
  2856. double_ecc_errs++;
  2857. DBG_PRINT(INIT_DBG, "%s: Device indicates ",
  2858. dev->name);
  2859. DBG_PRINT(INIT_DBG, "double ECC error!!\n");
  2860. if (nic->device_type != XFRAME_II_DEVICE) {
  2861. /* Reset XframeI only if critical error */
  2862. if (val64 & (MC_ERR_REG_MIRI_ECC_DB_ERR_0 |
  2863. MC_ERR_REG_MIRI_ECC_DB_ERR_1)) {
  2864. netif_stop_queue(dev);
  2865. schedule_work(&nic->rst_timer_task);
  2866. nic->mac_control.stats_info->sw_stat.
  2867. soft_reset_cnt++;
  2868. }
  2869. }
  2870. } else {
  2871. nic->mac_control.stats_info->sw_stat.
  2872. single_ecc_errs++;
  2873. }
  2874. }
  2875. /* In case of a serious error, the device will be Reset. */
  2876. val64 = readq(&bar0->serr_source);
  2877. if (val64 & SERR_SOURCE_ANY) {
  2878. nic->mac_control.stats_info->sw_stat.serious_err_cnt++;
  2879. DBG_PRINT(ERR_DBG, "%s: Device indicates ", dev->name);
  2880. DBG_PRINT(ERR_DBG, "serious error %llx!!\n",
  2881. (unsigned long long)val64);
  2882. netif_stop_queue(dev);
  2883. schedule_work(&nic->rst_timer_task);
  2884. nic->mac_control.stats_info->sw_stat.soft_reset_cnt++;
  2885. }
  2886. /*
  2887. * Also as mentioned in the latest Errata sheets if the PCC_FB_ECC
  2888. * Error occurs, the adapter will be recycled by disabling the
  2889. * adapter enable bit and enabling it again after the device
  2890. * becomes Quiescent.
  2891. */
  2892. val64 = readq(&bar0->pcc_err_reg);
  2893. writeq(val64, &bar0->pcc_err_reg);
  2894. if (val64 & PCC_FB_ECC_DB_ERR) {
  2895. u64 ac = readq(&bar0->adapter_control);
  2896. ac &= ~(ADAPTER_CNTL_EN);
  2897. writeq(ac, &bar0->adapter_control);
  2898. ac = readq(&bar0->adapter_control);
  2899. schedule_work(&nic->set_link_task);
  2900. }
  2901. /* Check for data parity error */
  2902. val64 = readq(&bar0->pic_int_status);
  2903. if (val64 & PIC_INT_GPIO) {
  2904. val64 = readq(&bar0->gpio_int_reg);
  2905. if (val64 & GPIO_INT_REG_DP_ERR_INT) {
  2906. nic->mac_control.stats_info->sw_stat.parity_err_cnt++;
  2907. schedule_work(&nic->rst_timer_task);
  2908. nic->mac_control.stats_info->sw_stat.soft_reset_cnt++;
  2909. }
  2910. }
  2911. /* Check for ring full counter */
  2912. if (nic->device_type & XFRAME_II_DEVICE) {
  2913. val64 = readq(&bar0->ring_bump_counter1);
  2914. for (i=0; i<4; i++) {
  2915. cnt = ( val64 & vBIT(0xFFFF,(i*16),16));
  2916. cnt >>= 64 - ((i+1)*16);
  2917. nic->mac_control.stats_info->sw_stat.ring_full_cnt
  2918. += cnt;
  2919. }
  2920. val64 = readq(&bar0->ring_bump_counter2);
  2921. for (i=0; i<4; i++) {
  2922. cnt = ( val64 & vBIT(0xFFFF,(i*16),16));
  2923. cnt >>= 64 - ((i+1)*16);
  2924. nic->mac_control.stats_info->sw_stat.ring_full_cnt
  2925. += cnt;
  2926. }
  2927. }
  2928. /* Other type of interrupts are not being handled now, TODO */
  2929. }
  2930. /**
  2931. * wait_for_cmd_complete - waits for a command to complete.
  2932. * @sp : private member of the device structure, which is a pointer to the
  2933. * s2io_nic structure.
  2934. * Description: Function that waits for a command to Write into RMAC
  2935. * ADDR DATA registers to be completed and returns either success or
  2936. * error depending on whether the command was complete or not.
  2937. * Return value:
  2938. * SUCCESS on success and FAILURE on failure.
  2939. */
  2940. static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit,
  2941. int bit_state)
  2942. {
  2943. int ret = FAILURE, cnt = 0, delay = 1;
  2944. u64 val64;
  2945. if ((bit_state != S2IO_BIT_RESET) && (bit_state != S2IO_BIT_SET))
  2946. return FAILURE;
  2947. do {
  2948. val64 = readq(addr);
  2949. if (bit_state == S2IO_BIT_RESET) {
  2950. if (!(val64 & busy_bit)) {
  2951. ret = SUCCESS;
  2952. break;
  2953. }
  2954. } else {
  2955. if (!(val64 & busy_bit)) {
  2956. ret = SUCCESS;
  2957. break;
  2958. }
  2959. }
  2960. if(in_interrupt())
  2961. mdelay(delay);
  2962. else
  2963. msleep(delay);
  2964. if (++cnt >= 10)
  2965. delay = 50;
  2966. } while (cnt < 20);
  2967. return ret;
  2968. }
  2969. /*
  2970. * check_pci_device_id - Checks if the device id is supported
  2971. * @id : device id
  2972. * Description: Function to check if the pci device id is supported by driver.
  2973. * Return value: Actual device id if supported else PCI_ANY_ID
  2974. */
  2975. static u16 check_pci_device_id(u16 id)
  2976. {
  2977. switch (id) {
  2978. case PCI_DEVICE_ID_HERC_WIN:
  2979. case PCI_DEVICE_ID_HERC_UNI:
  2980. return XFRAME_II_DEVICE;
  2981. case PCI_DEVICE_ID_S2IO_UNI:
  2982. case PCI_DEVICE_ID_S2IO_WIN:
  2983. return XFRAME_I_DEVICE;
  2984. default:
  2985. return PCI_ANY_ID;
  2986. }
  2987. }
  2988. /**
  2989. * s2io_reset - Resets the card.
  2990. * @sp : private member of the device structure.
  2991. * Description: Function to Reset the card. This function then also
  2992. * restores the previously saved PCI configuration space registers as
  2993. * the card reset also resets the configuration space.
  2994. * Return value:
  2995. * void.
  2996. */
  2997. static void s2io_reset(struct s2io_nic * sp)
  2998. {
  2999. struct XENA_dev_config __iomem *bar0 = sp->bar0;
  3000. u64 val64;
  3001. u16 subid, pci_cmd;
  3002. int i;
  3003. u16 val16;
  3004. DBG_PRINT(INIT_DBG,"%s - Resetting XFrame card %s\n",
  3005. __FUNCTION__, sp->dev->name);
  3006. /* Back up the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
  3007. pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd));
  3008. if (sp->device_type == XFRAME_II_DEVICE) {
  3009. int ret;
  3010. ret = pci_set_power_state(sp->pdev, 3);
  3011. if (!ret)
  3012. ret = pci_set_power_state(sp->pdev, 0);
  3013. else {
  3014. DBG_PRINT(ERR_DBG,"%s PME based SW_Reset failed!\n",
  3015. __FUNCTION__);
  3016. goto old_way;
  3017. }
  3018. msleep(20);
  3019. goto new_way;
  3020. }
  3021. old_way:
  3022. val64 = SW_RESET_ALL;
  3023. writeq(val64, &bar0->sw_reset);
  3024. new_way:
  3025. if (strstr(sp->product_name, "CX4")) {
  3026. msleep(750);
  3027. }
  3028. msleep(250);
  3029. for (i = 0; i < S2IO_MAX_PCI_CONFIG_SPACE_REINIT; i++) {
  3030. /* Restore the PCI state saved during initialization. */
  3031. pci_restore_state(sp->pdev);
  3032. pci_read_config_word(sp->pdev, 0x2, &val16);
  3033. if (check_pci_device_id(val16) != (u16)PCI_ANY_ID)
  3034. break;
  3035. msleep(200);
  3036. }
  3037. if (check_pci_device_id(val16) == (u16)PCI_ANY_ID) {
  3038. DBG_PRINT(ERR_DBG,"%s SW_Reset failed!\n", __FUNCTION__);
  3039. }
  3040. pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, pci_cmd);
  3041. s2io_init_pci(sp);
  3042. /* Set swapper to enable I/O register access */
  3043. s2io_set_swapper(sp);
  3044. /* Restore the MSIX table entries from local variables */
  3045. restore_xmsi_data(sp);
  3046. /* Clear certain PCI/PCI-X fields after reset */
  3047. if (sp->device_type == XFRAME_II_DEVICE) {
  3048. /* Clear "detected parity error" bit */
  3049. pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000);
  3050. /* Clearing PCIX Ecc status register */
  3051. pci_write_config_dword(sp->pdev, 0x68, 0x7C);
  3052. /* Clearing PCI_STATUS error reflected here */
  3053. writeq(BIT(62), &bar0->txpic_int_reg);
  3054. }
  3055. /* Reset device statistics maintained by OS */
  3056. memset(&sp->stats, 0, sizeof (struct net_device_stats));
  3057. /* SXE-002: Configure link and activity LED to turn it off */
  3058. subid = sp->pdev->subsystem_device;
  3059. if (((subid & 0xFF) >= 0x07) &&
  3060. (sp->device_type == XFRAME_I_DEVICE)) {
  3061. val64 = readq(&bar0->gpio_control);
  3062. val64 |= 0x0000800000000000ULL;
  3063. writeq(val64, &bar0->gpio_control);
  3064. val64 = 0x0411040400000000ULL;
  3065. writeq(val64, (void __iomem *)bar0 + 0x2700);
  3066. }
  3067. /*
  3068. * Clear spurious ECC interrupts that would have occured on
  3069. * XFRAME II cards after reset.
  3070. */
  3071. if (sp->device_type == XFRAME_II_DEVICE) {
  3072. val64 = readq(&bar0->pcc_err_reg);
  3073. writeq(val64, &bar0->pcc_err_reg);
  3074. }
  3075. sp->device_enabled_once = FALSE;
  3076. }
  3077. /**
  3078. * s2io_set_swapper - to set the swapper controle on the card
  3079. * @sp : private member of the device structure,
  3080. * pointer to the s2io_nic structure.
  3081. * Description: Function to set the swapper control on the card
  3082. * correctly depending on the 'endianness' of the system.
  3083. * Return value:
  3084. * SUCCESS on success and FAILURE on failure.
  3085. */
  3086. static int s2io_set_swapper(struct s2io_nic * sp)
  3087. {
  3088. struct net_device *dev = sp->dev;
  3089. struct XENA_dev_config __iomem *bar0 = sp->bar0;
  3090. u64 val64, valt, valr;
  3091. /*
  3092. * Set proper endian settings and verify the same by reading
  3093. * the PIF Feed-back register.
  3094. */
  3095. val64 = readq(&bar0->pif_rd_swapper_fb);
  3096. if (val64 != 0x0123456789ABCDEFULL) {
  3097. int i = 0;
  3098. u64 value[] = { 0xC30000C3C30000C3ULL, /* FE=1, SE=1 */
  3099. 0x8100008181000081ULL, /* FE=1, SE=0 */
  3100. 0x4200004242000042ULL, /* FE=0, SE=1 */
  3101. 0}; /* FE=0, SE=0 */
  3102. while(i<4) {
  3103. writeq(value[i], &bar0->swapper_ctrl);
  3104. val64 = readq(&bar0->pif_rd_swapper_fb);
  3105. if (val64 == 0x0123456789ABCDEFULL)
  3106. break;
  3107. i++;
  3108. }
  3109. if (i == 4) {
  3110. DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
  3111. dev->name);
  3112. DBG_PRINT(ERR_DBG, "feedback read %llx\n",
  3113. (unsigned long long) val64);
  3114. return FAILURE;
  3115. }
  3116. valr = value[i];
  3117. } else {
  3118. valr = readq(&bar0->swapper_ctrl);
  3119. }
  3120. valt = 0x0123456789ABCDEFULL;
  3121. writeq(valt, &bar0->xmsi_address);
  3122. val64 = readq(&bar0->xmsi_address);
  3123. if(val64 != valt) {
  3124. int i = 0;
  3125. u64 value[] = { 0x00C3C30000C3C300ULL, /* FE=1, SE=1 */
  3126. 0x0081810000818100ULL, /* FE=1, SE=0 */
  3127. 0x0042420000424200ULL, /* FE=0, SE=1 */
  3128. 0}; /* FE=0, SE=0 */
  3129. while(i<4) {
  3130. writeq((value[i] | valr), &bar0->swapper_ctrl);
  3131. writeq(valt, &bar0->xmsi_address);
  3132. val64 = readq(&bar0->xmsi_address);
  3133. if(val64 == valt)
  3134. break;
  3135. i++;
  3136. }
  3137. if(i == 4) {
  3138. unsigned long long x = val64;
  3139. DBG_PRINT(ERR_DBG, "Write failed, Xmsi_addr ");
  3140. DBG_PRINT(ERR_DBG, "reads:0x%llx\n", x);
  3141. return FAILURE;
  3142. }
  3143. }
  3144. val64 = readq(&bar0->swapper_ctrl);
  3145. val64 &= 0xFFFF000000000000ULL;
  3146. #ifdef __BIG_ENDIAN
  3147. /*
  3148. * The device by default set to a big endian format, so a
  3149. * big endian driver need not set anything.
  3150. */
  3151. val64 |= (SWAPPER_CTRL_TXP_FE |
  3152. SWAPPER_CTRL_TXP_SE |
  3153. SWAPPER_CTRL_TXD_R_FE |
  3154. SWAPPER_CTRL_TXD_W_FE |
  3155. SWAPPER_CTRL_TXF_R_FE |
  3156. SWAPPER_CTRL_RXD_R_FE |
  3157. SWAPPER_CTRL_RXD_W_FE |
  3158. SWAPPER_CTRL_RXF_W_FE |
  3159. SWAPPER_CTRL_XMSI_FE |
  3160. SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
  3161. if (sp->intr_type == INTA)
  3162. val64 |= SWAPPER_CTRL_XMSI_SE;
  3163. writeq(val64, &bar0->swapper_ctrl);
  3164. #else
  3165. /*
  3166. * Initially we enable all bits to make it accessible by the
  3167. * driver, then we selectively enable only those bits that
  3168. * we want to set.
  3169. */
  3170. val64 |= (SWAPPER_CTRL_TXP_FE |
  3171. SWAPPER_CTRL_TXP_SE |
  3172. SWAPPER_CTRL_TXD_R_FE |
  3173. SWAPPER_CTRL_TXD_R_SE |
  3174. SWAPPER_CTRL_TXD_W_FE |
  3175. SWAPPER_CTRL_TXD_W_SE |
  3176. SWAPPER_CTRL_TXF_R_FE |
  3177. SWAPPER_CTRL_RXD_R_FE |
  3178. SWAPPER_CTRL_RXD_R_SE |
  3179. SWAPPER_CTRL_RXD_W_FE |
  3180. SWAPPER_CTRL_RXD_W_SE |
  3181. SWAPPER_CTRL_RXF_W_FE |
  3182. SWAPPER_CTRL_XMSI_FE |
  3183. SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
  3184. if (sp->intr_type == INTA)
  3185. val64 |= SWAPPER_CTRL_XMSI_SE;
  3186. writeq(val64, &bar0->swapper_ctrl);
  3187. #endif
  3188. val64 = readq(&bar0->swapper_ctrl);
  3189. /*
  3190. * Verifying if endian settings are accurate by reading a
  3191. * feedback register.
  3192. */
  3193. val64 = readq(&bar0->pif_rd_swapper_fb);
  3194. if (val64 != 0x0123456789ABCDEFULL) {
  3195. /* Endian settings are incorrect, calls for another dekko. */
  3196. DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
  3197. dev->name);
  3198. DBG_PRINT(ERR_DBG, "feedback read %llx\n",
  3199. (unsigned long long) val64);
  3200. return FAILURE;
  3201. }
  3202. return SUCCESS;
  3203. }
  3204. static int wait_for_msix_trans(struct s2io_nic *nic, int i)
  3205. {
  3206. struct XENA_dev_config __iomem *bar0 = nic->bar0;
  3207. u64 val64;
  3208. int ret = 0, cnt = 0;
  3209. do {
  3210. val64 = readq(&bar0->xmsi_access);
  3211. if (!(val64 & BIT(15)))
  3212. break;
  3213. mdelay(1);
  3214. cnt++;
  3215. } while(cnt < 5);
  3216. if (cnt == 5) {
  3217. DBG_PRINT(ERR_DBG, "XMSI # %d Access failed\n", i);
  3218. ret = 1;
  3219. }
  3220. return ret;
  3221. }
  3222. static void restore_xmsi_data(struct s2io_nic *nic)
  3223. {
  3224. struct XENA_dev_config __iomem *bar0 = nic->bar0;
  3225. u64 val64;
  3226. int i;
  3227. for (i=0; i < MAX_REQUESTED_MSI_X; i++) {
  3228. writeq(nic->msix_info[i].addr, &bar0->xmsi_address);
  3229. writeq(nic->msix_info[i].data, &bar0->xmsi_data);
  3230. val64 = (BIT(7) | BIT(15) | vBIT(i, 26, 6));
  3231. writeq(val64, &bar0->xmsi_access);
  3232. if (wait_for_msix_trans(nic, i)) {
  3233. DBG_PRINT(ERR_DBG, "failed in %s\n", __FUNCTION__);
  3234. continue;
  3235. }
  3236. }
  3237. }
  3238. static void store_xmsi_data(struct s2io_nic *nic)
  3239. {
  3240. struct XENA_dev_config __iomem *bar0 = nic->bar0;
  3241. u64 val64, addr, data;
  3242. int i;
  3243. /* Store and display */
  3244. for (i=0; i < MAX_REQUESTED_MSI_X; i++) {
  3245. val64 = (BIT(15) | vBIT(i, 26, 6));
  3246. writeq(val64, &bar0->xmsi_access);
  3247. if (wait_for_msix_trans(nic, i)) {
  3248. DBG_PRINT(ERR_DBG, "failed in %s\n", __FUNCTION__);
  3249. continue;
  3250. }
  3251. addr = readq(&bar0->xmsi_address);
  3252. data = readq(&bar0->xmsi_data);
  3253. if (addr && data) {
  3254. nic->msix_info[i].addr = addr;
  3255. nic->msix_info[i].data = data;
  3256. }
  3257. }
  3258. }
  3259. int s2io_enable_msi(struct s2io_nic *nic)
  3260. {
  3261. struct XENA_dev_config __iomem *bar0 = nic->bar0;
  3262. u16 msi_ctrl, msg_val;
  3263. struct config_param *config = &nic->config;
  3264. struct net_device *dev = nic->dev;
  3265. u64 val64, tx_mat, rx_mat;
  3266. int i, err;
  3267. val64 = readq(&bar0->pic_control);
  3268. val64 &= ~BIT(1);
  3269. writeq(val64, &bar0->pic_control);
  3270. err = pci_enable_msi(nic->pdev);
  3271. if (err) {
  3272. DBG_PRINT(ERR_DBG, "%s: enabling MSI failed\n",
  3273. nic->dev->name);
  3274. return err;
  3275. }
  3276. /*
  3277. * Enable MSI and use MSI-1 in stead of the standard MSI-0
  3278. * for interrupt handling.
  3279. */
  3280. pci_read_config_word(nic->pdev, 0x4c, &msg_val);
  3281. msg_val ^= 0x1;
  3282. pci_write_config_word(nic->pdev, 0x4c, msg_val);
  3283. pci_read_config_word(nic->pdev, 0x4c, &msg_val);
  3284. pci_read_config_word(nic->pdev, 0x42, &msi_ctrl);
  3285. msi_ctrl |= 0x10;
  3286. pci_write_config_word(nic->pdev, 0x42, msi_ctrl);
  3287. /* program MSI-1 into all usable Tx_Mat and Rx_Mat fields */
  3288. tx_mat = readq(&bar0->tx_mat0_n[0]);
  3289. for (i=0; i<config->tx_fifo_num; i++) {
  3290. tx_mat |= TX_MAT_SET(i, 1);
  3291. }
  3292. writeq(tx_mat, &bar0->tx_mat0_n[0]);
  3293. rx_mat = readq(&bar0->rx_mat);
  3294. for (i=0; i<config->rx_ring_num; i++) {
  3295. rx_mat |= RX_MAT_SET(i, 1);
  3296. }
  3297. writeq(rx_mat, &bar0->rx_mat);
  3298. dev->irq = nic->pdev->irq;
  3299. return 0;
  3300. }
  3301. static int s2io_enable_msi_x(struct s2io_nic *nic)
  3302. {
  3303. struct XENA_dev_config __iomem *bar0 = nic->bar0;
  3304. u64 tx_mat, rx_mat;
  3305. u16 msi_control; /* Temp variable */
  3306. int ret, i, j, msix_indx = 1;
  3307. nic->entries = kmalloc(MAX_REQUESTED_MSI_X * sizeof(struct msix_entry),
  3308. GFP_KERNEL);
  3309. if (nic->entries == NULL) {
  3310. DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n", __FUNCTION__);
  3311. return -ENOMEM;
  3312. }
  3313. memset(nic->entries, 0, MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
  3314. nic->s2io_entries =
  3315. kmalloc(MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry),
  3316. GFP_KERNEL);
  3317. if (nic->s2io_entries == NULL) {
  3318. DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n", __FUNCTION__);
  3319. kfree(nic->entries);
  3320. return -ENOMEM;
  3321. }
  3322. memset(nic->s2io_entries, 0,
  3323. MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry));
  3324. for (i=0; i< MAX_REQUESTED_MSI_X; i++) {
  3325. nic->entries[i].entry = i;
  3326. nic->s2io_entries[i].entry = i;
  3327. nic->s2io_entries[i].arg = NULL;
  3328. nic->s2io_entries[i].in_use = 0;
  3329. }
  3330. tx_mat = readq(&bar0->tx_mat0_n[0]);
  3331. for (i=0; i<nic->config.tx_fifo_num; i++, msix_indx++) {
  3332. tx_mat |= TX_MAT_SET(i, msix_indx);
  3333. nic->s2io_entries[msix_indx].arg = &nic->mac_control.fifos[i];
  3334. nic->s2io_entries[msix_indx].type = MSIX_FIFO_TYPE;
  3335. nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
  3336. }
  3337. writeq(tx_mat, &bar0->tx_mat0_n[0]);
  3338. if (!nic->config.bimodal) {
  3339. rx_mat = readq(&bar0->rx_mat);
  3340. for (j=0; j<nic->config.rx_ring_num; j++, msix_indx++) {
  3341. rx_mat |= RX_MAT_SET(j, msix_indx);
  3342. nic->s2io_entries[msix_indx].arg = &nic->mac_control.rings[j];
  3343. nic->s2io_entries[msix_indx].type = MSIX_RING_TYPE;
  3344. nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
  3345. }
  3346. writeq(rx_mat, &bar0->rx_mat);
  3347. } else {
  3348. tx_mat = readq(&bar0->tx_mat0_n[7]);
  3349. for (j=0; j<nic->config.rx_ring_num; j++, msix_indx++) {
  3350. tx_mat |= TX_MAT_SET(i, msix_indx);
  3351. nic->s2io_entries[msix_indx].arg = &nic->mac_control.rings[j];
  3352. nic->s2io_entries[msix_indx].type = MSIX_RING_TYPE;
  3353. nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
  3354. }
  3355. writeq(tx_mat, &bar0->tx_mat0_n[7]);
  3356. }
  3357. nic->avail_msix_vectors = 0;
  3358. ret = pci_enable_msix(nic->pdev, nic->entries, MAX_REQUESTED_MSI_X);
  3359. /* We fail init if error or we get less vectors than min required */
  3360. if (ret >= (nic->config.tx_fifo_num + nic->config.rx_ring_num + 1)) {
  3361. nic->avail_msix_vectors = ret;
  3362. ret = pci_enable_msix(nic->pdev, nic->entries, ret);
  3363. }
  3364. if (ret) {
  3365. DBG_PRINT(ERR_DBG, "%s: Enabling MSIX failed\n", nic->dev->name);
  3366. kfree(nic->entries);
  3367. kfree(nic->s2io_entries);
  3368. nic->entries = NULL;
  3369. nic->s2io_entries = NULL;
  3370. nic->avail_msix_vectors = 0;
  3371. return -ENOMEM;
  3372. }
  3373. if (!nic->avail_msix_vectors)
  3374. nic->avail_msix_vectors = MAX_REQUESTED_MSI_X;
  3375. /*
  3376. * To enable MSI-X, MSI also needs to be enabled, due to a bug
  3377. * in the herc NIC. (Temp change, needs to be removed later)
  3378. */
  3379. pci_read_config_word(nic->pdev, 0x42, &msi_control);
  3380. msi_control |= 0x1; /* Enable MSI */
  3381. pci_write_config_word(nic->pdev, 0x42, msi_control);
  3382. return 0;
  3383. }
  3384. /* ********************************************************* *
  3385. * Functions defined below concern the OS part of the driver *
  3386. * ********************************************************* */
  3387. /**
  3388. * s2io_open - open entry point of the driver
  3389. * @dev : pointer to the device structure.
  3390. * Description:
  3391. * This function is the open entry point of the driver. It mainly calls a
  3392. * function to allocate Rx buffers and inserts them into the buffer
  3393. * descriptors and then enables the Rx part of the NIC.
  3394. * Return value:
  3395. * 0 on success and an appropriate (-)ve integer as defined in errno.h
  3396. * file on failure.
  3397. */
  3398. static int s2io_open(struct net_device *dev)
  3399. {
  3400. struct s2io_nic *sp = dev->priv;
  3401. int err = 0;
  3402. /*
  3403. * Make sure you have link off by default every time
  3404. * Nic is initialized
  3405. */
  3406. netif_carrier_off(dev);
  3407. sp->last_link_state = 0;
  3408. /* Initialize H/W and enable interrupts */
  3409. err = s2io_card_up(sp);
  3410. if (err) {
  3411. DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
  3412. dev->name);
  3413. goto hw_init_failed;
  3414. }
  3415. if (s2io_set_mac_addr(dev, dev->dev_addr) == FAILURE) {
  3416. DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n");
  3417. s2io_card_down(sp);
  3418. err = -ENODEV;
  3419. goto hw_init_failed;
  3420. }
  3421. netif_start_queue(dev);
  3422. return 0;
  3423. hw_init_failed:
  3424. if (sp->intr_type == MSI_X) {
  3425. if (sp->entries)
  3426. kfree(sp->entries);
  3427. if (sp->s2io_entries)
  3428. kfree(sp->s2io_entries);
  3429. }
  3430. return err;
  3431. }
  3432. /**
  3433. * s2io_close -close entry point of the driver
  3434. * @dev : device pointer.
  3435. * Description:
  3436. * This is the stop entry point of the driver. It needs to undo exactly
  3437. * whatever was done by the open entry point,thus it's usually referred to
  3438. * as the close function.Among other things this function mainly stops the
  3439. * Rx side of the NIC and frees all the Rx buffers in the Rx rings.
  3440. * Return value:
  3441. * 0 on success and an appropriate (-)ve integer as defined in errno.h
  3442. * file on failure.
  3443. */
  3444. static int s2io_close(struct net_device *dev)
  3445. {
  3446. struct s2io_nic *sp = dev->priv;
  3447. netif_stop_queue(dev);
  3448. /* Reset card, kill tasklet and free Tx and Rx buffers. */
  3449. s2io_card_down(sp);
  3450. sp->device_close_flag = TRUE; /* Device is shut down. */
  3451. return 0;
  3452. }
  3453. /**
  3454. * s2io_xmit - Tx entry point of te driver
  3455. * @skb : the socket buffer containing the Tx data.
  3456. * @dev : device pointer.
  3457. * Description :
  3458. * This function is the Tx entry point of the driver. S2IO NIC supports
  3459. * certain protocol assist features on Tx side, namely CSO, S/G, LSO.
  3460. * NOTE: when device cant queue the pkt,just the trans_start variable will
  3461. * not be upadted.
  3462. * Return value:
  3463. * 0 on success & 1 on failure.
  3464. */
  3465. static int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
  3466. {
  3467. struct s2io_nic *sp = dev->priv;
  3468. u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off;
  3469. register u64 val64;
  3470. struct TxD *txdp;
  3471. struct TxFIFO_element __iomem *tx_fifo;
  3472. unsigned long flags;
  3473. u16 vlan_tag = 0;
  3474. int vlan_priority = 0;
  3475. struct mac_info *mac_control;
  3476. struct config_param *config;
  3477. int offload_type;
  3478. mac_control = &sp->mac_control;
  3479. config = &sp->config;
  3480. DBG_PRINT(TX_DBG, "%s: In Neterion Tx routine\n", dev->name);
  3481. spin_lock_irqsave(&sp->tx_lock, flags);
  3482. if (atomic_read(&sp->card_state) == CARD_DOWN) {
  3483. DBG_PRINT(TX_DBG, "%s: Card going down for reset\n",
  3484. dev->name);
  3485. spin_unlock_irqrestore(&sp->tx_lock, flags);
  3486. dev_kfree_skb(skb);
  3487. return 0;
  3488. }
  3489. queue = 0;
  3490. /* Get Fifo number to Transmit based on vlan priority */
  3491. if (sp->vlgrp && vlan_tx_tag_present(skb)) {
  3492. vlan_tag = vlan_tx_tag_get(skb);
  3493. vlan_priority = vlan_tag >> 13;
  3494. queue = config->fifo_mapping[vlan_priority];
  3495. }
  3496. put_off = (u16) mac_control->fifos[queue].tx_curr_put_info.offset;
  3497. get_off = (u16) mac_control->fifos[queue].tx_curr_get_info.offset;
  3498. txdp = (struct TxD *) mac_control->fifos[queue].list_info[put_off].
  3499. list_virt_addr;
  3500. queue_len = mac_control->fifos[queue].tx_curr_put_info.fifo_len + 1;
  3501. /* Avoid "put" pointer going beyond "get" pointer */
  3502. if (txdp->Host_Control ||
  3503. ((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
  3504. DBG_PRINT(TX_DBG, "Error in xmit, No free TXDs.\n");
  3505. netif_stop_queue(dev);
  3506. dev_kfree_skb(skb);
  3507. spin_unlock_irqrestore(&sp->tx_lock, flags);
  3508. return 0;
  3509. }
  3510. /* A buffer with no data will be dropped */
  3511. if (!skb->len) {
  3512. DBG_PRINT(TX_DBG, "%s:Buffer has no data..\n", dev->name);
  3513. dev_kfree_skb(skb);
  3514. spin_unlock_irqrestore(&sp->tx_lock, flags);
  3515. return 0;
  3516. }
  3517. offload_type = s2io_offload_type(skb);
  3518. if (offload_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
  3519. txdp->Control_1 |= TXD_TCP_LSO_EN;
  3520. txdp->Control_1 |= TXD_TCP_LSO_MSS(s2io_tcp_mss(skb));
  3521. }
  3522. if (skb->ip_summed == CHECKSUM_PARTIAL) {
  3523. txdp->Control_2 |=
  3524. (TXD_TX_CKO_IPV4_EN | TXD_TX_CKO_TCP_EN |
  3525. TXD_TX_CKO_UDP_EN);
  3526. }
  3527. txdp->Control_1 |= TXD_GATHER_CODE_FIRST;
  3528. txdp->Control_1 |= TXD_LIST_OWN_XENA;
  3529. txdp->Control_2 |= config->tx_intr_type;
  3530. if (sp->vlgrp && vlan_tx_tag_present(skb)) {
  3531. txdp->Control_2 |= TXD_VLAN_ENABLE;
  3532. txdp->Control_2 |= TXD_VLAN_TAG(vlan_tag);
  3533. }
  3534. frg_len = skb->len - skb->data_len;
  3535. if (offload_type == SKB_GSO_UDP) {
  3536. int ufo_size;
  3537. ufo_size = s2io_udp_mss(skb);
  3538. ufo_size &= ~7;
  3539. txdp->Control_1 |= TXD_UFO_EN;
  3540. txdp->Control_1 |= TXD_UFO_MSS(ufo_size);
  3541. txdp->Control_1 |= TXD_BUFFER0_SIZE(8);
  3542. #ifdef __BIG_ENDIAN
  3543. sp->ufo_in_band_v[put_off] =
  3544. (u64)skb_shinfo(skb)->ip6_frag_id;
  3545. #else
  3546. sp->ufo_in_band_v[put_off] =
  3547. (u64)skb_shinfo(skb)->ip6_frag_id << 32;
  3548. #endif
  3549. txdp->Host_Control = (unsigned long)sp->ufo_in_band_v;
  3550. txdp->Buffer_Pointer = pci_map_single(sp->pdev,
  3551. sp->ufo_in_band_v,
  3552. sizeof(u64), PCI_DMA_TODEVICE);
  3553. txdp++;
  3554. }
  3555. txdp->Buffer_Pointer = pci_map_single
  3556. (sp->pdev, skb->data, frg_len, PCI_DMA_TODEVICE);
  3557. txdp->Host_Control = (unsigned long) skb;
  3558. txdp->Control_1 |= TXD_BUFFER0_SIZE(frg_len);
  3559. if (offload_type == SKB_GSO_UDP)
  3560. txdp->Control_1 |= TXD_UFO_EN;
  3561. frg_cnt = skb_shinfo(skb)->nr_frags;
  3562. /* For fragmented SKB. */
  3563. for (i = 0; i < frg_cnt; i++) {
  3564. skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
  3565. /* A '0' length fragment will be ignored */
  3566. if (!frag->size)
  3567. continue;
  3568. txdp++;
  3569. txdp->Buffer_Pointer = (u64) pci_map_page
  3570. (sp->pdev, frag->page, frag->page_offset,
  3571. frag->size, PCI_DMA_TODEVICE);
  3572. txdp->Control_1 = TXD_BUFFER0_SIZE(frag->size);
  3573. if (offload_type == SKB_GSO_UDP)
  3574. txdp->Control_1 |= TXD_UFO_EN;
  3575. }
  3576. txdp->Control_1 |= TXD_GATHER_CODE_LAST;
  3577. if (offload_type == SKB_GSO_UDP)
  3578. frg_cnt++; /* as Txd0 was used for inband header */
  3579. tx_fifo = mac_control->tx_FIFO_start[queue];
  3580. val64 = mac_control->fifos[queue].list_info[put_off].list_phy_addr;
  3581. writeq(val64, &tx_fifo->TxDL_Pointer);
  3582. val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
  3583. TX_FIFO_LAST_LIST);
  3584. if (offload_type)
  3585. val64 |= TX_FIFO_SPECIAL_FUNC;
  3586. writeq(val64, &tx_fifo->List_Control);
  3587. mmiowb();
  3588. put_off++;
  3589. if (put_off == mac_control->fifos[queue].tx_curr_put_info.fifo_len + 1)
  3590. put_off = 0;
  3591. mac_control->fifos[queue].tx_curr_put_info.offset = put_off;
  3592. /* Avoid "put" pointer going beyond "get" pointer */
  3593. if (((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
  3594. sp->mac_control.stats_info->sw_stat.fifo_full_cnt++;
  3595. DBG_PRINT(TX_DBG,
  3596. "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
  3597. put_off, get_off);
  3598. netif_stop_queue(dev);
  3599. }
  3600. dev->trans_start = jiffies;
  3601. spin_unlock_irqrestore(&sp->tx_lock, flags);
  3602. return 0;
  3603. }
  3604. static void
  3605. s2io_alarm_handle(unsigned long data)
  3606. {
  3607. struct s2io_nic *sp = (struct s2io_nic *)data;
  3608. alarm_intr_handler(sp);
  3609. mod_timer(&sp->alarm_timer, jiffies + HZ / 2);
  3610. }
  3611. static int s2io_chk_rx_buffers(struct s2io_nic *sp, int rng_n)
  3612. {
  3613. int rxb_size, level;
  3614. if (!sp->lro) {
  3615. rxb_size = atomic_read(&sp->rx_bufs_left[rng_n]);
  3616. level = rx_buffer_level(sp, rxb_size, rng_n);
  3617. if ((level == PANIC) && (!TASKLET_IN_USE)) {
  3618. int ret;
  3619. DBG_PRINT(INTR_DBG, "%s: Rx BD hit ", __FUNCTION__);
  3620. DBG_PRINT(INTR_DBG, "PANIC levels\n");
  3621. if ((ret = fill_rx_buffers(sp, rng_n)) == -ENOMEM) {
  3622. DBG_PRINT(ERR_DBG, "Out of memory in %s",
  3623. __FUNCTION__);
  3624. clear_bit(0, (&sp->tasklet_status));
  3625. return -1;
  3626. }
  3627. clear_bit(0, (&sp->tasklet_status));
  3628. } else if (level == LOW)
  3629. tasklet_schedule(&sp->task);
  3630. } else if (fill_rx_buffers(sp, rng_n) == -ENOMEM) {
  3631. DBG_PRINT(ERR_DBG, "%s:Out of memory", sp->dev->name);
  3632. DBG_PRINT(ERR_DBG, " in Rx Intr!!\n");
  3633. }
  3634. return 0;
  3635. }
  3636. static irqreturn_t s2io_msi_handle(int irq, void *dev_id)
  3637. {
  3638. struct net_device *dev = (struct net_device *) dev_id;
  3639. struct s2io_nic *sp = dev->priv;
  3640. int i;
  3641. struct mac_info *mac_control;
  3642. struct config_param *config;
  3643. atomic_inc(&sp->isr_cnt);
  3644. mac_control = &sp->mac_control;
  3645. config = &sp->config;
  3646. DBG_PRINT(INTR_DBG, "%s: MSI handler\n", __FUNCTION__);
  3647. /* If Intr is because of Rx Traffic */
  3648. for (i = 0; i < config->rx_ring_num; i++)
  3649. rx_intr_handler(&mac_control->rings[i]);
  3650. /* If Intr is because of Tx Traffic */
  3651. for (i = 0; i < config->tx_fifo_num; i++)
  3652. tx_intr_handler(&mac_control->fifos[i]);
  3653. /*
  3654. * If the Rx buffer count is below the panic threshold then
  3655. * reallocate the buffers from the interrupt handler itself,
  3656. * else schedule a tasklet to reallocate the buffers.
  3657. */
  3658. for (i = 0; i < config->rx_ring_num; i++)
  3659. s2io_chk_rx_buffers(sp, i);
  3660. atomic_dec(&sp->isr_cnt);
  3661. return IRQ_HANDLED;
  3662. }
  3663. static irqreturn_t s2io_msix_ring_handle(int irq, void *dev_id)
  3664. {
  3665. struct ring_info *ring = (struct ring_info *)dev_id;
  3666. struct s2io_nic *sp = ring->nic;
  3667. atomic_inc(&sp->isr_cnt);
  3668. rx_intr_handler(ring);
  3669. s2io_chk_rx_buffers(sp, ring->ring_no);
  3670. atomic_dec(&sp->isr_cnt);
  3671. return IRQ_HANDLED;
  3672. }
  3673. static irqreturn_t s2io_msix_fifo_handle(int irq, void *dev_id)
  3674. {
  3675. struct fifo_info *fifo = (struct fifo_info *)dev_id;
  3676. struct s2io_nic *sp = fifo->nic;
  3677. atomic_inc(&sp->isr_cnt);
  3678. tx_intr_handler(fifo);
  3679. atomic_dec(&sp->isr_cnt);
  3680. return IRQ_HANDLED;
  3681. }
  3682. static void s2io_txpic_intr_handle(struct s2io_nic *sp)
  3683. {
  3684. struct XENA_dev_config __iomem *bar0 = sp->bar0;
  3685. u64 val64;
  3686. val64 = readq(&bar0->pic_int_status);
  3687. if (val64 & PIC_INT_GPIO) {
  3688. val64 = readq(&bar0->gpio_int_reg);
  3689. if ((val64 & GPIO_INT_REG_LINK_DOWN) &&
  3690. (val64 & GPIO_INT_REG_LINK_UP)) {
  3691. /*
  3692. * This is unstable state so clear both up/down
  3693. * interrupt and adapter to re-evaluate the link state.
  3694. */
  3695. val64 |= GPIO_INT_REG_LINK_DOWN;
  3696. val64 |= GPIO_INT_REG_LINK_UP;
  3697. writeq(val64, &bar0->gpio_int_reg);
  3698. val64 = readq(&bar0->gpio_int_mask);
  3699. val64 &= ~(GPIO_INT_MASK_LINK_UP |
  3700. GPIO_INT_MASK_LINK_DOWN);
  3701. writeq(val64, &bar0->gpio_int_mask);
  3702. }
  3703. else if (val64 & GPIO_INT_REG_LINK_UP) {
  3704. val64 = readq(&bar0->adapter_status);
  3705. /* Enable Adapter */
  3706. val64 = readq(&bar0->adapter_control);
  3707. val64 |= ADAPTER_CNTL_EN;
  3708. writeq(val64, &bar0->adapter_control);
  3709. val64 |= ADAPTER_LED_ON;
  3710. writeq(val64, &bar0->adapter_control);
  3711. if (!sp->device_enabled_once)
  3712. sp->device_enabled_once = 1;
  3713. s2io_link(sp, LINK_UP);
  3714. /*
  3715. * unmask link down interrupt and mask link-up
  3716. * intr
  3717. */
  3718. val64 = readq(&bar0->gpio_int_mask);
  3719. val64 &= ~GPIO_INT_MASK_LINK_DOWN;
  3720. val64 |= GPIO_INT_MASK_LINK_UP;
  3721. writeq(val64, &bar0->gpio_int_mask);
  3722. }else if (val64 & GPIO_INT_REG_LINK_DOWN) {
  3723. val64 = readq(&bar0->adapter_status);
  3724. s2io_link(sp, LINK_DOWN);
  3725. /* Link is down so unmaks link up interrupt */
  3726. val64 = readq(&bar0->gpio_int_mask);
  3727. val64 &= ~GPIO_INT_MASK_LINK_UP;
  3728. val64 |= GPIO_INT_MASK_LINK_DOWN;
  3729. writeq(val64, &bar0->gpio_int_mask);
  3730. /* turn off LED */
  3731. val64 = readq(&bar0->adapter_control);
  3732. val64 = val64 &(~ADAPTER_LED_ON);
  3733. writeq(val64, &bar0->adapter_control);
  3734. }
  3735. }
  3736. val64 = readq(&bar0->gpio_int_mask);
  3737. }
  3738. /**
  3739. * s2io_isr - ISR handler of the device .
  3740. * @irq: the irq of the device.
  3741. * @dev_id: a void pointer to the dev structure of the NIC.
  3742. * Description: This function is the ISR handler of the device. It
  3743. * identifies the reason for the interrupt and calls the relevant
  3744. * service routines. As a contongency measure, this ISR allocates the
  3745. * recv buffers, if their numbers are below the panic value which is
  3746. * presently set to 25% of the original number of rcv buffers allocated.
  3747. * Return value:
  3748. * IRQ_HANDLED: will be returned if IRQ was handled by this routine
  3749. * IRQ_NONE: will be returned if interrupt is not from our device
  3750. */
  3751. static irqreturn_t s2io_isr(int irq, void *dev_id)
  3752. {
  3753. struct net_device *dev = (struct net_device *) dev_id;
  3754. struct s2io_nic *sp = dev->priv;
  3755. struct XENA_dev_config __iomem *bar0 = sp->bar0;
  3756. int i;
  3757. u64 reason = 0;
  3758. struct mac_info *mac_control;
  3759. struct config_param *config;
  3760. atomic_inc(&sp->isr_cnt);
  3761. mac_control = &sp->mac_control;
  3762. config = &sp->config;
  3763. /*
  3764. * Identify the cause for interrupt and call the appropriate
  3765. * interrupt handler. Causes for the interrupt could be;
  3766. * 1. Rx of packet.
  3767. * 2. Tx complete.
  3768. * 3. Link down.
  3769. * 4. Error in any functional blocks of the NIC.
  3770. */
  3771. reason = readq(&bar0->general_int_status);
  3772. if (!reason) {
  3773. /* The interrupt was not raised by us. */
  3774. atomic_dec(&sp->isr_cnt);
  3775. return IRQ_NONE;
  3776. }
  3777. else if (unlikely(reason == S2IO_MINUS_ONE) ) {
  3778. /* Disable device and get out */
  3779. atomic_dec(&sp->isr_cnt);
  3780. return IRQ_NONE;
  3781. }
  3782. if (napi) {
  3783. if (reason & GEN_INTR_RXTRAFFIC) {
  3784. if ( likely ( netif_rx_schedule_prep(dev)) ) {
  3785. __netif_rx_schedule(dev);
  3786. writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_mask);
  3787. }
  3788. else
  3789. writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
  3790. }
  3791. } else {
  3792. /*
  3793. * Rx handler is called by default, without checking for the
  3794. * cause of interrupt.
  3795. * rx_traffic_int reg is an R1 register, writing all 1's
  3796. * will ensure that the actual interrupt causing bit get's
  3797. * cleared and hence a read can be avoided.
  3798. */
  3799. if (reason & GEN_INTR_RXTRAFFIC)
  3800. writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
  3801. for (i = 0; i < config->rx_ring_num; i++) {
  3802. rx_intr_handler(&mac_control->rings[i]);
  3803. }
  3804. }
  3805. /*
  3806. * tx_traffic_int reg is an R1 register, writing all 1's
  3807. * will ensure that the actual interrupt causing bit get's
  3808. * cleared and hence a read can be avoided.
  3809. */
  3810. if (reason & GEN_INTR_TXTRAFFIC)
  3811. writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
  3812. for (i = 0; i < config->tx_fifo_num; i++)
  3813. tx_intr_handler(&mac_control->fifos[i]);
  3814. if (reason & GEN_INTR_TXPIC)
  3815. s2io_txpic_intr_handle(sp);
  3816. /*
  3817. * If the Rx buffer count is below the panic threshold then
  3818. * reallocate the buffers from the interrupt handler itself,
  3819. * else schedule a tasklet to reallocate the buffers.
  3820. */
  3821. if (!napi) {
  3822. for (i = 0; i < config->rx_ring_num; i++)
  3823. s2io_chk_rx_buffers(sp, i);
  3824. }
  3825. writeq(0, &bar0->general_int_mask);
  3826. readl(&bar0->general_int_status);
  3827. atomic_dec(&sp->isr_cnt);
  3828. return IRQ_HANDLED;
  3829. }
  3830. /**
  3831. * s2io_updt_stats -
  3832. */
  3833. static void s2io_updt_stats(struct s2io_nic *sp)
  3834. {
  3835. struct XENA_dev_config __iomem *bar0 = sp->bar0;
  3836. u64 val64;
  3837. int cnt = 0;
  3838. if (atomic_read(&sp->card_state) == CARD_UP) {
  3839. /* Apprx 30us on a 133 MHz bus */
  3840. val64 = SET_UPDT_CLICKS(10) |
  3841. STAT_CFG_ONE_SHOT_EN | STAT_CFG_STAT_EN;
  3842. writeq(val64, &bar0->stat_cfg);
  3843. do {
  3844. udelay(100);
  3845. val64 = readq(&bar0->stat_cfg);
  3846. if (!(val64 & BIT(0)))
  3847. break;
  3848. cnt++;
  3849. if (cnt == 5)
  3850. break; /* Updt failed */
  3851. } while(1);
  3852. } else {
  3853. memset(sp->mac_control.stats_info, 0, sizeof(struct stat_block));
  3854. }
  3855. }
  3856. /**
  3857. * s2io_get_stats - Updates the device statistics structure.
  3858. * @dev : pointer to the device structure.
  3859. * Description:
  3860. * This function updates the device statistics structure in the s2io_nic
  3861. * structure and returns a pointer to the same.
  3862. * Return value:
  3863. * pointer to the updated net_device_stats structure.
  3864. */
  3865. static struct net_device_stats *s2io_get_stats(struct net_device *dev)
  3866. {
  3867. struct s2io_nic *sp = dev->priv;
  3868. struct mac_info *mac_control;
  3869. struct config_param *config;
  3870. mac_control = &sp->mac_control;
  3871. config = &sp->config;
  3872. /* Configure Stats for immediate updt */
  3873. s2io_updt_stats(sp);
  3874. sp->stats.tx_packets =
  3875. le32_to_cpu(mac_control->stats_info->tmac_frms);
  3876. sp->stats.tx_errors =
  3877. le32_to_cpu(mac_control->stats_info->tmac_any_err_frms);
  3878. sp->stats.rx_errors =
  3879. le64_to_cpu(mac_control->stats_info->rmac_drop_frms);
  3880. sp->stats.multicast =
  3881. le32_to_cpu(mac_control->stats_info->rmac_vld_mcst_frms);
  3882. sp->stats.rx_length_errors =
  3883. le64_to_cpu(mac_control->stats_info->rmac_long_frms);
  3884. return (&sp->stats);
  3885. }
  3886. /**
  3887. * s2io_set_multicast - entry point for multicast address enable/disable.
  3888. * @dev : pointer to the device structure
  3889. * Description:
  3890. * This function is a driver entry point which gets called by the kernel
  3891. * whenever multicast addresses must be enabled/disabled. This also gets
  3892. * called to set/reset promiscuous mode. Depending on the deivce flag, we
  3893. * determine, if multicast address must be enabled or if promiscuous mode
  3894. * is to be disabled etc.
  3895. * Return value:
  3896. * void.
  3897. */
  3898. static void s2io_set_multicast(struct net_device *dev)
  3899. {
  3900. int i, j, prev_cnt;
  3901. struct dev_mc_list *mclist;
  3902. struct s2io_nic *sp = dev->priv;
  3903. struct XENA_dev_config __iomem *bar0 = sp->bar0;
  3904. u64 val64 = 0, multi_mac = 0x010203040506ULL, mask =
  3905. 0xfeffffffffffULL;
  3906. u64 dis_addr = 0xffffffffffffULL, mac_addr = 0;
  3907. void __iomem *add;
  3908. if ((dev->flags & IFF_ALLMULTI) && (!sp->m_cast_flg)) {
  3909. /* Enable all Multicast addresses */
  3910. writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac),
  3911. &bar0->rmac_addr_data0_mem);
  3912. writeq(RMAC_ADDR_DATA1_MEM_MASK(mask),
  3913. &bar0->rmac_addr_data1_mem);
  3914. val64 = RMAC_ADDR_CMD_MEM_WE |
  3915. RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
  3916. RMAC_ADDR_CMD_MEM_OFFSET(MAC_MC_ALL_MC_ADDR_OFFSET);
  3917. writeq(val64, &bar0->rmac_addr_cmd_mem);
  3918. /* Wait till command completes */
  3919. wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
  3920. RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
  3921. S2IO_BIT_RESET);
  3922. sp->m_cast_flg = 1;
  3923. sp->all_multi_pos = MAC_MC_ALL_MC_ADDR_OFFSET;
  3924. } else if ((dev->flags & IFF_ALLMULTI) && (sp->m_cast_flg)) {
  3925. /* Disable all Multicast addresses */
  3926. writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
  3927. &bar0->rmac_addr_data0_mem);
  3928. writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0),
  3929. &bar0->rmac_addr_data1_mem);
  3930. val64 = RMAC_ADDR_CMD_MEM_WE |
  3931. RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
  3932. RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos);
  3933. writeq(val64, &bar0->rmac_addr_cmd_mem);
  3934. /* Wait till command completes */
  3935. wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
  3936. RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
  3937. S2IO_BIT_RESET);
  3938. sp->m_cast_flg = 0;
  3939. sp->all_multi_pos = 0;
  3940. }
  3941. if ((dev->flags & IFF_PROMISC) && (!sp->promisc_flg)) {
  3942. /* Put the NIC into promiscuous mode */
  3943. add = &bar0->mac_cfg;
  3944. val64 = readq(&bar0->mac_cfg);
  3945. val64 |= MAC_CFG_RMAC_PROM_ENABLE;
  3946. writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
  3947. writel((u32) val64, add);
  3948. writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
  3949. writel((u32) (val64 >> 32), (add + 4));
  3950. if (vlan_tag_strip != 1) {
  3951. val64 = readq(&bar0->rx_pa_cfg);
  3952. val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
  3953. writeq(val64, &bar0->rx_pa_cfg);
  3954. vlan_strip_flag = 0;
  3955. }
  3956. val64 = readq(&bar0->mac_cfg);
  3957. sp->promisc_flg = 1;
  3958. DBG_PRINT(INFO_DBG, "%s: entered promiscuous mode\n",
  3959. dev->name);
  3960. } else if (!(dev->flags & IFF_PROMISC) && (sp->promisc_flg)) {
  3961. /* Remove the NIC from promiscuous mode */
  3962. add = &bar0->mac_cfg;
  3963. val64 = readq(&bar0->mac_cfg);
  3964. val64 &= ~MAC_CFG_RMAC_PROM_ENABLE;
  3965. writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
  3966. writel((u32) val64, add);
  3967. writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
  3968. writel((u32) (val64 >> 32), (add + 4));
  3969. if (vlan_tag_strip != 0) {
  3970. val64 = readq(&bar0->rx_pa_cfg);
  3971. val64 |= RX_PA_CFG_STRIP_VLAN_TAG;
  3972. writeq(val64, &bar0->rx_pa_cfg);
  3973. vlan_strip_flag = 1;
  3974. }
  3975. val64 = readq(&bar0->mac_cfg);
  3976. sp->promisc_flg = 0;
  3977. DBG_PRINT(INFO_DBG, "%s: left promiscuous mode\n",
  3978. dev->name);
  3979. }
  3980. /* Update individual M_CAST address list */
  3981. if ((!sp->m_cast_flg) && dev->mc_count) {
  3982. if (dev->mc_count >
  3983. (MAX_ADDRS_SUPPORTED - MAC_MC_ADDR_START_OFFSET - 1)) {
  3984. DBG_PRINT(ERR_DBG, "%s: No more Rx filters ",
  3985. dev->name);
  3986. DBG_PRINT(ERR_DBG, "can be added, please enable ");
  3987. DBG_PRINT(ERR_DBG, "ALL_MULTI instead\n");
  3988. return;
  3989. }
  3990. prev_cnt = sp->mc_addr_count;
  3991. sp->mc_addr_count = dev->mc_count;
  3992. /* Clear out the previous list of Mc in the H/W. */
  3993. for (i = 0; i < prev_cnt; i++) {
  3994. writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
  3995. &bar0->rmac_addr_data0_mem);
  3996. writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
  3997. &bar0->rmac_addr_data1_mem);
  3998. val64 = RMAC_ADDR_CMD_MEM_WE |
  3999. RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
  4000. RMAC_ADDR_CMD_MEM_OFFSET
  4001. (MAC_MC_ADDR_START_OFFSET + i);
  4002. writeq(val64, &bar0->rmac_addr_cmd_mem);
  4003. /* Wait for command completes */
  4004. if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
  4005. RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
  4006. S2IO_BIT_RESET)) {
  4007. DBG_PRINT(ERR_DBG, "%s: Adding ",
  4008. dev->name);
  4009. DBG_PRINT(ERR_DBG, "Multicasts failed\n");
  4010. return;
  4011. }
  4012. }
  4013. /* Create the new Rx filter list and update the same in H/W. */
  4014. for (i = 0, mclist = dev->mc_list; i < dev->mc_count;
  4015. i++, mclist = mclist->next) {
  4016. memcpy(sp->usr_addrs[i].addr, mclist->dmi_addr,
  4017. ETH_ALEN);
  4018. mac_addr = 0;
  4019. for (j = 0; j < ETH_ALEN; j++) {
  4020. mac_addr |= mclist->dmi_addr[j];
  4021. mac_addr <<= 8;
  4022. }
  4023. mac_addr >>= 8;
  4024. writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
  4025. &bar0->rmac_addr_data0_mem);
  4026. writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
  4027. &bar0->rmac_addr_data1_mem);
  4028. val64 = RMAC_ADDR_CMD_MEM_WE |
  4029. RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
  4030. RMAC_ADDR_CMD_MEM_OFFSET
  4031. (i + MAC_MC_ADDR_START_OFFSET);
  4032. writeq(val64, &bar0->rmac_addr_cmd_mem);
  4033. /* Wait for command completes */
  4034. if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
  4035. RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
  4036. S2IO_BIT_RESET)) {
  4037. DBG_PRINT(ERR_DBG, "%s: Adding ",
  4038. dev->name);
  4039. DBG_PRINT(ERR_DBG, "Multicasts failed\n");
  4040. return;
  4041. }
  4042. }
  4043. }
  4044. }
  4045. /**
  4046. * s2io_set_mac_addr - Programs the Xframe mac address
  4047. * @dev : pointer to the device structure.
  4048. * @addr: a uchar pointer to the new mac address which is to be set.
  4049. * Description : This procedure will program the Xframe to receive
  4050. * frames with new Mac Address
  4051. * Return value: SUCCESS on success and an appropriate (-)ve integer
  4052. * as defined in errno.h file on failure.
  4053. */
  4054. static int s2io_set_mac_addr(struct net_device *dev, u8 * addr)
  4055. {
  4056. struct s2io_nic *sp = dev->priv;
  4057. struct XENA_dev_config __iomem *bar0 = sp->bar0;
  4058. register u64 val64, mac_addr = 0;
  4059. int i;
  4060. /*
  4061. * Set the new MAC address as the new unicast filter and reflect this
  4062. * change on the device address registered with the OS. It will be
  4063. * at offset 0.
  4064. */
  4065. for (i = 0; i < ETH_ALEN; i++) {
  4066. mac_addr <<= 8;
  4067. mac_addr |= addr[i];
  4068. }
  4069. writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
  4070. &bar0->rmac_addr_data0_mem);
  4071. val64 =
  4072. RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
  4073. RMAC_ADDR_CMD_MEM_OFFSET(0);
  4074. writeq(val64, &bar0->rmac_addr_cmd_mem);
  4075. /* Wait till command completes */
  4076. if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
  4077. RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING, S2IO_BIT_RESET)) {
  4078. DBG_PRINT(ERR_DBG, "%s: set_mac_addr failed\n", dev->name);
  4079. return FAILURE;
  4080. }
  4081. return SUCCESS;
  4082. }
  4083. /**
  4084. * s2io_ethtool_sset - Sets different link parameters.
  4085. * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
  4086. * @info: pointer to the structure with parameters given by ethtool to set
  4087. * link information.
  4088. * Description:
  4089. * The function sets different link parameters provided by the user onto
  4090. * the NIC.
  4091. * Return value:
  4092. * 0 on success.
  4093. */
  4094. static int s2io_ethtool_sset(struct net_device *dev,
  4095. struct ethtool_cmd *info)
  4096. {
  4097. struct s2io_nic *sp = dev->priv;
  4098. if ((info->autoneg == AUTONEG_ENABLE) ||
  4099. (info->speed != SPEED_10000) || (info->duplex != DUPLEX_FULL))
  4100. return -EINVAL;
  4101. else {
  4102. s2io_close(sp->dev);
  4103. s2io_open(sp->dev);
  4104. }
  4105. return 0;
  4106. }
  4107. /**
  4108. * s2io_ethtol_gset - Return link specific information.
  4109. * @sp : private member of the device structure, pointer to the
  4110. * s2io_nic structure.
  4111. * @info : pointer to the structure with parameters given by ethtool
  4112. * to return link information.
  4113. * Description:
  4114. * Returns link specific information like speed, duplex etc.. to ethtool.
  4115. * Return value :
  4116. * return 0 on success.
  4117. */
  4118. static int s2io_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info)
  4119. {
  4120. struct s2io_nic *sp = dev->priv;
  4121. info->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
  4122. info->advertising = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
  4123. info->port = PORT_FIBRE;
  4124. /* info->transceiver?? TODO */
  4125. if (netif_carrier_ok(sp->dev)) {
  4126. info->speed = 10000;
  4127. info->duplex = DUPLEX_FULL;
  4128. } else {
  4129. info->speed = -1;
  4130. info->duplex = -1;
  4131. }
  4132. info->autoneg = AUTONEG_DISABLE;
  4133. return 0;
  4134. }
  4135. /**
  4136. * s2io_ethtool_gdrvinfo - Returns driver specific information.
  4137. * @sp : private member of the device structure, which is a pointer to the
  4138. * s2io_nic structure.
  4139. * @info : pointer to the structure with parameters given by ethtool to
  4140. * return driver information.
  4141. * Description:
  4142. * Returns driver specefic information like name, version etc.. to ethtool.
  4143. * Return value:
  4144. * void
  4145. */
  4146. static void s2io_ethtool_gdrvinfo(struct net_device *dev,
  4147. struct ethtool_drvinfo *info)
  4148. {
  4149. struct s2io_nic *sp = dev->priv;
  4150. strncpy(info->driver, s2io_driver_name, sizeof(info->driver));
  4151. strncpy(info->version, s2io_driver_version, sizeof(info->version));
  4152. strncpy(info->fw_version, "", sizeof(info->fw_version));
  4153. strncpy(info->bus_info, pci_name(sp->pdev), sizeof(info->bus_info));
  4154. info->regdump_len = XENA_REG_SPACE;
  4155. info->eedump_len = XENA_EEPROM_SPACE;
  4156. info->testinfo_len = S2IO_TEST_LEN;
  4157. info->n_stats = S2IO_STAT_LEN;
  4158. }
  4159. /**
  4160. * s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer.
  4161. * @sp: private member of the device structure, which is a pointer to the
  4162. * s2io_nic structure.
  4163. * @regs : pointer to the structure with parameters given by ethtool for
  4164. * dumping the registers.
  4165. * @reg_space: The input argumnet into which all the registers are dumped.
  4166. * Description:
  4167. * Dumps the entire register space of xFrame NIC into the user given
  4168. * buffer area.
  4169. * Return value :
  4170. * void .
  4171. */
  4172. static void s2io_ethtool_gregs(struct net_device *dev,
  4173. struct ethtool_regs *regs, void *space)
  4174. {
  4175. int i;
  4176. u64 reg;
  4177. u8 *reg_space = (u8 *) space;
  4178. struct s2io_nic *sp = dev->priv;
  4179. regs->len = XENA_REG_SPACE;
  4180. regs->version = sp->pdev->subsystem_device;
  4181. for (i = 0; i < regs->len; i += 8) {
  4182. reg = readq(sp->bar0 + i);
  4183. memcpy((reg_space + i), &reg, 8);
  4184. }
  4185. }
  4186. /**
  4187. * s2io_phy_id - timer function that alternates adapter LED.
  4188. * @data : address of the private member of the device structure, which
  4189. * is a pointer to the s2io_nic structure, provided as an u32.
  4190. * Description: This is actually the timer function that alternates the
  4191. * adapter LED bit of the adapter control bit to set/reset every time on
  4192. * invocation. The timer is set for 1/2 a second, hence tha NIC blinks
  4193. * once every second.
  4194. */
  4195. static void s2io_phy_id(unsigned long data)
  4196. {
  4197. struct s2io_nic *sp = (struct s2io_nic *) data;
  4198. struct XENA_dev_config __iomem *bar0 = sp->bar0;
  4199. u64 val64 = 0;
  4200. u16 subid;
  4201. subid = sp->pdev->subsystem_device;
  4202. if ((sp->device_type == XFRAME_II_DEVICE) ||
  4203. ((subid & 0xFF) >= 0x07)) {
  4204. val64 = readq(&bar0->gpio_control);
  4205. val64 ^= GPIO_CTRL_GPIO_0;
  4206. writeq(val64, &bar0->gpio_control);
  4207. } else {
  4208. val64 = readq(&bar0->adapter_control);
  4209. val64 ^= ADAPTER_LED_ON;
  4210. writeq(val64, &bar0->adapter_control);
  4211. }
  4212. mod_timer(&sp->id_timer, jiffies + HZ / 2);
  4213. }
  4214. /**
  4215. * s2io_ethtool_idnic - To physically identify the nic on the system.
  4216. * @sp : private member of the device structure, which is a pointer to the
  4217. * s2io_nic structure.
  4218. * @id : pointer to the structure with identification parameters given by
  4219. * ethtool.
  4220. * Description: Used to physically identify the NIC on the system.
  4221. * The Link LED will blink for a time specified by the user for
  4222. * identification.
  4223. * NOTE: The Link has to be Up to be able to blink the LED. Hence
  4224. * identification is possible only if it's link is up.
  4225. * Return value:
  4226. * int , returns 0 on success
  4227. */
  4228. static int s2io_ethtool_idnic(struct net_device *dev, u32 data)
  4229. {
  4230. u64 val64 = 0, last_gpio_ctrl_val;
  4231. struct s2io_nic *sp = dev->priv;
  4232. struct XENA_dev_config __iomem *bar0 = sp->bar0;
  4233. u16 subid;
  4234. subid = sp->pdev->subsystem_device;
  4235. last_gpio_ctrl_val = readq(&bar0->gpio_control);
  4236. if ((sp->device_type == XFRAME_I_DEVICE) &&
  4237. ((subid & 0xFF) < 0x07)) {
  4238. val64 = readq(&bar0->adapter_control);
  4239. if (!(val64 & ADAPTER_CNTL_EN)) {
  4240. printk(KERN_ERR
  4241. "Adapter Link down, cannot blink LED\n");
  4242. return -EFAULT;
  4243. }
  4244. }
  4245. if (sp->id_timer.function == NULL) {
  4246. init_timer(&sp->id_timer);
  4247. sp->id_timer.function = s2io_phy_id;
  4248. sp->id_timer.data = (unsigned long) sp;
  4249. }
  4250. mod_timer(&sp->id_timer, jiffies);
  4251. if (data)
  4252. msleep_interruptible(data * HZ);
  4253. else
  4254. msleep_interruptible(MAX_FLICKER_TIME);
  4255. del_timer_sync(&sp->id_timer);
  4256. if (CARDS_WITH_FAULTY_LINK_INDICATORS(sp->device_type, subid)) {
  4257. writeq(last_gpio_ctrl_val, &bar0->gpio_control);
  4258. last_gpio_ctrl_val = readq(&bar0->gpio_control);
  4259. }
  4260. return 0;
  4261. }
  4262. /**
  4263. * s2io_ethtool_getpause_data -Pause frame frame generation and reception.
  4264. * @sp : private member of the device structure, which is a pointer to the
  4265. * s2io_nic structure.
  4266. * @ep : pointer to the structure with pause parameters given by ethtool.
  4267. * Description:
  4268. * Returns the Pause frame generation and reception capability of the NIC.
  4269. * Return value:
  4270. * void
  4271. */
  4272. static void s2io_ethtool_getpause_data(struct net_device *dev,
  4273. struct ethtool_pauseparam *ep)
  4274. {
  4275. u64 val64;
  4276. struct s2io_nic *sp = dev->priv;
  4277. struct XENA_dev_config __iomem *bar0 = sp->bar0;
  4278. val64 = readq(&bar0->rmac_pause_cfg);
  4279. if (val64 & RMAC_PAUSE_GEN_ENABLE)
  4280. ep->tx_pause = TRUE;
  4281. if (val64 & RMAC_PAUSE_RX_ENABLE)
  4282. ep->rx_pause = TRUE;
  4283. ep->autoneg = FALSE;
  4284. }
  4285. /**
  4286. * s2io_ethtool_setpause_data - set/reset pause frame generation.
  4287. * @sp : private member of the device structure, which is a pointer to the
  4288. * s2io_nic structure.
  4289. * @ep : pointer to the structure with pause parameters given by ethtool.
  4290. * Description:
  4291. * It can be used to set or reset Pause frame generation or reception
  4292. * support of the NIC.
  4293. * Return value:
  4294. * int, returns 0 on Success
  4295. */
  4296. static int s2io_ethtool_setpause_data(struct net_device *dev,
  4297. struct ethtool_pauseparam *ep)
  4298. {
  4299. u64 val64;
  4300. struct s2io_nic *sp = dev->priv;
  4301. struct XENA_dev_config __iomem *bar0 = sp->bar0;
  4302. val64 = readq(&bar0->rmac_pause_cfg);
  4303. if (ep->tx_pause)
  4304. val64 |= RMAC_PAUSE_GEN_ENABLE;
  4305. else
  4306. val64 &= ~RMAC_PAUSE_GEN_ENABLE;
  4307. if (ep->rx_pause)
  4308. val64 |= RMAC_PAUSE_RX_ENABLE;
  4309. else
  4310. val64 &= ~RMAC_PAUSE_RX_ENABLE;
  4311. writeq(val64, &bar0->rmac_pause_cfg);
  4312. return 0;
  4313. }
  4314. /**
  4315. * read_eeprom - reads 4 bytes of data from user given offset.
  4316. * @sp : private member of the device structure, which is a pointer to the
  4317. * s2io_nic structure.
  4318. * @off : offset at which the data must be written
  4319. * @data : Its an output parameter where the data read at the given
  4320. * offset is stored.
  4321. * Description:
  4322. * Will read 4 bytes of data from the user given offset and return the
  4323. * read data.
  4324. * NOTE: Will allow to read only part of the EEPROM visible through the
  4325. * I2C bus.
  4326. * Return value:
  4327. * -1 on failure and 0 on success.
  4328. */
  4329. #define S2IO_DEV_ID 5
  4330. static int read_eeprom(struct s2io_nic * sp, int off, u64 * data)
  4331. {
  4332. int ret = -1;
  4333. u32 exit_cnt = 0;
  4334. u64 val64;
  4335. struct XENA_dev_config __iomem *bar0 = sp->bar0;
  4336. if (sp->device_type == XFRAME_I_DEVICE) {
  4337. val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
  4338. I2C_CONTROL_BYTE_CNT(0x3) | I2C_CONTROL_READ |
  4339. I2C_CONTROL_CNTL_START;
  4340. SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
  4341. while (exit_cnt < 5) {
  4342. val64 = readq(&bar0->i2c_control);
  4343. if (I2C_CONTROL_CNTL_END(val64)) {
  4344. *data = I2C_CONTROL_GET_DATA(val64);
  4345. ret = 0;
  4346. break;
  4347. }
  4348. msleep(50);
  4349. exit_cnt++;
  4350. }
  4351. }
  4352. if (sp->device_type == XFRAME_II_DEVICE) {
  4353. val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
  4354. SPI_CONTROL_BYTECNT(0x3) |
  4355. SPI_CONTROL_CMD(0x3) | SPI_CONTROL_ADDR(off);
  4356. SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
  4357. val64 |= SPI_CONTROL_REQ;
  4358. SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
  4359. while (exit_cnt < 5) {
  4360. val64 = readq(&bar0->spi_control);
  4361. if (val64 & SPI_CONTROL_NACK) {
  4362. ret = 1;
  4363. break;
  4364. } else if (val64 & SPI_CONTROL_DONE) {
  4365. *data = readq(&bar0->spi_data);
  4366. *data &= 0xffffff;
  4367. ret = 0;
  4368. break;
  4369. }
  4370. msleep(50);
  4371. exit_cnt++;
  4372. }
  4373. }
  4374. return ret;
  4375. }
  4376. /**
  4377. * write_eeprom - actually writes the relevant part of the data value.
  4378. * @sp : private member of the device structure, which is a pointer to the
  4379. * s2io_nic structure.
  4380. * @off : offset at which the data must be written
  4381. * @data : The data that is to be written
  4382. * @cnt : Number of bytes of the data that are actually to be written into
  4383. * the Eeprom. (max of 3)
  4384. * Description:
  4385. * Actually writes the relevant part of the data value into the Eeprom
  4386. * through the I2C bus.
  4387. * Return value:
  4388. * 0 on success, -1 on failure.
  4389. */
  4390. static int write_eeprom(struct s2io_nic * sp, int off, u64 data, int cnt)
  4391. {
  4392. int exit_cnt = 0, ret = -1;
  4393. u64 val64;
  4394. struct XENA_dev_config __iomem *bar0 = sp->bar0;
  4395. if (sp->device_type == XFRAME_I_DEVICE) {
  4396. val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
  4397. I2C_CONTROL_BYTE_CNT(cnt) | I2C_CONTROL_SET_DATA((u32)data) |
  4398. I2C_CONTROL_CNTL_START;
  4399. SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
  4400. while (exit_cnt < 5) {
  4401. val64 = readq(&bar0->i2c_control);
  4402. if (I2C_CONTROL_CNTL_END(val64)) {
  4403. if (!(val64 & I2C_CONTROL_NACK))
  4404. ret = 0;
  4405. break;
  4406. }
  4407. msleep(50);
  4408. exit_cnt++;
  4409. }
  4410. }
  4411. if (sp->device_type == XFRAME_II_DEVICE) {
  4412. int write_cnt = (cnt == 8) ? 0 : cnt;
  4413. writeq(SPI_DATA_WRITE(data,(cnt<<3)), &bar0->spi_data);
  4414. val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
  4415. SPI_CONTROL_BYTECNT(write_cnt) |
  4416. SPI_CONTROL_CMD(0x2) | SPI_CONTROL_ADDR(off);
  4417. SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
  4418. val64 |= SPI_CONTROL_REQ;
  4419. SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
  4420. while (exit_cnt < 5) {
  4421. val64 = readq(&bar0->spi_control);
  4422. if (val64 & SPI_CONTROL_NACK) {
  4423. ret = 1;
  4424. break;
  4425. } else if (val64 & SPI_CONTROL_DONE) {
  4426. ret = 0;
  4427. break;
  4428. }
  4429. msleep(50);
  4430. exit_cnt++;
  4431. }
  4432. }
  4433. return ret;
  4434. }
  4435. static void s2io_vpd_read(struct s2io_nic *nic)
  4436. {
  4437. u8 *vpd_data;
  4438. u8 data;
  4439. int i=0, cnt, fail = 0;
  4440. int vpd_addr = 0x80;
  4441. if (nic->device_type == XFRAME_II_DEVICE) {
  4442. strcpy(nic->product_name, "Xframe II 10GbE network adapter");
  4443. vpd_addr = 0x80;
  4444. }
  4445. else {
  4446. strcpy(nic->product_name, "Xframe I 10GbE network adapter");
  4447. vpd_addr = 0x50;
  4448. }
  4449. strcpy(nic->serial_num, "NOT AVAILABLE");
  4450. vpd_data = kmalloc(256, GFP_KERNEL);
  4451. if (!vpd_data)
  4452. return;
  4453. for (i = 0; i < 256; i +=4 ) {
  4454. pci_write_config_byte(nic->pdev, (vpd_addr + 2), i);
  4455. pci_read_config_byte(nic->pdev, (vpd_addr + 2), &data);
  4456. pci_write_config_byte(nic->pdev, (vpd_addr + 3), 0);
  4457. for (cnt = 0; cnt <5; cnt++) {
  4458. msleep(2);
  4459. pci_read_config_byte(nic->pdev, (vpd_addr + 3), &data);
  4460. if (data == 0x80)
  4461. break;
  4462. }
  4463. if (cnt >= 5) {
  4464. DBG_PRINT(ERR_DBG, "Read of VPD data failed\n");
  4465. fail = 1;
  4466. break;
  4467. }
  4468. pci_read_config_dword(nic->pdev, (vpd_addr + 4),
  4469. (u32 *)&vpd_data[i]);
  4470. }
  4471. if(!fail) {
  4472. /* read serial number of adapter */
  4473. for (cnt = 0; cnt < 256; cnt++) {
  4474. if ((vpd_data[cnt] == 'S') &&
  4475. (vpd_data[cnt+1] == 'N') &&
  4476. (vpd_data[cnt+2] < VPD_STRING_LEN)) {
  4477. memset(nic->serial_num, 0, VPD_STRING_LEN);
  4478. memcpy(nic->serial_num, &vpd_data[cnt + 3],
  4479. vpd_data[cnt+2]);
  4480. break;
  4481. }
  4482. }
  4483. }
  4484. if ((!fail) && (vpd_data[1] < VPD_STRING_LEN)) {
  4485. memset(nic->product_name, 0, vpd_data[1]);
  4486. memcpy(nic->product_name, &vpd_data[3], vpd_data[1]);
  4487. }
  4488. kfree(vpd_data);
  4489. }
  4490. /**
  4491. * s2io_ethtool_geeprom - reads the value stored in the Eeprom.
  4492. * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
  4493. * @eeprom : pointer to the user level structure provided by ethtool,
  4494. * containing all relevant information.
  4495. * @data_buf : user defined value to be written into Eeprom.
  4496. * Description: Reads the values stored in the Eeprom at given offset
  4497. * for a given length. Stores these values int the input argument data
  4498. * buffer 'data_buf' and returns these to the caller (ethtool.)
  4499. * Return value:
  4500. * int 0 on success
  4501. */
  4502. static int s2io_ethtool_geeprom(struct net_device *dev,
  4503. struct ethtool_eeprom *eeprom, u8 * data_buf)
  4504. {
  4505. u32 i, valid;
  4506. u64 data;
  4507. struct s2io_nic *sp = dev->priv;
  4508. eeprom->magic = sp->pdev->vendor | (sp->pdev->device << 16);
  4509. if ((eeprom->offset + eeprom->len) > (XENA_EEPROM_SPACE))
  4510. eeprom->len = XENA_EEPROM_SPACE - eeprom->offset;
  4511. for (i = 0; i < eeprom->len; i += 4) {
  4512. if (read_eeprom(sp, (eeprom->offset + i), &data)) {
  4513. DBG_PRINT(ERR_DBG, "Read of EEPROM failed\n");
  4514. return -EFAULT;
  4515. }
  4516. valid = INV(data);
  4517. memcpy((data_buf + i), &valid, 4);
  4518. }
  4519. return 0;
  4520. }
  4521. /**
  4522. * s2io_ethtool_seeprom - tries to write the user provided value in Eeprom
  4523. * @sp : private member of the device structure, which is a pointer to the
  4524. * s2io_nic structure.
  4525. * @eeprom : pointer to the user level structure provided by ethtool,
  4526. * containing all relevant information.
  4527. * @data_buf ; user defined value to be written into Eeprom.
  4528. * Description:
  4529. * Tries to write the user provided value in the Eeprom, at the offset
  4530. * given by the user.
  4531. * Return value:
  4532. * 0 on success, -EFAULT on failure.
  4533. */
  4534. static int s2io_ethtool_seeprom(struct net_device *dev,
  4535. struct ethtool_eeprom *eeprom,
  4536. u8 * data_buf)
  4537. {
  4538. int len = eeprom->len, cnt = 0;
  4539. u64 valid = 0, data;
  4540. struct s2io_nic *sp = dev->priv;
  4541. if (eeprom->magic != (sp->pdev->vendor | (sp->pdev->device << 16))) {
  4542. DBG_PRINT(ERR_DBG,
  4543. "ETHTOOL_WRITE_EEPROM Err: Magic value ");
  4544. DBG_PRINT(ERR_DBG, "is wrong, Its not 0x%x\n",
  4545. eeprom->magic);
  4546. return -EFAULT;
  4547. }
  4548. while (len) {
  4549. data = (u32) data_buf[cnt] & 0x000000FF;
  4550. if (data) {
  4551. valid = (u32) (data << 24);
  4552. } else
  4553. valid = data;
  4554. if (write_eeprom(sp, (eeprom->offset + cnt), valid, 0)) {
  4555. DBG_PRINT(ERR_DBG,
  4556. "ETHTOOL_WRITE_EEPROM Err: Cannot ");
  4557. DBG_PRINT(ERR_DBG,
  4558. "write into the specified offset\n");
  4559. return -EFAULT;
  4560. }
  4561. cnt++;
  4562. len--;
  4563. }
  4564. return 0;
  4565. }
  4566. /**
  4567. * s2io_register_test - reads and writes into all clock domains.
  4568. * @sp : private member of the device structure, which is a pointer to the
  4569. * s2io_nic structure.
  4570. * @data : variable that returns the result of each of the test conducted b
  4571. * by the driver.
  4572. * Description:
  4573. * Read and write into all clock domains. The NIC has 3 clock domains,
  4574. * see that registers in all the three regions are accessible.
  4575. * Return value:
  4576. * 0 on success.
  4577. */
  4578. static int s2io_register_test(struct s2io_nic * sp, uint64_t * data)
  4579. {
  4580. struct XENA_dev_config __iomem *bar0 = sp->bar0;
  4581. u64 val64 = 0, exp_val;
  4582. int fail = 0;
  4583. val64 = readq(&bar0->pif_rd_swapper_fb);
  4584. if (val64 != 0x123456789abcdefULL) {
  4585. fail = 1;
  4586. DBG_PRINT(INFO_DBG, "Read Test level 1 fails\n");
  4587. }
  4588. val64 = readq(&bar0->rmac_pause_cfg);
  4589. if (val64 != 0xc000ffff00000000ULL) {
  4590. fail = 1;
  4591. DBG_PRINT(INFO_DBG, "Read Test level 2 fails\n");
  4592. }
  4593. val64 = readq(&bar0->rx_queue_cfg);
  4594. if (sp->device_type == XFRAME_II_DEVICE)
  4595. exp_val = 0x0404040404040404ULL;
  4596. else
  4597. exp_val = 0x0808080808080808ULL;
  4598. if (val64 != exp_val) {
  4599. fail = 1;
  4600. DBG_PRINT(INFO_DBG, "Read Test level 3 fails\n");
  4601. }
  4602. val64 = readq(&bar0->xgxs_efifo_cfg);
  4603. if (val64 != 0x000000001923141EULL) {
  4604. fail = 1;
  4605. DBG_PRINT(INFO_DBG, "Read Test level 4 fails\n");
  4606. }
  4607. val64 = 0x5A5A5A5A5A5A5A5AULL;
  4608. writeq(val64, &bar0->xmsi_data);
  4609. val64 = readq(&bar0->xmsi_data);
  4610. if (val64 != 0x5A5A5A5A5A5A5A5AULL) {
  4611. fail = 1;
  4612. DBG_PRINT(ERR_DBG, "Write Test level 1 fails\n");
  4613. }
  4614. val64 = 0xA5A5A5A5A5A5A5A5ULL;
  4615. writeq(val64, &bar0->xmsi_data);
  4616. val64 = readq(&bar0->xmsi_data);
  4617. if (val64 != 0xA5A5A5A5A5A5A5A5ULL) {
  4618. fail = 1;
  4619. DBG_PRINT(ERR_DBG, "Write Test level 2 fails\n");
  4620. }
  4621. *data = fail;
  4622. return fail;
  4623. }
  4624. /**
  4625. * s2io_eeprom_test - to verify that EEprom in the xena can be programmed.
  4626. * @sp : private member of the device structure, which is a pointer to the
  4627. * s2io_nic structure.
  4628. * @data:variable that returns the result of each of the test conducted by
  4629. * the driver.
  4630. * Description:
  4631. * Verify that EEPROM in the xena can be programmed using I2C_CONTROL
  4632. * register.
  4633. * Return value:
  4634. * 0 on success.
  4635. */
  4636. static int s2io_eeprom_test(struct s2io_nic * sp, uint64_t * data)
  4637. {
  4638. int fail = 0;
  4639. u64 ret_data, org_4F0, org_7F0;
  4640. u8 saved_4F0 = 0, saved_7F0 = 0;
  4641. struct net_device *dev = sp->dev;
  4642. /* Test Write Error at offset 0 */
  4643. /* Note that SPI interface allows write access to all areas
  4644. * of EEPROM. Hence doing all negative testing only for Xframe I.
  4645. */
  4646. if (sp->device_type == XFRAME_I_DEVICE)
  4647. if (!write_eeprom(sp, 0, 0, 3))
  4648. fail = 1;
  4649. /* Save current values at offsets 0x4F0 and 0x7F0 */
  4650. if (!read_eeprom(sp, 0x4F0, &org_4F0))
  4651. saved_4F0 = 1;
  4652. if (!read_eeprom(sp, 0x7F0, &org_7F0))
  4653. saved_7F0 = 1;
  4654. /* Test Write at offset 4f0 */
  4655. if (write_eeprom(sp, 0x4F0, 0x012345, 3))
  4656. fail = 1;
  4657. if (read_eeprom(sp, 0x4F0, &ret_data))
  4658. fail = 1;
  4659. if (ret_data != 0x012345) {
  4660. DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x4F0. "
  4661. "Data written %llx Data read %llx\n",
  4662. dev->name, (unsigned long long)0x12345,
  4663. (unsigned long long)ret_data);
  4664. fail = 1;
  4665. }
  4666. /* Reset the EEPROM data go FFFF */
  4667. write_eeprom(sp, 0x4F0, 0xFFFFFF, 3);
  4668. /* Test Write Request Error at offset 0x7c */
  4669. if (sp->device_type == XFRAME_I_DEVICE)
  4670. if (!write_eeprom(sp, 0x07C, 0, 3))
  4671. fail = 1;
  4672. /* Test Write Request at offset 0x7f0 */
  4673. if (write_eeprom(sp, 0x7F0, 0x012345, 3))
  4674. fail = 1;
  4675. if (read_eeprom(sp, 0x7F0, &ret_data))
  4676. fail = 1;
  4677. if (ret_data != 0x012345) {
  4678. DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x7F0. "
  4679. "Data written %llx Data read %llx\n",
  4680. dev->name, (unsigned long long)0x12345,
  4681. (unsigned long long)ret_data);
  4682. fail = 1;
  4683. }
  4684. /* Reset the EEPROM data go FFFF */
  4685. write_eeprom(sp, 0x7F0, 0xFFFFFF, 3);
  4686. if (sp->device_type == XFRAME_I_DEVICE) {
  4687. /* Test Write Error at offset 0x80 */
  4688. if (!write_eeprom(sp, 0x080, 0, 3))
  4689. fail = 1;
  4690. /* Test Write Error at offset 0xfc */
  4691. if (!write_eeprom(sp, 0x0FC, 0, 3))
  4692. fail = 1;
  4693. /* Test Write Error at offset 0x100 */
  4694. if (!write_eeprom(sp, 0x100, 0, 3))
  4695. fail = 1;
  4696. /* Test Write Error at offset 4ec */
  4697. if (!write_eeprom(sp, 0x4EC, 0, 3))
  4698. fail = 1;
  4699. }
  4700. /* Restore values at offsets 0x4F0 and 0x7F0 */
  4701. if (saved_4F0)
  4702. write_eeprom(sp, 0x4F0, org_4F0, 3);
  4703. if (saved_7F0)
  4704. write_eeprom(sp, 0x7F0, org_7F0, 3);
  4705. *data = fail;
  4706. return fail;
  4707. }
  4708. /**
  4709. * s2io_bist_test - invokes the MemBist test of the card .
  4710. * @sp : private member of the device structure, which is a pointer to the
  4711. * s2io_nic structure.
  4712. * @data:variable that returns the result of each of the test conducted by
  4713. * the driver.
  4714. * Description:
  4715. * This invokes the MemBist test of the card. We give around
  4716. * 2 secs time for the Test to complete. If it's still not complete
  4717. * within this peiod, we consider that the test failed.
  4718. * Return value:
  4719. * 0 on success and -1 on failure.
  4720. */
  4721. static int s2io_bist_test(struct s2io_nic * sp, uint64_t * data)
  4722. {
  4723. u8 bist = 0;
  4724. int cnt = 0, ret = -1;
  4725. pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
  4726. bist |= PCI_BIST_START;
  4727. pci_write_config_word(sp->pdev, PCI_BIST, bist);
  4728. while (cnt < 20) {
  4729. pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
  4730. if (!(bist & PCI_BIST_START)) {
  4731. *data = (bist & PCI_BIST_CODE_MASK);
  4732. ret = 0;
  4733. break;
  4734. }
  4735. msleep(100);
  4736. cnt++;
  4737. }
  4738. return ret;
  4739. }
  4740. /**
  4741. * s2io-link_test - verifies the link state of the nic
  4742. * @sp ; private member of the device structure, which is a pointer to the
  4743. * s2io_nic structure.
  4744. * @data: variable that returns the result of each of the test conducted by
  4745. * the driver.
  4746. * Description:
  4747. * The function verifies the link state of the NIC and updates the input
  4748. * argument 'data' appropriately.
  4749. * Return value:
  4750. * 0 on success.
  4751. */
  4752. static int s2io_link_test(struct s2io_nic * sp, uint64_t * data)
  4753. {
  4754. struct XENA_dev_config __iomem *bar0 = sp->bar0;
  4755. u64 val64;
  4756. val64 = readq(&bar0->adapter_status);
  4757. if(!(LINK_IS_UP(val64)))
  4758. *data = 1;
  4759. else
  4760. *data = 0;
  4761. return *data;
  4762. }
  4763. /**
  4764. * s2io_rldram_test - offline test for access to the RldRam chip on the NIC
  4765. * @sp - private member of the device structure, which is a pointer to the
  4766. * s2io_nic structure.
  4767. * @data - variable that returns the result of each of the test
  4768. * conducted by the driver.
  4769. * Description:
  4770. * This is one of the offline test that tests the read and write
  4771. * access to the RldRam chip on the NIC.
  4772. * Return value:
  4773. * 0 on success.
  4774. */
  4775. static int s2io_rldram_test(struct s2io_nic * sp, uint64_t * data)
  4776. {
  4777. struct XENA_dev_config __iomem *bar0 = sp->bar0;
  4778. u64 val64;
  4779. int cnt, iteration = 0, test_fail = 0;
  4780. val64 = readq(&bar0->adapter_control);
  4781. val64 &= ~ADAPTER_ECC_EN;
  4782. writeq(val64, &bar0->adapter_control);
  4783. val64 = readq(&bar0->mc_rldram_test_ctrl);
  4784. val64 |= MC_RLDRAM_TEST_MODE;
  4785. SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
  4786. val64 = readq(&bar0->mc_rldram_mrs);
  4787. val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE;
  4788. SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
  4789. val64 |= MC_RLDRAM_MRS_ENABLE;
  4790. SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
  4791. while (iteration < 2) {
  4792. val64 = 0x55555555aaaa0000ULL;
  4793. if (iteration == 1) {
  4794. val64 ^= 0xFFFFFFFFFFFF0000ULL;
  4795. }
  4796. writeq(val64, &bar0->mc_rldram_test_d0);
  4797. val64 = 0xaaaa5a5555550000ULL;
  4798. if (iteration == 1) {
  4799. val64 ^= 0xFFFFFFFFFFFF0000ULL;
  4800. }
  4801. writeq(val64, &bar0->mc_rldram_test_d1);
  4802. val64 = 0x55aaaaaaaa5a0000ULL;
  4803. if (iteration == 1) {
  4804. val64 ^= 0xFFFFFFFFFFFF0000ULL;
  4805. }
  4806. writeq(val64, &bar0->mc_rldram_test_d2);
  4807. val64 = (u64) (0x0000003ffffe0100ULL);
  4808. writeq(val64, &bar0->mc_rldram_test_add);
  4809. val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_WRITE |
  4810. MC_RLDRAM_TEST_GO;
  4811. SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
  4812. for (cnt = 0; cnt < 5; cnt++) {
  4813. val64 = readq(&bar0->mc_rldram_test_ctrl);
  4814. if (val64 & MC_RLDRAM_TEST_DONE)
  4815. break;
  4816. msleep(200);
  4817. }
  4818. if (cnt == 5)
  4819. break;
  4820. val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_GO;
  4821. SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
  4822. for (cnt = 0; cnt < 5; cnt++) {
  4823. val64 = readq(&bar0->mc_rldram_test_ctrl);
  4824. if (val64 & MC_RLDRAM_TEST_DONE)
  4825. break;
  4826. msleep(500);
  4827. }
  4828. if (cnt == 5)
  4829. break;
  4830. val64 = readq(&bar0->mc_rldram_test_ctrl);
  4831. if (!(val64 & MC_RLDRAM_TEST_PASS))
  4832. test_fail = 1;
  4833. iteration++;
  4834. }
  4835. *data = test_fail;
  4836. /* Bring the adapter out of test mode */
  4837. SPECIAL_REG_WRITE(0, &bar0->mc_rldram_test_ctrl, LF);
  4838. return test_fail;
  4839. }
  4840. /**
  4841. * s2io_ethtool_test - conducts 6 tsets to determine the health of card.
  4842. * @sp : private member of the device structure, which is a pointer to the
  4843. * s2io_nic structure.
  4844. * @ethtest : pointer to a ethtool command specific structure that will be
  4845. * returned to the user.
  4846. * @data : variable that returns the result of each of the test
  4847. * conducted by the driver.
  4848. * Description:
  4849. * This function conducts 6 tests ( 4 offline and 2 online) to determine
  4850. * the health of the card.
  4851. * Return value:
  4852. * void
  4853. */
  4854. static void s2io_ethtool_test(struct net_device *dev,
  4855. struct ethtool_test *ethtest,
  4856. uint64_t * data)
  4857. {
  4858. struct s2io_nic *sp = dev->priv;
  4859. int orig_state = netif_running(sp->dev);
  4860. if (ethtest->flags == ETH_TEST_FL_OFFLINE) {
  4861. /* Offline Tests. */
  4862. if (orig_state)
  4863. s2io_close(sp->dev);
  4864. if (s2io_register_test(sp, &data[0]))
  4865. ethtest->flags |= ETH_TEST_FL_FAILED;
  4866. s2io_reset(sp);
  4867. if (s2io_rldram_test(sp, &data[3]))
  4868. ethtest->flags |= ETH_TEST_FL_FAILED;
  4869. s2io_reset(sp);
  4870. if (s2io_eeprom_test(sp, &data[1]))
  4871. ethtest->flags |= ETH_TEST_FL_FAILED;
  4872. if (s2io_bist_test(sp, &data[4]))
  4873. ethtest->flags |= ETH_TEST_FL_FAILED;
  4874. if (orig_state)
  4875. s2io_open(sp->dev);
  4876. data[2] = 0;
  4877. } else {
  4878. /* Online Tests. */
  4879. if (!orig_state) {
  4880. DBG_PRINT(ERR_DBG,
  4881. "%s: is not up, cannot run test\n",
  4882. dev->name);
  4883. data[0] = -1;
  4884. data[1] = -1;
  4885. data[2] = -1;
  4886. data[3] = -1;
  4887. data[4] = -1;
  4888. }
  4889. if (s2io_link_test(sp, &data[2]))
  4890. ethtest->flags |= ETH_TEST_FL_FAILED;
  4891. data[0] = 0;
  4892. data[1] = 0;
  4893. data[3] = 0;
  4894. data[4] = 0;
  4895. }
  4896. }
  4897. static void s2io_get_ethtool_stats(struct net_device *dev,
  4898. struct ethtool_stats *estats,
  4899. u64 * tmp_stats)
  4900. {
  4901. int i = 0;
  4902. struct s2io_nic *sp = dev->priv;
  4903. struct stat_block *stat_info = sp->mac_control.stats_info;
  4904. s2io_updt_stats(sp);
  4905. tmp_stats[i++] =
  4906. (u64)le32_to_cpu(stat_info->tmac_frms_oflow) << 32 |
  4907. le32_to_cpu(stat_info->tmac_frms);
  4908. tmp_stats[i++] =
  4909. (u64)le32_to_cpu(stat_info->tmac_data_octets_oflow) << 32 |
  4910. le32_to_cpu(stat_info->tmac_data_octets);
  4911. tmp_stats[i++] = le64_to_cpu(stat_info->tmac_drop_frms);
  4912. tmp_stats[i++] =
  4913. (u64)le32_to_cpu(stat_info->tmac_mcst_frms_oflow) << 32 |
  4914. le32_to_cpu(stat_info->tmac_mcst_frms);
  4915. tmp_stats[i++] =
  4916. (u64)le32_to_cpu(stat_info->tmac_bcst_frms_oflow) << 32 |
  4917. le32_to_cpu(stat_info->tmac_bcst_frms);
  4918. tmp_stats[i++] = le64_to_cpu(stat_info->tmac_pause_ctrl_frms);
  4919. tmp_stats[i++] =
  4920. (u64)le32_to_cpu(stat_info->tmac_ttl_octets_oflow) << 32 |
  4921. le32_to_cpu(stat_info->tmac_ttl_octets);
  4922. tmp_stats[i++] =
  4923. (u64)le32_to_cpu(stat_info->tmac_ucst_frms_oflow) << 32 |
  4924. le32_to_cpu(stat_info->tmac_ucst_frms);
  4925. tmp_stats[i++] =
  4926. (u64)le32_to_cpu(stat_info->tmac_nucst_frms_oflow) << 32 |
  4927. le32_to_cpu(stat_info->tmac_nucst_frms);
  4928. tmp_stats[i++] =
  4929. (u64)le32_to_cpu(stat_info->tmac_any_err_frms_oflow) << 32 |
  4930. le32_to_cpu(stat_info->tmac_any_err_frms);
  4931. tmp_stats[i++] = le64_to_cpu(stat_info->tmac_ttl_less_fb_octets);
  4932. tmp_stats[i++] = le64_to_cpu(stat_info->tmac_vld_ip_octets);
  4933. tmp_stats[i++] =
  4934. (u64)le32_to_cpu(stat_info->tmac_vld_ip_oflow) << 32 |
  4935. le32_to_cpu(stat_info->tmac_vld_ip);
  4936. tmp_stats[i++] =
  4937. (u64)le32_to_cpu(stat_info->tmac_drop_ip_oflow) << 32 |
  4938. le32_to_cpu(stat_info->tmac_drop_ip);
  4939. tmp_stats[i++] =
  4940. (u64)le32_to_cpu(stat_info->tmac_icmp_oflow) << 32 |
  4941. le32_to_cpu(stat_info->tmac_icmp);
  4942. tmp_stats[i++] =
  4943. (u64)le32_to_cpu(stat_info->tmac_rst_tcp_oflow) << 32 |
  4944. le32_to_cpu(stat_info->tmac_rst_tcp);
  4945. tmp_stats[i++] = le64_to_cpu(stat_info->tmac_tcp);
  4946. tmp_stats[i++] = (u64)le32_to_cpu(stat_info->tmac_udp_oflow) << 32 |
  4947. le32_to_cpu(stat_info->tmac_udp);
  4948. tmp_stats[i++] =
  4949. (u64)le32_to_cpu(stat_info->rmac_vld_frms_oflow) << 32 |
  4950. le32_to_cpu(stat_info->rmac_vld_frms);
  4951. tmp_stats[i++] =
  4952. (u64)le32_to_cpu(stat_info->rmac_data_octets_oflow) << 32 |
  4953. le32_to_cpu(stat_info->rmac_data_octets);
  4954. tmp_stats[i++] = le64_to_cpu(stat_info->rmac_fcs_err_frms);
  4955. tmp_stats[i++] = le64_to_cpu(stat_info->rmac_drop_frms);
  4956. tmp_stats[i++] =
  4957. (u64)le32_to_cpu(stat_info->rmac_vld_mcst_frms_oflow) << 32 |
  4958. le32_to_cpu(stat_info->rmac_vld_mcst_frms);
  4959. tmp_stats[i++] =
  4960. (u64)le32_to_cpu(stat_info->rmac_vld_bcst_frms_oflow) << 32 |
  4961. le32_to_cpu(stat_info->rmac_vld_bcst_frms);
  4962. tmp_stats[i++] = le32_to_cpu(stat_info->rmac_in_rng_len_err_frms);
  4963. tmp_stats[i++] = le32_to_cpu(stat_info->rmac_out_rng_len_err_frms);
  4964. tmp_stats[i++] = le64_to_cpu(stat_info->rmac_long_frms);
  4965. tmp_stats[i++] = le64_to_cpu(stat_info->rmac_pause_ctrl_frms);
  4966. tmp_stats[i++] = le64_to_cpu(stat_info->rmac_unsup_ctrl_frms);
  4967. tmp_stats[i++] =
  4968. (u64)le32_to_cpu(stat_info->rmac_ttl_octets_oflow) << 32 |
  4969. le32_to_cpu(stat_info->rmac_ttl_octets);
  4970. tmp_stats[i++] =
  4971. (u64)le32_to_cpu(stat_info->rmac_accepted_ucst_frms_oflow)
  4972. << 32 | le32_to_cpu(stat_info->rmac_accepted_ucst_frms);
  4973. tmp_stats[i++] =
  4974. (u64)le32_to_cpu(stat_info->rmac_accepted_nucst_frms_oflow)
  4975. << 32 | le32_to_cpu(stat_info->rmac_accepted_nucst_frms);
  4976. tmp_stats[i++] =
  4977. (u64)le32_to_cpu(stat_info->rmac_discarded_frms_oflow) << 32 |
  4978. le32_to_cpu(stat_info->rmac_discarded_frms);
  4979. tmp_stats[i++] =
  4980. (u64)le32_to_cpu(stat_info->rmac_drop_events_oflow)
  4981. << 32 | le32_to_cpu(stat_info->rmac_drop_events);
  4982. tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_less_fb_octets);
  4983. tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_frms);
  4984. tmp_stats[i++] =
  4985. (u64)le32_to_cpu(stat_info->rmac_usized_frms_oflow) << 32 |
  4986. le32_to_cpu(stat_info->rmac_usized_frms);
  4987. tmp_stats[i++] =
  4988. (u64)le32_to_cpu(stat_info->rmac_osized_frms_oflow) << 32 |
  4989. le32_to_cpu(stat_info->rmac_osized_frms);
  4990. tmp_stats[i++] =
  4991. (u64)le32_to_cpu(stat_info->rmac_frag_frms_oflow) << 32 |
  4992. le32_to_cpu(stat_info->rmac_frag_frms);
  4993. tmp_stats[i++] =
  4994. (u64)le32_to_cpu(stat_info->rmac_jabber_frms_oflow) << 32 |
  4995. le32_to_cpu(stat_info->rmac_jabber_frms);
  4996. tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_64_frms);
  4997. tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_65_127_frms);
  4998. tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_128_255_frms);
  4999. tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_256_511_frms);
  5000. tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_512_1023_frms);
  5001. tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_1024_1518_frms);
  5002. tmp_stats[i++] =
  5003. (u64)le32_to_cpu(stat_info->rmac_ip_oflow) << 32 |
  5004. le32_to_cpu(stat_info->rmac_ip);
  5005. tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ip_octets);
  5006. tmp_stats[i++] = le32_to_cpu(stat_info->rmac_hdr_err_ip);
  5007. tmp_stats[i++] =
  5008. (u64)le32_to_cpu(stat_info->rmac_drop_ip_oflow) << 32 |
  5009. le32_to_cpu(stat_info->rmac_drop_ip);
  5010. tmp_stats[i++] =
  5011. (u64)le32_to_cpu(stat_info->rmac_icmp_oflow) << 32 |
  5012. le32_to_cpu(stat_info->rmac_icmp);
  5013. tmp_stats[i++] = le64_to_cpu(stat_info->rmac_tcp);
  5014. tmp_stats[i++] =
  5015. (u64)le32_to_cpu(stat_info->rmac_udp_oflow) << 32 |
  5016. le32_to_cpu(stat_info->rmac_udp);
  5017. tmp_stats[i++] =
  5018. (u64)le32_to_cpu(stat_info->rmac_err_drp_udp_oflow) << 32 |
  5019. le32_to_cpu(stat_info->rmac_err_drp_udp);
  5020. tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_err_sym);
  5021. tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q0);
  5022. tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q1);
  5023. tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q2);
  5024. tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q3);
  5025. tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q4);
  5026. tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q5);
  5027. tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q6);
  5028. tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q7);
  5029. tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q0);
  5030. tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q1);
  5031. tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q2);
  5032. tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q3);
  5033. tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q4);
  5034. tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q5);
  5035. tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q6);
  5036. tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q7);
  5037. tmp_stats[i++] =
  5038. (u64)le32_to_cpu(stat_info->rmac_pause_cnt_oflow) << 32 |
  5039. le32_to_cpu(stat_info->rmac_pause_cnt);
  5040. tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_data_err_cnt);
  5041. tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_ctrl_err_cnt);
  5042. tmp_stats[i++] =
  5043. (u64)le32_to_cpu(stat_info->rmac_accepted_ip_oflow) << 32 |
  5044. le32_to_cpu(stat_info->rmac_accepted_ip);
  5045. tmp_stats[i++] = le32_to_cpu(stat_info->rmac_err_tcp);
  5046. tmp_stats[i++] = le32_to_cpu(stat_info->rd_req_cnt);
  5047. tmp_stats[i++] = le32_to_cpu(stat_info->new_rd_req_cnt);
  5048. tmp_stats[i++] = le32_to_cpu(stat_info->new_rd_req_rtry_cnt);
  5049. tmp_stats[i++] = le32_to_cpu(stat_info->rd_rtry_cnt);
  5050. tmp_stats[i++] = le32_to_cpu(stat_info->wr_rtry_rd_ack_cnt);
  5051. tmp_stats[i++] = le32_to_cpu(stat_info->wr_req_cnt);
  5052. tmp_stats[i++] = le32_to_cpu(stat_info->new_wr_req_cnt);
  5053. tmp_stats[i++] = le32_to_cpu(stat_info->new_wr_req_rtry_cnt);
  5054. tmp_stats[i++] = le32_to_cpu(stat_info->wr_rtry_cnt);
  5055. tmp_stats[i++] = le32_to_cpu(stat_info->wr_disc_cnt);
  5056. tmp_stats[i++] = le32_to_cpu(stat_info->rd_rtry_wr_ack_cnt);
  5057. tmp_stats[i++] = le32_to_cpu(stat_info->txp_wr_cnt);
  5058. tmp_stats[i++] = le32_to_cpu(stat_info->txd_rd_cnt);
  5059. tmp_stats[i++] = le32_to_cpu(stat_info->txd_wr_cnt);
  5060. tmp_stats[i++] = le32_to_cpu(stat_info->rxd_rd_cnt);
  5061. tmp_stats[i++] = le32_to_cpu(stat_info->rxd_wr_cnt);
  5062. tmp_stats[i++] = le32_to_cpu(stat_info->txf_rd_cnt);
  5063. tmp_stats[i++] = le32_to_cpu(stat_info->rxf_wr_cnt);
  5064. tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_1519_4095_frms);
  5065. tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_4096_8191_frms);
  5066. tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_8192_max_frms);
  5067. tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_gt_max_frms);
  5068. tmp_stats[i++] = le64_to_cpu(stat_info->rmac_osized_alt_frms);
  5069. tmp_stats[i++] = le64_to_cpu(stat_info->rmac_jabber_alt_frms);
  5070. tmp_stats[i++] = le64_to_cpu(stat_info->rmac_gt_max_alt_frms);
  5071. tmp_stats[i++] = le64_to_cpu(stat_info->rmac_vlan_frms);
  5072. tmp_stats[i++] = le32_to_cpu(stat_info->rmac_len_discard);
  5073. tmp_stats[i++] = le32_to_cpu(stat_info->rmac_fcs_discard);
  5074. tmp_stats[i++] = le32_to_cpu(stat_info->rmac_pf_discard);
  5075. tmp_stats[i++] = le32_to_cpu(stat_info->rmac_da_discard);
  5076. tmp_stats[i++] = le32_to_cpu(stat_info->rmac_red_discard);
  5077. tmp_stats[i++] = le32_to_cpu(stat_info->rmac_rts_discard);
  5078. tmp_stats[i++] = le32_to_cpu(stat_info->rmac_ingm_full_discard);
  5079. tmp_stats[i++] = le32_to_cpu(stat_info->link_fault_cnt);
  5080. tmp_stats[i++] = 0;
  5081. tmp_stats[i++] = stat_info->sw_stat.single_ecc_errs;
  5082. tmp_stats[i++] = stat_info->sw_stat.double_ecc_errs;
  5083. tmp_stats[i++] = stat_info->sw_stat.parity_err_cnt;
  5084. tmp_stats[i++] = stat_info->sw_stat.serious_err_cnt;
  5085. tmp_stats[i++] = stat_info->sw_stat.soft_reset_cnt;
  5086. tmp_stats[i++] = stat_info->sw_stat.fifo_full_cnt;
  5087. tmp_stats[i++] = stat_info->sw_stat.ring_full_cnt;
  5088. tmp_stats[i++] = stat_info->xpak_stat.alarm_transceiver_temp_high;
  5089. tmp_stats[i++] = stat_info->xpak_stat.alarm_transceiver_temp_low;
  5090. tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_bias_current_high;
  5091. tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_bias_current_low;
  5092. tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_output_power_high;
  5093. tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_output_power_low;
  5094. tmp_stats[i++] = stat_info->xpak_stat.warn_transceiver_temp_high;
  5095. tmp_stats[i++] = stat_info->xpak_stat.warn_transceiver_temp_low;
  5096. tmp_stats[i++] = stat_info->xpak_stat.warn_laser_bias_current_high;
  5097. tmp_stats[i++] = stat_info->xpak_stat.warn_laser_bias_current_low;
  5098. tmp_stats[i++] = stat_info->xpak_stat.warn_laser_output_power_high;
  5099. tmp_stats[i++] = stat_info->xpak_stat.warn_laser_output_power_low;
  5100. tmp_stats[i++] = stat_info->sw_stat.clubbed_frms_cnt;
  5101. tmp_stats[i++] = stat_info->sw_stat.sending_both;
  5102. tmp_stats[i++] = stat_info->sw_stat.outof_sequence_pkts;
  5103. tmp_stats[i++] = stat_info->sw_stat.flush_max_pkts;
  5104. if (stat_info->sw_stat.num_aggregations) {
  5105. u64 tmp = stat_info->sw_stat.sum_avg_pkts_aggregated;
  5106. int count = 0;
  5107. /*
  5108. * Since 64-bit divide does not work on all platforms,
  5109. * do repeated subtraction.
  5110. */
  5111. while (tmp >= stat_info->sw_stat.num_aggregations) {
  5112. tmp -= stat_info->sw_stat.num_aggregations;
  5113. count++;
  5114. }
  5115. tmp_stats[i++] = count;
  5116. }
  5117. else
  5118. tmp_stats[i++] = 0;
  5119. }
  5120. static int s2io_ethtool_get_regs_len(struct net_device *dev)
  5121. {
  5122. return (XENA_REG_SPACE);
  5123. }
  5124. static u32 s2io_ethtool_get_rx_csum(struct net_device * dev)
  5125. {
  5126. struct s2io_nic *sp = dev->priv;
  5127. return (sp->rx_csum);
  5128. }
  5129. static int s2io_ethtool_set_rx_csum(struct net_device *dev, u32 data)
  5130. {
  5131. struct s2io_nic *sp = dev->priv;
  5132. if (data)
  5133. sp->rx_csum = 1;
  5134. else
  5135. sp->rx_csum = 0;
  5136. return 0;
  5137. }
  5138. static int s2io_get_eeprom_len(struct net_device *dev)
  5139. {
  5140. return (XENA_EEPROM_SPACE);
  5141. }
  5142. static int s2io_ethtool_self_test_count(struct net_device *dev)
  5143. {
  5144. return (S2IO_TEST_LEN);
  5145. }
  5146. static void s2io_ethtool_get_strings(struct net_device *dev,
  5147. u32 stringset, u8 * data)
  5148. {
  5149. switch (stringset) {
  5150. case ETH_SS_TEST:
  5151. memcpy(data, s2io_gstrings, S2IO_STRINGS_LEN);
  5152. break;
  5153. case ETH_SS_STATS:
  5154. memcpy(data, &ethtool_stats_keys,
  5155. sizeof(ethtool_stats_keys));
  5156. }
  5157. }
  5158. static int s2io_ethtool_get_stats_count(struct net_device *dev)
  5159. {
  5160. return (S2IO_STAT_LEN);
  5161. }
  5162. static int s2io_ethtool_op_set_tx_csum(struct net_device *dev, u32 data)
  5163. {
  5164. if (data)
  5165. dev->features |= NETIF_F_IP_CSUM;
  5166. else
  5167. dev->features &= ~NETIF_F_IP_CSUM;
  5168. return 0;
  5169. }
  5170. static u32 s2io_ethtool_op_get_tso(struct net_device *dev)
  5171. {
  5172. return (dev->features & NETIF_F_TSO) != 0;
  5173. }
  5174. static int s2io_ethtool_op_set_tso(struct net_device *dev, u32 data)
  5175. {
  5176. if (data)
  5177. dev->features |= (NETIF_F_TSO | NETIF_F_TSO6);
  5178. else
  5179. dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
  5180. return 0;
  5181. }
  5182. static const struct ethtool_ops netdev_ethtool_ops = {
  5183. .get_settings = s2io_ethtool_gset,
  5184. .set_settings = s2io_ethtool_sset,
  5185. .get_drvinfo = s2io_ethtool_gdrvinfo,
  5186. .get_regs_len = s2io_ethtool_get_regs_len,
  5187. .get_regs = s2io_ethtool_gregs,
  5188. .get_link = ethtool_op_get_link,
  5189. .get_eeprom_len = s2io_get_eeprom_len,
  5190. .get_eeprom = s2io_ethtool_geeprom,
  5191. .set_eeprom = s2io_ethtool_seeprom,
  5192. .get_pauseparam = s2io_ethtool_getpause_data,
  5193. .set_pauseparam = s2io_ethtool_setpause_data,
  5194. .get_rx_csum = s2io_ethtool_get_rx_csum,
  5195. .set_rx_csum = s2io_ethtool_set_rx_csum,
  5196. .get_tx_csum = ethtool_op_get_tx_csum,
  5197. .set_tx_csum = s2io_ethtool_op_set_tx_csum,
  5198. .get_sg = ethtool_op_get_sg,
  5199. .set_sg = ethtool_op_set_sg,
  5200. .get_tso = s2io_ethtool_op_get_tso,
  5201. .set_tso = s2io_ethtool_op_set_tso,
  5202. .get_ufo = ethtool_op_get_ufo,
  5203. .set_ufo = ethtool_op_set_ufo,
  5204. .self_test_count = s2io_ethtool_self_test_count,
  5205. .self_test = s2io_ethtool_test,
  5206. .get_strings = s2io_ethtool_get_strings,
  5207. .phys_id = s2io_ethtool_idnic,
  5208. .get_stats_count = s2io_ethtool_get_stats_count,
  5209. .get_ethtool_stats = s2io_get_ethtool_stats
  5210. };
  5211. /**
  5212. * s2io_ioctl - Entry point for the Ioctl
  5213. * @dev : Device pointer.
  5214. * @ifr : An IOCTL specefic structure, that can contain a pointer to
  5215. * a proprietary structure used to pass information to the driver.
  5216. * @cmd : This is used to distinguish between the different commands that
  5217. * can be passed to the IOCTL functions.
  5218. * Description:
  5219. * Currently there are no special functionality supported in IOCTL, hence
  5220. * function always return EOPNOTSUPPORTED
  5221. */
  5222. static int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
  5223. {
  5224. return -EOPNOTSUPP;
  5225. }
  5226. /**
  5227. * s2io_change_mtu - entry point to change MTU size for the device.
  5228. * @dev : device pointer.
  5229. * @new_mtu : the new MTU size for the device.
  5230. * Description: A driver entry point to change MTU size for the device.
  5231. * Before changing the MTU the device must be stopped.
  5232. * Return value:
  5233. * 0 on success and an appropriate (-)ve integer as defined in errno.h
  5234. * file on failure.
  5235. */
  5236. static int s2io_change_mtu(struct net_device *dev, int new_mtu)
  5237. {
  5238. struct s2io_nic *sp = dev->priv;
  5239. if ((new_mtu < MIN_MTU) || (new_mtu > S2IO_JUMBO_SIZE)) {
  5240. DBG_PRINT(ERR_DBG, "%s: MTU size is invalid.\n",
  5241. dev->name);
  5242. return -EPERM;
  5243. }
  5244. dev->mtu = new_mtu;
  5245. if (netif_running(dev)) {
  5246. s2io_card_down(sp);
  5247. netif_stop_queue(dev);
  5248. if (s2io_card_up(sp)) {
  5249. DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
  5250. __FUNCTION__);
  5251. }
  5252. if (netif_queue_stopped(dev))
  5253. netif_wake_queue(dev);
  5254. } else { /* Device is down */
  5255. struct XENA_dev_config __iomem *bar0 = sp->bar0;
  5256. u64 val64 = new_mtu;
  5257. writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
  5258. }
  5259. return 0;
  5260. }
  5261. /**
  5262. * s2io_tasklet - Bottom half of the ISR.
  5263. * @dev_adr : address of the device structure in dma_addr_t format.
  5264. * Description:
  5265. * This is the tasklet or the bottom half of the ISR. This is
  5266. * an extension of the ISR which is scheduled by the scheduler to be run
  5267. * when the load on the CPU is low. All low priority tasks of the ISR can
  5268. * be pushed into the tasklet. For now the tasklet is used only to
  5269. * replenish the Rx buffers in the Rx buffer descriptors.
  5270. * Return value:
  5271. * void.
  5272. */
  5273. static void s2io_tasklet(unsigned long dev_addr)
  5274. {
  5275. struct net_device *dev = (struct net_device *) dev_addr;
  5276. struct s2io_nic *sp = dev->priv;
  5277. int i, ret;
  5278. struct mac_info *mac_control;
  5279. struct config_param *config;
  5280. mac_control = &sp->mac_control;
  5281. config = &sp->config;
  5282. if (!TASKLET_IN_USE) {
  5283. for (i = 0; i < config->rx_ring_num; i++) {
  5284. ret = fill_rx_buffers(sp, i);
  5285. if (ret == -ENOMEM) {
  5286. DBG_PRINT(ERR_DBG, "%s: Out of ",
  5287. dev->name);
  5288. DBG_PRINT(ERR_DBG, "memory in tasklet\n");
  5289. break;
  5290. } else if (ret == -EFILL) {
  5291. DBG_PRINT(ERR_DBG,
  5292. "%s: Rx Ring %d is full\n",
  5293. dev->name, i);
  5294. break;
  5295. }
  5296. }
  5297. clear_bit(0, (&sp->tasklet_status));
  5298. }
  5299. }
  5300. /**
  5301. * s2io_set_link - Set the LInk status
  5302. * @data: long pointer to device private structue
  5303. * Description: Sets the link status for the adapter
  5304. */
  5305. static void s2io_set_link(struct work_struct *work)
  5306. {
  5307. struct s2io_nic *nic = container_of(work, struct s2io_nic, set_link_task);
  5308. struct net_device *dev = nic->dev;
  5309. struct XENA_dev_config __iomem *bar0 = nic->bar0;
  5310. register u64 val64;
  5311. u16 subid;
  5312. rtnl_lock();
  5313. if (!netif_running(dev))
  5314. goto out_unlock;
  5315. if (test_and_set_bit(0, &(nic->link_state))) {
  5316. /* The card is being reset, no point doing anything */
  5317. goto out_unlock;
  5318. }
  5319. subid = nic->pdev->subsystem_device;
  5320. if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
  5321. /*
  5322. * Allow a small delay for the NICs self initiated
  5323. * cleanup to complete.
  5324. */
  5325. msleep(100);
  5326. }
  5327. val64 = readq(&bar0->adapter_status);
  5328. if (LINK_IS_UP(val64)) {
  5329. if (!(readq(&bar0->adapter_control) & ADAPTER_CNTL_EN)) {
  5330. if (verify_xena_quiescence(nic)) {
  5331. val64 = readq(&bar0->adapter_control);
  5332. val64 |= ADAPTER_CNTL_EN;
  5333. writeq(val64, &bar0->adapter_control);
  5334. if (CARDS_WITH_FAULTY_LINK_INDICATORS(
  5335. nic->device_type, subid)) {
  5336. val64 = readq(&bar0->gpio_control);
  5337. val64 |= GPIO_CTRL_GPIO_0;
  5338. writeq(val64, &bar0->gpio_control);
  5339. val64 = readq(&bar0->gpio_control);
  5340. } else {
  5341. val64 |= ADAPTER_LED_ON;
  5342. writeq(val64, &bar0->adapter_control);
  5343. }
  5344. nic->device_enabled_once = TRUE;
  5345. } else {
  5346. DBG_PRINT(ERR_DBG, "%s: Error: ", dev->name);
  5347. DBG_PRINT(ERR_DBG, "device is not Quiescent\n");
  5348. netif_stop_queue(dev);
  5349. }
  5350. }
  5351. val64 = readq(&bar0->adapter_status);
  5352. if (!LINK_IS_UP(val64)) {
  5353. DBG_PRINT(ERR_DBG, "%s:", dev->name);
  5354. DBG_PRINT(ERR_DBG, " Link down after enabling ");
  5355. DBG_PRINT(ERR_DBG, "device \n");
  5356. } else
  5357. s2io_link(nic, LINK_UP);
  5358. } else {
  5359. if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
  5360. subid)) {
  5361. val64 = readq(&bar0->gpio_control);
  5362. val64 &= ~GPIO_CTRL_GPIO_0;
  5363. writeq(val64, &bar0->gpio_control);
  5364. val64 = readq(&bar0->gpio_control);
  5365. }
  5366. s2io_link(nic, LINK_DOWN);
  5367. }
  5368. clear_bit(0, &(nic->link_state));
  5369. out_unlock:
  5370. rtnl_lock();
  5371. }
  5372. static int set_rxd_buffer_pointer(struct s2io_nic *sp, struct RxD_t *rxdp,
  5373. struct buffAdd *ba,
  5374. struct sk_buff **skb, u64 *temp0, u64 *temp1,
  5375. u64 *temp2, int size)
  5376. {
  5377. struct net_device *dev = sp->dev;
  5378. struct sk_buff *frag_list;
  5379. if ((sp->rxd_mode == RXD_MODE_1) && (rxdp->Host_Control == 0)) {
  5380. /* allocate skb */
  5381. if (*skb) {
  5382. DBG_PRINT(INFO_DBG, "SKB is not NULL\n");
  5383. /*
  5384. * As Rx frame are not going to be processed,
  5385. * using same mapped address for the Rxd
  5386. * buffer pointer
  5387. */
  5388. ((struct RxD1*)rxdp)->Buffer0_ptr = *temp0;
  5389. } else {
  5390. *skb = dev_alloc_skb(size);
  5391. if (!(*skb)) {
  5392. DBG_PRINT(ERR_DBG, "%s: Out of ", dev->name);
  5393. DBG_PRINT(ERR_DBG, "memory to allocate SKBs\n");
  5394. return -ENOMEM ;
  5395. }
  5396. /* storing the mapped addr in a temp variable
  5397. * such it will be used for next rxd whose
  5398. * Host Control is NULL
  5399. */
  5400. ((struct RxD1*)rxdp)->Buffer0_ptr = *temp0 =
  5401. pci_map_single( sp->pdev, (*skb)->data,
  5402. size - NET_IP_ALIGN,
  5403. PCI_DMA_FROMDEVICE);
  5404. rxdp->Host_Control = (unsigned long) (*skb);
  5405. }
  5406. } else if ((sp->rxd_mode == RXD_MODE_3B) && (rxdp->Host_Control == 0)) {
  5407. /* Two buffer Mode */
  5408. if (*skb) {
  5409. ((struct RxD3*)rxdp)->Buffer2_ptr = *temp2;
  5410. ((struct RxD3*)rxdp)->Buffer0_ptr = *temp0;
  5411. ((struct RxD3*)rxdp)->Buffer1_ptr = *temp1;
  5412. } else {
  5413. *skb = dev_alloc_skb(size);
  5414. if (!(*skb)) {
  5415. DBG_PRINT(ERR_DBG, "%s: dev_alloc_skb failed\n",
  5416. dev->name);
  5417. return -ENOMEM;
  5418. }
  5419. ((struct RxD3*)rxdp)->Buffer2_ptr = *temp2 =
  5420. pci_map_single(sp->pdev, (*skb)->data,
  5421. dev->mtu + 4,
  5422. PCI_DMA_FROMDEVICE);
  5423. ((struct RxD3*)rxdp)->Buffer0_ptr = *temp0 =
  5424. pci_map_single( sp->pdev, ba->ba_0, BUF0_LEN,
  5425. PCI_DMA_FROMDEVICE);
  5426. rxdp->Host_Control = (unsigned long) (*skb);
  5427. /* Buffer-1 will be dummy buffer not used */
  5428. ((struct RxD3*)rxdp)->Buffer1_ptr = *temp1 =
  5429. pci_map_single(sp->pdev, ba->ba_1, BUF1_LEN,
  5430. PCI_DMA_FROMDEVICE);
  5431. }
  5432. } else if ((rxdp->Host_Control == 0)) {
  5433. /* Three buffer mode */
  5434. if (*skb) {
  5435. ((struct RxD3*)rxdp)->Buffer0_ptr = *temp0;
  5436. ((struct RxD3*)rxdp)->Buffer1_ptr = *temp1;
  5437. ((struct RxD3*)rxdp)->Buffer2_ptr = *temp2;
  5438. } else {
  5439. *skb = dev_alloc_skb(size);
  5440. if (!(*skb)) {
  5441. DBG_PRINT(ERR_DBG, "%s: dev_alloc_skb failed\n",
  5442. dev->name);
  5443. return -ENOMEM;
  5444. }
  5445. ((struct RxD3*)rxdp)->Buffer0_ptr = *temp0 =
  5446. pci_map_single(sp->pdev, ba->ba_0, BUF0_LEN,
  5447. PCI_DMA_FROMDEVICE);
  5448. /* Buffer-1 receives L3/L4 headers */
  5449. ((struct RxD3*)rxdp)->Buffer1_ptr = *temp1 =
  5450. pci_map_single( sp->pdev, (*skb)->data,
  5451. l3l4hdr_size + 4,
  5452. PCI_DMA_FROMDEVICE);
  5453. /*
  5454. * skb_shinfo(skb)->frag_list will have L4
  5455. * data payload
  5456. */
  5457. skb_shinfo(*skb)->frag_list = dev_alloc_skb(dev->mtu +
  5458. ALIGN_SIZE);
  5459. if (skb_shinfo(*skb)->frag_list == NULL) {
  5460. DBG_PRINT(ERR_DBG, "%s: dev_alloc_skb \
  5461. failed\n ", dev->name);
  5462. return -ENOMEM ;
  5463. }
  5464. frag_list = skb_shinfo(*skb)->frag_list;
  5465. frag_list->next = NULL;
  5466. /*
  5467. * Buffer-2 receives L4 data payload
  5468. */
  5469. ((struct RxD3*)rxdp)->Buffer2_ptr = *temp2 =
  5470. pci_map_single( sp->pdev, frag_list->data,
  5471. dev->mtu, PCI_DMA_FROMDEVICE);
  5472. }
  5473. }
  5474. return 0;
  5475. }
  5476. static void set_rxd_buffer_size(struct s2io_nic *sp, struct RxD_t *rxdp,
  5477. int size)
  5478. {
  5479. struct net_device *dev = sp->dev;
  5480. if (sp->rxd_mode == RXD_MODE_1) {
  5481. rxdp->Control_2 = SET_BUFFER0_SIZE_1( size - NET_IP_ALIGN);
  5482. } else if (sp->rxd_mode == RXD_MODE_3B) {
  5483. rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
  5484. rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
  5485. rxdp->Control_2 |= SET_BUFFER2_SIZE_3( dev->mtu + 4);
  5486. } else {
  5487. rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
  5488. rxdp->Control_2 |= SET_BUFFER1_SIZE_3(l3l4hdr_size + 4);
  5489. rxdp->Control_2 |= SET_BUFFER2_SIZE_3(dev->mtu);
  5490. }
  5491. }
  5492. static int rxd_owner_bit_reset(struct s2io_nic *sp)
  5493. {
  5494. int i, j, k, blk_cnt = 0, size;
  5495. struct mac_info * mac_control = &sp->mac_control;
  5496. struct config_param *config = &sp->config;
  5497. struct net_device *dev = sp->dev;
  5498. struct RxD_t *rxdp = NULL;
  5499. struct sk_buff *skb = NULL;
  5500. struct buffAdd *ba = NULL;
  5501. u64 temp0_64 = 0, temp1_64 = 0, temp2_64 = 0;
  5502. /* Calculate the size based on ring mode */
  5503. size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
  5504. HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
  5505. if (sp->rxd_mode == RXD_MODE_1)
  5506. size += NET_IP_ALIGN;
  5507. else if (sp->rxd_mode == RXD_MODE_3B)
  5508. size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
  5509. else
  5510. size = l3l4hdr_size + ALIGN_SIZE + BUF0_LEN + 4;
  5511. for (i = 0; i < config->rx_ring_num; i++) {
  5512. blk_cnt = config->rx_cfg[i].num_rxd /
  5513. (rxd_count[sp->rxd_mode] +1);
  5514. for (j = 0; j < blk_cnt; j++) {
  5515. for (k = 0; k < rxd_count[sp->rxd_mode]; k++) {
  5516. rxdp = mac_control->rings[i].
  5517. rx_blocks[j].rxds[k].virt_addr;
  5518. if(sp->rxd_mode >= RXD_MODE_3A)
  5519. ba = &mac_control->rings[i].ba[j][k];
  5520. if (set_rxd_buffer_pointer(sp, rxdp, ba,
  5521. &skb,(u64 *)&temp0_64,
  5522. (u64 *)&temp1_64,
  5523. (u64 *)&temp2_64,
  5524. size) == ENOMEM) {
  5525. return 0;
  5526. }
  5527. set_rxd_buffer_size(sp, rxdp, size);
  5528. wmb();
  5529. /* flip the Ownership bit to Hardware */
  5530. rxdp->Control_1 |= RXD_OWN_XENA;
  5531. }
  5532. }
  5533. }
  5534. return 0;
  5535. }
  5536. static int s2io_add_isr(struct s2io_nic * sp)
  5537. {
  5538. int ret = 0;
  5539. struct net_device *dev = sp->dev;
  5540. int err = 0;
  5541. if (sp->intr_type == MSI)
  5542. ret = s2io_enable_msi(sp);
  5543. else if (sp->intr_type == MSI_X)
  5544. ret = s2io_enable_msi_x(sp);
  5545. if (ret) {
  5546. DBG_PRINT(ERR_DBG, "%s: Defaulting to INTA\n", dev->name);
  5547. sp->intr_type = INTA;
  5548. }
  5549. /* Store the values of the MSIX table in the struct s2io_nic structure */
  5550. store_xmsi_data(sp);
  5551. /* After proper initialization of H/W, register ISR */
  5552. if (sp->intr_type == MSI) {
  5553. err = request_irq((int) sp->pdev->irq, s2io_msi_handle,
  5554. IRQF_SHARED, sp->name, dev);
  5555. if (err) {
  5556. pci_disable_msi(sp->pdev);
  5557. DBG_PRINT(ERR_DBG, "%s: MSI registration failed\n",
  5558. dev->name);
  5559. return -1;
  5560. }
  5561. }
  5562. if (sp->intr_type == MSI_X) {
  5563. int i, msix_tx_cnt=0,msix_rx_cnt=0;
  5564. for (i=1; (sp->s2io_entries[i].in_use == MSIX_FLG); i++) {
  5565. if (sp->s2io_entries[i].type == MSIX_FIFO_TYPE) {
  5566. sprintf(sp->desc[i], "%s:MSI-X-%d-TX",
  5567. dev->name, i);
  5568. err = request_irq(sp->entries[i].vector,
  5569. s2io_msix_fifo_handle, 0, sp->desc[i],
  5570. sp->s2io_entries[i].arg);
  5571. /* If either data or addr is zero print it */
  5572. if(!(sp->msix_info[i].addr &&
  5573. sp->msix_info[i].data)) {
  5574. DBG_PRINT(ERR_DBG, "%s @ Addr:0x%llx"
  5575. "Data:0x%lx\n",sp->desc[i],
  5576. (unsigned long long)
  5577. sp->msix_info[i].addr,
  5578. (unsigned long)
  5579. ntohl(sp->msix_info[i].data));
  5580. } else {
  5581. msix_tx_cnt++;
  5582. }
  5583. } else {
  5584. sprintf(sp->desc[i], "%s:MSI-X-%d-RX",
  5585. dev->name, i);
  5586. err = request_irq(sp->entries[i].vector,
  5587. s2io_msix_ring_handle, 0, sp->desc[i],
  5588. sp->s2io_entries[i].arg);
  5589. /* If either data or addr is zero print it */
  5590. if(!(sp->msix_info[i].addr &&
  5591. sp->msix_info[i].data)) {
  5592. DBG_PRINT(ERR_DBG, "%s @ Addr:0x%llx"
  5593. "Data:0x%lx\n",sp->desc[i],
  5594. (unsigned long long)
  5595. sp->msix_info[i].addr,
  5596. (unsigned long)
  5597. ntohl(sp->msix_info[i].data));
  5598. } else {
  5599. msix_rx_cnt++;
  5600. }
  5601. }
  5602. if (err) {
  5603. DBG_PRINT(ERR_DBG,"%s:MSI-X-%d registration "
  5604. "failed\n", dev->name, i);
  5605. DBG_PRINT(ERR_DBG, "Returned: %d\n", err);
  5606. return -1;
  5607. }
  5608. sp->s2io_entries[i].in_use = MSIX_REGISTERED_SUCCESS;
  5609. }
  5610. printk("MSI-X-TX %d entries enabled\n",msix_tx_cnt);
  5611. printk("MSI-X-RX %d entries enabled\n",msix_rx_cnt);
  5612. }
  5613. if (sp->intr_type == INTA) {
  5614. err = request_irq((int) sp->pdev->irq, s2io_isr, IRQF_SHARED,
  5615. sp->name, dev);
  5616. if (err) {
  5617. DBG_PRINT(ERR_DBG, "%s: ISR registration failed\n",
  5618. dev->name);
  5619. return -1;
  5620. }
  5621. }
  5622. return 0;
  5623. }
  5624. static void s2io_rem_isr(struct s2io_nic * sp)
  5625. {
  5626. int cnt = 0;
  5627. struct net_device *dev = sp->dev;
  5628. if (sp->intr_type == MSI_X) {
  5629. int i;
  5630. u16 msi_control;
  5631. for (i=1; (sp->s2io_entries[i].in_use ==
  5632. MSIX_REGISTERED_SUCCESS); i++) {
  5633. int vector = sp->entries[i].vector;
  5634. void *arg = sp->s2io_entries[i].arg;
  5635. free_irq(vector, arg);
  5636. }
  5637. pci_read_config_word(sp->pdev, 0x42, &msi_control);
  5638. msi_control &= 0xFFFE; /* Disable MSI */
  5639. pci_write_config_word(sp->pdev, 0x42, msi_control);
  5640. pci_disable_msix(sp->pdev);
  5641. } else {
  5642. free_irq(sp->pdev->irq, dev);
  5643. if (sp->intr_type == MSI) {
  5644. u16 val;
  5645. pci_disable_msi(sp->pdev);
  5646. pci_read_config_word(sp->pdev, 0x4c, &val);
  5647. val ^= 0x1;
  5648. pci_write_config_word(sp->pdev, 0x4c, val);
  5649. }
  5650. }
  5651. /* Waiting till all Interrupt handlers are complete */
  5652. cnt = 0;
  5653. do {
  5654. msleep(10);
  5655. if (!atomic_read(&sp->isr_cnt))
  5656. break;
  5657. cnt++;
  5658. } while(cnt < 5);
  5659. }
  5660. static void s2io_card_down(struct s2io_nic * sp)
  5661. {
  5662. int cnt = 0;
  5663. struct XENA_dev_config __iomem *bar0 = sp->bar0;
  5664. unsigned long flags;
  5665. register u64 val64 = 0;
  5666. del_timer_sync(&sp->alarm_timer);
  5667. /* If s2io_set_link task is executing, wait till it completes. */
  5668. while (test_and_set_bit(0, &(sp->link_state))) {
  5669. msleep(50);
  5670. }
  5671. atomic_set(&sp->card_state, CARD_DOWN);
  5672. /* disable Tx and Rx traffic on the NIC */
  5673. stop_nic(sp);
  5674. s2io_rem_isr(sp);
  5675. /* Kill tasklet. */
  5676. tasklet_kill(&sp->task);
  5677. /* Check if the device is Quiescent and then Reset the NIC */
  5678. do {
  5679. /* As per the HW requirement we need to replenish the
  5680. * receive buffer to avoid the ring bump. Since there is
  5681. * no intention of processing the Rx frame at this pointwe are
  5682. * just settting the ownership bit of rxd in Each Rx
  5683. * ring to HW and set the appropriate buffer size
  5684. * based on the ring mode
  5685. */
  5686. rxd_owner_bit_reset(sp);
  5687. val64 = readq(&bar0->adapter_status);
  5688. if (verify_xena_quiescence(sp)) {
  5689. if(verify_pcc_quiescent(sp, sp->device_enabled_once))
  5690. break;
  5691. }
  5692. msleep(50);
  5693. cnt++;
  5694. if (cnt == 10) {
  5695. DBG_PRINT(ERR_DBG,
  5696. "s2io_close:Device not Quiescent ");
  5697. DBG_PRINT(ERR_DBG, "adaper status reads 0x%llx\n",
  5698. (unsigned long long) val64);
  5699. break;
  5700. }
  5701. } while (1);
  5702. s2io_reset(sp);
  5703. spin_lock_irqsave(&sp->tx_lock, flags);
  5704. /* Free all Tx buffers */
  5705. free_tx_buffers(sp);
  5706. spin_unlock_irqrestore(&sp->tx_lock, flags);
  5707. /* Free all Rx buffers */
  5708. spin_lock_irqsave(&sp->rx_lock, flags);
  5709. free_rx_buffers(sp);
  5710. spin_unlock_irqrestore(&sp->rx_lock, flags);
  5711. clear_bit(0, &(sp->link_state));
  5712. }
  5713. static int s2io_card_up(struct s2io_nic * sp)
  5714. {
  5715. int i, ret = 0;
  5716. struct mac_info *mac_control;
  5717. struct config_param *config;
  5718. struct net_device *dev = (struct net_device *) sp->dev;
  5719. u16 interruptible;
  5720. /* Initialize the H/W I/O registers */
  5721. if (init_nic(sp) != 0) {
  5722. DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
  5723. dev->name);
  5724. s2io_reset(sp);
  5725. return -ENODEV;
  5726. }
  5727. /*
  5728. * Initializing the Rx buffers. For now we are considering only 1
  5729. * Rx ring and initializing buffers into 30 Rx blocks
  5730. */
  5731. mac_control = &sp->mac_control;
  5732. config = &sp->config;
  5733. for (i = 0; i < config->rx_ring_num; i++) {
  5734. if ((ret = fill_rx_buffers(sp, i))) {
  5735. DBG_PRINT(ERR_DBG, "%s: Out of memory in Open\n",
  5736. dev->name);
  5737. s2io_reset(sp);
  5738. free_rx_buffers(sp);
  5739. return -ENOMEM;
  5740. }
  5741. DBG_PRINT(INFO_DBG, "Buf in ring:%d is %d:\n", i,
  5742. atomic_read(&sp->rx_bufs_left[i]));
  5743. }
  5744. /* Maintain the state prior to the open */
  5745. if (sp->promisc_flg)
  5746. sp->promisc_flg = 0;
  5747. if (sp->m_cast_flg) {
  5748. sp->m_cast_flg = 0;
  5749. sp->all_multi_pos= 0;
  5750. }
  5751. /* Setting its receive mode */
  5752. s2io_set_multicast(dev);
  5753. if (sp->lro) {
  5754. /* Initialize max aggregatable pkts per session based on MTU */
  5755. sp->lro_max_aggr_per_sess = ((1<<16) - 1) / dev->mtu;
  5756. /* Check if we can use(if specified) user provided value */
  5757. if (lro_max_pkts < sp->lro_max_aggr_per_sess)
  5758. sp->lro_max_aggr_per_sess = lro_max_pkts;
  5759. }
  5760. /* Enable Rx Traffic and interrupts on the NIC */
  5761. if (start_nic(sp)) {
  5762. DBG_PRINT(ERR_DBG, "%s: Starting NIC failed\n", dev->name);
  5763. s2io_reset(sp);
  5764. free_rx_buffers(sp);
  5765. return -ENODEV;
  5766. }
  5767. /* Add interrupt service routine */
  5768. if (s2io_add_isr(sp) != 0) {
  5769. if (sp->intr_type == MSI_X)
  5770. s2io_rem_isr(sp);
  5771. s2io_reset(sp);
  5772. free_rx_buffers(sp);
  5773. return -ENODEV;
  5774. }
  5775. S2IO_TIMER_CONF(sp->alarm_timer, s2io_alarm_handle, sp, (HZ/2));
  5776. /* Enable tasklet for the device */
  5777. tasklet_init(&sp->task, s2io_tasklet, (unsigned long) dev);
  5778. /* Enable select interrupts */
  5779. if (sp->intr_type != INTA)
  5780. en_dis_able_nic_intrs(sp, ENA_ALL_INTRS, DISABLE_INTRS);
  5781. else {
  5782. interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
  5783. interruptible |= TX_PIC_INTR | RX_PIC_INTR;
  5784. interruptible |= TX_MAC_INTR | RX_MAC_INTR;
  5785. en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
  5786. }
  5787. atomic_set(&sp->card_state, CARD_UP);
  5788. return 0;
  5789. }
  5790. /**
  5791. * s2io_restart_nic - Resets the NIC.
  5792. * @data : long pointer to the device private structure
  5793. * Description:
  5794. * This function is scheduled to be run by the s2io_tx_watchdog
  5795. * function after 0.5 secs to reset the NIC. The idea is to reduce
  5796. * the run time of the watch dog routine which is run holding a
  5797. * spin lock.
  5798. */
  5799. static void s2io_restart_nic(struct work_struct *work)
  5800. {
  5801. struct s2io_nic *sp = container_of(work, struct s2io_nic, rst_timer_task);
  5802. struct net_device *dev = sp->dev;
  5803. rtnl_lock();
  5804. if (!netif_running(dev))
  5805. goto out_unlock;
  5806. s2io_card_down(sp);
  5807. if (s2io_card_up(sp)) {
  5808. DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
  5809. dev->name);
  5810. }
  5811. netif_wake_queue(dev);
  5812. DBG_PRINT(ERR_DBG, "%s: was reset by Tx watchdog timer\n",
  5813. dev->name);
  5814. out_unlock:
  5815. rtnl_unlock();
  5816. }
  5817. /**
  5818. * s2io_tx_watchdog - Watchdog for transmit side.
  5819. * @dev : Pointer to net device structure
  5820. * Description:
  5821. * This function is triggered if the Tx Queue is stopped
  5822. * for a pre-defined amount of time when the Interface is still up.
  5823. * If the Interface is jammed in such a situation, the hardware is
  5824. * reset (by s2io_close) and restarted again (by s2io_open) to
  5825. * overcome any problem that might have been caused in the hardware.
  5826. * Return value:
  5827. * void
  5828. */
  5829. static void s2io_tx_watchdog(struct net_device *dev)
  5830. {
  5831. struct s2io_nic *sp = dev->priv;
  5832. if (netif_carrier_ok(dev)) {
  5833. schedule_work(&sp->rst_timer_task);
  5834. sp->mac_control.stats_info->sw_stat.soft_reset_cnt++;
  5835. }
  5836. }
  5837. /**
  5838. * rx_osm_handler - To perform some OS related operations on SKB.
  5839. * @sp: private member of the device structure,pointer to s2io_nic structure.
  5840. * @skb : the socket buffer pointer.
  5841. * @len : length of the packet
  5842. * @cksum : FCS checksum of the frame.
  5843. * @ring_no : the ring from which this RxD was extracted.
  5844. * Description:
  5845. * This function is called by the Rx interrupt serivce routine to perform
  5846. * some OS related operations on the SKB before passing it to the upper
  5847. * layers. It mainly checks if the checksum is OK, if so adds it to the
  5848. * SKBs cksum variable, increments the Rx packet count and passes the SKB
  5849. * to the upper layer. If the checksum is wrong, it increments the Rx
  5850. * packet error count, frees the SKB and returns error.
  5851. * Return value:
  5852. * SUCCESS on success and -1 on failure.
  5853. */
  5854. static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp)
  5855. {
  5856. struct s2io_nic *sp = ring_data->nic;
  5857. struct net_device *dev = (struct net_device *) sp->dev;
  5858. struct sk_buff *skb = (struct sk_buff *)
  5859. ((unsigned long) rxdp->Host_Control);
  5860. int ring_no = ring_data->ring_no;
  5861. u16 l3_csum, l4_csum;
  5862. unsigned long long err = rxdp->Control_1 & RXD_T_CODE;
  5863. struct lro *lro;
  5864. skb->dev = dev;
  5865. if (err) {
  5866. /* Check for parity error */
  5867. if (err & 0x1) {
  5868. sp->mac_control.stats_info->sw_stat.parity_err_cnt++;
  5869. }
  5870. /*
  5871. * Drop the packet if bad transfer code. Exception being
  5872. * 0x5, which could be due to unsupported IPv6 extension header.
  5873. * In this case, we let stack handle the packet.
  5874. * Note that in this case, since checksum will be incorrect,
  5875. * stack will validate the same.
  5876. */
  5877. if (err && ((err >> 48) != 0x5)) {
  5878. DBG_PRINT(ERR_DBG, "%s: Rx error Value: 0x%llx\n",
  5879. dev->name, err);
  5880. sp->stats.rx_crc_errors++;
  5881. dev_kfree_skb(skb);
  5882. atomic_dec(&sp->rx_bufs_left[ring_no]);
  5883. rxdp->Host_Control = 0;
  5884. return 0;
  5885. }
  5886. }
  5887. /* Updating statistics */
  5888. rxdp->Host_Control = 0;
  5889. sp->rx_pkt_count++;
  5890. sp->stats.rx_packets++;
  5891. if (sp->rxd_mode == RXD_MODE_1) {
  5892. int len = RXD_GET_BUFFER0_SIZE_1(rxdp->Control_2);
  5893. sp->stats.rx_bytes += len;
  5894. skb_put(skb, len);
  5895. } else if (sp->rxd_mode >= RXD_MODE_3A) {
  5896. int get_block = ring_data->rx_curr_get_info.block_index;
  5897. int get_off = ring_data->rx_curr_get_info.offset;
  5898. int buf0_len = RXD_GET_BUFFER0_SIZE_3(rxdp->Control_2);
  5899. int buf2_len = RXD_GET_BUFFER2_SIZE_3(rxdp->Control_2);
  5900. unsigned char *buff = skb_push(skb, buf0_len);
  5901. struct buffAdd *ba = &ring_data->ba[get_block][get_off];
  5902. sp->stats.rx_bytes += buf0_len + buf2_len;
  5903. memcpy(buff, ba->ba_0, buf0_len);
  5904. if (sp->rxd_mode == RXD_MODE_3A) {
  5905. int buf1_len = RXD_GET_BUFFER1_SIZE_3(rxdp->Control_2);
  5906. skb_put(skb, buf1_len);
  5907. skb->len += buf2_len;
  5908. skb->data_len += buf2_len;
  5909. skb_put(skb_shinfo(skb)->frag_list, buf2_len);
  5910. sp->stats.rx_bytes += buf1_len;
  5911. } else
  5912. skb_put(skb, buf2_len);
  5913. }
  5914. if ((rxdp->Control_1 & TCP_OR_UDP_FRAME) && ((!sp->lro) ||
  5915. (sp->lro && (!(rxdp->Control_1 & RXD_FRAME_IP_FRAG)))) &&
  5916. (sp->rx_csum)) {
  5917. l3_csum = RXD_GET_L3_CKSUM(rxdp->Control_1);
  5918. l4_csum = RXD_GET_L4_CKSUM(rxdp->Control_1);
  5919. if ((l3_csum == L3_CKSUM_OK) && (l4_csum == L4_CKSUM_OK)) {
  5920. /*
  5921. * NIC verifies if the Checksum of the received
  5922. * frame is Ok or not and accordingly returns
  5923. * a flag in the RxD.
  5924. */
  5925. skb->ip_summed = CHECKSUM_UNNECESSARY;
  5926. if (sp->lro) {
  5927. u32 tcp_len;
  5928. u8 *tcp;
  5929. int ret = 0;
  5930. ret = s2io_club_tcp_session(skb->data, &tcp,
  5931. &tcp_len, &lro, rxdp, sp);
  5932. switch (ret) {
  5933. case 3: /* Begin anew */
  5934. lro->parent = skb;
  5935. goto aggregate;
  5936. case 1: /* Aggregate */
  5937. {
  5938. lro_append_pkt(sp, lro,
  5939. skb, tcp_len);
  5940. goto aggregate;
  5941. }
  5942. case 4: /* Flush session */
  5943. {
  5944. lro_append_pkt(sp, lro,
  5945. skb, tcp_len);
  5946. queue_rx_frame(lro->parent);
  5947. clear_lro_session(lro);
  5948. sp->mac_control.stats_info->
  5949. sw_stat.flush_max_pkts++;
  5950. goto aggregate;
  5951. }
  5952. case 2: /* Flush both */
  5953. lro->parent->data_len =
  5954. lro->frags_len;
  5955. sp->mac_control.stats_info->
  5956. sw_stat.sending_both++;
  5957. queue_rx_frame(lro->parent);
  5958. clear_lro_session(lro);
  5959. goto send_up;
  5960. case 0: /* sessions exceeded */
  5961. case -1: /* non-TCP or not
  5962. * L2 aggregatable
  5963. */
  5964. case 5: /*
  5965. * First pkt in session not
  5966. * L3/L4 aggregatable
  5967. */
  5968. break;
  5969. default:
  5970. DBG_PRINT(ERR_DBG,
  5971. "%s: Samadhana!!\n",
  5972. __FUNCTION__);
  5973. BUG();
  5974. }
  5975. }
  5976. } else {
  5977. /*
  5978. * Packet with erroneous checksum, let the
  5979. * upper layers deal with it.
  5980. */
  5981. skb->ip_summed = CHECKSUM_NONE;
  5982. }
  5983. } else {
  5984. skb->ip_summed = CHECKSUM_NONE;
  5985. }
  5986. if (!sp->lro) {
  5987. skb->protocol = eth_type_trans(skb, dev);
  5988. if ((sp->vlgrp && RXD_GET_VLAN_TAG(rxdp->Control_2) &&
  5989. vlan_strip_flag)) {
  5990. /* Queueing the vlan frame to the upper layer */
  5991. if (napi)
  5992. vlan_hwaccel_receive_skb(skb, sp->vlgrp,
  5993. RXD_GET_VLAN_TAG(rxdp->Control_2));
  5994. else
  5995. vlan_hwaccel_rx(skb, sp->vlgrp,
  5996. RXD_GET_VLAN_TAG(rxdp->Control_2));
  5997. } else {
  5998. if (napi)
  5999. netif_receive_skb(skb);
  6000. else
  6001. netif_rx(skb);
  6002. }
  6003. } else {
  6004. send_up:
  6005. queue_rx_frame(skb);
  6006. }
  6007. dev->last_rx = jiffies;
  6008. aggregate:
  6009. atomic_dec(&sp->rx_bufs_left[ring_no]);
  6010. return SUCCESS;
  6011. }
  6012. /**
  6013. * s2io_link - stops/starts the Tx queue.
  6014. * @sp : private member of the device structure, which is a pointer to the
  6015. * s2io_nic structure.
  6016. * @link : inidicates whether link is UP/DOWN.
  6017. * Description:
  6018. * This function stops/starts the Tx queue depending on whether the link
  6019. * status of the NIC is is down or up. This is called by the Alarm
  6020. * interrupt handler whenever a link change interrupt comes up.
  6021. * Return value:
  6022. * void.
  6023. */
  6024. static void s2io_link(struct s2io_nic * sp, int link)
  6025. {
  6026. struct net_device *dev = (struct net_device *) sp->dev;
  6027. if (link != sp->last_link_state) {
  6028. if (link == LINK_DOWN) {
  6029. DBG_PRINT(ERR_DBG, "%s: Link down\n", dev->name);
  6030. netif_carrier_off(dev);
  6031. } else {
  6032. DBG_PRINT(ERR_DBG, "%s: Link Up\n", dev->name);
  6033. netif_carrier_on(dev);
  6034. }
  6035. }
  6036. sp->last_link_state = link;
  6037. }
  6038. /**
  6039. * get_xena_rev_id - to identify revision ID of xena.
  6040. * @pdev : PCI Dev structure
  6041. * Description:
  6042. * Function to identify the Revision ID of xena.
  6043. * Return value:
  6044. * returns the revision ID of the device.
  6045. */
  6046. static int get_xena_rev_id(struct pci_dev *pdev)
  6047. {
  6048. u8 id = 0;
  6049. int ret;
  6050. ret = pci_read_config_byte(pdev, PCI_REVISION_ID, (u8 *) & id);
  6051. return id;
  6052. }
  6053. /**
  6054. * s2io_init_pci -Initialization of PCI and PCI-X configuration registers .
  6055. * @sp : private member of the device structure, which is a pointer to the
  6056. * s2io_nic structure.
  6057. * Description:
  6058. * This function initializes a few of the PCI and PCI-X configuration registers
  6059. * with recommended values.
  6060. * Return value:
  6061. * void
  6062. */
  6063. static void s2io_init_pci(struct s2io_nic * sp)
  6064. {
  6065. u16 pci_cmd = 0, pcix_cmd = 0;
  6066. /* Enable Data Parity Error Recovery in PCI-X command register. */
  6067. pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
  6068. &(pcix_cmd));
  6069. pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
  6070. (pcix_cmd | 1));
  6071. pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
  6072. &(pcix_cmd));
  6073. /* Set the PErr Response bit in PCI command register. */
  6074. pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
  6075. pci_write_config_word(sp->pdev, PCI_COMMAND,
  6076. (pci_cmd | PCI_COMMAND_PARITY));
  6077. pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
  6078. }
  6079. static int s2io_verify_parm(struct pci_dev *pdev, u8 *dev_intr_type)
  6080. {
  6081. if ( tx_fifo_num > 8) {
  6082. DBG_PRINT(ERR_DBG, "s2io: Requested number of Tx fifos not "
  6083. "supported\n");
  6084. DBG_PRINT(ERR_DBG, "s2io: Default to 8 Tx fifos\n");
  6085. tx_fifo_num = 8;
  6086. }
  6087. if ( rx_ring_num > 8) {
  6088. DBG_PRINT(ERR_DBG, "s2io: Requested number of Rx rings not "
  6089. "supported\n");
  6090. DBG_PRINT(ERR_DBG, "s2io: Default to 8 Rx rings\n");
  6091. rx_ring_num = 8;
  6092. }
  6093. if (*dev_intr_type != INTA)
  6094. napi = 0;
  6095. #ifndef CONFIG_PCI_MSI
  6096. if (*dev_intr_type != INTA) {
  6097. DBG_PRINT(ERR_DBG, "s2io: This kernel does not support"
  6098. "MSI/MSI-X. Defaulting to INTA\n");
  6099. *dev_intr_type = INTA;
  6100. }
  6101. #else
  6102. if (*dev_intr_type > MSI_X) {
  6103. DBG_PRINT(ERR_DBG, "s2io: Wrong intr_type requested. "
  6104. "Defaulting to INTA\n");
  6105. *dev_intr_type = INTA;
  6106. }
  6107. #endif
  6108. if ((*dev_intr_type == MSI_X) &&
  6109. ((pdev->device != PCI_DEVICE_ID_HERC_WIN) &&
  6110. (pdev->device != PCI_DEVICE_ID_HERC_UNI))) {
  6111. DBG_PRINT(ERR_DBG, "s2io: Xframe I does not support MSI_X. "
  6112. "Defaulting to INTA\n");
  6113. *dev_intr_type = INTA;
  6114. }
  6115. if (rx_ring_mode > 3) {
  6116. DBG_PRINT(ERR_DBG, "s2io: Requested ring mode not supported\n");
  6117. DBG_PRINT(ERR_DBG, "s2io: Defaulting to 3-buffer mode\n");
  6118. rx_ring_mode = 3;
  6119. }
  6120. return SUCCESS;
  6121. }
  6122. /**
  6123. * rts_ds_steer - Receive traffic steering based on IPv4 or IPv6 TOS
  6124. * or Traffic class respectively.
  6125. * @nic: device peivate variable
  6126. * Description: The function configures the receive steering to
  6127. * desired receive ring.
  6128. * Return Value: SUCCESS on success and
  6129. * '-1' on failure (endian settings incorrect).
  6130. */
  6131. static int rts_ds_steer(struct s2io_nic *nic, u8 ds_codepoint, u8 ring)
  6132. {
  6133. struct XENA_dev_config __iomem *bar0 = nic->bar0;
  6134. register u64 val64 = 0;
  6135. if (ds_codepoint > 63)
  6136. return FAILURE;
  6137. val64 = RTS_DS_MEM_DATA(ring);
  6138. writeq(val64, &bar0->rts_ds_mem_data);
  6139. val64 = RTS_DS_MEM_CTRL_WE |
  6140. RTS_DS_MEM_CTRL_STROBE_NEW_CMD |
  6141. RTS_DS_MEM_CTRL_OFFSET(ds_codepoint);
  6142. writeq(val64, &bar0->rts_ds_mem_ctrl);
  6143. return wait_for_cmd_complete(&bar0->rts_ds_mem_ctrl,
  6144. RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED,
  6145. S2IO_BIT_RESET);
  6146. }
  6147. /**
  6148. * s2io_init_nic - Initialization of the adapter .
  6149. * @pdev : structure containing the PCI related information of the device.
  6150. * @pre: List of PCI devices supported by the driver listed in s2io_tbl.
  6151. * Description:
  6152. * The function initializes an adapter identified by the pci_dec structure.
  6153. * All OS related initialization including memory and device structure and
  6154. * initlaization of the device private variable is done. Also the swapper
  6155. * control register is initialized to enable read and write into the I/O
  6156. * registers of the device.
  6157. * Return value:
  6158. * returns 0 on success and negative on failure.
  6159. */
  6160. static int __devinit
  6161. s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
  6162. {
  6163. struct s2io_nic *sp;
  6164. struct net_device *dev;
  6165. int i, j, ret;
  6166. int dma_flag = FALSE;
  6167. u32 mac_up, mac_down;
  6168. u64 val64 = 0, tmp64 = 0;
  6169. struct XENA_dev_config __iomem *bar0 = NULL;
  6170. u16 subid;
  6171. struct mac_info *mac_control;
  6172. struct config_param *config;
  6173. int mode;
  6174. u8 dev_intr_type = intr_type;
  6175. if ((ret = s2io_verify_parm(pdev, &dev_intr_type)))
  6176. return ret;
  6177. if ((ret = pci_enable_device(pdev))) {
  6178. DBG_PRINT(ERR_DBG,
  6179. "s2io_init_nic: pci_enable_device failed\n");
  6180. return ret;
  6181. }
  6182. if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
  6183. DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 64bit DMA\n");
  6184. dma_flag = TRUE;
  6185. if (pci_set_consistent_dma_mask
  6186. (pdev, DMA_64BIT_MASK)) {
  6187. DBG_PRINT(ERR_DBG,
  6188. "Unable to obtain 64bit DMA for \
  6189. consistent allocations\n");
  6190. pci_disable_device(pdev);
  6191. return -ENOMEM;
  6192. }
  6193. } else if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
  6194. DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 32bit DMA\n");
  6195. } else {
  6196. pci_disable_device(pdev);
  6197. return -ENOMEM;
  6198. }
  6199. if (dev_intr_type != MSI_X) {
  6200. if (pci_request_regions(pdev, s2io_driver_name)) {
  6201. DBG_PRINT(ERR_DBG, "Request Regions failed\n");
  6202. pci_disable_device(pdev);
  6203. return -ENODEV;
  6204. }
  6205. }
  6206. else {
  6207. if (!(request_mem_region(pci_resource_start(pdev, 0),
  6208. pci_resource_len(pdev, 0), s2io_driver_name))) {
  6209. DBG_PRINT(ERR_DBG, "bar0 Request Regions failed\n");
  6210. pci_disable_device(pdev);
  6211. return -ENODEV;
  6212. }
  6213. if (!(request_mem_region(pci_resource_start(pdev, 2),
  6214. pci_resource_len(pdev, 2), s2io_driver_name))) {
  6215. DBG_PRINT(ERR_DBG, "bar1 Request Regions failed\n");
  6216. release_mem_region(pci_resource_start(pdev, 0),
  6217. pci_resource_len(pdev, 0));
  6218. pci_disable_device(pdev);
  6219. return -ENODEV;
  6220. }
  6221. }
  6222. dev = alloc_etherdev(sizeof(struct s2io_nic));
  6223. if (dev == NULL) {
  6224. DBG_PRINT(ERR_DBG, "Device allocation failed\n");
  6225. pci_disable_device(pdev);
  6226. pci_release_regions(pdev);
  6227. return -ENODEV;
  6228. }
  6229. pci_set_master(pdev);
  6230. pci_set_drvdata(pdev, dev);
  6231. SET_MODULE_OWNER(dev);
  6232. SET_NETDEV_DEV(dev, &pdev->dev);
  6233. /* Private member variable initialized to s2io NIC structure */
  6234. sp = dev->priv;
  6235. memset(sp, 0, sizeof(struct s2io_nic));
  6236. sp->dev = dev;
  6237. sp->pdev = pdev;
  6238. sp->high_dma_flag = dma_flag;
  6239. sp->device_enabled_once = FALSE;
  6240. if (rx_ring_mode == 1)
  6241. sp->rxd_mode = RXD_MODE_1;
  6242. if (rx_ring_mode == 2)
  6243. sp->rxd_mode = RXD_MODE_3B;
  6244. if (rx_ring_mode == 3)
  6245. sp->rxd_mode = RXD_MODE_3A;
  6246. sp->intr_type = dev_intr_type;
  6247. if ((pdev->device == PCI_DEVICE_ID_HERC_WIN) ||
  6248. (pdev->device == PCI_DEVICE_ID_HERC_UNI))
  6249. sp->device_type = XFRAME_II_DEVICE;
  6250. else
  6251. sp->device_type = XFRAME_I_DEVICE;
  6252. sp->lro = lro;
  6253. /* Initialize some PCI/PCI-X fields of the NIC. */
  6254. s2io_init_pci(sp);
  6255. /*
  6256. * Setting the device configuration parameters.
  6257. * Most of these parameters can be specified by the user during
  6258. * module insertion as they are module loadable parameters. If
  6259. * these parameters are not not specified during load time, they
  6260. * are initialized with default values.
  6261. */
  6262. mac_control = &sp->mac_control;
  6263. config = &sp->config;
  6264. /* Tx side parameters. */
  6265. config->tx_fifo_num = tx_fifo_num;
  6266. for (i = 0; i < MAX_TX_FIFOS; i++) {
  6267. config->tx_cfg[i].fifo_len = tx_fifo_len[i];
  6268. config->tx_cfg[i].fifo_priority = i;
  6269. }
  6270. /* mapping the QoS priority to the configured fifos */
  6271. for (i = 0; i < MAX_TX_FIFOS; i++)
  6272. config->fifo_mapping[i] = fifo_map[config->tx_fifo_num][i];
  6273. config->tx_intr_type = TXD_INT_TYPE_UTILZ;
  6274. for (i = 0; i < config->tx_fifo_num; i++) {
  6275. config->tx_cfg[i].f_no_snoop =
  6276. (NO_SNOOP_TXD | NO_SNOOP_TXD_BUFFER);
  6277. if (config->tx_cfg[i].fifo_len < 65) {
  6278. config->tx_intr_type = TXD_INT_TYPE_PER_LIST;
  6279. break;
  6280. }
  6281. }
  6282. /* + 2 because one Txd for skb->data and one Txd for UFO */
  6283. config->max_txds = MAX_SKB_FRAGS + 2;
  6284. /* Rx side parameters. */
  6285. config->rx_ring_num = rx_ring_num;
  6286. for (i = 0; i < MAX_RX_RINGS; i++) {
  6287. config->rx_cfg[i].num_rxd = rx_ring_sz[i] *
  6288. (rxd_count[sp->rxd_mode] + 1);
  6289. config->rx_cfg[i].ring_priority = i;
  6290. }
  6291. for (i = 0; i < rx_ring_num; i++) {
  6292. config->rx_cfg[i].ring_org = RING_ORG_BUFF1;
  6293. config->rx_cfg[i].f_no_snoop =
  6294. (NO_SNOOP_RXD | NO_SNOOP_RXD_BUFFER);
  6295. }
  6296. /* Setting Mac Control parameters */
  6297. mac_control->rmac_pause_time = rmac_pause_time;
  6298. mac_control->mc_pause_threshold_q0q3 = mc_pause_threshold_q0q3;
  6299. mac_control->mc_pause_threshold_q4q7 = mc_pause_threshold_q4q7;
  6300. /* Initialize Ring buffer parameters. */
  6301. for (i = 0; i < config->rx_ring_num; i++)
  6302. atomic_set(&sp->rx_bufs_left[i], 0);
  6303. /* Initialize the number of ISRs currently running */
  6304. atomic_set(&sp->isr_cnt, 0);
  6305. /* initialize the shared memory used by the NIC and the host */
  6306. if (init_shared_mem(sp)) {
  6307. DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n",
  6308. dev->name);
  6309. ret = -ENOMEM;
  6310. goto mem_alloc_failed;
  6311. }
  6312. sp->bar0 = ioremap(pci_resource_start(pdev, 0),
  6313. pci_resource_len(pdev, 0));
  6314. if (!sp->bar0) {
  6315. DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem1\n",
  6316. dev->name);
  6317. ret = -ENOMEM;
  6318. goto bar0_remap_failed;
  6319. }
  6320. sp->bar1 = ioremap(pci_resource_start(pdev, 2),
  6321. pci_resource_len(pdev, 2));
  6322. if (!sp->bar1) {
  6323. DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem2\n",
  6324. dev->name);
  6325. ret = -ENOMEM;
  6326. goto bar1_remap_failed;
  6327. }
  6328. dev->irq = pdev->irq;
  6329. dev->base_addr = (unsigned long) sp->bar0;
  6330. /* Initializing the BAR1 address as the start of the FIFO pointer. */
  6331. for (j = 0; j < MAX_TX_FIFOS; j++) {
  6332. mac_control->tx_FIFO_start[j] = (struct TxFIFO_element __iomem *)
  6333. (sp->bar1 + (j * 0x00020000));
  6334. }
  6335. /* Driver entry points */
  6336. dev->open = &s2io_open;
  6337. dev->stop = &s2io_close;
  6338. dev->hard_start_xmit = &s2io_xmit;
  6339. dev->get_stats = &s2io_get_stats;
  6340. dev->set_multicast_list = &s2io_set_multicast;
  6341. dev->do_ioctl = &s2io_ioctl;
  6342. dev->change_mtu = &s2io_change_mtu;
  6343. SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
  6344. dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
  6345. dev->vlan_rx_register = s2io_vlan_rx_register;
  6346. dev->vlan_rx_kill_vid = (void *)s2io_vlan_rx_kill_vid;
  6347. /*
  6348. * will use eth_mac_addr() for dev->set_mac_address
  6349. * mac address will be set every time dev->open() is called
  6350. */
  6351. dev->poll = s2io_poll;
  6352. dev->weight = 32;
  6353. #ifdef CONFIG_NET_POLL_CONTROLLER
  6354. dev->poll_controller = s2io_netpoll;
  6355. #endif
  6356. dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
  6357. if (sp->high_dma_flag == TRUE)
  6358. dev->features |= NETIF_F_HIGHDMA;
  6359. dev->features |= NETIF_F_TSO;
  6360. dev->features |= NETIF_F_TSO6;
  6361. if ((sp->device_type & XFRAME_II_DEVICE) && (ufo)) {
  6362. dev->features |= NETIF_F_UFO;
  6363. dev->features |= NETIF_F_HW_CSUM;
  6364. }
  6365. dev->tx_timeout = &s2io_tx_watchdog;
  6366. dev->watchdog_timeo = WATCH_DOG_TIMEOUT;
  6367. INIT_WORK(&sp->rst_timer_task, s2io_restart_nic);
  6368. INIT_WORK(&sp->set_link_task, s2io_set_link);
  6369. pci_save_state(sp->pdev);
  6370. /* Setting swapper control on the NIC, for proper reset operation */
  6371. if (s2io_set_swapper(sp)) {
  6372. DBG_PRINT(ERR_DBG, "%s:swapper settings are wrong\n",
  6373. dev->name);
  6374. ret = -EAGAIN;
  6375. goto set_swap_failed;
  6376. }
  6377. /* Verify if the Herc works on the slot its placed into */
  6378. if (sp->device_type & XFRAME_II_DEVICE) {
  6379. mode = s2io_verify_pci_mode(sp);
  6380. if (mode < 0) {
  6381. DBG_PRINT(ERR_DBG, "%s: ", __FUNCTION__);
  6382. DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n");
  6383. ret = -EBADSLT;
  6384. goto set_swap_failed;
  6385. }
  6386. }
  6387. /* Not needed for Herc */
  6388. if (sp->device_type & XFRAME_I_DEVICE) {
  6389. /*
  6390. * Fix for all "FFs" MAC address problems observed on
  6391. * Alpha platforms
  6392. */
  6393. fix_mac_address(sp);
  6394. s2io_reset(sp);
  6395. }
  6396. /*
  6397. * MAC address initialization.
  6398. * For now only one mac address will be read and used.
  6399. */
  6400. bar0 = sp->bar0;
  6401. val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
  6402. RMAC_ADDR_CMD_MEM_OFFSET(0 + MAC_MAC_ADDR_START_OFFSET);
  6403. writeq(val64, &bar0->rmac_addr_cmd_mem);
  6404. wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
  6405. RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING, S2IO_BIT_RESET);
  6406. tmp64 = readq(&bar0->rmac_addr_data0_mem);
  6407. mac_down = (u32) tmp64;
  6408. mac_up = (u32) (tmp64 >> 32);
  6409. memset(sp->def_mac_addr[0].mac_addr, 0, sizeof(ETH_ALEN));
  6410. sp->def_mac_addr[0].mac_addr[3] = (u8) (mac_up);
  6411. sp->def_mac_addr[0].mac_addr[2] = (u8) (mac_up >> 8);
  6412. sp->def_mac_addr[0].mac_addr[1] = (u8) (mac_up >> 16);
  6413. sp->def_mac_addr[0].mac_addr[0] = (u8) (mac_up >> 24);
  6414. sp->def_mac_addr[0].mac_addr[5] = (u8) (mac_down >> 16);
  6415. sp->def_mac_addr[0].mac_addr[4] = (u8) (mac_down >> 24);
  6416. /* Set the factory defined MAC address initially */
  6417. dev->addr_len = ETH_ALEN;
  6418. memcpy(dev->dev_addr, sp->def_mac_addr, ETH_ALEN);
  6419. /* reset Nic and bring it to known state */
  6420. s2io_reset(sp);
  6421. /*
  6422. * Initialize the tasklet status and link state flags
  6423. * and the card state parameter
  6424. */
  6425. atomic_set(&(sp->card_state), 0);
  6426. sp->tasklet_status = 0;
  6427. sp->link_state = 0;
  6428. /* Initialize spinlocks */
  6429. spin_lock_init(&sp->tx_lock);
  6430. if (!napi)
  6431. spin_lock_init(&sp->put_lock);
  6432. spin_lock_init(&sp->rx_lock);
  6433. /*
  6434. * SXE-002: Configure link and activity LED to init state
  6435. * on driver load.
  6436. */
  6437. subid = sp->pdev->subsystem_device;
  6438. if ((subid & 0xFF) >= 0x07) {
  6439. val64 = readq(&bar0->gpio_control);
  6440. val64 |= 0x0000800000000000ULL;
  6441. writeq(val64, &bar0->gpio_control);
  6442. val64 = 0x0411040400000000ULL;
  6443. writeq(val64, (void __iomem *) bar0 + 0x2700);
  6444. val64 = readq(&bar0->gpio_control);
  6445. }
  6446. sp->rx_csum = 1; /* Rx chksum verify enabled by default */
  6447. if (register_netdev(dev)) {
  6448. DBG_PRINT(ERR_DBG, "Device registration failed\n");
  6449. ret = -ENODEV;
  6450. goto register_failed;
  6451. }
  6452. s2io_vpd_read(sp);
  6453. DBG_PRINT(ERR_DBG, "Copyright(c) 2002-2005 Neterion Inc.\n");
  6454. DBG_PRINT(ERR_DBG, "%s: Neterion %s (rev %d)\n",dev->name,
  6455. sp->product_name, get_xena_rev_id(sp->pdev));
  6456. DBG_PRINT(ERR_DBG, "%s: Driver version %s\n", dev->name,
  6457. s2io_driver_version);
  6458. DBG_PRINT(ERR_DBG, "%s: MAC ADDR: "
  6459. "%02x:%02x:%02x:%02x:%02x:%02x", dev->name,
  6460. sp->def_mac_addr[0].mac_addr[0],
  6461. sp->def_mac_addr[0].mac_addr[1],
  6462. sp->def_mac_addr[0].mac_addr[2],
  6463. sp->def_mac_addr[0].mac_addr[3],
  6464. sp->def_mac_addr[0].mac_addr[4],
  6465. sp->def_mac_addr[0].mac_addr[5]);
  6466. DBG_PRINT(ERR_DBG, "SERIAL NUMBER: %s\n", sp->serial_num);
  6467. if (sp->device_type & XFRAME_II_DEVICE) {
  6468. mode = s2io_print_pci_mode(sp);
  6469. if (mode < 0) {
  6470. DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n");
  6471. ret = -EBADSLT;
  6472. unregister_netdev(dev);
  6473. goto set_swap_failed;
  6474. }
  6475. }
  6476. switch(sp->rxd_mode) {
  6477. case RXD_MODE_1:
  6478. DBG_PRINT(ERR_DBG, "%s: 1-Buffer receive mode enabled\n",
  6479. dev->name);
  6480. break;
  6481. case RXD_MODE_3B:
  6482. DBG_PRINT(ERR_DBG, "%s: 2-Buffer receive mode enabled\n",
  6483. dev->name);
  6484. break;
  6485. case RXD_MODE_3A:
  6486. DBG_PRINT(ERR_DBG, "%s: 3-Buffer receive mode enabled\n",
  6487. dev->name);
  6488. break;
  6489. }
  6490. if (napi)
  6491. DBG_PRINT(ERR_DBG, "%s: NAPI enabled\n", dev->name);
  6492. switch(sp->intr_type) {
  6493. case INTA:
  6494. DBG_PRINT(ERR_DBG, "%s: Interrupt type INTA\n", dev->name);
  6495. break;
  6496. case MSI:
  6497. DBG_PRINT(ERR_DBG, "%s: Interrupt type MSI\n", dev->name);
  6498. break;
  6499. case MSI_X:
  6500. DBG_PRINT(ERR_DBG, "%s: Interrupt type MSI-X\n", dev->name);
  6501. break;
  6502. }
  6503. if (sp->lro)
  6504. DBG_PRINT(ERR_DBG, "%s: Large receive offload enabled\n",
  6505. dev->name);
  6506. if (ufo)
  6507. DBG_PRINT(ERR_DBG, "%s: UDP Fragmentation Offload(UFO)"
  6508. " enabled\n", dev->name);
  6509. /* Initialize device name */
  6510. sprintf(sp->name, "%s Neterion %s", dev->name, sp->product_name);
  6511. /* Initialize bimodal Interrupts */
  6512. sp->config.bimodal = bimodal;
  6513. if (!(sp->device_type & XFRAME_II_DEVICE) && bimodal) {
  6514. sp->config.bimodal = 0;
  6515. DBG_PRINT(ERR_DBG,"%s:Bimodal intr not supported by Xframe I\n",
  6516. dev->name);
  6517. }
  6518. /*
  6519. * Make Link state as off at this point, when the Link change
  6520. * interrupt comes the state will be automatically changed to
  6521. * the right state.
  6522. */
  6523. netif_carrier_off(dev);
  6524. return 0;
  6525. register_failed:
  6526. set_swap_failed:
  6527. iounmap(sp->bar1);
  6528. bar1_remap_failed:
  6529. iounmap(sp->bar0);
  6530. bar0_remap_failed:
  6531. mem_alloc_failed:
  6532. free_shared_mem(sp);
  6533. pci_disable_device(pdev);
  6534. if (dev_intr_type != MSI_X)
  6535. pci_release_regions(pdev);
  6536. else {
  6537. release_mem_region(pci_resource_start(pdev, 0),
  6538. pci_resource_len(pdev, 0));
  6539. release_mem_region(pci_resource_start(pdev, 2),
  6540. pci_resource_len(pdev, 2));
  6541. }
  6542. pci_set_drvdata(pdev, NULL);
  6543. free_netdev(dev);
  6544. return ret;
  6545. }
  6546. /**
  6547. * s2io_rem_nic - Free the PCI device
  6548. * @pdev: structure containing the PCI related information of the device.
  6549. * Description: This function is called by the Pci subsystem to release a
  6550. * PCI device and free up all resource held up by the device. This could
  6551. * be in response to a Hot plug event or when the driver is to be removed
  6552. * from memory.
  6553. */
  6554. static void __devexit s2io_rem_nic(struct pci_dev *pdev)
  6555. {
  6556. struct net_device *dev =
  6557. (struct net_device *) pci_get_drvdata(pdev);
  6558. struct s2io_nic *sp;
  6559. if (dev == NULL) {
  6560. DBG_PRINT(ERR_DBG, "Driver Data is NULL!!\n");
  6561. return;
  6562. }
  6563. flush_scheduled_work();
  6564. sp = dev->priv;
  6565. unregister_netdev(dev);
  6566. free_shared_mem(sp);
  6567. iounmap(sp->bar0);
  6568. iounmap(sp->bar1);
  6569. if (sp->intr_type != MSI_X)
  6570. pci_release_regions(pdev);
  6571. else {
  6572. release_mem_region(pci_resource_start(pdev, 0),
  6573. pci_resource_len(pdev, 0));
  6574. release_mem_region(pci_resource_start(pdev, 2),
  6575. pci_resource_len(pdev, 2));
  6576. }
  6577. pci_set_drvdata(pdev, NULL);
  6578. free_netdev(dev);
  6579. pci_disable_device(pdev);
  6580. }
  6581. /**
  6582. * s2io_starter - Entry point for the driver
  6583. * Description: This function is the entry point for the driver. It verifies
  6584. * the module loadable parameters and initializes PCI configuration space.
  6585. */
  6586. int __init s2io_starter(void)
  6587. {
  6588. return pci_register_driver(&s2io_driver);
  6589. }
  6590. /**
  6591. * s2io_closer - Cleanup routine for the driver
  6592. * Description: This function is the cleanup routine for the driver. It unregist * ers the driver.
  6593. */
  6594. static __exit void s2io_closer(void)
  6595. {
  6596. pci_unregister_driver(&s2io_driver);
  6597. DBG_PRINT(INIT_DBG, "cleanup done\n");
  6598. }
  6599. module_init(s2io_starter);
  6600. module_exit(s2io_closer);
  6601. static int check_L2_lro_capable(u8 *buffer, struct iphdr **ip,
  6602. struct tcphdr **tcp, struct RxD_t *rxdp)
  6603. {
  6604. int ip_off;
  6605. u8 l2_type = (u8)((rxdp->Control_1 >> 37) & 0x7), ip_len;
  6606. if (!(rxdp->Control_1 & RXD_FRAME_PROTO_TCP)) {
  6607. DBG_PRINT(INIT_DBG,"%s: Non-TCP frames not supported for LRO\n",
  6608. __FUNCTION__);
  6609. return -1;
  6610. }
  6611. /* TODO:
  6612. * By default the VLAN field in the MAC is stripped by the card, if this
  6613. * feature is turned off in rx_pa_cfg register, then the ip_off field
  6614. * has to be shifted by a further 2 bytes
  6615. */
  6616. switch (l2_type) {
  6617. case 0: /* DIX type */
  6618. case 4: /* DIX type with VLAN */
  6619. ip_off = HEADER_ETHERNET_II_802_3_SIZE;
  6620. break;
  6621. /* LLC, SNAP etc are considered non-mergeable */
  6622. default:
  6623. return -1;
  6624. }
  6625. *ip = (struct iphdr *)((u8 *)buffer + ip_off);
  6626. ip_len = (u8)((*ip)->ihl);
  6627. ip_len <<= 2;
  6628. *tcp = (struct tcphdr *)((unsigned long)*ip + ip_len);
  6629. return 0;
  6630. }
  6631. static int check_for_socket_match(struct lro *lro, struct iphdr *ip,
  6632. struct tcphdr *tcp)
  6633. {
  6634. DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
  6635. if ((lro->iph->saddr != ip->saddr) || (lro->iph->daddr != ip->daddr) ||
  6636. (lro->tcph->source != tcp->source) || (lro->tcph->dest != tcp->dest))
  6637. return -1;
  6638. return 0;
  6639. }
  6640. static inline int get_l4_pyld_length(struct iphdr *ip, struct tcphdr *tcp)
  6641. {
  6642. return(ntohs(ip->tot_len) - (ip->ihl << 2) - (tcp->doff << 2));
  6643. }
  6644. static void initiate_new_session(struct lro *lro, u8 *l2h,
  6645. struct iphdr *ip, struct tcphdr *tcp, u32 tcp_pyld_len)
  6646. {
  6647. DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
  6648. lro->l2h = l2h;
  6649. lro->iph = ip;
  6650. lro->tcph = tcp;
  6651. lro->tcp_next_seq = tcp_pyld_len + ntohl(tcp->seq);
  6652. lro->tcp_ack = ntohl(tcp->ack_seq);
  6653. lro->sg_num = 1;
  6654. lro->total_len = ntohs(ip->tot_len);
  6655. lro->frags_len = 0;
  6656. /*
  6657. * check if we saw TCP timestamp. Other consistency checks have
  6658. * already been done.
  6659. */
  6660. if (tcp->doff == 8) {
  6661. u32 *ptr;
  6662. ptr = (u32 *)(tcp+1);
  6663. lro->saw_ts = 1;
  6664. lro->cur_tsval = *(ptr+1);
  6665. lro->cur_tsecr = *(ptr+2);
  6666. }
  6667. lro->in_use = 1;
  6668. }
  6669. static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro)
  6670. {
  6671. struct iphdr *ip = lro->iph;
  6672. struct tcphdr *tcp = lro->tcph;
  6673. __sum16 nchk;
  6674. struct stat_block *statinfo = sp->mac_control.stats_info;
  6675. DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
  6676. /* Update L3 header */
  6677. ip->tot_len = htons(lro->total_len);
  6678. ip->check = 0;
  6679. nchk = ip_fast_csum((u8 *)lro->iph, ip->ihl);
  6680. ip->check = nchk;
  6681. /* Update L4 header */
  6682. tcp->ack_seq = lro->tcp_ack;
  6683. tcp->window = lro->window;
  6684. /* Update tsecr field if this session has timestamps enabled */
  6685. if (lro->saw_ts) {
  6686. u32 *ptr = (u32 *)(tcp + 1);
  6687. *(ptr+2) = lro->cur_tsecr;
  6688. }
  6689. /* Update counters required for calculation of
  6690. * average no. of packets aggregated.
  6691. */
  6692. statinfo->sw_stat.sum_avg_pkts_aggregated += lro->sg_num;
  6693. statinfo->sw_stat.num_aggregations++;
  6694. }
  6695. static void aggregate_new_rx(struct lro *lro, struct iphdr *ip,
  6696. struct tcphdr *tcp, u32 l4_pyld)
  6697. {
  6698. DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
  6699. lro->total_len += l4_pyld;
  6700. lro->frags_len += l4_pyld;
  6701. lro->tcp_next_seq += l4_pyld;
  6702. lro->sg_num++;
  6703. /* Update ack seq no. and window ad(from this pkt) in LRO object */
  6704. lro->tcp_ack = tcp->ack_seq;
  6705. lro->window = tcp->window;
  6706. if (lro->saw_ts) {
  6707. u32 *ptr;
  6708. /* Update tsecr and tsval from this packet */
  6709. ptr = (u32 *) (tcp + 1);
  6710. lro->cur_tsval = *(ptr + 1);
  6711. lro->cur_tsecr = *(ptr + 2);
  6712. }
  6713. }
  6714. static int verify_l3_l4_lro_capable(struct lro *l_lro, struct iphdr *ip,
  6715. struct tcphdr *tcp, u32 tcp_pyld_len)
  6716. {
  6717. u8 *ptr;
  6718. DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
  6719. if (!tcp_pyld_len) {
  6720. /* Runt frame or a pure ack */
  6721. return -1;
  6722. }
  6723. if (ip->ihl != 5) /* IP has options */
  6724. return -1;
  6725. /* If we see CE codepoint in IP header, packet is not mergeable */
  6726. if (INET_ECN_is_ce(ipv4_get_dsfield(ip)))
  6727. return -1;
  6728. /* If we see ECE or CWR flags in TCP header, packet is not mergeable */
  6729. if (tcp->urg || tcp->psh || tcp->rst || tcp->syn || tcp->fin ||
  6730. tcp->ece || tcp->cwr || !tcp->ack) {
  6731. /*
  6732. * Currently recognize only the ack control word and
  6733. * any other control field being set would result in
  6734. * flushing the LRO session
  6735. */
  6736. return -1;
  6737. }
  6738. /*
  6739. * Allow only one TCP timestamp option. Don't aggregate if
  6740. * any other options are detected.
  6741. */
  6742. if (tcp->doff != 5 && tcp->doff != 8)
  6743. return -1;
  6744. if (tcp->doff == 8) {
  6745. ptr = (u8 *)(tcp + 1);
  6746. while (*ptr == TCPOPT_NOP)
  6747. ptr++;
  6748. if (*ptr != TCPOPT_TIMESTAMP || *(ptr+1) != TCPOLEN_TIMESTAMP)
  6749. return -1;
  6750. /* Ensure timestamp value increases monotonically */
  6751. if (l_lro)
  6752. if (l_lro->cur_tsval > *((u32 *)(ptr+2)))
  6753. return -1;
  6754. /* timestamp echo reply should be non-zero */
  6755. if (*((u32 *)(ptr+6)) == 0)
  6756. return -1;
  6757. }
  6758. return 0;
  6759. }
  6760. static int
  6761. s2io_club_tcp_session(u8 *buffer, u8 **tcp, u32 *tcp_len, struct lro **lro,
  6762. struct RxD_t *rxdp, struct s2io_nic *sp)
  6763. {
  6764. struct iphdr *ip;
  6765. struct tcphdr *tcph;
  6766. int ret = 0, i;
  6767. if (!(ret = check_L2_lro_capable(buffer, &ip, (struct tcphdr **)tcp,
  6768. rxdp))) {
  6769. DBG_PRINT(INFO_DBG,"IP Saddr: %x Daddr: %x\n",
  6770. ip->saddr, ip->daddr);
  6771. } else {
  6772. return ret;
  6773. }
  6774. tcph = (struct tcphdr *)*tcp;
  6775. *tcp_len = get_l4_pyld_length(ip, tcph);
  6776. for (i=0; i<MAX_LRO_SESSIONS; i++) {
  6777. struct lro *l_lro = &sp->lro0_n[i];
  6778. if (l_lro->in_use) {
  6779. if (check_for_socket_match(l_lro, ip, tcph))
  6780. continue;
  6781. /* Sock pair matched */
  6782. *lro = l_lro;
  6783. if ((*lro)->tcp_next_seq != ntohl(tcph->seq)) {
  6784. DBG_PRINT(INFO_DBG, "%s:Out of order. expected "
  6785. "0x%x, actual 0x%x\n", __FUNCTION__,
  6786. (*lro)->tcp_next_seq,
  6787. ntohl(tcph->seq));
  6788. sp->mac_control.stats_info->
  6789. sw_stat.outof_sequence_pkts++;
  6790. ret = 2;
  6791. break;
  6792. }
  6793. if (!verify_l3_l4_lro_capable(l_lro, ip, tcph,*tcp_len))
  6794. ret = 1; /* Aggregate */
  6795. else
  6796. ret = 2; /* Flush both */
  6797. break;
  6798. }
  6799. }
  6800. if (ret == 0) {
  6801. /* Before searching for available LRO objects,
  6802. * check if the pkt is L3/L4 aggregatable. If not
  6803. * don't create new LRO session. Just send this
  6804. * packet up.
  6805. */
  6806. if (verify_l3_l4_lro_capable(NULL, ip, tcph, *tcp_len)) {
  6807. return 5;
  6808. }
  6809. for (i=0; i<MAX_LRO_SESSIONS; i++) {
  6810. struct lro *l_lro = &sp->lro0_n[i];
  6811. if (!(l_lro->in_use)) {
  6812. *lro = l_lro;
  6813. ret = 3; /* Begin anew */
  6814. break;
  6815. }
  6816. }
  6817. }
  6818. if (ret == 0) { /* sessions exceeded */
  6819. DBG_PRINT(INFO_DBG,"%s:All LRO sessions already in use\n",
  6820. __FUNCTION__);
  6821. *lro = NULL;
  6822. return ret;
  6823. }
  6824. switch (ret) {
  6825. case 3:
  6826. initiate_new_session(*lro, buffer, ip, tcph, *tcp_len);
  6827. break;
  6828. case 2:
  6829. update_L3L4_header(sp, *lro);
  6830. break;
  6831. case 1:
  6832. aggregate_new_rx(*lro, ip, tcph, *tcp_len);
  6833. if ((*lro)->sg_num == sp->lro_max_aggr_per_sess) {
  6834. update_L3L4_header(sp, *lro);
  6835. ret = 4; /* Flush the LRO */
  6836. }
  6837. break;
  6838. default:
  6839. DBG_PRINT(ERR_DBG,"%s:Dont know, can't say!!\n",
  6840. __FUNCTION__);
  6841. break;
  6842. }
  6843. return ret;
  6844. }
  6845. static void clear_lro_session(struct lro *lro)
  6846. {
  6847. static u16 lro_struct_size = sizeof(struct lro);
  6848. memset(lro, 0, lro_struct_size);
  6849. }
  6850. static void queue_rx_frame(struct sk_buff *skb)
  6851. {
  6852. struct net_device *dev = skb->dev;
  6853. skb->protocol = eth_type_trans(skb, dev);
  6854. if (napi)
  6855. netif_receive_skb(skb);
  6856. else
  6857. netif_rx(skb);
  6858. }
  6859. static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro,
  6860. struct sk_buff *skb,
  6861. u32 tcp_len)
  6862. {
  6863. struct sk_buff *first = lro->parent;
  6864. first->len += tcp_len;
  6865. first->data_len = lro->frags_len;
  6866. skb_pull(skb, (skb->len - tcp_len));
  6867. if (skb_shinfo(first)->frag_list)
  6868. lro->last_frag->next = skb;
  6869. else
  6870. skb_shinfo(first)->frag_list = skb;
  6871. first->truesize += skb->truesize;
  6872. lro->last_frag = skb;
  6873. sp->mac_control.stats_info->sw_stat.clubbed_frms_cnt++;
  6874. return;
  6875. }