mthca_main.c 33 KB

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  1. /*
  2. * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
  3. * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
  4. * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
  5. *
  6. * This software is available to you under a choice of one of two
  7. * licenses. You may choose to be licensed under the terms of the GNU
  8. * General Public License (GPL) Version 2, available from the file
  9. * COPYING in the main directory of this source tree, or the
  10. * OpenIB.org BSD license below:
  11. *
  12. * Redistribution and use in source and binary forms, with or
  13. * without modification, are permitted provided that the following
  14. * conditions are met:
  15. *
  16. * - Redistributions of source code must retain the above
  17. * copyright notice, this list of conditions and the following
  18. * disclaimer.
  19. *
  20. * - Redistributions in binary form must reproduce the above
  21. * copyright notice, this list of conditions and the following
  22. * disclaimer in the documentation and/or other materials
  23. * provided with the distribution.
  24. *
  25. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32. * SOFTWARE.
  33. *
  34. * $Id: mthca_main.c 1396 2004-12-28 04:10:27Z roland $
  35. */
  36. #include <linux/config.h>
  37. #include <linux/module.h>
  38. #include <linux/init.h>
  39. #include <linux/errno.h>
  40. #include <linux/pci.h>
  41. #include <linux/interrupt.h>
  42. #include "mthca_dev.h"
  43. #include "mthca_config_reg.h"
  44. #include "mthca_cmd.h"
  45. #include "mthca_profile.h"
  46. #include "mthca_memfree.h"
  47. MODULE_AUTHOR("Roland Dreier");
  48. MODULE_DESCRIPTION("Mellanox InfiniBand HCA low-level driver");
  49. MODULE_LICENSE("Dual BSD/GPL");
  50. MODULE_VERSION(DRV_VERSION);
  51. #ifdef CONFIG_INFINIBAND_MTHCA_DEBUG
  52. int mthca_debug_level = 0;
  53. module_param_named(debug_level, mthca_debug_level, int, 0644);
  54. MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
  55. #endif /* CONFIG_INFINIBAND_MTHCA_DEBUG */
  56. #ifdef CONFIG_PCI_MSI
  57. static int msi_x = 0;
  58. module_param(msi_x, int, 0444);
  59. MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
  60. static int msi = 0;
  61. module_param(msi, int, 0444);
  62. MODULE_PARM_DESC(msi, "attempt to use MSI if nonzero");
  63. #else /* CONFIG_PCI_MSI */
  64. #define msi_x (0)
  65. #define msi (0)
  66. #endif /* CONFIG_PCI_MSI */
  67. static int tune_pci = 0;
  68. module_param(tune_pci, int, 0444);
  69. MODULE_PARM_DESC(tune_pci, "increase PCI burst from the default set by BIOS if nonzero");
  70. static const char mthca_version[] __devinitdata =
  71. DRV_NAME ": Mellanox InfiniBand HCA driver v"
  72. DRV_VERSION " (" DRV_RELDATE ")\n";
  73. static struct mthca_profile default_profile = {
  74. .num_qp = 1 << 16,
  75. .rdb_per_qp = 4,
  76. .num_cq = 1 << 16,
  77. .num_mcg = 1 << 13,
  78. .num_mpt = 1 << 17,
  79. .num_mtt = 1 << 20,
  80. .num_udav = 1 << 15, /* Tavor only */
  81. .fmr_reserved_mtts = 1 << 18, /* Tavor only */
  82. .uarc_size = 1 << 18, /* Arbel only */
  83. };
  84. static int __devinit mthca_tune_pci(struct mthca_dev *mdev)
  85. {
  86. int cap;
  87. u16 val;
  88. if (!tune_pci)
  89. return 0;
  90. /* First try to max out Read Byte Count */
  91. cap = pci_find_capability(mdev->pdev, PCI_CAP_ID_PCIX);
  92. if (cap) {
  93. if (pci_read_config_word(mdev->pdev, cap + PCI_X_CMD, &val)) {
  94. mthca_err(mdev, "Couldn't read PCI-X command register, "
  95. "aborting.\n");
  96. return -ENODEV;
  97. }
  98. val = (val & ~PCI_X_CMD_MAX_READ) | (3 << 2);
  99. if (pci_write_config_word(mdev->pdev, cap + PCI_X_CMD, val)) {
  100. mthca_err(mdev, "Couldn't write PCI-X command register, "
  101. "aborting.\n");
  102. return -ENODEV;
  103. }
  104. } else if (!(mdev->mthca_flags & MTHCA_FLAG_PCIE))
  105. mthca_info(mdev, "No PCI-X capability, not setting RBC.\n");
  106. cap = pci_find_capability(mdev->pdev, PCI_CAP_ID_EXP);
  107. if (cap) {
  108. if (pci_read_config_word(mdev->pdev, cap + PCI_EXP_DEVCTL, &val)) {
  109. mthca_err(mdev, "Couldn't read PCI Express device control "
  110. "register, aborting.\n");
  111. return -ENODEV;
  112. }
  113. val = (val & ~PCI_EXP_DEVCTL_READRQ) | (5 << 12);
  114. if (pci_write_config_word(mdev->pdev, cap + PCI_EXP_DEVCTL, val)) {
  115. mthca_err(mdev, "Couldn't write PCI Express device control "
  116. "register, aborting.\n");
  117. return -ENODEV;
  118. }
  119. } else if (mdev->mthca_flags & MTHCA_FLAG_PCIE)
  120. mthca_info(mdev, "No PCI Express capability, "
  121. "not setting Max Read Request Size.\n");
  122. return 0;
  123. }
  124. static int __devinit mthca_dev_lim(struct mthca_dev *mdev, struct mthca_dev_lim *dev_lim)
  125. {
  126. int err;
  127. u8 status;
  128. err = mthca_QUERY_DEV_LIM(mdev, dev_lim, &status);
  129. if (err) {
  130. mthca_err(mdev, "QUERY_DEV_LIM command failed, aborting.\n");
  131. return err;
  132. }
  133. if (status) {
  134. mthca_err(mdev, "QUERY_DEV_LIM returned status 0x%02x, "
  135. "aborting.\n", status);
  136. return -EINVAL;
  137. }
  138. if (dev_lim->min_page_sz > PAGE_SIZE) {
  139. mthca_err(mdev, "HCA minimum page size of %d bigger than "
  140. "kernel PAGE_SIZE of %ld, aborting.\n",
  141. dev_lim->min_page_sz, PAGE_SIZE);
  142. return -ENODEV;
  143. }
  144. if (dev_lim->num_ports > MTHCA_MAX_PORTS) {
  145. mthca_err(mdev, "HCA has %d ports, but we only support %d, "
  146. "aborting.\n",
  147. dev_lim->num_ports, MTHCA_MAX_PORTS);
  148. return -ENODEV;
  149. }
  150. if (dev_lim->uar_size > pci_resource_len(mdev->pdev, 2)) {
  151. mthca_err(mdev, "HCA reported UAR size of 0x%x bigger than "
  152. "PCI resource 2 size of 0x%lx, aborting.\n",
  153. dev_lim->uar_size, pci_resource_len(mdev->pdev, 2));
  154. return -ENODEV;
  155. }
  156. mdev->limits.num_ports = dev_lim->num_ports;
  157. mdev->limits.vl_cap = dev_lim->max_vl;
  158. mdev->limits.mtu_cap = dev_lim->max_mtu;
  159. mdev->limits.gid_table_len = dev_lim->max_gids;
  160. mdev->limits.pkey_table_len = dev_lim->max_pkeys;
  161. mdev->limits.local_ca_ack_delay = dev_lim->local_ca_ack_delay;
  162. mdev->limits.max_sg = dev_lim->max_sg;
  163. mdev->limits.max_wqes = dev_lim->max_qp_sz;
  164. mdev->limits.max_qp_init_rdma = dev_lim->max_requester_per_qp;
  165. mdev->limits.reserved_qps = dev_lim->reserved_qps;
  166. mdev->limits.max_srq_wqes = dev_lim->max_srq_sz;
  167. mdev->limits.reserved_srqs = dev_lim->reserved_srqs;
  168. mdev->limits.reserved_eecs = dev_lim->reserved_eecs;
  169. mdev->limits.max_desc_sz = dev_lim->max_desc_sz;
  170. /*
  171. * Subtract 1 from the limit because we need to allocate a
  172. * spare CQE so the HCA HW can tell the difference between an
  173. * empty CQ and a full CQ.
  174. */
  175. mdev->limits.max_cqes = dev_lim->max_cq_sz - 1;
  176. mdev->limits.reserved_cqs = dev_lim->reserved_cqs;
  177. mdev->limits.reserved_eqs = dev_lim->reserved_eqs;
  178. mdev->limits.reserved_mtts = dev_lim->reserved_mtts;
  179. mdev->limits.reserved_mrws = dev_lim->reserved_mrws;
  180. mdev->limits.reserved_uars = dev_lim->reserved_uars;
  181. mdev->limits.reserved_pds = dev_lim->reserved_pds;
  182. mdev->limits.port_width_cap = dev_lim->max_port_width;
  183. mdev->limits.page_size_cap = ~(u32) (dev_lim->min_page_sz - 1);
  184. mdev->limits.flags = dev_lim->flags;
  185. /*
  186. * For old FW that doesn't return static rate support, use a
  187. * value of 0x3 (only static rate values of 0 or 1 are handled),
  188. * except on Sinai, where even old FW can handle static rate
  189. * values of 2 and 3.
  190. */
  191. if (dev_lim->stat_rate_support)
  192. mdev->limits.stat_rate_support = dev_lim->stat_rate_support;
  193. else if (mdev->mthca_flags & MTHCA_FLAG_SINAI_OPT)
  194. mdev->limits.stat_rate_support = 0xf;
  195. else
  196. mdev->limits.stat_rate_support = 0x3;
  197. /* IB_DEVICE_RESIZE_MAX_WR not supported by driver.
  198. May be doable since hardware supports it for SRQ.
  199. IB_DEVICE_N_NOTIFY_CQ is supported by hardware but not by driver.
  200. IB_DEVICE_SRQ_RESIZE is supported by hardware but SRQ is not
  201. supported by driver. */
  202. mdev->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
  203. IB_DEVICE_PORT_ACTIVE_EVENT |
  204. IB_DEVICE_SYS_IMAGE_GUID |
  205. IB_DEVICE_RC_RNR_NAK_GEN;
  206. if (dev_lim->flags & DEV_LIM_FLAG_BAD_PKEY_CNTR)
  207. mdev->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
  208. if (dev_lim->flags & DEV_LIM_FLAG_BAD_QKEY_CNTR)
  209. mdev->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
  210. if (dev_lim->flags & DEV_LIM_FLAG_RAW_MULTI)
  211. mdev->device_cap_flags |= IB_DEVICE_RAW_MULTI;
  212. if (dev_lim->flags & DEV_LIM_FLAG_AUTO_PATH_MIG)
  213. mdev->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
  214. if (dev_lim->flags & DEV_LIM_FLAG_UD_AV_PORT_ENFORCE)
  215. mdev->device_cap_flags |= IB_DEVICE_UD_AV_PORT_ENFORCE;
  216. if (dev_lim->flags & DEV_LIM_FLAG_SRQ)
  217. mdev->mthca_flags |= MTHCA_FLAG_SRQ;
  218. return 0;
  219. }
  220. static int __devinit mthca_init_tavor(struct mthca_dev *mdev)
  221. {
  222. u8 status;
  223. int err;
  224. struct mthca_dev_lim dev_lim;
  225. struct mthca_profile profile;
  226. struct mthca_init_hca_param init_hca;
  227. err = mthca_SYS_EN(mdev, &status);
  228. if (err) {
  229. mthca_err(mdev, "SYS_EN command failed, aborting.\n");
  230. return err;
  231. }
  232. if (status) {
  233. mthca_err(mdev, "SYS_EN returned status 0x%02x, "
  234. "aborting.\n", status);
  235. return -EINVAL;
  236. }
  237. err = mthca_QUERY_FW(mdev, &status);
  238. if (err) {
  239. mthca_err(mdev, "QUERY_FW command failed, aborting.\n");
  240. goto err_disable;
  241. }
  242. if (status) {
  243. mthca_err(mdev, "QUERY_FW returned status 0x%02x, "
  244. "aborting.\n", status);
  245. err = -EINVAL;
  246. goto err_disable;
  247. }
  248. err = mthca_QUERY_DDR(mdev, &status);
  249. if (err) {
  250. mthca_err(mdev, "QUERY_DDR command failed, aborting.\n");
  251. goto err_disable;
  252. }
  253. if (status) {
  254. mthca_err(mdev, "QUERY_DDR returned status 0x%02x, "
  255. "aborting.\n", status);
  256. err = -EINVAL;
  257. goto err_disable;
  258. }
  259. err = mthca_dev_lim(mdev, &dev_lim);
  260. if (err) {
  261. mthca_err(mdev, "QUERY_DEV_LIM command failed, aborting.\n");
  262. goto err_disable;
  263. }
  264. profile = default_profile;
  265. profile.num_uar = dev_lim.uar_size / PAGE_SIZE;
  266. profile.uarc_size = 0;
  267. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  268. profile.num_srq = dev_lim.max_srqs;
  269. err = mthca_make_profile(mdev, &profile, &dev_lim, &init_hca);
  270. if (err < 0)
  271. goto err_disable;
  272. err = mthca_INIT_HCA(mdev, &init_hca, &status);
  273. if (err) {
  274. mthca_err(mdev, "INIT_HCA command failed, aborting.\n");
  275. goto err_disable;
  276. }
  277. if (status) {
  278. mthca_err(mdev, "INIT_HCA returned status 0x%02x, "
  279. "aborting.\n", status);
  280. err = -EINVAL;
  281. goto err_disable;
  282. }
  283. return 0;
  284. err_disable:
  285. mthca_SYS_DIS(mdev, &status);
  286. return err;
  287. }
  288. static int __devinit mthca_load_fw(struct mthca_dev *mdev)
  289. {
  290. u8 status;
  291. int err;
  292. /* FIXME: use HCA-attached memory for FW if present */
  293. mdev->fw.arbel.fw_icm =
  294. mthca_alloc_icm(mdev, mdev->fw.arbel.fw_pages,
  295. GFP_HIGHUSER | __GFP_NOWARN);
  296. if (!mdev->fw.arbel.fw_icm) {
  297. mthca_err(mdev, "Couldn't allocate FW area, aborting.\n");
  298. return -ENOMEM;
  299. }
  300. err = mthca_MAP_FA(mdev, mdev->fw.arbel.fw_icm, &status);
  301. if (err) {
  302. mthca_err(mdev, "MAP_FA command failed, aborting.\n");
  303. goto err_free;
  304. }
  305. if (status) {
  306. mthca_err(mdev, "MAP_FA returned status 0x%02x, aborting.\n", status);
  307. err = -EINVAL;
  308. goto err_free;
  309. }
  310. err = mthca_RUN_FW(mdev, &status);
  311. if (err) {
  312. mthca_err(mdev, "RUN_FW command failed, aborting.\n");
  313. goto err_unmap_fa;
  314. }
  315. if (status) {
  316. mthca_err(mdev, "RUN_FW returned status 0x%02x, aborting.\n", status);
  317. err = -EINVAL;
  318. goto err_unmap_fa;
  319. }
  320. return 0;
  321. err_unmap_fa:
  322. mthca_UNMAP_FA(mdev, &status);
  323. err_free:
  324. mthca_free_icm(mdev, mdev->fw.arbel.fw_icm);
  325. return err;
  326. }
  327. static int __devinit mthca_init_icm(struct mthca_dev *mdev,
  328. struct mthca_dev_lim *dev_lim,
  329. struct mthca_init_hca_param *init_hca,
  330. u64 icm_size)
  331. {
  332. u64 aux_pages;
  333. u8 status;
  334. int err;
  335. err = mthca_SET_ICM_SIZE(mdev, icm_size, &aux_pages, &status);
  336. if (err) {
  337. mthca_err(mdev, "SET_ICM_SIZE command failed, aborting.\n");
  338. return err;
  339. }
  340. if (status) {
  341. mthca_err(mdev, "SET_ICM_SIZE returned status 0x%02x, "
  342. "aborting.\n", status);
  343. return -EINVAL;
  344. }
  345. mthca_dbg(mdev, "%lld KB of HCA context requires %lld KB aux memory.\n",
  346. (unsigned long long) icm_size >> 10,
  347. (unsigned long long) aux_pages << 2);
  348. mdev->fw.arbel.aux_icm = mthca_alloc_icm(mdev, aux_pages,
  349. GFP_HIGHUSER | __GFP_NOWARN);
  350. if (!mdev->fw.arbel.aux_icm) {
  351. mthca_err(mdev, "Couldn't allocate aux memory, aborting.\n");
  352. return -ENOMEM;
  353. }
  354. err = mthca_MAP_ICM_AUX(mdev, mdev->fw.arbel.aux_icm, &status);
  355. if (err) {
  356. mthca_err(mdev, "MAP_ICM_AUX command failed, aborting.\n");
  357. goto err_free_aux;
  358. }
  359. if (status) {
  360. mthca_err(mdev, "MAP_ICM_AUX returned status 0x%02x, aborting.\n", status);
  361. err = -EINVAL;
  362. goto err_free_aux;
  363. }
  364. err = mthca_map_eq_icm(mdev, init_hca->eqc_base);
  365. if (err) {
  366. mthca_err(mdev, "Failed to map EQ context memory, aborting.\n");
  367. goto err_unmap_aux;
  368. }
  369. mdev->mr_table.mtt_table = mthca_alloc_icm_table(mdev, init_hca->mtt_base,
  370. MTHCA_MTT_SEG_SIZE,
  371. mdev->limits.num_mtt_segs,
  372. mdev->limits.reserved_mtts, 1);
  373. if (!mdev->mr_table.mtt_table) {
  374. mthca_err(mdev, "Failed to map MTT context memory, aborting.\n");
  375. err = -ENOMEM;
  376. goto err_unmap_eq;
  377. }
  378. mdev->mr_table.mpt_table = mthca_alloc_icm_table(mdev, init_hca->mpt_base,
  379. dev_lim->mpt_entry_sz,
  380. mdev->limits.num_mpts,
  381. mdev->limits.reserved_mrws, 1);
  382. if (!mdev->mr_table.mpt_table) {
  383. mthca_err(mdev, "Failed to map MPT context memory, aborting.\n");
  384. err = -ENOMEM;
  385. goto err_unmap_mtt;
  386. }
  387. mdev->qp_table.qp_table = mthca_alloc_icm_table(mdev, init_hca->qpc_base,
  388. dev_lim->qpc_entry_sz,
  389. mdev->limits.num_qps,
  390. mdev->limits.reserved_qps, 0);
  391. if (!mdev->qp_table.qp_table) {
  392. mthca_err(mdev, "Failed to map QP context memory, aborting.\n");
  393. err = -ENOMEM;
  394. goto err_unmap_mpt;
  395. }
  396. mdev->qp_table.eqp_table = mthca_alloc_icm_table(mdev, init_hca->eqpc_base,
  397. dev_lim->eqpc_entry_sz,
  398. mdev->limits.num_qps,
  399. mdev->limits.reserved_qps, 0);
  400. if (!mdev->qp_table.eqp_table) {
  401. mthca_err(mdev, "Failed to map EQP context memory, aborting.\n");
  402. err = -ENOMEM;
  403. goto err_unmap_qp;
  404. }
  405. mdev->qp_table.rdb_table = mthca_alloc_icm_table(mdev, init_hca->rdb_base,
  406. MTHCA_RDB_ENTRY_SIZE,
  407. mdev->limits.num_qps <<
  408. mdev->qp_table.rdb_shift,
  409. 0, 0);
  410. if (!mdev->qp_table.rdb_table) {
  411. mthca_err(mdev, "Failed to map RDB context memory, aborting\n");
  412. err = -ENOMEM;
  413. goto err_unmap_eqp;
  414. }
  415. mdev->cq_table.table = mthca_alloc_icm_table(mdev, init_hca->cqc_base,
  416. dev_lim->cqc_entry_sz,
  417. mdev->limits.num_cqs,
  418. mdev->limits.reserved_cqs, 0);
  419. if (!mdev->cq_table.table) {
  420. mthca_err(mdev, "Failed to map CQ context memory, aborting.\n");
  421. err = -ENOMEM;
  422. goto err_unmap_rdb;
  423. }
  424. if (mdev->mthca_flags & MTHCA_FLAG_SRQ) {
  425. mdev->srq_table.table =
  426. mthca_alloc_icm_table(mdev, init_hca->srqc_base,
  427. dev_lim->srq_entry_sz,
  428. mdev->limits.num_srqs,
  429. mdev->limits.reserved_srqs, 0);
  430. if (!mdev->srq_table.table) {
  431. mthca_err(mdev, "Failed to map SRQ context memory, "
  432. "aborting.\n");
  433. err = -ENOMEM;
  434. goto err_unmap_cq;
  435. }
  436. }
  437. /*
  438. * It's not strictly required, but for simplicity just map the
  439. * whole multicast group table now. The table isn't very big
  440. * and it's a lot easier than trying to track ref counts.
  441. */
  442. mdev->mcg_table.table = mthca_alloc_icm_table(mdev, init_hca->mc_base,
  443. MTHCA_MGM_ENTRY_SIZE,
  444. mdev->limits.num_mgms +
  445. mdev->limits.num_amgms,
  446. mdev->limits.num_mgms +
  447. mdev->limits.num_amgms,
  448. 0);
  449. if (!mdev->mcg_table.table) {
  450. mthca_err(mdev, "Failed to map MCG context memory, aborting.\n");
  451. err = -ENOMEM;
  452. goto err_unmap_srq;
  453. }
  454. return 0;
  455. err_unmap_srq:
  456. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  457. mthca_free_icm_table(mdev, mdev->srq_table.table);
  458. err_unmap_cq:
  459. mthca_free_icm_table(mdev, mdev->cq_table.table);
  460. err_unmap_rdb:
  461. mthca_free_icm_table(mdev, mdev->qp_table.rdb_table);
  462. err_unmap_eqp:
  463. mthca_free_icm_table(mdev, mdev->qp_table.eqp_table);
  464. err_unmap_qp:
  465. mthca_free_icm_table(mdev, mdev->qp_table.qp_table);
  466. err_unmap_mpt:
  467. mthca_free_icm_table(mdev, mdev->mr_table.mpt_table);
  468. err_unmap_mtt:
  469. mthca_free_icm_table(mdev, mdev->mr_table.mtt_table);
  470. err_unmap_eq:
  471. mthca_unmap_eq_icm(mdev);
  472. err_unmap_aux:
  473. mthca_UNMAP_ICM_AUX(mdev, &status);
  474. err_free_aux:
  475. mthca_free_icm(mdev, mdev->fw.arbel.aux_icm);
  476. return err;
  477. }
  478. static void mthca_free_icms(struct mthca_dev *mdev)
  479. {
  480. u8 status;
  481. mthca_free_icm_table(mdev, mdev->mcg_table.table);
  482. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  483. mthca_free_icm_table(mdev, mdev->srq_table.table);
  484. mthca_free_icm_table(mdev, mdev->cq_table.table);
  485. mthca_free_icm_table(mdev, mdev->qp_table.rdb_table);
  486. mthca_free_icm_table(mdev, mdev->qp_table.eqp_table);
  487. mthca_free_icm_table(mdev, mdev->qp_table.qp_table);
  488. mthca_free_icm_table(mdev, mdev->mr_table.mpt_table);
  489. mthca_free_icm_table(mdev, mdev->mr_table.mtt_table);
  490. mthca_unmap_eq_icm(mdev);
  491. mthca_UNMAP_ICM_AUX(mdev, &status);
  492. mthca_free_icm(mdev, mdev->fw.arbel.aux_icm);
  493. }
  494. static int __devinit mthca_init_arbel(struct mthca_dev *mdev)
  495. {
  496. struct mthca_dev_lim dev_lim;
  497. struct mthca_profile profile;
  498. struct mthca_init_hca_param init_hca;
  499. u64 icm_size;
  500. u8 status;
  501. int err;
  502. err = mthca_QUERY_FW(mdev, &status);
  503. if (err) {
  504. mthca_err(mdev, "QUERY_FW command failed, aborting.\n");
  505. return err;
  506. }
  507. if (status) {
  508. mthca_err(mdev, "QUERY_FW returned status 0x%02x, "
  509. "aborting.\n", status);
  510. return -EINVAL;
  511. }
  512. err = mthca_ENABLE_LAM(mdev, &status);
  513. if (err) {
  514. mthca_err(mdev, "ENABLE_LAM command failed, aborting.\n");
  515. return err;
  516. }
  517. if (status == MTHCA_CMD_STAT_LAM_NOT_PRE) {
  518. mthca_dbg(mdev, "No HCA-attached memory (running in MemFree mode)\n");
  519. mdev->mthca_flags |= MTHCA_FLAG_NO_LAM;
  520. } else if (status) {
  521. mthca_err(mdev, "ENABLE_LAM returned status 0x%02x, "
  522. "aborting.\n", status);
  523. return -EINVAL;
  524. }
  525. err = mthca_load_fw(mdev);
  526. if (err) {
  527. mthca_err(mdev, "Failed to start FW, aborting.\n");
  528. goto err_disable;
  529. }
  530. err = mthca_dev_lim(mdev, &dev_lim);
  531. if (err) {
  532. mthca_err(mdev, "QUERY_DEV_LIM command failed, aborting.\n");
  533. goto err_stop_fw;
  534. }
  535. profile = default_profile;
  536. profile.num_uar = dev_lim.uar_size / PAGE_SIZE;
  537. profile.num_udav = 0;
  538. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  539. profile.num_srq = dev_lim.max_srqs;
  540. icm_size = mthca_make_profile(mdev, &profile, &dev_lim, &init_hca);
  541. if ((int) icm_size < 0) {
  542. err = icm_size;
  543. goto err_stop_fw;
  544. }
  545. err = mthca_init_icm(mdev, &dev_lim, &init_hca, icm_size);
  546. if (err)
  547. goto err_stop_fw;
  548. err = mthca_INIT_HCA(mdev, &init_hca, &status);
  549. if (err) {
  550. mthca_err(mdev, "INIT_HCA command failed, aborting.\n");
  551. goto err_free_icm;
  552. }
  553. if (status) {
  554. mthca_err(mdev, "INIT_HCA returned status 0x%02x, "
  555. "aborting.\n", status);
  556. err = -EINVAL;
  557. goto err_free_icm;
  558. }
  559. return 0;
  560. err_free_icm:
  561. mthca_free_icms(mdev);
  562. err_stop_fw:
  563. mthca_UNMAP_FA(mdev, &status);
  564. mthca_free_icm(mdev, mdev->fw.arbel.fw_icm);
  565. err_disable:
  566. if (!(mdev->mthca_flags & MTHCA_FLAG_NO_LAM))
  567. mthca_DISABLE_LAM(mdev, &status);
  568. return err;
  569. }
  570. static void mthca_close_hca(struct mthca_dev *mdev)
  571. {
  572. u8 status;
  573. mthca_CLOSE_HCA(mdev, 0, &status);
  574. if (mthca_is_memfree(mdev)) {
  575. mthca_free_icms(mdev);
  576. mthca_UNMAP_FA(mdev, &status);
  577. mthca_free_icm(mdev, mdev->fw.arbel.fw_icm);
  578. if (!(mdev->mthca_flags & MTHCA_FLAG_NO_LAM))
  579. mthca_DISABLE_LAM(mdev, &status);
  580. } else
  581. mthca_SYS_DIS(mdev, &status);
  582. }
  583. static int __devinit mthca_init_hca(struct mthca_dev *mdev)
  584. {
  585. u8 status;
  586. int err;
  587. struct mthca_adapter adapter;
  588. if (mthca_is_memfree(mdev))
  589. err = mthca_init_arbel(mdev);
  590. else
  591. err = mthca_init_tavor(mdev);
  592. if (err)
  593. return err;
  594. err = mthca_QUERY_ADAPTER(mdev, &adapter, &status);
  595. if (err) {
  596. mthca_err(mdev, "QUERY_ADAPTER command failed, aborting.\n");
  597. goto err_close;
  598. }
  599. if (status) {
  600. mthca_err(mdev, "QUERY_ADAPTER returned status 0x%02x, "
  601. "aborting.\n", status);
  602. err = -EINVAL;
  603. goto err_close;
  604. }
  605. mdev->eq_table.inta_pin = adapter.inta_pin;
  606. mdev->rev_id = adapter.revision_id;
  607. memcpy(mdev->board_id, adapter.board_id, sizeof mdev->board_id);
  608. return 0;
  609. err_close:
  610. mthca_close_hca(mdev);
  611. return err;
  612. }
  613. static int __devinit mthca_setup_hca(struct mthca_dev *dev)
  614. {
  615. int err;
  616. u8 status;
  617. MTHCA_INIT_DOORBELL_LOCK(&dev->doorbell_lock);
  618. err = mthca_init_uar_table(dev);
  619. if (err) {
  620. mthca_err(dev, "Failed to initialize "
  621. "user access region table, aborting.\n");
  622. return err;
  623. }
  624. err = mthca_uar_alloc(dev, &dev->driver_uar);
  625. if (err) {
  626. mthca_err(dev, "Failed to allocate driver access region, "
  627. "aborting.\n");
  628. goto err_uar_table_free;
  629. }
  630. dev->kar = ioremap(dev->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
  631. if (!dev->kar) {
  632. mthca_err(dev, "Couldn't map kernel access region, "
  633. "aborting.\n");
  634. err = -ENOMEM;
  635. goto err_uar_free;
  636. }
  637. err = mthca_init_pd_table(dev);
  638. if (err) {
  639. mthca_err(dev, "Failed to initialize "
  640. "protection domain table, aborting.\n");
  641. goto err_kar_unmap;
  642. }
  643. err = mthca_init_mr_table(dev);
  644. if (err) {
  645. mthca_err(dev, "Failed to initialize "
  646. "memory region table, aborting.\n");
  647. goto err_pd_table_free;
  648. }
  649. err = mthca_pd_alloc(dev, 1, &dev->driver_pd);
  650. if (err) {
  651. mthca_err(dev, "Failed to create driver PD, "
  652. "aborting.\n");
  653. goto err_mr_table_free;
  654. }
  655. err = mthca_init_eq_table(dev);
  656. if (err) {
  657. mthca_err(dev, "Failed to initialize "
  658. "event queue table, aborting.\n");
  659. goto err_pd_free;
  660. }
  661. err = mthca_cmd_use_events(dev);
  662. if (err) {
  663. mthca_err(dev, "Failed to switch to event-driven "
  664. "firmware commands, aborting.\n");
  665. goto err_eq_table_free;
  666. }
  667. err = mthca_NOP(dev, &status);
  668. if (err || status) {
  669. mthca_err(dev, "NOP command failed to generate interrupt (IRQ %d), aborting.\n",
  670. dev->mthca_flags & MTHCA_FLAG_MSI_X ?
  671. dev->eq_table.eq[MTHCA_EQ_CMD].msi_x_vector :
  672. dev->pdev->irq);
  673. if (dev->mthca_flags & (MTHCA_FLAG_MSI | MTHCA_FLAG_MSI_X))
  674. mthca_err(dev, "Try again with MSI/MSI-X disabled.\n");
  675. else
  676. mthca_err(dev, "BIOS or ACPI interrupt routing problem?\n");
  677. goto err_cmd_poll;
  678. }
  679. mthca_dbg(dev, "NOP command IRQ test passed\n");
  680. err = mthca_init_cq_table(dev);
  681. if (err) {
  682. mthca_err(dev, "Failed to initialize "
  683. "completion queue table, aborting.\n");
  684. goto err_cmd_poll;
  685. }
  686. err = mthca_init_srq_table(dev);
  687. if (err) {
  688. mthca_err(dev, "Failed to initialize "
  689. "shared receive queue table, aborting.\n");
  690. goto err_cq_table_free;
  691. }
  692. err = mthca_init_qp_table(dev);
  693. if (err) {
  694. mthca_err(dev, "Failed to initialize "
  695. "queue pair table, aborting.\n");
  696. goto err_srq_table_free;
  697. }
  698. err = mthca_init_av_table(dev);
  699. if (err) {
  700. mthca_err(dev, "Failed to initialize "
  701. "address vector table, aborting.\n");
  702. goto err_qp_table_free;
  703. }
  704. err = mthca_init_mcg_table(dev);
  705. if (err) {
  706. mthca_err(dev, "Failed to initialize "
  707. "multicast group table, aborting.\n");
  708. goto err_av_table_free;
  709. }
  710. return 0;
  711. err_av_table_free:
  712. mthca_cleanup_av_table(dev);
  713. err_qp_table_free:
  714. mthca_cleanup_qp_table(dev);
  715. err_srq_table_free:
  716. mthca_cleanup_srq_table(dev);
  717. err_cq_table_free:
  718. mthca_cleanup_cq_table(dev);
  719. err_cmd_poll:
  720. mthca_cmd_use_polling(dev);
  721. err_eq_table_free:
  722. mthca_cleanup_eq_table(dev);
  723. err_pd_free:
  724. mthca_pd_free(dev, &dev->driver_pd);
  725. err_mr_table_free:
  726. mthca_cleanup_mr_table(dev);
  727. err_pd_table_free:
  728. mthca_cleanup_pd_table(dev);
  729. err_kar_unmap:
  730. iounmap(dev->kar);
  731. err_uar_free:
  732. mthca_uar_free(dev, &dev->driver_uar);
  733. err_uar_table_free:
  734. mthca_cleanup_uar_table(dev);
  735. return err;
  736. }
  737. static int __devinit mthca_request_regions(struct pci_dev *pdev,
  738. int ddr_hidden)
  739. {
  740. int err;
  741. /*
  742. * We can't just use pci_request_regions() because the MSI-X
  743. * table is right in the middle of the first BAR. If we did
  744. * pci_request_region and grab all of the first BAR, then
  745. * setting up MSI-X would fail, since the PCI core wants to do
  746. * request_mem_region on the MSI-X vector table.
  747. *
  748. * So just request what we need right now, and request any
  749. * other regions we need when setting up EQs.
  750. */
  751. if (!request_mem_region(pci_resource_start(pdev, 0) + MTHCA_HCR_BASE,
  752. MTHCA_HCR_SIZE, DRV_NAME))
  753. return -EBUSY;
  754. err = pci_request_region(pdev, 2, DRV_NAME);
  755. if (err)
  756. goto err_bar2_failed;
  757. if (!ddr_hidden) {
  758. err = pci_request_region(pdev, 4, DRV_NAME);
  759. if (err)
  760. goto err_bar4_failed;
  761. }
  762. return 0;
  763. err_bar4_failed:
  764. pci_release_region(pdev, 2);
  765. err_bar2_failed:
  766. release_mem_region(pci_resource_start(pdev, 0) + MTHCA_HCR_BASE,
  767. MTHCA_HCR_SIZE);
  768. return err;
  769. }
  770. static void mthca_release_regions(struct pci_dev *pdev,
  771. int ddr_hidden)
  772. {
  773. if (!ddr_hidden)
  774. pci_release_region(pdev, 4);
  775. pci_release_region(pdev, 2);
  776. release_mem_region(pci_resource_start(pdev, 0) + MTHCA_HCR_BASE,
  777. MTHCA_HCR_SIZE);
  778. }
  779. static int __devinit mthca_enable_msi_x(struct mthca_dev *mdev)
  780. {
  781. struct msix_entry entries[3];
  782. int err;
  783. entries[0].entry = 0;
  784. entries[1].entry = 1;
  785. entries[2].entry = 2;
  786. err = pci_enable_msix(mdev->pdev, entries, ARRAY_SIZE(entries));
  787. if (err) {
  788. if (err > 0)
  789. mthca_info(mdev, "Only %d MSI-X vectors available, "
  790. "not using MSI-X\n", err);
  791. return err;
  792. }
  793. mdev->eq_table.eq[MTHCA_EQ_COMP ].msi_x_vector = entries[0].vector;
  794. mdev->eq_table.eq[MTHCA_EQ_ASYNC].msi_x_vector = entries[1].vector;
  795. mdev->eq_table.eq[MTHCA_EQ_CMD ].msi_x_vector = entries[2].vector;
  796. return 0;
  797. }
  798. /* Types of supported HCA */
  799. enum {
  800. TAVOR, /* MT23108 */
  801. ARBEL_COMPAT, /* MT25208 in Tavor compat mode */
  802. ARBEL_NATIVE, /* MT25208 with extended features */
  803. SINAI /* MT25204 */
  804. };
  805. #define MTHCA_FW_VER(major, minor, subminor) \
  806. (((u64) (major) << 32) | ((u64) (minor) << 16) | (u64) (subminor))
  807. static struct {
  808. u64 latest_fw;
  809. u32 flags;
  810. } mthca_hca_table[] = {
  811. [TAVOR] = { .latest_fw = MTHCA_FW_VER(3, 4, 0),
  812. .flags = 0 },
  813. [ARBEL_COMPAT] = { .latest_fw = MTHCA_FW_VER(4, 7, 400),
  814. .flags = MTHCA_FLAG_PCIE },
  815. [ARBEL_NATIVE] = { .latest_fw = MTHCA_FW_VER(5, 1, 0),
  816. .flags = MTHCA_FLAG_MEMFREE |
  817. MTHCA_FLAG_PCIE },
  818. [SINAI] = { .latest_fw = MTHCA_FW_VER(1, 0, 800),
  819. .flags = MTHCA_FLAG_MEMFREE |
  820. MTHCA_FLAG_PCIE |
  821. MTHCA_FLAG_SINAI_OPT }
  822. };
  823. static int __devinit mthca_init_one(struct pci_dev *pdev,
  824. const struct pci_device_id *id)
  825. {
  826. static int mthca_version_printed = 0;
  827. int ddr_hidden = 0;
  828. int err;
  829. struct mthca_dev *mdev;
  830. if (!mthca_version_printed) {
  831. printk(KERN_INFO "%s", mthca_version);
  832. ++mthca_version_printed;
  833. }
  834. printk(KERN_INFO PFX "Initializing %s\n",
  835. pci_name(pdev));
  836. if (id->driver_data >= ARRAY_SIZE(mthca_hca_table)) {
  837. printk(KERN_ERR PFX "%s has invalid driver data %lx\n",
  838. pci_name(pdev), id->driver_data);
  839. return -ENODEV;
  840. }
  841. err = pci_enable_device(pdev);
  842. if (err) {
  843. dev_err(&pdev->dev, "Cannot enable PCI device, "
  844. "aborting.\n");
  845. return err;
  846. }
  847. /*
  848. * Check for BARs. We expect 0: 1MB, 2: 8MB, 4: DDR (may not
  849. * be present)
  850. */
  851. if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
  852. pci_resource_len(pdev, 0) != 1 << 20) {
  853. dev_err(&pdev->dev, "Missing DCS, aborting.\n");
  854. err = -ENODEV;
  855. goto err_disable_pdev;
  856. }
  857. if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
  858. dev_err(&pdev->dev, "Missing UAR, aborting.\n");
  859. err = -ENODEV;
  860. goto err_disable_pdev;
  861. }
  862. if (!(pci_resource_flags(pdev, 4) & IORESOURCE_MEM))
  863. ddr_hidden = 1;
  864. err = mthca_request_regions(pdev, ddr_hidden);
  865. if (err) {
  866. dev_err(&pdev->dev, "Cannot obtain PCI resources, "
  867. "aborting.\n");
  868. goto err_disable_pdev;
  869. }
  870. pci_set_master(pdev);
  871. err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
  872. if (err) {
  873. dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n");
  874. err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  875. if (err) {
  876. dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n");
  877. goto err_free_res;
  878. }
  879. }
  880. err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
  881. if (err) {
  882. dev_warn(&pdev->dev, "Warning: couldn't set 64-bit "
  883. "consistent PCI DMA mask.\n");
  884. err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
  885. if (err) {
  886. dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, "
  887. "aborting.\n");
  888. goto err_free_res;
  889. }
  890. }
  891. mdev = (struct mthca_dev *) ib_alloc_device(sizeof *mdev);
  892. if (!mdev) {
  893. dev_err(&pdev->dev, "Device struct alloc failed, "
  894. "aborting.\n");
  895. err = -ENOMEM;
  896. goto err_free_res;
  897. }
  898. mdev->pdev = pdev;
  899. mdev->mthca_flags = mthca_hca_table[id->driver_data].flags;
  900. if (ddr_hidden)
  901. mdev->mthca_flags |= MTHCA_FLAG_DDR_HIDDEN;
  902. /*
  903. * Now reset the HCA before we touch the PCI capabilities or
  904. * attempt a firmware command, since a boot ROM may have left
  905. * the HCA in an undefined state.
  906. */
  907. err = mthca_reset(mdev);
  908. if (err) {
  909. mthca_err(mdev, "Failed to reset HCA, aborting.\n");
  910. goto err_free_dev;
  911. }
  912. if (msi_x && !mthca_enable_msi_x(mdev))
  913. mdev->mthca_flags |= MTHCA_FLAG_MSI_X;
  914. if (msi && !(mdev->mthca_flags & MTHCA_FLAG_MSI_X) &&
  915. !pci_enable_msi(pdev))
  916. mdev->mthca_flags |= MTHCA_FLAG_MSI;
  917. if (mthca_cmd_init(mdev)) {
  918. mthca_err(mdev, "Failed to init command interface, aborting.\n");
  919. goto err_free_dev;
  920. }
  921. err = mthca_tune_pci(mdev);
  922. if (err)
  923. goto err_cmd;
  924. err = mthca_init_hca(mdev);
  925. if (err)
  926. goto err_cmd;
  927. if (mdev->fw_ver < mthca_hca_table[id->driver_data].latest_fw) {
  928. mthca_warn(mdev, "HCA FW version %d.%d.%d is old (%d.%d.%d is current).\n",
  929. (int) (mdev->fw_ver >> 32), (int) (mdev->fw_ver >> 16) & 0xffff,
  930. (int) (mdev->fw_ver & 0xffff),
  931. (int) (mthca_hca_table[id->driver_data].latest_fw >> 32),
  932. (int) (mthca_hca_table[id->driver_data].latest_fw >> 16) & 0xffff,
  933. (int) (mthca_hca_table[id->driver_data].latest_fw & 0xffff));
  934. mthca_warn(mdev, "If you have problems, try updating your HCA FW.\n");
  935. }
  936. err = mthca_setup_hca(mdev);
  937. if (err)
  938. goto err_close;
  939. err = mthca_register_device(mdev);
  940. if (err)
  941. goto err_cleanup;
  942. err = mthca_create_agents(mdev);
  943. if (err)
  944. goto err_unregister;
  945. pci_set_drvdata(pdev, mdev);
  946. return 0;
  947. err_unregister:
  948. mthca_unregister_device(mdev);
  949. err_cleanup:
  950. mthca_cleanup_mcg_table(mdev);
  951. mthca_cleanup_av_table(mdev);
  952. mthca_cleanup_qp_table(mdev);
  953. mthca_cleanup_srq_table(mdev);
  954. mthca_cleanup_cq_table(mdev);
  955. mthca_cmd_use_polling(mdev);
  956. mthca_cleanup_eq_table(mdev);
  957. mthca_pd_free(mdev, &mdev->driver_pd);
  958. mthca_cleanup_mr_table(mdev);
  959. mthca_cleanup_pd_table(mdev);
  960. mthca_cleanup_uar_table(mdev);
  961. err_close:
  962. mthca_close_hca(mdev);
  963. err_cmd:
  964. mthca_cmd_cleanup(mdev);
  965. err_free_dev:
  966. if (mdev->mthca_flags & MTHCA_FLAG_MSI_X)
  967. pci_disable_msix(pdev);
  968. if (mdev->mthca_flags & MTHCA_FLAG_MSI)
  969. pci_disable_msi(pdev);
  970. ib_dealloc_device(&mdev->ib_dev);
  971. err_free_res:
  972. mthca_release_regions(pdev, ddr_hidden);
  973. err_disable_pdev:
  974. pci_disable_device(pdev);
  975. pci_set_drvdata(pdev, NULL);
  976. return err;
  977. }
  978. static void __devexit mthca_remove_one(struct pci_dev *pdev)
  979. {
  980. struct mthca_dev *mdev = pci_get_drvdata(pdev);
  981. u8 status;
  982. int p;
  983. if (mdev) {
  984. mthca_free_agents(mdev);
  985. mthca_unregister_device(mdev);
  986. for (p = 1; p <= mdev->limits.num_ports; ++p)
  987. mthca_CLOSE_IB(mdev, p, &status);
  988. mthca_cleanup_mcg_table(mdev);
  989. mthca_cleanup_av_table(mdev);
  990. mthca_cleanup_qp_table(mdev);
  991. mthca_cleanup_srq_table(mdev);
  992. mthca_cleanup_cq_table(mdev);
  993. mthca_cmd_use_polling(mdev);
  994. mthca_cleanup_eq_table(mdev);
  995. mthca_pd_free(mdev, &mdev->driver_pd);
  996. mthca_cleanup_mr_table(mdev);
  997. mthca_cleanup_pd_table(mdev);
  998. iounmap(mdev->kar);
  999. mthca_uar_free(mdev, &mdev->driver_uar);
  1000. mthca_cleanup_uar_table(mdev);
  1001. mthca_close_hca(mdev);
  1002. mthca_cmd_cleanup(mdev);
  1003. if (mdev->mthca_flags & MTHCA_FLAG_MSI_X)
  1004. pci_disable_msix(pdev);
  1005. if (mdev->mthca_flags & MTHCA_FLAG_MSI)
  1006. pci_disable_msi(pdev);
  1007. ib_dealloc_device(&mdev->ib_dev);
  1008. mthca_release_regions(pdev, mdev->mthca_flags &
  1009. MTHCA_FLAG_DDR_HIDDEN);
  1010. pci_disable_device(pdev);
  1011. pci_set_drvdata(pdev, NULL);
  1012. }
  1013. }
  1014. static struct pci_device_id mthca_pci_table[] = {
  1015. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR),
  1016. .driver_data = TAVOR },
  1017. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_TAVOR),
  1018. .driver_data = TAVOR },
  1019. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT),
  1020. .driver_data = ARBEL_COMPAT },
  1021. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT),
  1022. .driver_data = ARBEL_COMPAT },
  1023. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_ARBEL),
  1024. .driver_data = ARBEL_NATIVE },
  1025. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_ARBEL),
  1026. .driver_data = ARBEL_NATIVE },
  1027. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_SINAI),
  1028. .driver_data = SINAI },
  1029. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_SINAI),
  1030. .driver_data = SINAI },
  1031. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_SINAI_OLD),
  1032. .driver_data = SINAI },
  1033. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_SINAI_OLD),
  1034. .driver_data = SINAI },
  1035. { 0, }
  1036. };
  1037. MODULE_DEVICE_TABLE(pci, mthca_pci_table);
  1038. static struct pci_driver mthca_driver = {
  1039. .name = DRV_NAME,
  1040. .id_table = mthca_pci_table,
  1041. .probe = mthca_init_one,
  1042. .remove = __devexit_p(mthca_remove_one)
  1043. };
  1044. static int __init mthca_init(void)
  1045. {
  1046. int ret;
  1047. ret = pci_register_driver(&mthca_driver);
  1048. return ret < 0 ? ret : 0;
  1049. }
  1050. static void __exit mthca_cleanup(void)
  1051. {
  1052. pci_unregister_driver(&mthca_driver);
  1053. }
  1054. module_init(mthca_init);
  1055. module_exit(mthca_cleanup);