hpt366.c 44 KB

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  1. /*
  2. * linux/drivers/ide/pci/hpt366.c Version 0.50 May 28, 2006
  3. *
  4. * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
  5. * Portions Copyright (C) 2001 Sun Microsystems, Inc.
  6. * Portions Copyright (C) 2003 Red Hat Inc
  7. * Portions Copyright (C) 2005-2006 MontaVista Software, Inc.
  8. *
  9. * Thanks to HighPoint Technologies for their assistance, and hardware.
  10. * Special Thanks to Jon Burchmore in SanDiego for the deep pockets, his
  11. * donation of an ABit BP6 mainboard, processor, and memory acellerated
  12. * development and support.
  13. *
  14. *
  15. * HighPoint has its own drivers (open source except for the RAID part)
  16. * available from http://www.highpoint-tech.com/BIOS%20+%20Driver/.
  17. * This may be useful to anyone wanting to work on this driver, however do not
  18. * trust them too much since the code tends to become less and less meaningful
  19. * as the time passes... :-/
  20. *
  21. * Note that final HPT370 support was done by force extraction of GPL.
  22. *
  23. * - add function for getting/setting power status of drive
  24. * - the HPT370's state machine can get confused. reset it before each dma
  25. * xfer to prevent that from happening.
  26. * - reset state engine whenever we get an error.
  27. * - check for busmaster state at end of dma.
  28. * - use new highpoint timings.
  29. * - detect bus speed using highpoint register.
  30. * - use pll if we don't have a clock table. added a 66MHz table that's
  31. * just 2x the 33MHz table.
  32. * - removed turnaround. NOTE: we never want to switch between pll and
  33. * pci clocks as the chip can glitch in those cases. the highpoint
  34. * approved workaround slows everything down too much to be useful. in
  35. * addition, we would have to serialize access to each chip.
  36. * Adrian Sun <a.sun@sun.com>
  37. *
  38. * add drive timings for 66MHz PCI bus,
  39. * fix ATA Cable signal detection, fix incorrect /proc info
  40. * add /proc display for per-drive PIO/DMA/UDMA mode and
  41. * per-channel ATA-33/66 Cable detect.
  42. * Duncan Laurie <void@sun.com>
  43. *
  44. * fixup /proc output for multiple controllers
  45. * Tim Hockin <thockin@sun.com>
  46. *
  47. * On hpt366:
  48. * Reset the hpt366 on error, reset on dma
  49. * Fix disabling Fast Interrupt hpt366.
  50. * Mike Waychison <crlf@sun.com>
  51. *
  52. * Added support for 372N clocking and clock switching. The 372N needs
  53. * different clocks on read/write. This requires overloading rw_disk and
  54. * other deeply crazy things. Thanks to <http://www.hoerstreich.de> for
  55. * keeping me sane.
  56. * Alan Cox <alan@redhat.com>
  57. *
  58. * - fix the clock turnaround code: it was writing to the wrong ports when
  59. * called for the secondary channel, caching the current clock mode per-
  60. * channel caused the cached register value to get out of sync with the
  61. * actual one, the channels weren't serialized, the turnaround shouldn't
  62. * be done on 66 MHz PCI bus
  63. * - avoid calibrating PLL twice as the second time results in a wrong PCI
  64. * frequency and thus in the wrong timings for the secondary channel
  65. * - disable UltraATA/133 for HPT372 and UltraATA/100 for HPT370 by default
  66. * as the ATA clock being used does not allow for this speed anyway
  67. * - add support for HPT302N and HPT371N clocking (the same as for HPT372N)
  68. * - HPT371/N are single channel chips, so avoid touching the primary channel
  69. * which exists only virtually (there's no pins for it)
  70. * - fix/remove bad/unused timing tables and use one set of tables for the whole
  71. * HPT37x chip family; save space by introducing the separate transfer mode
  72. * table in which the mode lookup is done
  73. * - use f_CNT value saved by the HighPoint BIOS as reading it directly gives
  74. * the wrong PCI frequency since DPLL has already been calibrated by BIOS
  75. * - fix the hotswap code: it caused RESET- to glitch when tristating the bus,
  76. * and for HPT36x the obsolete HDIO_TRISTATE_HWIF handler was called instead
  77. * - pass to init_chipset() handlers a copy of the IDE PCI device structure as
  78. * they tamper with its fields
  79. * - prefix the driver startup messages with the real chip name
  80. * - claim the extra 240 bytes of I/O space for all chips
  81. * - optimize the rate masking/filtering and the drive list lookup code
  82. * - use pci_get_slot() to get to the function 1 of HPT36x/374
  83. * - cache the channel's MCRs' offset; only touch the relevant MCR when detecting
  84. * the cable type on HPT374's function 1
  85. * - rename all the register related variables consistently
  86. * - make HPT36x's speedproc handler look the same way as HPT37x ones; fix the
  87. * PIO timing register mask for HPT37x
  88. * <source@mvista.com>
  89. *
  90. */
  91. #include <linux/types.h>
  92. #include <linux/module.h>
  93. #include <linux/kernel.h>
  94. #include <linux/delay.h>
  95. #include <linux/timer.h>
  96. #include <linux/mm.h>
  97. #include <linux/ioport.h>
  98. #include <linux/blkdev.h>
  99. #include <linux/hdreg.h>
  100. #include <linux/interrupt.h>
  101. #include <linux/pci.h>
  102. #include <linux/init.h>
  103. #include <linux/ide.h>
  104. #include <asm/uaccess.h>
  105. #include <asm/io.h>
  106. #include <asm/irq.h>
  107. /* various tuning parameters */
  108. #define HPT_RESET_STATE_ENGINE
  109. #undef HPT_DELAY_INTERRUPT
  110. #define HPT_SERIALIZE_IO 0
  111. static const char *quirk_drives[] = {
  112. "QUANTUM FIREBALLlct08 08",
  113. "QUANTUM FIREBALLP KA6.4",
  114. "QUANTUM FIREBALLP LM20.4",
  115. "QUANTUM FIREBALLP LM20.5",
  116. NULL
  117. };
  118. static const char *bad_ata100_5[] = {
  119. "IBM-DTLA-307075",
  120. "IBM-DTLA-307060",
  121. "IBM-DTLA-307045",
  122. "IBM-DTLA-307030",
  123. "IBM-DTLA-307020",
  124. "IBM-DTLA-307015",
  125. "IBM-DTLA-305040",
  126. "IBM-DTLA-305030",
  127. "IBM-DTLA-305020",
  128. "IC35L010AVER07-0",
  129. "IC35L020AVER07-0",
  130. "IC35L030AVER07-0",
  131. "IC35L040AVER07-0",
  132. "IC35L060AVER07-0",
  133. "WDC AC310200R",
  134. NULL
  135. };
  136. static const char *bad_ata66_4[] = {
  137. "IBM-DTLA-307075",
  138. "IBM-DTLA-307060",
  139. "IBM-DTLA-307045",
  140. "IBM-DTLA-307030",
  141. "IBM-DTLA-307020",
  142. "IBM-DTLA-307015",
  143. "IBM-DTLA-305040",
  144. "IBM-DTLA-305030",
  145. "IBM-DTLA-305020",
  146. "IC35L010AVER07-0",
  147. "IC35L020AVER07-0",
  148. "IC35L030AVER07-0",
  149. "IC35L040AVER07-0",
  150. "IC35L060AVER07-0",
  151. "WDC AC310200R",
  152. NULL
  153. };
  154. static const char *bad_ata66_3[] = {
  155. "WDC AC310200R",
  156. NULL
  157. };
  158. static const char *bad_ata33[] = {
  159. "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
  160. "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
  161. "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
  162. "Maxtor 90510D4",
  163. "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
  164. "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
  165. "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
  166. NULL
  167. };
  168. static u8 xfer_speeds[] = {
  169. XFER_UDMA_6,
  170. XFER_UDMA_5,
  171. XFER_UDMA_4,
  172. XFER_UDMA_3,
  173. XFER_UDMA_2,
  174. XFER_UDMA_1,
  175. XFER_UDMA_0,
  176. XFER_MW_DMA_2,
  177. XFER_MW_DMA_1,
  178. XFER_MW_DMA_0,
  179. XFER_PIO_4,
  180. XFER_PIO_3,
  181. XFER_PIO_2,
  182. XFER_PIO_1,
  183. XFER_PIO_0
  184. };
  185. /* Key for bus clock timings
  186. * 36x 37x
  187. * bits bits
  188. * 0:3 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
  189. * cycles = value + 1
  190. * 4:7 4:8 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
  191. * cycles = value + 1
  192. * 8:11 9:12 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
  193. * register access.
  194. * 12:15 13:17 cmd_low_time. Active time of DIOW_/DIOR_ during task file
  195. * register access.
  196. * 16:18 18:20 udma_cycle_time. Clock cycles for UDMA xfer.
  197. * - 21 CLK frequency: 0=ATA clock, 1=dual ATA clock.
  198. * 19:21 22:24 pre_high_time. Time to initialize the 1st cycle for PIO and
  199. * MW DMA xfer.
  200. * 22:24 25:27 cmd_pre_high_time. Time to initialize the 1st PIO cycle for
  201. * task file register access.
  202. * 28 28 UDMA enable.
  203. * 29 29 DMA enable.
  204. * 30 30 PIO MST enable. If set, the chip is in bus master mode during
  205. * PIO xfer.
  206. * 31 31 FIFO enable.
  207. */
  208. static u32 forty_base_hpt36x[] = {
  209. /* XFER_UDMA_6 */ 0x900fd943,
  210. /* XFER_UDMA_5 */ 0x900fd943,
  211. /* XFER_UDMA_4 */ 0x900fd943,
  212. /* XFER_UDMA_3 */ 0x900ad943,
  213. /* XFER_UDMA_2 */ 0x900bd943,
  214. /* XFER_UDMA_1 */ 0x9008d943,
  215. /* XFER_UDMA_0 */ 0x9008d943,
  216. /* XFER_MW_DMA_2 */ 0xa008d943,
  217. /* XFER_MW_DMA_1 */ 0xa010d955,
  218. /* XFER_MW_DMA_0 */ 0xa010d9fc,
  219. /* XFER_PIO_4 */ 0xc008d963,
  220. /* XFER_PIO_3 */ 0xc010d974,
  221. /* XFER_PIO_2 */ 0xc010d997,
  222. /* XFER_PIO_1 */ 0xc010d9c7,
  223. /* XFER_PIO_0 */ 0xc018d9d9
  224. };
  225. static u32 thirty_three_base_hpt36x[] = {
  226. /* XFER_UDMA_6 */ 0x90c9a731,
  227. /* XFER_UDMA_5 */ 0x90c9a731,
  228. /* XFER_UDMA_4 */ 0x90c9a731,
  229. /* XFER_UDMA_3 */ 0x90cfa731,
  230. /* XFER_UDMA_2 */ 0x90caa731,
  231. /* XFER_UDMA_1 */ 0x90cba731,
  232. /* XFER_UDMA_0 */ 0x90c8a731,
  233. /* XFER_MW_DMA_2 */ 0xa0c8a731,
  234. /* XFER_MW_DMA_1 */ 0xa0c8a732, /* 0xa0c8a733 */
  235. /* XFER_MW_DMA_0 */ 0xa0c8a797,
  236. /* XFER_PIO_4 */ 0xc0c8a731,
  237. /* XFER_PIO_3 */ 0xc0c8a742,
  238. /* XFER_PIO_2 */ 0xc0d0a753,
  239. /* XFER_PIO_1 */ 0xc0d0a7a3, /* 0xc0d0a793 */
  240. /* XFER_PIO_0 */ 0xc0d0a7aa /* 0xc0d0a7a7 */
  241. };
  242. static u32 twenty_five_base_hpt36x[] = {
  243. /* XFER_UDMA_6 */ 0x90c98521,
  244. /* XFER_UDMA_5 */ 0x90c98521,
  245. /* XFER_UDMA_4 */ 0x90c98521,
  246. /* XFER_UDMA_3 */ 0x90cf8521,
  247. /* XFER_UDMA_2 */ 0x90cf8521,
  248. /* XFER_UDMA_1 */ 0x90cb8521,
  249. /* XFER_UDMA_0 */ 0x90cb8521,
  250. /* XFER_MW_DMA_2 */ 0xa0ca8521,
  251. /* XFER_MW_DMA_1 */ 0xa0ca8532,
  252. /* XFER_MW_DMA_0 */ 0xa0ca8575,
  253. /* XFER_PIO_4 */ 0xc0ca8521,
  254. /* XFER_PIO_3 */ 0xc0ca8532,
  255. /* XFER_PIO_2 */ 0xc0ca8542,
  256. /* XFER_PIO_1 */ 0xc0d08572,
  257. /* XFER_PIO_0 */ 0xc0d08585
  258. };
  259. static u32 thirty_three_base_hpt37x[] = {
  260. /* XFER_UDMA_6 */ 0x12446231, /* 0x12646231 ?? */
  261. /* XFER_UDMA_5 */ 0x12446231,
  262. /* XFER_UDMA_4 */ 0x12446231,
  263. /* XFER_UDMA_3 */ 0x126c6231,
  264. /* XFER_UDMA_2 */ 0x12486231,
  265. /* XFER_UDMA_1 */ 0x124c6233,
  266. /* XFER_UDMA_0 */ 0x12506297,
  267. /* XFER_MW_DMA_2 */ 0x22406c31,
  268. /* XFER_MW_DMA_1 */ 0x22406c33,
  269. /* XFER_MW_DMA_0 */ 0x22406c97,
  270. /* XFER_PIO_4 */ 0x06414e31,
  271. /* XFER_PIO_3 */ 0x06414e42,
  272. /* XFER_PIO_2 */ 0x06414e53,
  273. /* XFER_PIO_1 */ 0x06814e93,
  274. /* XFER_PIO_0 */ 0x06814ea7
  275. };
  276. static u32 fifty_base_hpt37x[] = {
  277. /* XFER_UDMA_6 */ 0x12848242,
  278. /* XFER_UDMA_5 */ 0x12848242,
  279. /* XFER_UDMA_4 */ 0x12ac8242,
  280. /* XFER_UDMA_3 */ 0x128c8242,
  281. /* XFER_UDMA_2 */ 0x120c8242,
  282. /* XFER_UDMA_1 */ 0x12148254,
  283. /* XFER_UDMA_0 */ 0x121882ea,
  284. /* XFER_MW_DMA_2 */ 0x22808242,
  285. /* XFER_MW_DMA_1 */ 0x22808254,
  286. /* XFER_MW_DMA_0 */ 0x228082ea,
  287. /* XFER_PIO_4 */ 0x0a81f442,
  288. /* XFER_PIO_3 */ 0x0a81f443,
  289. /* XFER_PIO_2 */ 0x0a81f454,
  290. /* XFER_PIO_1 */ 0x0ac1f465,
  291. /* XFER_PIO_0 */ 0x0ac1f48a
  292. };
  293. static u32 sixty_six_base_hpt37x[] = {
  294. /* XFER_UDMA_6 */ 0x1c869c62,
  295. /* XFER_UDMA_5 */ 0x1cae9c62, /* 0x1c8a9c62 */
  296. /* XFER_UDMA_4 */ 0x1c8a9c62,
  297. /* XFER_UDMA_3 */ 0x1c8e9c62,
  298. /* XFER_UDMA_2 */ 0x1c929c62,
  299. /* XFER_UDMA_1 */ 0x1c9a9c62,
  300. /* XFER_UDMA_0 */ 0x1c829c62,
  301. /* XFER_MW_DMA_2 */ 0x2c829c62,
  302. /* XFER_MW_DMA_1 */ 0x2c829c66,
  303. /* XFER_MW_DMA_0 */ 0x2c829d2e,
  304. /* XFER_PIO_4 */ 0x0c829c62,
  305. /* XFER_PIO_3 */ 0x0c829c84,
  306. /* XFER_PIO_2 */ 0x0c829ca6,
  307. /* XFER_PIO_1 */ 0x0d029d26,
  308. /* XFER_PIO_0 */ 0x0d029d5e
  309. };
  310. #define HPT366_DEBUG_DRIVE_INFO 0
  311. #define HPT374_ALLOW_ATA133_6 0
  312. #define HPT371_ALLOW_ATA133_6 0
  313. #define HPT302_ALLOW_ATA133_6 0
  314. #define HPT372_ALLOW_ATA133_6 0
  315. #define HPT370_ALLOW_ATA100_5 0
  316. #define HPT366_ALLOW_ATA66_4 1
  317. #define HPT366_ALLOW_ATA66_3 1
  318. #define HPT366_MAX_DEVS 8
  319. #define F_LOW_PCI_33 0x23
  320. #define F_LOW_PCI_40 0x29
  321. #define F_LOW_PCI_50 0x2d
  322. #define F_LOW_PCI_66 0x42
  323. /*
  324. * Hold all the highpoint quirks and revision information in one
  325. * place.
  326. */
  327. struct hpt_info
  328. {
  329. u8 max_mode; /* Speeds allowed */
  330. u8 revision; /* Chipset revision */
  331. u8 flags; /* Chipset properties */
  332. #define PLL_MODE 1
  333. #define IS_3xxN 2
  334. #define PCI_66MHZ 4
  335. /* Speed table */
  336. u32 *speed;
  337. };
  338. /*
  339. * This wants fixing so that we do everything not by revision
  340. * (which breaks on the newest chips) but by creating an
  341. * enumeration of chip variants and using that
  342. */
  343. static __devinit u8 hpt_revision(struct pci_dev *dev)
  344. {
  345. u8 rev = 0;
  346. pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
  347. switch(dev->device) {
  348. /* Remap new 372N onto 372 */
  349. case PCI_DEVICE_ID_TTI_HPT372N:
  350. rev = PCI_DEVICE_ID_TTI_HPT372;
  351. break;
  352. case PCI_DEVICE_ID_TTI_HPT374:
  353. rev = PCI_DEVICE_ID_TTI_HPT374;
  354. break;
  355. case PCI_DEVICE_ID_TTI_HPT371:
  356. rev = PCI_DEVICE_ID_TTI_HPT371;
  357. break;
  358. case PCI_DEVICE_ID_TTI_HPT302:
  359. rev = PCI_DEVICE_ID_TTI_HPT302;
  360. break;
  361. case PCI_DEVICE_ID_TTI_HPT372:
  362. rev = PCI_DEVICE_ID_TTI_HPT372;
  363. break;
  364. default:
  365. break;
  366. }
  367. return rev;
  368. }
  369. static int check_in_drive_list(ide_drive_t *drive, const char **list)
  370. {
  371. struct hd_driveid *id = drive->id;
  372. while (*list)
  373. if (!strcmp(*list++,id->model))
  374. return 1;
  375. return 0;
  376. }
  377. static u8 hpt3xx_ratemask(ide_drive_t *drive)
  378. {
  379. struct hpt_info *info = ide_get_hwifdata(HWIF(drive));
  380. u8 mode = info->max_mode;
  381. if (!eighty_ninty_three(drive) && mode)
  382. mode = min(mode, (u8)1);
  383. return mode;
  384. }
  385. /*
  386. * Note for the future; the SATA hpt37x we must set
  387. * either PIO or UDMA modes 0,4,5
  388. */
  389. static u8 hpt3xx_ratefilter(ide_drive_t *drive, u8 speed)
  390. {
  391. struct hpt_info *info = ide_get_hwifdata(HWIF(drive));
  392. u8 mode = hpt3xx_ratemask(drive);
  393. if (drive->media != ide_disk)
  394. return min(speed, (u8)XFER_PIO_4);
  395. switch (mode) {
  396. case 0x04:
  397. speed = min(speed, (u8)XFER_UDMA_6);
  398. break;
  399. case 0x03:
  400. speed = min(speed, (u8)XFER_UDMA_5);
  401. if (info->revision >= 5)
  402. break;
  403. if (!check_in_drive_list(drive, bad_ata100_5))
  404. goto check_bad_ata33;
  405. /* fall thru */
  406. case 0x02:
  407. speed = min_t(u8, speed, XFER_UDMA_4);
  408. /*
  409. * CHECK ME, Does this need to be set to 5 ??
  410. */
  411. if (info->revision >= 3)
  412. goto check_bad_ata33;
  413. if (HPT366_ALLOW_ATA66_4 &&
  414. !check_in_drive_list(drive, bad_ata66_4))
  415. goto check_bad_ata33;
  416. speed = min_t(u8, speed, XFER_UDMA_3);
  417. if (HPT366_ALLOW_ATA66_3 &&
  418. !check_in_drive_list(drive, bad_ata66_3))
  419. goto check_bad_ata33;
  420. /* fall thru */
  421. case 0x01:
  422. speed = min_t(u8, speed, XFER_UDMA_2);
  423. check_bad_ata33:
  424. if (info->revision >= 4)
  425. break;
  426. if (!check_in_drive_list(drive, bad_ata33))
  427. break;
  428. /* fall thru */
  429. case 0x00:
  430. default:
  431. speed = min_t(u8, speed, XFER_MW_DMA_2);
  432. break;
  433. }
  434. return speed;
  435. }
  436. static u32 pci_bus_clock_list(u8 speed, u32 *chipset_table)
  437. {
  438. int i;
  439. /*
  440. * Lookup the transfer mode table to get the index into
  441. * the timing table.
  442. *
  443. * NOTE: For XFER_PIO_SLOW, PIO mode 0 timings will be used.
  444. */
  445. for (i = 0; i < ARRAY_SIZE(xfer_speeds) - 1; i++)
  446. if (xfer_speeds[i] == speed)
  447. break;
  448. return chipset_table[i];
  449. }
  450. static int hpt36x_tune_chipset(ide_drive_t *drive, u8 xferspeed)
  451. {
  452. ide_hwif_t *hwif = HWIF(drive);
  453. struct pci_dev *dev = hwif->pci_dev;
  454. struct hpt_info *info = ide_get_hwifdata (hwif);
  455. u8 speed = hpt3xx_ratefilter(drive, xferspeed);
  456. u8 itr_addr = drive->dn ? 0x44 : 0x40;
  457. u8 mcr_addr = hwif->select_data + 1;
  458. u8 mcr = 0;
  459. u32 new_itr, old_itr = 0;
  460. u32 itr_mask = (speed < XFER_MW_DMA_0) ? 0x30070000 : 0xc0000000;
  461. /*
  462. * Disable the "fast interrupt" prediction.
  463. */
  464. pci_read_config_byte(dev, mcr_addr, &mcr);
  465. if (mcr & 0x80)
  466. pci_write_config_byte(dev, mcr_addr, mcr & ~0x80);
  467. new_itr = pci_bus_clock_list(speed, info->speed);
  468. /*
  469. * Disable on-chip PIO FIFO/buffer (and PIO MST mode as well)
  470. * to avoid problems handling I/O errors later
  471. */
  472. pci_read_config_dword(dev, itr_addr, &old_itr);
  473. new_itr = (new_itr & ~itr_mask) | (old_itr & itr_mask);
  474. new_itr &= ~0xc0000000;
  475. pci_write_config_dword(dev, itr_addr, new_itr);
  476. return ide_config_drive_speed(drive, speed);
  477. }
  478. static int hpt370_tune_chipset(ide_drive_t *drive, u8 xferspeed)
  479. {
  480. ide_hwif_t *hwif = HWIF(drive);
  481. struct pci_dev *dev = hwif->pci_dev;
  482. struct hpt_info *info = ide_get_hwifdata (hwif);
  483. u8 speed = hpt3xx_ratefilter(drive, xferspeed);
  484. u8 mcr_addr = hwif->select_data + 1;
  485. u8 itr_addr = 0x40 + (drive->dn * 4);
  486. u8 new_mcr = 0, old_mcr = 0;
  487. u32 new_itr, old_itr = 0;
  488. u32 itr_mask = (speed < XFER_MW_DMA_0) ? 0x303c0000 : 0xc0000000;
  489. /*
  490. * Disable the "fast interrupt" prediction.
  491. * don't holdoff on interrupts. (== 0x01 despite what the docs say)
  492. */
  493. pci_read_config_byte(dev, mcr_addr, &old_mcr);
  494. new_mcr = old_mcr;
  495. if (new_mcr & 0x02)
  496. new_mcr &= ~0x02;
  497. #ifdef HPT_DELAY_INTERRUPT
  498. if (new_mcr & 0x01)
  499. new_mcr &= ~0x01;
  500. #else
  501. if ((new_mcr & 0x01) == 0)
  502. new_mcr |= 0x01;
  503. #endif
  504. if (new_mcr != old_mcr)
  505. pci_write_config_byte(dev, mcr_addr, new_mcr);
  506. new_itr = pci_bus_clock_list(speed, info->speed);
  507. pci_read_config_dword(dev, itr_addr, &old_itr);
  508. new_itr = (new_itr & ~itr_mask) | (old_itr & itr_mask);
  509. if (speed < XFER_MW_DMA_0)
  510. new_itr &= ~0x80000000; /* Disable on-chip PIO FIFO/buffer */
  511. pci_write_config_dword(dev, itr_addr, new_itr);
  512. return ide_config_drive_speed(drive, speed);
  513. }
  514. static int hpt372_tune_chipset(ide_drive_t *drive, u8 xferspeed)
  515. {
  516. ide_hwif_t *hwif = HWIF(drive);
  517. struct pci_dev *dev = hwif->pci_dev;
  518. struct hpt_info *info = ide_get_hwifdata (hwif);
  519. u8 speed = hpt3xx_ratefilter(drive, xferspeed);
  520. u8 mcr_addr = hwif->select_data + 1;
  521. u8 itr_addr = 0x40 + (drive->dn * 4);
  522. u8 mcr = 0;
  523. u32 new_itr, old_itr = 0;
  524. u32 itr_mask = (speed < XFER_MW_DMA_0) ? 0x303c0000 : 0xc0000000;
  525. /*
  526. * Disable the "fast interrupt" prediction.
  527. * don't holdoff on interrupts. (== 0x01 despite what the docs say)
  528. */
  529. pci_read_config_byte (dev, mcr_addr, &mcr);
  530. pci_write_config_byte(dev, mcr_addr, (mcr & ~0x07));
  531. new_itr = pci_bus_clock_list(speed, info->speed);
  532. pci_read_config_dword(dev, itr_addr, &old_itr);
  533. new_itr = (new_itr & ~itr_mask) | (old_itr & itr_mask);
  534. if (speed < XFER_MW_DMA_0)
  535. new_itr &= ~0x80000000; /* Disable on-chip PIO FIFO/buffer */
  536. pci_write_config_dword(dev, itr_addr, new_itr);
  537. return ide_config_drive_speed(drive, speed);
  538. }
  539. static int hpt3xx_tune_chipset (ide_drive_t *drive, u8 speed)
  540. {
  541. ide_hwif_t *hwif = drive->hwif;
  542. struct hpt_info *info = ide_get_hwifdata(hwif);
  543. if (info->revision >= 8)
  544. return hpt372_tune_chipset(drive, speed); /* not a typo */
  545. else if (info->revision >= 5)
  546. return hpt372_tune_chipset(drive, speed);
  547. else if (info->revision >= 3)
  548. return hpt370_tune_chipset(drive, speed);
  549. else /* hpt368: hpt_minimum_revision(dev, 2) */
  550. return hpt36x_tune_chipset(drive, speed);
  551. }
  552. static void hpt3xx_tune_drive (ide_drive_t *drive, u8 pio)
  553. {
  554. pio = ide_get_best_pio_mode(drive, 255, pio, NULL);
  555. (void) hpt3xx_tune_chipset(drive, (XFER_PIO_0 + pio));
  556. }
  557. /*
  558. * This allows the configuration of ide_pci chipset registers
  559. * for cards that learn about the drive's UDMA, DMA, PIO capabilities
  560. * after the drive is reported by the OS. Initially for designed for
  561. * HPT366 UDMA chipset by HighPoint|Triones Technologies, Inc.
  562. *
  563. * check_in_drive_lists(drive, bad_ata66_4)
  564. * check_in_drive_lists(drive, bad_ata66_3)
  565. * check_in_drive_lists(drive, bad_ata33)
  566. *
  567. */
  568. static int config_chipset_for_dma (ide_drive_t *drive)
  569. {
  570. u8 speed = ide_dma_speed(drive, hpt3xx_ratemask(drive));
  571. ide_hwif_t *hwif = drive->hwif;
  572. struct hpt_info *info = ide_get_hwifdata(hwif);
  573. if (!speed)
  574. return 0;
  575. /* If we don't have any timings we can't do a lot */
  576. if (info->speed == NULL)
  577. return 0;
  578. (void) hpt3xx_tune_chipset(drive, speed);
  579. return ide_dma_enable(drive);
  580. }
  581. static int hpt3xx_quirkproc(ide_drive_t *drive)
  582. {
  583. struct hd_driveid *id = drive->id;
  584. const char **list = quirk_drives;
  585. while (*list)
  586. if (strstr(id->model, *list++))
  587. return 1;
  588. return 0;
  589. }
  590. static void hpt3xx_intrproc (ide_drive_t *drive)
  591. {
  592. ide_hwif_t *hwif = HWIF(drive);
  593. if (drive->quirk_list)
  594. return;
  595. /* drives in the quirk_list may not like intr setups/cleanups */
  596. hwif->OUTB(drive->ctl | 2, IDE_CONTROL_REG);
  597. }
  598. static void hpt3xx_maskproc (ide_drive_t *drive, int mask)
  599. {
  600. ide_hwif_t *hwif = HWIF(drive);
  601. struct pci_dev *dev = hwif->pci_dev;
  602. struct hpt_info *info = ide_get_hwifdata(hwif);
  603. if (drive->quirk_list) {
  604. if (info->revision >= 3) {
  605. u8 scr1 = 0;
  606. pci_read_config_byte(dev, 0x5a, &scr1);
  607. if (((scr1 & 0x10) >> 4) != mask) {
  608. if (mask)
  609. scr1 |= 0x10;
  610. else
  611. scr1 &= ~0x10;
  612. pci_write_config_byte(dev, 0x5a, scr1);
  613. }
  614. } else {
  615. if (mask)
  616. disable_irq(hwif->irq);
  617. else
  618. enable_irq (hwif->irq);
  619. }
  620. } else
  621. hwif->OUTB(mask ? (drive->ctl | 2) : (drive->ctl & ~2),
  622. IDE_CONTROL_REG);
  623. }
  624. static int hpt366_config_drive_xfer_rate (ide_drive_t *drive)
  625. {
  626. ide_hwif_t *hwif = drive->hwif;
  627. struct hd_driveid *id = drive->id;
  628. drive->init_speed = 0;
  629. if ((id->capability & 1) && drive->autodma) {
  630. if (ide_use_dma(drive)) {
  631. if (config_chipset_for_dma(drive))
  632. return hwif->ide_dma_on(drive);
  633. }
  634. goto fast_ata_pio;
  635. } else if ((id->capability & 8) || (id->field_valid & 2)) {
  636. fast_ata_pio:
  637. hpt3xx_tune_drive(drive, 5);
  638. return hwif->ide_dma_off_quietly(drive);
  639. }
  640. /* IORDY not supported */
  641. return 0;
  642. }
  643. /*
  644. * This is specific to the HPT366 UDMA chipset
  645. * by HighPoint|Triones Technologies, Inc.
  646. */
  647. static int hpt366_ide_dma_lostirq(ide_drive_t *drive)
  648. {
  649. struct pci_dev *dev = HWIF(drive)->pci_dev;
  650. u8 mcr1 = 0, mcr3 = 0, scr1 = 0;
  651. pci_read_config_byte(dev, 0x50, &mcr1);
  652. pci_read_config_byte(dev, 0x52, &mcr3);
  653. pci_read_config_byte(dev, 0x5a, &scr1);
  654. printk("%s: (%s) mcr1=0x%02x, mcr3=0x%02x, scr1=0x%02x\n",
  655. drive->name, __FUNCTION__, mcr1, mcr3, scr1);
  656. if (scr1 & 0x10)
  657. pci_write_config_byte(dev, 0x5a, scr1 & ~0x10);
  658. return __ide_dma_lostirq(drive);
  659. }
  660. static void hpt370_clear_engine (ide_drive_t *drive)
  661. {
  662. ide_hwif_t *hwif = HWIF(drive);
  663. pci_write_config_byte(hwif->pci_dev, hwif->select_data, 0x37);
  664. udelay(10);
  665. }
  666. static void hpt370_ide_dma_start(ide_drive_t *drive)
  667. {
  668. #ifdef HPT_RESET_STATE_ENGINE
  669. hpt370_clear_engine(drive);
  670. #endif
  671. ide_dma_start(drive);
  672. }
  673. static int hpt370_ide_dma_end (ide_drive_t *drive)
  674. {
  675. ide_hwif_t *hwif = HWIF(drive);
  676. u8 dma_stat = hwif->INB(hwif->dma_status);
  677. if (dma_stat & 0x01) {
  678. /* wait a little */
  679. udelay(20);
  680. dma_stat = hwif->INB(hwif->dma_status);
  681. }
  682. if ((dma_stat & 0x01) != 0)
  683. /* fallthrough */
  684. (void) HWIF(drive)->ide_dma_timeout(drive);
  685. return __ide_dma_end(drive);
  686. }
  687. static void hpt370_lostirq_timeout (ide_drive_t *drive)
  688. {
  689. ide_hwif_t *hwif = HWIF(drive);
  690. u8 bfifo = 0;
  691. u8 dma_stat = 0, dma_cmd = 0;
  692. pci_read_config_byte(HWIF(drive)->pci_dev, hwif->select_data + 2, &bfifo);
  693. printk(KERN_DEBUG "%s: %d bytes in FIFO\n", drive->name, bfifo);
  694. hpt370_clear_engine(drive);
  695. /* get dma command mode */
  696. dma_cmd = hwif->INB(hwif->dma_command);
  697. /* stop dma */
  698. hwif->OUTB(dma_cmd & ~0x1, hwif->dma_command);
  699. dma_stat = hwif->INB(hwif->dma_status);
  700. /* clear errors */
  701. hwif->OUTB(dma_stat | 0x6, hwif->dma_status);
  702. }
  703. static int hpt370_ide_dma_timeout (ide_drive_t *drive)
  704. {
  705. hpt370_lostirq_timeout(drive);
  706. hpt370_clear_engine(drive);
  707. return __ide_dma_timeout(drive);
  708. }
  709. static int hpt370_ide_dma_lostirq (ide_drive_t *drive)
  710. {
  711. hpt370_lostirq_timeout(drive);
  712. hpt370_clear_engine(drive);
  713. return __ide_dma_lostirq(drive);
  714. }
  715. /* returns 1 if DMA IRQ issued, 0 otherwise */
  716. static int hpt374_ide_dma_test_irq(ide_drive_t *drive)
  717. {
  718. ide_hwif_t *hwif = HWIF(drive);
  719. u16 bfifo = 0;
  720. u8 dma_stat;
  721. pci_read_config_word(hwif->pci_dev, hwif->select_data + 2, &bfifo);
  722. if (bfifo & 0x1FF) {
  723. // printk("%s: %d bytes in FIFO\n", drive->name, bfifo);
  724. return 0;
  725. }
  726. dma_stat = hwif->INB(hwif->dma_status);
  727. /* return 1 if INTR asserted */
  728. if (dma_stat & 4)
  729. return 1;
  730. if (!drive->waiting_for_dma)
  731. printk(KERN_WARNING "%s: (%s) called while not waiting\n",
  732. drive->name, __FUNCTION__);
  733. return 0;
  734. }
  735. static int hpt374_ide_dma_end(ide_drive_t *drive)
  736. {
  737. ide_hwif_t *hwif = HWIF(drive);
  738. struct pci_dev *dev = hwif->pci_dev;
  739. u8 mcr = 0, mcr_addr = hwif->select_data;
  740. u8 bwsr = 0, mask = hwif->channel ? 0x02 : 0x01;
  741. pci_read_config_byte(dev, 0x6a, &bwsr);
  742. pci_read_config_byte(dev, mcr_addr, &mcr);
  743. if (bwsr & mask)
  744. pci_write_config_byte(dev, mcr_addr, mcr | 0x30);
  745. return __ide_dma_end(drive);
  746. }
  747. /**
  748. * hpt3xxn_set_clock - perform clock switching dance
  749. * @hwif: hwif to switch
  750. * @mode: clocking mode (0x21 for write, 0x23 otherwise)
  751. *
  752. * Switch the DPLL clock on the HPT3xxN devices. This is a right mess.
  753. * NOTE: avoid touching the disabled primary channel on HPT371N -- it
  754. * doesn't physically exist anyway...
  755. */
  756. static void hpt3xxn_set_clock(ide_hwif_t *hwif, u8 mode)
  757. {
  758. u8 mcr1, scr2 = hwif->INB(hwif->dma_master + 0x7b);
  759. if ((scr2 & 0x7f) == mode)
  760. return;
  761. /* MISC. control register 1 has the channel enable bit... */
  762. mcr1 = hwif->INB(hwif->dma_master + 0x70);
  763. /* Tristate the bus */
  764. if (mcr1 & 0x04)
  765. hwif->OUTB(0x80, hwif->dma_master + 0x73);
  766. hwif->OUTB(0x80, hwif->dma_master + 0x77);
  767. /* Switch clock and reset channels */
  768. hwif->OUTB(mode, hwif->dma_master + 0x7b);
  769. hwif->OUTB(0xc0, hwif->dma_master + 0x79);
  770. /* Reset state machines */
  771. if (mcr1 & 0x04)
  772. hwif->OUTB(0x37, hwif->dma_master + 0x70);
  773. hwif->OUTB(0x37, hwif->dma_master + 0x74);
  774. /* Complete reset */
  775. hwif->OUTB(0x00, hwif->dma_master + 0x79);
  776. /* Reconnect channels to bus */
  777. if (mcr1 & 0x04)
  778. hwif->OUTB(0x00, hwif->dma_master + 0x73);
  779. hwif->OUTB(0x00, hwif->dma_master + 0x77);
  780. }
  781. /**
  782. * hpt3xxn_rw_disk - prepare for I/O
  783. * @drive: drive for command
  784. * @rq: block request structure
  785. *
  786. * This is called when a disk I/O is issued to HPT3xxN.
  787. * We need it because of the clock switching.
  788. */
  789. static void hpt3xxn_rw_disk(ide_drive_t *drive, struct request *rq)
  790. {
  791. ide_hwif_t *hwif = HWIF(drive);
  792. u8 wantclock = rq_data_dir(rq) ? 0x23 : 0x21;
  793. hpt3xxn_set_clock(hwif, wantclock);
  794. }
  795. /*
  796. * Set/get power state for a drive.
  797. * NOTE: affects both drives on each channel.
  798. *
  799. * When we turn the power back on, we need to re-initialize things.
  800. */
  801. #define TRISTATE_BIT 0x8000
  802. static int hpt3xx_busproc(ide_drive_t *drive, int state)
  803. {
  804. ide_hwif_t *hwif = HWIF(drive);
  805. struct pci_dev *dev = hwif->pci_dev;
  806. u8 mcr_addr = hwif->select_data + 2;
  807. u8 resetmask = hwif->channel ? 0x80 : 0x40;
  808. u8 bsr2 = 0;
  809. u16 mcr = 0;
  810. hwif->bus_state = state;
  811. /* Grab the status. */
  812. pci_read_config_word(dev, mcr_addr, &mcr);
  813. pci_read_config_byte(dev, 0x59, &bsr2);
  814. /*
  815. * Set the state. We don't set it if we don't need to do so.
  816. * Make sure that the drive knows that it has failed if it's off.
  817. */
  818. switch (state) {
  819. case BUSSTATE_ON:
  820. if (!(bsr2 & resetmask))
  821. return 0;
  822. hwif->drives[0].failures = hwif->drives[1].failures = 0;
  823. pci_write_config_byte(dev, 0x59, bsr2 & ~resetmask);
  824. pci_write_config_word(dev, mcr_addr, mcr & ~TRISTATE_BIT);
  825. return 0;
  826. case BUSSTATE_OFF:
  827. if ((bsr2 & resetmask) && !(mcr & TRISTATE_BIT))
  828. return 0;
  829. mcr &= ~TRISTATE_BIT;
  830. break;
  831. case BUSSTATE_TRISTATE:
  832. if ((bsr2 & resetmask) && (mcr & TRISTATE_BIT))
  833. return 0;
  834. mcr |= TRISTATE_BIT;
  835. break;
  836. default:
  837. return -EINVAL;
  838. }
  839. hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
  840. hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
  841. pci_write_config_word(dev, mcr_addr, mcr);
  842. pci_write_config_byte(dev, 0x59, bsr2 | resetmask);
  843. return 0;
  844. }
  845. static void __devinit hpt366_clocking(ide_hwif_t *hwif)
  846. {
  847. u32 itr1 = 0;
  848. struct hpt_info *info = ide_get_hwifdata(hwif);
  849. pci_read_config_dword(hwif->pci_dev, 0x40, &itr1);
  850. /* detect bus speed by looking at control reg timing: */
  851. switch((itr1 >> 8) & 7) {
  852. case 5:
  853. info->speed = forty_base_hpt36x;
  854. break;
  855. case 9:
  856. info->speed = twenty_five_base_hpt36x;
  857. break;
  858. case 7:
  859. default:
  860. info->speed = thirty_three_base_hpt36x;
  861. break;
  862. }
  863. }
  864. static void __devinit hpt37x_clocking(ide_hwif_t *hwif)
  865. {
  866. struct hpt_info *info = ide_get_hwifdata(hwif);
  867. struct pci_dev *dev = hwif->pci_dev;
  868. char *name = hwif->cds->name;
  869. int adjust, i;
  870. u16 freq = 0;
  871. u32 pll, temp = 0;
  872. u8 scr2 = 0, mcr1 = 0;
  873. /*
  874. * default to pci clock. make sure MA15/16 are set to output
  875. * to prevent drives having problems with 40-pin cables. Needed
  876. * for some drives such as IBM-DTLA which will not enter ready
  877. * state on reset when PDIAG is a input.
  878. *
  879. * ToDo: should we set 0x21 when using PLL mode ?
  880. */
  881. pci_write_config_byte(dev, 0x5b, 0x23);
  882. /*
  883. * We'll have to read f_CNT value in order to determine
  884. * the PCI clock frequency according to the following ratio:
  885. *
  886. * f_CNT = Fpci * 192 / Fdpll
  887. *
  888. * First try reading the register in which the HighPoint BIOS
  889. * saves f_CNT value before reprogramming the DPLL from its
  890. * default setting (which differs for the various chips).
  891. * NOTE: This register is only accessible via I/O space.
  892. *
  893. * In case the signature check fails, we'll have to resort to
  894. * reading the f_CNT register itself in hopes that nobody has
  895. * touched the DPLL yet...
  896. */
  897. temp = inl(pci_resource_start(dev, 4) + 0x90);
  898. if ((temp & 0xFFFFF000) != 0xABCDE000) {
  899. printk(KERN_WARNING "%s: no clock data saved by BIOS\n", name);
  900. /* Calculate the average value of f_CNT */
  901. for (temp = i = 0; i < 128; i++) {
  902. pci_read_config_word(dev, 0x78, &freq);
  903. temp += freq & 0x1ff;
  904. mdelay(1);
  905. }
  906. freq = temp / 128;
  907. } else
  908. freq = temp & 0x1ff;
  909. /*
  910. * HPT3xxN chips use different PCI clock information.
  911. * Currently we always set up the PLL for them.
  912. */
  913. if (info->flags & IS_3xxN) {
  914. if(freq < 0x55)
  915. pll = F_LOW_PCI_33;
  916. else if(freq < 0x70)
  917. pll = F_LOW_PCI_40;
  918. else if(freq < 0x7F)
  919. pll = F_LOW_PCI_50;
  920. else
  921. pll = F_LOW_PCI_66;
  922. } else {
  923. if(freq < 0x9C)
  924. pll = F_LOW_PCI_33;
  925. else if(freq < 0xb0)
  926. pll = F_LOW_PCI_40;
  927. else if(freq <0xc8)
  928. pll = F_LOW_PCI_50;
  929. else
  930. pll = F_LOW_PCI_66;
  931. }
  932. printk(KERN_INFO "%s: FREQ: %d, PLL: %d\n", name, freq, pll);
  933. if (!(info->flags & IS_3xxN)) {
  934. if (pll == F_LOW_PCI_33) {
  935. info->speed = thirty_three_base_hpt37x;
  936. printk(KERN_DEBUG "%s: using 33MHz PCI clock\n", name);
  937. } else if (pll == F_LOW_PCI_40) {
  938. /* Unsupported */
  939. } else if (pll == F_LOW_PCI_50) {
  940. info->speed = fifty_base_hpt37x;
  941. printk(KERN_DEBUG "%s: using 50MHz PCI clock\n", name);
  942. } else {
  943. info->speed = sixty_six_base_hpt37x;
  944. printk(KERN_DEBUG "%s: using 66MHz PCI clock\n", name);
  945. }
  946. }
  947. if (pll == F_LOW_PCI_66)
  948. info->flags |= PCI_66MHZ;
  949. /*
  950. * only try the pll if we don't have a table for the clock
  951. * speed that we're running at. NOTE: the internal PLL will
  952. * result in slow reads when using a 33MHz PCI clock. we also
  953. * don't like to use the PLL because it will cause glitches
  954. * on PRST/SRST when the HPT state engine gets reset.
  955. *
  956. * ToDo: Use 66MHz PLL when ATA133 devices are present on a
  957. * 372 device so we can get ATA133 support
  958. */
  959. if (info->speed)
  960. goto init_hpt37X_done;
  961. info->flags |= PLL_MODE;
  962. /*
  963. * Adjust the PLL based upon the PCI clock, enable it, and
  964. * wait for stabilization...
  965. */
  966. adjust = 0;
  967. freq = (pll < F_LOW_PCI_50) ? 2 : 4;
  968. while (adjust++ < 6) {
  969. pci_write_config_dword(dev, 0x5c, (freq + pll) << 16 |
  970. pll | 0x100);
  971. /* wait for clock stabilization */
  972. for (i = 0; i < 0x50000; i++) {
  973. pci_read_config_byte(dev, 0x5b, &scr2);
  974. if (scr2 & 0x80) {
  975. /* spin looking for the clock to destabilize */
  976. for (i = 0; i < 0x1000; ++i) {
  977. pci_read_config_byte(dev, 0x5b,
  978. &scr2);
  979. if ((scr2 & 0x80) == 0)
  980. goto pll_recal;
  981. }
  982. pci_read_config_dword(dev, 0x5c, &pll);
  983. pci_write_config_dword(dev, 0x5c,
  984. pll & ~0x100);
  985. pci_write_config_byte(dev, 0x5b, 0x21);
  986. info->speed = fifty_base_hpt37x;
  987. printk("%s: using 50MHz internal PLL\n", name);
  988. goto init_hpt37X_done;
  989. }
  990. }
  991. pll_recal:
  992. if (adjust & 1)
  993. pll -= (adjust >> 1);
  994. else
  995. pll += (adjust >> 1);
  996. }
  997. init_hpt37X_done:
  998. if (!info->speed)
  999. printk(KERN_ERR "%s: unknown bus timing [%d %d].\n",
  1000. name, pll, freq);
  1001. /*
  1002. * Reset the state engines.
  1003. * NOTE: avoid accidentally enabling the primary channel on HPT371N.
  1004. */
  1005. pci_read_config_byte(dev, 0x50, &mcr1);
  1006. if (mcr1 & 0x04)
  1007. pci_write_config_byte(dev, 0x50, 0x37);
  1008. pci_write_config_byte(dev, 0x54, 0x37);
  1009. udelay(100);
  1010. }
  1011. static int __devinit init_hpt37x(struct pci_dev *dev)
  1012. {
  1013. u8 scr1;
  1014. pci_read_config_byte (dev, 0x5a, &scr1);
  1015. /* interrupt force enable */
  1016. pci_write_config_byte(dev, 0x5a, (scr1 & ~0x10));
  1017. return 0;
  1018. }
  1019. static int __devinit init_hpt366(struct pci_dev *dev)
  1020. {
  1021. u8 mcr = 0;
  1022. /*
  1023. * Disable the "fast interrupt" prediction.
  1024. */
  1025. pci_read_config_byte(dev, 0x51, &mcr);
  1026. if (mcr & 0x80)
  1027. pci_write_config_byte(dev, 0x51, mcr & ~0x80);
  1028. return 0;
  1029. }
  1030. static unsigned int __devinit init_chipset_hpt366(struct pci_dev *dev, const char *name)
  1031. {
  1032. int ret = 0;
  1033. /*
  1034. * FIXME: Not portable. Also, why do we enable the ROM in the first place?
  1035. * We don't seem to be using it.
  1036. */
  1037. if (dev->resource[PCI_ROM_RESOURCE].start)
  1038. pci_write_config_dword(dev, PCI_ROM_ADDRESS,
  1039. dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
  1040. pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
  1041. pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
  1042. pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
  1043. pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
  1044. if (hpt_revision(dev) >= 3)
  1045. ret = init_hpt37x(dev);
  1046. else
  1047. ret = init_hpt366(dev);
  1048. if (ret)
  1049. return ret;
  1050. return dev->irq;
  1051. }
  1052. static void __devinit init_hwif_hpt366(ide_hwif_t *hwif)
  1053. {
  1054. struct pci_dev *dev = hwif->pci_dev;
  1055. struct hpt_info *info = ide_get_hwifdata(hwif);
  1056. int serialize = HPT_SERIALIZE_IO;
  1057. u8 scr1 = 0, ata66 = (hwif->channel) ? 0x01 : 0x02;
  1058. /* Cache the channel's MISC. control registers' offset */
  1059. hwif->select_data = hwif->channel ? 0x54 : 0x50;
  1060. hwif->tuneproc = &hpt3xx_tune_drive;
  1061. hwif->speedproc = &hpt3xx_tune_chipset;
  1062. hwif->quirkproc = &hpt3xx_quirkproc;
  1063. hwif->intrproc = &hpt3xx_intrproc;
  1064. hwif->maskproc = &hpt3xx_maskproc;
  1065. hwif->busproc = &hpt3xx_busproc;
  1066. /*
  1067. * HPT3xxN chips have some complications:
  1068. *
  1069. * - on 33 MHz PCI we must clock switch
  1070. * - on 66 MHz PCI we must NOT use the PCI clock
  1071. */
  1072. if ((info->flags & (IS_3xxN | PCI_66MHZ)) == IS_3xxN) {
  1073. /*
  1074. * Clock is shared between the channels,
  1075. * so we'll have to serialize them... :-(
  1076. */
  1077. serialize = 1;
  1078. hwif->rw_disk = &hpt3xxn_rw_disk;
  1079. }
  1080. /*
  1081. * The HPT37x uses the CBLID pins as outputs for MA15/MA16
  1082. * address lines to access an external EEPROM. To read valid
  1083. * cable detect state the pins must be enabled as inputs.
  1084. */
  1085. if (info->revision >= 8 && (PCI_FUNC(dev->devfn) & 1)) {
  1086. /*
  1087. * HPT374 PCI function 1
  1088. * - set bit 15 of reg 0x52 to enable TCBLID as input
  1089. * - set bit 15 of reg 0x56 to enable FCBLID as input
  1090. */
  1091. u8 mcr_addr = hwif->select_data + 2;
  1092. u16 mcr;
  1093. pci_read_config_word (dev, mcr_addr, &mcr);
  1094. pci_write_config_word(dev, mcr_addr, (mcr | 0x8000));
  1095. /* now read cable id register */
  1096. pci_read_config_byte (dev, 0x5a, &scr1);
  1097. pci_write_config_word(dev, mcr_addr, mcr);
  1098. } else if (info->revision >= 3) {
  1099. /*
  1100. * HPT370/372 and 374 pcifn 0
  1101. * - clear bit 0 of reg 0x5b to enable P/SCBLID as inputs
  1102. */
  1103. u8 scr2 = 0;
  1104. pci_read_config_byte (dev, 0x5b, &scr2);
  1105. pci_write_config_byte(dev, 0x5b, (scr2 & ~1));
  1106. /* now read cable id register */
  1107. pci_read_config_byte (dev, 0x5a, &scr1);
  1108. pci_write_config_byte(dev, 0x5b, scr2);
  1109. } else
  1110. pci_read_config_byte (dev, 0x5a, &scr1);
  1111. /* Serialize access to this device */
  1112. if (serialize && hwif->mate)
  1113. hwif->serialized = hwif->mate->serialized = 1;
  1114. /*
  1115. * Set up ioctl for power status.
  1116. * NOTE: power affects both drives on each channel.
  1117. */
  1118. hwif->busproc = &hpt3xx_busproc;
  1119. if (!hwif->dma_base) {
  1120. hwif->drives[0].autotune = 1;
  1121. hwif->drives[1].autotune = 1;
  1122. return;
  1123. }
  1124. hwif->ultra_mask = 0x7f;
  1125. hwif->mwdma_mask = 0x07;
  1126. if (!(hwif->udma_four))
  1127. hwif->udma_four = ((scr1 & ata66) ? 0 : 1);
  1128. hwif->ide_dma_check = &hpt366_config_drive_xfer_rate;
  1129. if (info->revision >= 8) {
  1130. hwif->ide_dma_test_irq = &hpt374_ide_dma_test_irq;
  1131. hwif->ide_dma_end = &hpt374_ide_dma_end;
  1132. } else if (info->revision >= 5) {
  1133. hwif->ide_dma_test_irq = &hpt374_ide_dma_test_irq;
  1134. hwif->ide_dma_end = &hpt374_ide_dma_end;
  1135. } else if (info->revision >= 3) {
  1136. hwif->dma_start = &hpt370_ide_dma_start;
  1137. hwif->ide_dma_end = &hpt370_ide_dma_end;
  1138. hwif->ide_dma_timeout = &hpt370_ide_dma_timeout;
  1139. hwif->ide_dma_lostirq = &hpt370_ide_dma_lostirq;
  1140. } else if (info->revision >= 2)
  1141. hwif->ide_dma_lostirq = &hpt366_ide_dma_lostirq;
  1142. else
  1143. hwif->ide_dma_lostirq = &hpt366_ide_dma_lostirq;
  1144. if (!noautodma)
  1145. hwif->autodma = 1;
  1146. hwif->drives[0].autodma = hwif->autodma;
  1147. hwif->drives[1].autodma = hwif->autodma;
  1148. }
  1149. static void __devinit init_dma_hpt366(ide_hwif_t *hwif, unsigned long dmabase)
  1150. {
  1151. struct pci_dev *dev = hwif->pci_dev;
  1152. struct hpt_info *info = ide_get_hwifdata(hwif);
  1153. u8 masterdma = 0, slavedma = 0;
  1154. u8 dma_new = 0, dma_old = 0;
  1155. unsigned long flags;
  1156. if (!dmabase)
  1157. return;
  1158. if(info->speed == NULL) {
  1159. printk(KERN_WARNING "%s: no known IDE timings, disabling DMA.\n",
  1160. hwif->cds->name);
  1161. return;
  1162. }
  1163. dma_old = hwif->INB(dmabase+2);
  1164. local_irq_save(flags);
  1165. dma_new = dma_old;
  1166. pci_read_config_byte(dev, hwif->channel ? 0x4b : 0x43, &masterdma);
  1167. pci_read_config_byte(dev, hwif->channel ? 0x4f : 0x47, &slavedma);
  1168. if (masterdma & 0x30) dma_new |= 0x20;
  1169. if ( slavedma & 0x30) dma_new |= 0x40;
  1170. if (dma_new != dma_old)
  1171. hwif->OUTB(dma_new, dmabase + 2);
  1172. local_irq_restore(flags);
  1173. ide_setup_dma(hwif, dmabase, 8);
  1174. }
  1175. /*
  1176. * We "borrow" this hook in order to set the data structures
  1177. * up early enough before dma or init_hwif calls are made.
  1178. */
  1179. static void __devinit init_iops_hpt366(ide_hwif_t *hwif)
  1180. {
  1181. struct hpt_info *info = kzalloc(sizeof(struct hpt_info), GFP_KERNEL);
  1182. struct pci_dev *dev = hwif->pci_dev;
  1183. u16 did = dev->device;
  1184. u8 mode, rid = 0;
  1185. if(info == NULL) {
  1186. printk(KERN_WARNING "%s: out of memory.\n", hwif->cds->name);
  1187. return;
  1188. }
  1189. ide_set_hwifdata(hwif, info);
  1190. /* Avoid doing the same thing twice. */
  1191. if (hwif->channel && hwif->mate) {
  1192. memcpy(info, ide_get_hwifdata(hwif->mate), sizeof(struct hpt_info));
  1193. return;
  1194. }
  1195. pci_read_config_byte(dev, PCI_REVISION_ID, &rid);
  1196. if (( did == PCI_DEVICE_ID_TTI_HPT366 && rid == 6) ||
  1197. ((did == PCI_DEVICE_ID_TTI_HPT372 ||
  1198. did == PCI_DEVICE_ID_TTI_HPT302 ||
  1199. did == PCI_DEVICE_ID_TTI_HPT371) && rid > 1) ||
  1200. did == PCI_DEVICE_ID_TTI_HPT372N)
  1201. info->flags |= IS_3xxN;
  1202. rid = info->revision = hpt_revision(dev);
  1203. if (rid >= 8) /* HPT374 */
  1204. mode = HPT374_ALLOW_ATA133_6 ? 4 : 3;
  1205. else if (rid >= 7) /* HPT371 and HPT371N */
  1206. mode = HPT371_ALLOW_ATA133_6 ? 4 : 3;
  1207. else if (rid >= 6) /* HPT302 and HPT302N */
  1208. mode = HPT302_ALLOW_ATA133_6 ? 4 : 3;
  1209. else if (rid >= 5) /* HPT372, HPT372A, and HPT372N */
  1210. mode = HPT372_ALLOW_ATA133_6 ? 4 : 3;
  1211. else if (rid >= 3) /* HPT370 and HPT370A */
  1212. mode = HPT370_ALLOW_ATA100_5 ? 3 : 2;
  1213. else /* HPT366 and HPT368 */
  1214. mode = (HPT366_ALLOW_ATA66_4 || HPT366_ALLOW_ATA66_3) ? 2 : 1;
  1215. info->max_mode = mode;
  1216. if (rid >= 3)
  1217. hpt37x_clocking(hwif);
  1218. else
  1219. hpt366_clocking(hwif);
  1220. }
  1221. static int __devinit init_setup_hpt374(struct pci_dev *dev, ide_pci_device_t *d)
  1222. {
  1223. struct pci_dev *dev2;
  1224. if (PCI_FUNC(dev->devfn) & 1)
  1225. return -ENODEV;
  1226. if ((dev2 = pci_get_slot(dev->bus, dev->devfn + 1)) != NULL) {
  1227. int ret;
  1228. if (dev2->irq != dev->irq) {
  1229. /* FIXME: we need a core pci_set_interrupt() */
  1230. dev2->irq = dev->irq;
  1231. printk(KERN_WARNING "%s: PCI config space interrupt "
  1232. "fixed.\n", d->name);
  1233. }
  1234. ret = ide_setup_pci_devices(dev, dev2, d);
  1235. if (ret < 0)
  1236. pci_dev_put(dev2);
  1237. return ret;
  1238. }
  1239. return ide_setup_pci_device(dev, d);
  1240. }
  1241. static int __devinit init_setup_hpt372n(struct pci_dev *dev, ide_pci_device_t *d)
  1242. {
  1243. return ide_setup_pci_device(dev, d);
  1244. }
  1245. static int __devinit init_setup_hpt371(struct pci_dev *dev, ide_pci_device_t *d)
  1246. {
  1247. u8 rev = 0, mcr1 = 0;
  1248. pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
  1249. if (rev > 1)
  1250. d->name = "HPT371N";
  1251. /*
  1252. * HPT371 chips physically have only one channel, the secondary one,
  1253. * but the primary channel registers do exist! Go figure...
  1254. * So, we manually disable the non-existing channel here
  1255. * (if the BIOS hasn't done this already).
  1256. */
  1257. pci_read_config_byte(dev, 0x50, &mcr1);
  1258. if (mcr1 & 0x04)
  1259. pci_write_config_byte(dev, 0x50, mcr1 & ~0x04);
  1260. return ide_setup_pci_device(dev, d);
  1261. }
  1262. static int __devinit init_setup_hpt372a(struct pci_dev *dev, ide_pci_device_t *d)
  1263. {
  1264. u8 rev = 0;
  1265. pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
  1266. if (rev > 1)
  1267. d->name = "HPT372N";
  1268. return ide_setup_pci_device(dev, d);
  1269. }
  1270. static int __devinit init_setup_hpt302(struct pci_dev *dev, ide_pci_device_t *d)
  1271. {
  1272. u8 rev = 0;
  1273. pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
  1274. if (rev > 1)
  1275. d->name = "HPT302N";
  1276. return ide_setup_pci_device(dev, d);
  1277. }
  1278. static int __devinit init_setup_hpt366(struct pci_dev *dev, ide_pci_device_t *d)
  1279. {
  1280. struct pci_dev *dev2;
  1281. u8 rev = 0;
  1282. static char *chipset_names[] = { "HPT366", "HPT366", "HPT368",
  1283. "HPT370", "HPT370A", "HPT372",
  1284. "HPT372N" };
  1285. if (PCI_FUNC(dev->devfn) & 1)
  1286. return -ENODEV;
  1287. pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
  1288. if (rev > 6)
  1289. rev = 6;
  1290. d->name = chipset_names[rev];
  1291. if (rev > 2)
  1292. goto init_single;
  1293. d->channels = 1;
  1294. if ((dev2 = pci_get_slot(dev->bus, dev->devfn + 1)) != NULL) {
  1295. u8 pin1 = 0, pin2 = 0;
  1296. int ret;
  1297. pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin1);
  1298. pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin2);
  1299. if (pin1 != pin2 && dev->irq == dev2->irq) {
  1300. d->bootable = ON_BOARD;
  1301. printk("%s: onboard version of chipset, pin1=%d pin2=%d\n",
  1302. d->name, pin1, pin2);
  1303. }
  1304. ret = ide_setup_pci_devices(dev, dev2, d);
  1305. if (ret < 0)
  1306. pci_dev_put(dev2);
  1307. return ret;
  1308. }
  1309. init_single:
  1310. return ide_setup_pci_device(dev, d);
  1311. }
  1312. static ide_pci_device_t hpt366_chipsets[] __devinitdata = {
  1313. { /* 0 */
  1314. .name = "HPT366",
  1315. .init_setup = init_setup_hpt366,
  1316. .init_chipset = init_chipset_hpt366,
  1317. .init_iops = init_iops_hpt366,
  1318. .init_hwif = init_hwif_hpt366,
  1319. .init_dma = init_dma_hpt366,
  1320. .channels = 2,
  1321. .autodma = AUTODMA,
  1322. .bootable = OFF_BOARD,
  1323. .extra = 240
  1324. },{ /* 1 */
  1325. .name = "HPT372A",
  1326. .init_setup = init_setup_hpt372a,
  1327. .init_chipset = init_chipset_hpt366,
  1328. .init_iops = init_iops_hpt366,
  1329. .init_hwif = init_hwif_hpt366,
  1330. .init_dma = init_dma_hpt366,
  1331. .channels = 2,
  1332. .autodma = AUTODMA,
  1333. .bootable = OFF_BOARD,
  1334. .extra = 240
  1335. },{ /* 2 */
  1336. .name = "HPT302",
  1337. .init_setup = init_setup_hpt302,
  1338. .init_chipset = init_chipset_hpt366,
  1339. .init_iops = init_iops_hpt366,
  1340. .init_hwif = init_hwif_hpt366,
  1341. .init_dma = init_dma_hpt366,
  1342. .channels = 2,
  1343. .autodma = AUTODMA,
  1344. .bootable = OFF_BOARD,
  1345. .extra = 240
  1346. },{ /* 3 */
  1347. .name = "HPT371",
  1348. .init_setup = init_setup_hpt371,
  1349. .init_chipset = init_chipset_hpt366,
  1350. .init_iops = init_iops_hpt366,
  1351. .init_hwif = init_hwif_hpt366,
  1352. .init_dma = init_dma_hpt366,
  1353. .channels = 2,
  1354. .autodma = AUTODMA,
  1355. .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
  1356. .bootable = OFF_BOARD,
  1357. .extra = 240
  1358. },{ /* 4 */
  1359. .name = "HPT374",
  1360. .init_setup = init_setup_hpt374,
  1361. .init_chipset = init_chipset_hpt366,
  1362. .init_iops = init_iops_hpt366,
  1363. .init_hwif = init_hwif_hpt366,
  1364. .init_dma = init_dma_hpt366,
  1365. .channels = 2, /* 4 */
  1366. .autodma = AUTODMA,
  1367. .bootable = OFF_BOARD,
  1368. .extra = 240
  1369. },{ /* 5 */
  1370. .name = "HPT372N",
  1371. .init_setup = init_setup_hpt372n,
  1372. .init_chipset = init_chipset_hpt366,
  1373. .init_iops = init_iops_hpt366,
  1374. .init_hwif = init_hwif_hpt366,
  1375. .init_dma = init_dma_hpt366,
  1376. .channels = 2, /* 4 */
  1377. .autodma = AUTODMA,
  1378. .bootable = OFF_BOARD,
  1379. .extra = 240
  1380. }
  1381. };
  1382. /**
  1383. * hpt366_init_one - called when an HPT366 is found
  1384. * @dev: the hpt366 device
  1385. * @id: the matching pci id
  1386. *
  1387. * Called when the PCI registration layer (or the IDE initialization)
  1388. * finds a device matching our IDE device tables.
  1389. *
  1390. * NOTE: since we'll have to modify some fields of the ide_pci_device_t
  1391. * structure depending on the chip's revision, we'd better pass a local
  1392. * copy down the call chain...
  1393. */
  1394. static int __devinit hpt366_init_one(struct pci_dev *dev, const struct pci_device_id *id)
  1395. {
  1396. ide_pci_device_t d = hpt366_chipsets[id->driver_data];
  1397. return d.init_setup(dev, &d);
  1398. }
  1399. static struct pci_device_id hpt366_pci_tbl[] = {
  1400. { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT366, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
  1401. { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT372, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
  1402. { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT302, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
  1403. { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
  1404. { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT374, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
  1405. { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT372N, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5},
  1406. { 0, },
  1407. };
  1408. MODULE_DEVICE_TABLE(pci, hpt366_pci_tbl);
  1409. static struct pci_driver driver = {
  1410. .name = "HPT366_IDE",
  1411. .id_table = hpt366_pci_tbl,
  1412. .probe = hpt366_init_one,
  1413. };
  1414. static int __init hpt366_ide_init(void)
  1415. {
  1416. return ide_pci_register_driver(&driver);
  1417. }
  1418. module_init(hpt366_ide_init);
  1419. MODULE_AUTHOR("Andre Hedrick");
  1420. MODULE_DESCRIPTION("PCI driver module for Highpoint HPT366 IDE");
  1421. MODULE_LICENSE("GPL");