mpspec.h 3.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127
  1. #ifndef _AM_X86_MPSPEC_H
  2. #define _AM_X86_MPSPEC_H
  3. #include <linux/init.h>
  4. #include <asm/mpspec_def.h>
  5. #ifdef CONFIG_X86_32
  6. #include <mach_mpspec.h>
  7. extern unsigned int def_to_bigsmp;
  8. extern int apic_version[MAX_APICS];
  9. extern u8 apicid_2_node[];
  10. extern int pic_mode;
  11. #define MAX_APICID 256
  12. #else
  13. #define MAX_MP_BUSSES 256
  14. /* Each PCI slot may be a combo card with its own bus. 4 IRQ pins per slot. */
  15. #define MAX_IRQ_SOURCES (MAX_MP_BUSSES * 4)
  16. #endif
  17. extern void early_find_smp_config(void);
  18. extern void early_get_smp_config(void);
  19. #if defined(CONFIG_MCA) || defined(CONFIG_EISA)
  20. extern int mp_bus_id_to_type[MAX_MP_BUSSES];
  21. #endif
  22. extern DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
  23. extern unsigned int boot_cpu_physical_apicid;
  24. extern int smp_found_config;
  25. extern int mpc_default_type;
  26. extern unsigned long mp_lapic_addr;
  27. extern void find_smp_config(void);
  28. extern void get_smp_config(void);
  29. extern void early_reserve_e820_mpc_new(void);
  30. void __cpuinit generic_processor_info(int apicid, int version);
  31. #ifdef CONFIG_ACPI
  32. extern void mp_register_ioapic(int id, u32 address, u32 gsi_base);
  33. extern void mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger,
  34. u32 gsi);
  35. extern void mp_config_acpi_legacy_irqs(void);
  36. extern int mp_register_gsi(u32 gsi, int edge_level, int active_high_low);
  37. extern void MP_intsrc_info(struct mpc_config_intsrc *m);
  38. #ifdef CONFIG_X86_IO_APIC
  39. extern int mp_config_acpi_gsi(unsigned char number, unsigned int devfn, u8 pin,
  40. u32 gsi, int triggering, int polarity);
  41. #else
  42. static inline int
  43. mp_config_acpi_gsi(unsigned char number, unsigned int devfn, u8 pin,
  44. u32 gsi, int triggering, int polarity)
  45. {
  46. return 0;
  47. }
  48. #endif
  49. #endif /* CONFIG_ACPI */
  50. #define PHYSID_ARRAY_SIZE BITS_TO_LONGS(MAX_APICS)
  51. struct physid_mask {
  52. unsigned long mask[PHYSID_ARRAY_SIZE];
  53. };
  54. typedef struct physid_mask physid_mask_t;
  55. #define physid_set(physid, map) set_bit(physid, (map).mask)
  56. #define physid_clear(physid, map) clear_bit(physid, (map).mask)
  57. #define physid_isset(physid, map) test_bit(physid, (map).mask)
  58. #define physid_test_and_set(physid, map) \
  59. test_and_set_bit(physid, (map).mask)
  60. #define physids_and(dst, src1, src2) \
  61. bitmap_and((dst).mask, (src1).mask, (src2).mask, MAX_APICS)
  62. #define physids_or(dst, src1, src2) \
  63. bitmap_or((dst).mask, (src1).mask, (src2).mask, MAX_APICS)
  64. #define physids_clear(map) \
  65. bitmap_zero((map).mask, MAX_APICS)
  66. #define physids_complement(dst, src) \
  67. bitmap_complement((dst).mask, (src).mask, MAX_APICS)
  68. #define physids_empty(map) \
  69. bitmap_empty((map).mask, MAX_APICS)
  70. #define physids_equal(map1, map2) \
  71. bitmap_equal((map1).mask, (map2).mask, MAX_APICS)
  72. #define physids_weight(map) \
  73. bitmap_weight((map).mask, MAX_APICS)
  74. #define physids_shift_right(d, s, n) \
  75. bitmap_shift_right((d).mask, (s).mask, n, MAX_APICS)
  76. #define physids_shift_left(d, s, n) \
  77. bitmap_shift_left((d).mask, (s).mask, n, MAX_APICS)
  78. #define physids_coerce(map) ((map).mask[0])
  79. #define physids_promote(physids) \
  80. ({ \
  81. physid_mask_t __physid_mask = PHYSID_MASK_NONE; \
  82. __physid_mask.mask[0] = physids; \
  83. __physid_mask; \
  84. })
  85. #define physid_mask_of_physid(physid) \
  86. ({ \
  87. physid_mask_t __physid_mask = PHYSID_MASK_NONE; \
  88. physid_set(physid, __physid_mask); \
  89. __physid_mask; \
  90. })
  91. #define PHYSID_MASK_ALL { {[0 ... PHYSID_ARRAY_SIZE-1] = ~0UL} }
  92. #define PHYSID_MASK_NONE { {[0 ... PHYSID_ARRAY_SIZE-1] = 0UL} }
  93. extern physid_mask_t phys_cpu_present_map;
  94. #endif