au1000_pb1x00.c 9.0 KB

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  1. /*
  2. *
  3. * Alchemy Semi Pb1x00 boards specific pcmcia routines.
  4. *
  5. * Copyright 2002 MontaVista Software Inc.
  6. * Author: MontaVista Software, Inc.
  7. * ppopov@mvista.com or source@mvista.com
  8. *
  9. * ########################################################################
  10. *
  11. * This program is free software; you can distribute it and/or modify it
  12. * under the terms of the GNU General Public License (Version 2) as
  13. * published by the Free Software Foundation.
  14. *
  15. * This program is distributed in the hope it will be useful, but WITHOUT
  16. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  17. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  18. * for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License along
  21. * with this program; if not, write to the Free Software Foundation, Inc.,
  22. * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  23. */
  24. #include <linux/module.h>
  25. #include <linux/init.h>
  26. #include <linux/delay.h>
  27. #include <linux/ioport.h>
  28. #include <linux/kernel.h>
  29. #include <linux/tqueue.h>
  30. #include <linux/timer.h>
  31. #include <linux/mm.h>
  32. #include <linux/proc_fs.h>
  33. #include <linux/types.h>
  34. #include <pcmcia/cs_types.h>
  35. #include <pcmcia/cs.h>
  36. #include <pcmcia/ss.h>
  37. #include <pcmcia/cistpl.h>
  38. #include <pcmcia/bus_ops.h>
  39. #include <asm/io.h>
  40. #include <asm/irq.h>
  41. #include <asm/system.h>
  42. #include <asm/au1000.h>
  43. #include <asm/au1000_pcmcia.h>
  44. #define debug(fmt, arg...) do { } while (0)
  45. #ifdef CONFIG_MIPS_PB1000
  46. #include <asm/pb1000.h>
  47. #define PCMCIA_IRQ AU1000_GPIO_15
  48. #elif defined (CONFIG_MIPS_PB1500)
  49. #include <asm/pb1500.h>
  50. #define PCMCIA_IRQ AU1500_GPIO_203
  51. #elif defined (CONFIG_MIPS_PB1100)
  52. #include <asm/pb1100.h>
  53. #define PCMCIA_IRQ AU1000_GPIO_11
  54. #endif
  55. static int pb1x00_pcmcia_init(struct pcmcia_init *init)
  56. {
  57. #ifdef CONFIG_MIPS_PB1000
  58. u16 pcr;
  59. pcr = PCR_SLOT_0_RST | PCR_SLOT_1_RST;
  60. au_writel(0x8000, PB1000_MDR); /* clear pcmcia interrupt */
  61. au_sync_delay(100);
  62. au_writel(0x4000, PB1000_MDR); /* enable pcmcia interrupt */
  63. au_sync();
  64. pcr |= SET_VCC_VPP(VCC_HIZ,VPP_HIZ,0);
  65. pcr |= SET_VCC_VPP(VCC_HIZ,VPP_HIZ,1);
  66. au_writel(pcr, PB1000_PCR);
  67. au_sync_delay(20);
  68. return PCMCIA_NUM_SOCKS;
  69. #else /* fixme -- take care of the Pb1500 at some point */
  70. u16 pcr;
  71. pcr = au_readw(PCMCIA_BOARD_REG) & ~0xf; /* turn off power */
  72. pcr &= ~(PC_DEASSERT_RST | PC_DRV_EN);
  73. au_writew(pcr, PCMCIA_BOARD_REG);
  74. au_sync_delay(500);
  75. return PCMCIA_NUM_SOCKS;
  76. #endif
  77. }
  78. static int pb1x00_pcmcia_shutdown(void)
  79. {
  80. #ifdef CONFIG_MIPS_PB1000
  81. u16 pcr;
  82. pcr = PCR_SLOT_0_RST | PCR_SLOT_1_RST;
  83. pcr |= SET_VCC_VPP(VCC_HIZ,VPP_HIZ,0);
  84. pcr |= SET_VCC_VPP(VCC_HIZ,VPP_HIZ,1);
  85. au_writel(pcr, PB1000_PCR);
  86. au_sync_delay(20);
  87. return 0;
  88. #else
  89. u16 pcr;
  90. pcr = au_readw(PCMCIA_BOARD_REG) & ~0xf; /* turn off power */
  91. pcr &= ~(PC_DEASSERT_RST | PC_DRV_EN);
  92. au_writew(pcr, PCMCIA_BOARD_REG);
  93. au_sync_delay(2);
  94. return 0;
  95. #endif
  96. }
  97. static int
  98. pb1x00_pcmcia_socket_state(unsigned sock, struct pcmcia_state *state)
  99. {
  100. u32 inserted0, inserted1;
  101. u16 vs0, vs1;
  102. #ifdef CONFIG_MIPS_PB1000
  103. vs0 = vs1 = (u16)au_readl(PB1000_ACR1);
  104. inserted0 = !(vs0 & (ACR1_SLOT_0_CD1 | ACR1_SLOT_0_CD2));
  105. inserted1 = !(vs1 & (ACR1_SLOT_1_CD1 | ACR1_SLOT_1_CD2));
  106. vs0 = (vs0 >> 4) & 0x3;
  107. vs1 = (vs1 >> 12) & 0x3;
  108. #else
  109. vs0 = (au_readw(BOARD_STATUS_REG) >> 4) & 0x3;
  110. #ifdef CONFIG_MIPS_PB1500
  111. inserted0 = !((au_readl(GPIO2_PINSTATE) >> 1) & 0x1); /* gpio 201 */
  112. #else /* Pb1100 */
  113. inserted0 = !((au_readl(SYS_PINSTATERD) >> 9) & 0x1); /* gpio 9 */
  114. #endif
  115. inserted1 = 0;
  116. #endif
  117. state->ready = 0;
  118. state->vs_Xv = 0;
  119. state->vs_3v = 0;
  120. state->detect = 0;
  121. if (sock == 0) {
  122. if (inserted0) {
  123. switch (vs0) {
  124. case 0:
  125. case 2:
  126. state->vs_3v=1;
  127. break;
  128. case 3: /* 5V */
  129. break;
  130. default:
  131. /* return without setting 'detect' */
  132. printk(KERN_ERR "pb1x00 bad VS (%d)\n",
  133. vs0);
  134. return 0;
  135. }
  136. state->detect = 1;
  137. }
  138. }
  139. else {
  140. if (inserted1) {
  141. switch (vs1) {
  142. case 0:
  143. case 2:
  144. state->vs_3v=1;
  145. break;
  146. case 3: /* 5V */
  147. break;
  148. default:
  149. /* return without setting 'detect' */
  150. printk(KERN_ERR "pb1x00 bad VS (%d)\n",
  151. vs1);
  152. return 0;
  153. }
  154. state->detect = 1;
  155. }
  156. }
  157. if (state->detect) {
  158. state->ready = 1;
  159. }
  160. state->bvd1=1;
  161. state->bvd2=1;
  162. state->wrprot=0;
  163. return 1;
  164. }
  165. static int pb1x00_pcmcia_get_irq_info(struct pcmcia_irq_info *info)
  166. {
  167. if(info->sock > PCMCIA_MAX_SOCK) return -1;
  168. /*
  169. * Even in the case of the Pb1000, both sockets are connected
  170. * to the same irq line.
  171. */
  172. info->irq = PCMCIA_IRQ;
  173. return 0;
  174. }
  175. static int
  176. pb1x00_pcmcia_configure_socket(const struct pcmcia_configure *configure)
  177. {
  178. u16 pcr;
  179. if(configure->sock > PCMCIA_MAX_SOCK) return -1;
  180. #ifdef CONFIG_MIPS_PB1000
  181. pcr = au_readl(PB1000_PCR);
  182. if (configure->sock == 0) {
  183. pcr &= ~(PCR_SLOT_0_VCC0 | PCR_SLOT_0_VCC1 |
  184. PCR_SLOT_0_VPP0 | PCR_SLOT_0_VPP1);
  185. }
  186. else {
  187. pcr &= ~(PCR_SLOT_1_VCC0 | PCR_SLOT_1_VCC1 |
  188. PCR_SLOT_1_VPP0 | PCR_SLOT_1_VPP1);
  189. }
  190. pcr &= ~PCR_SLOT_0_RST;
  191. debug("Vcc %dV Vpp %dV, pcr %x\n",
  192. configure->vcc, configure->vpp, pcr);
  193. switch(configure->vcc){
  194. case 0: /* Vcc 0 */
  195. switch(configure->vpp) {
  196. case 0:
  197. pcr |= SET_VCC_VPP(VCC_HIZ,VPP_GND,
  198. configure->sock);
  199. break;
  200. case 12:
  201. pcr |= SET_VCC_VPP(VCC_HIZ,VPP_12V,
  202. configure->sock);
  203. break;
  204. case 50:
  205. pcr |= SET_VCC_VPP(VCC_HIZ,VPP_5V,
  206. configure->sock);
  207. break;
  208. case 33:
  209. pcr |= SET_VCC_VPP(VCC_HIZ,VPP_3V,
  210. configure->sock);
  211. break;
  212. default:
  213. pcr |= SET_VCC_VPP(VCC_HIZ,VPP_HIZ,
  214. configure->sock);
  215. printk("%s: bad Vcc/Vpp (%d:%d)\n",
  216. __func__,
  217. configure->vcc,
  218. configure->vpp);
  219. break;
  220. }
  221. break;
  222. case 50: /* Vcc 5V */
  223. switch(configure->vpp) {
  224. case 0:
  225. pcr |= SET_VCC_VPP(VCC_5V,VPP_GND,
  226. configure->sock);
  227. break;
  228. case 50:
  229. pcr |= SET_VCC_VPP(VCC_5V,VPP_5V,
  230. configure->sock);
  231. break;
  232. case 12:
  233. pcr |= SET_VCC_VPP(VCC_5V,VPP_12V,
  234. configure->sock);
  235. break;
  236. case 33:
  237. pcr |= SET_VCC_VPP(VCC_5V,VPP_3V,
  238. configure->sock);
  239. break;
  240. default:
  241. pcr |= SET_VCC_VPP(VCC_HIZ,VPP_HIZ,
  242. configure->sock);
  243. printk("%s: bad Vcc/Vpp (%d:%d)\n",
  244. __func__,
  245. configure->vcc,
  246. configure->vpp);
  247. break;
  248. }
  249. break;
  250. case 33: /* Vcc 3.3V */
  251. switch(configure->vpp) {
  252. case 0:
  253. pcr |= SET_VCC_VPP(VCC_3V,VPP_GND,
  254. configure->sock);
  255. break;
  256. case 50:
  257. pcr |= SET_VCC_VPP(VCC_3V,VPP_5V,
  258. configure->sock);
  259. break;
  260. case 12:
  261. pcr |= SET_VCC_VPP(VCC_3V,VPP_12V,
  262. configure->sock);
  263. break;
  264. case 33:
  265. pcr |= SET_VCC_VPP(VCC_3V,VPP_3V,
  266. configure->sock);
  267. break;
  268. default:
  269. pcr |= SET_VCC_VPP(VCC_HIZ,VPP_HIZ,
  270. configure->sock);
  271. printk("%s: bad Vcc/Vpp (%d:%d)\n",
  272. __func__,
  273. configure->vcc,
  274. configure->vpp);
  275. break;
  276. }
  277. break;
  278. default: /* what's this ? */
  279. pcr |= SET_VCC_VPP(VCC_HIZ,VPP_HIZ,configure->sock);
  280. printk(KERN_ERR "%s: bad Vcc %d\n",
  281. __func__, configure->vcc);
  282. break;
  283. }
  284. if (configure->sock == 0) {
  285. pcr &= ~(PCR_SLOT_0_RST);
  286. if (configure->reset)
  287. pcr |= PCR_SLOT_0_RST;
  288. }
  289. else {
  290. pcr &= ~(PCR_SLOT_1_RST);
  291. if (configure->reset)
  292. pcr |= PCR_SLOT_1_RST;
  293. }
  294. au_writel(pcr, PB1000_PCR);
  295. au_sync_delay(300);
  296. #else
  297. pcr = au_readw(PCMCIA_BOARD_REG) & ~0xf;
  298. debug("Vcc %dV Vpp %dV, pcr %x, reset %d\n",
  299. configure->vcc, configure->vpp, pcr, configure->reset);
  300. switch(configure->vcc){
  301. case 0: /* Vcc 0 */
  302. pcr |= SET_VCC_VPP(0,0);
  303. break;
  304. case 50: /* Vcc 5V */
  305. switch(configure->vpp) {
  306. case 0:
  307. pcr |= SET_VCC_VPP(2,0);
  308. break;
  309. case 50:
  310. pcr |= SET_VCC_VPP(2,1);
  311. break;
  312. case 12:
  313. pcr |= SET_VCC_VPP(2,2);
  314. break;
  315. case 33:
  316. default:
  317. pcr |= SET_VCC_VPP(0,0);
  318. printk("%s: bad Vcc/Vpp (%d:%d)\n",
  319. __func__,
  320. configure->vcc,
  321. configure->vpp);
  322. break;
  323. }
  324. break;
  325. case 33: /* Vcc 3.3V */
  326. switch(configure->vpp) {
  327. case 0:
  328. pcr |= SET_VCC_VPP(1,0);
  329. break;
  330. case 12:
  331. pcr |= SET_VCC_VPP(1,2);
  332. break;
  333. case 33:
  334. pcr |= SET_VCC_VPP(1,1);
  335. break;
  336. case 50:
  337. default:
  338. pcr |= SET_VCC_VPP(0,0);
  339. printk("%s: bad Vcc/Vpp (%d:%d)\n",
  340. __func__,
  341. configure->vcc,
  342. configure->vpp);
  343. break;
  344. }
  345. break;
  346. default: /* what's this ? */
  347. pcr |= SET_VCC_VPP(0,0);
  348. printk(KERN_ERR "%s: bad Vcc %d\n",
  349. __func__, configure->vcc);
  350. break;
  351. }
  352. au_writew(pcr, PCMCIA_BOARD_REG);
  353. au_sync_delay(300);
  354. if (!configure->reset) {
  355. pcr |= PC_DRV_EN;
  356. au_writew(pcr, PCMCIA_BOARD_REG);
  357. au_sync_delay(100);
  358. pcr |= PC_DEASSERT_RST;
  359. au_writew(pcr, PCMCIA_BOARD_REG);
  360. au_sync_delay(100);
  361. }
  362. else {
  363. pcr &= ~(PC_DEASSERT_RST | PC_DRV_EN);
  364. au_writew(pcr, PCMCIA_BOARD_REG);
  365. au_sync_delay(100);
  366. }
  367. #endif
  368. return 0;
  369. }
  370. struct pcmcia_low_level pb1x00_pcmcia_ops = {
  371. pb1x00_pcmcia_init,
  372. pb1x00_pcmcia_shutdown,
  373. pb1x00_pcmcia_socket_state,
  374. pb1x00_pcmcia_get_irq_info,
  375. pb1x00_pcmcia_configure_socket
  376. };