ps3vram.c 21 KB

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  1. /*
  2. * ps3vram - Use extra PS3 video ram as MTD block device.
  3. *
  4. * Copyright 2009 Sony Corporation
  5. *
  6. * Based on the MTD ps3vram driver, which is
  7. * Copyright (c) 2007-2008 Jim Paris <jim@jtan.com>
  8. * Added support RSX DMA Vivien Chappelier <vivien.chappelier@free.fr>
  9. */
  10. #include <linux/blkdev.h>
  11. #include <linux/delay.h>
  12. #include <linux/proc_fs.h>
  13. #include <linux/seq_file.h>
  14. #include <asm/firmware.h>
  15. #include <asm/lv1call.h>
  16. #include <asm/ps3.h>
  17. #define DEVICE_NAME "ps3vram"
  18. #define XDR_BUF_SIZE (2 * 1024 * 1024) /* XDR buffer (must be 1MiB aligned) */
  19. #define XDR_IOIF 0x0c000000
  20. #define FIFO_BASE XDR_IOIF
  21. #define FIFO_SIZE (64 * 1024)
  22. #define DMA_PAGE_SIZE (4 * 1024)
  23. #define CACHE_PAGE_SIZE (256 * 1024)
  24. #define CACHE_PAGE_COUNT ((XDR_BUF_SIZE - FIFO_SIZE) / CACHE_PAGE_SIZE)
  25. #define CACHE_OFFSET CACHE_PAGE_SIZE
  26. #define FIFO_OFFSET 0
  27. #define CTRL_PUT 0x10
  28. #define CTRL_GET 0x11
  29. #define CTRL_TOP 0x15
  30. #define UPLOAD_SUBCH 1
  31. #define DOWNLOAD_SUBCH 2
  32. #define NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN 0x0000030c
  33. #define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY 0x00000104
  34. #define L1GPU_CONTEXT_ATTRIBUTE_FB_BLIT 0x601
  35. #define CACHE_PAGE_PRESENT 1
  36. #define CACHE_PAGE_DIRTY 2
  37. struct ps3vram_tag {
  38. unsigned int address;
  39. unsigned int flags;
  40. };
  41. struct ps3vram_cache {
  42. unsigned int page_count;
  43. unsigned int page_size;
  44. struct ps3vram_tag *tags;
  45. unsigned int hit;
  46. unsigned int miss;
  47. };
  48. struct ps3vram_priv {
  49. struct request_queue *queue;
  50. struct gendisk *gendisk;
  51. u64 size;
  52. u64 memory_handle;
  53. u64 context_handle;
  54. u32 *ctrl;
  55. u32 *reports;
  56. u8 __iomem *ddr_base;
  57. u8 *xdr_buf;
  58. u32 *fifo_base;
  59. u32 *fifo_ptr;
  60. struct ps3vram_cache cache;
  61. /* Used to serialize cache/DMA operations */
  62. struct mutex lock;
  63. };
  64. static int ps3vram_major;
  65. static struct block_device_operations ps3vram_fops = {
  66. .owner = THIS_MODULE,
  67. };
  68. #define DMA_NOTIFIER_HANDLE_BASE 0x66604200 /* first DMA notifier handle */
  69. #define DMA_NOTIFIER_OFFSET_BASE 0x1000 /* first DMA notifier offset */
  70. #define DMA_NOTIFIER_SIZE 0x40
  71. #define NOTIFIER 7 /* notifier used for completion report */
  72. static char *size = "256M";
  73. module_param(size, charp, 0);
  74. MODULE_PARM_DESC(size, "memory size");
  75. static u32 *ps3vram_get_notifier(u32 *reports, int notifier)
  76. {
  77. return (void *)reports + DMA_NOTIFIER_OFFSET_BASE +
  78. DMA_NOTIFIER_SIZE * notifier;
  79. }
  80. static void ps3vram_notifier_reset(struct ps3_system_bus_device *dev)
  81. {
  82. struct ps3vram_priv *priv = dev->core.driver_data;
  83. u32 *notify = ps3vram_get_notifier(priv->reports, NOTIFIER);
  84. int i;
  85. for (i = 0; i < 4; i++)
  86. notify[i] = 0xffffffff;
  87. }
  88. static int ps3vram_notifier_wait(struct ps3_system_bus_device *dev,
  89. unsigned int timeout_ms)
  90. {
  91. struct ps3vram_priv *priv = dev->core.driver_data;
  92. u32 *notify = ps3vram_get_notifier(priv->reports, NOTIFIER);
  93. unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
  94. do {
  95. if (!notify[3])
  96. return 0;
  97. msleep(1);
  98. } while (time_before(jiffies, timeout));
  99. return -ETIMEDOUT;
  100. }
  101. static void ps3vram_init_ring(struct ps3_system_bus_device *dev)
  102. {
  103. struct ps3vram_priv *priv = dev->core.driver_data;
  104. priv->ctrl[CTRL_PUT] = FIFO_BASE + FIFO_OFFSET;
  105. priv->ctrl[CTRL_GET] = FIFO_BASE + FIFO_OFFSET;
  106. }
  107. static int ps3vram_wait_ring(struct ps3_system_bus_device *dev,
  108. unsigned int timeout_ms)
  109. {
  110. struct ps3vram_priv *priv = dev->core.driver_data;
  111. unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
  112. do {
  113. if (priv->ctrl[CTRL_PUT] == priv->ctrl[CTRL_GET])
  114. return 0;
  115. msleep(1);
  116. } while (time_before(jiffies, timeout));
  117. dev_warn(&dev->core, "FIFO timeout (%08x/%08x/%08x)\n",
  118. priv->ctrl[CTRL_PUT], priv->ctrl[CTRL_GET],
  119. priv->ctrl[CTRL_TOP]);
  120. return -ETIMEDOUT;
  121. }
  122. static void ps3vram_out_ring(struct ps3vram_priv *priv, u32 data)
  123. {
  124. *(priv->fifo_ptr)++ = data;
  125. }
  126. static void ps3vram_begin_ring(struct ps3vram_priv *priv, u32 chan, u32 tag,
  127. u32 size)
  128. {
  129. ps3vram_out_ring(priv, (size << 18) | (chan << 13) | tag);
  130. }
  131. static void ps3vram_rewind_ring(struct ps3_system_bus_device *dev)
  132. {
  133. struct ps3vram_priv *priv = dev->core.driver_data;
  134. int status;
  135. ps3vram_out_ring(priv, 0x20000000 | (FIFO_BASE + FIFO_OFFSET));
  136. priv->ctrl[CTRL_PUT] = FIFO_BASE + FIFO_OFFSET;
  137. /* asking the HV for a blit will kick the FIFO */
  138. status = lv1_gpu_context_attribute(priv->context_handle,
  139. L1GPU_CONTEXT_ATTRIBUTE_FB_BLIT, 0,
  140. 0, 0, 0);
  141. if (status)
  142. dev_err(&dev->core,
  143. "%s: lv1_gpu_context_attribute failed %d\n", __func__,
  144. status);
  145. priv->fifo_ptr = priv->fifo_base;
  146. }
  147. static void ps3vram_fire_ring(struct ps3_system_bus_device *dev)
  148. {
  149. struct ps3vram_priv *priv = dev->core.driver_data;
  150. int status;
  151. mutex_lock(&ps3_gpu_mutex);
  152. priv->ctrl[CTRL_PUT] = FIFO_BASE + FIFO_OFFSET +
  153. (priv->fifo_ptr - priv->fifo_base) * sizeof(u32);
  154. /* asking the HV for a blit will kick the FIFO */
  155. status = lv1_gpu_context_attribute(priv->context_handle,
  156. L1GPU_CONTEXT_ATTRIBUTE_FB_BLIT, 0,
  157. 0, 0, 0);
  158. if (status)
  159. dev_err(&dev->core,
  160. "%s: lv1_gpu_context_attribute failed %d\n", __func__,
  161. status);
  162. if ((priv->fifo_ptr - priv->fifo_base) * sizeof(u32) >
  163. FIFO_SIZE - 1024) {
  164. dev_dbg(&dev->core, "FIFO full, rewinding\n");
  165. ps3vram_wait_ring(dev, 200);
  166. ps3vram_rewind_ring(dev);
  167. }
  168. mutex_unlock(&ps3_gpu_mutex);
  169. }
  170. static void ps3vram_bind(struct ps3_system_bus_device *dev)
  171. {
  172. struct ps3vram_priv *priv = dev->core.driver_data;
  173. ps3vram_begin_ring(priv, UPLOAD_SUBCH, 0, 1);
  174. ps3vram_out_ring(priv, 0x31337303);
  175. ps3vram_begin_ring(priv, UPLOAD_SUBCH, 0x180, 3);
  176. ps3vram_out_ring(priv, DMA_NOTIFIER_HANDLE_BASE + NOTIFIER);
  177. ps3vram_out_ring(priv, 0xfeed0001); /* DMA system RAM instance */
  178. ps3vram_out_ring(priv, 0xfeed0000); /* DMA video RAM instance */
  179. ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, 0, 1);
  180. ps3vram_out_ring(priv, 0x3137c0de);
  181. ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, 0x180, 3);
  182. ps3vram_out_ring(priv, DMA_NOTIFIER_HANDLE_BASE + NOTIFIER);
  183. ps3vram_out_ring(priv, 0xfeed0000); /* DMA video RAM instance */
  184. ps3vram_out_ring(priv, 0xfeed0001); /* DMA system RAM instance */
  185. ps3vram_fire_ring(dev);
  186. }
  187. static int ps3vram_upload(struct ps3_system_bus_device *dev,
  188. unsigned int src_offset, unsigned int dst_offset,
  189. int len, int count)
  190. {
  191. struct ps3vram_priv *priv = dev->core.driver_data;
  192. ps3vram_begin_ring(priv, UPLOAD_SUBCH,
  193. NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
  194. ps3vram_out_ring(priv, XDR_IOIF + src_offset);
  195. ps3vram_out_ring(priv, dst_offset);
  196. ps3vram_out_ring(priv, len);
  197. ps3vram_out_ring(priv, len);
  198. ps3vram_out_ring(priv, len);
  199. ps3vram_out_ring(priv, count);
  200. ps3vram_out_ring(priv, (1 << 8) | 1);
  201. ps3vram_out_ring(priv, 0);
  202. ps3vram_notifier_reset(dev);
  203. ps3vram_begin_ring(priv, UPLOAD_SUBCH,
  204. NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY, 1);
  205. ps3vram_out_ring(priv, 0);
  206. ps3vram_begin_ring(priv, UPLOAD_SUBCH, 0x100, 1);
  207. ps3vram_out_ring(priv, 0);
  208. ps3vram_fire_ring(dev);
  209. if (ps3vram_notifier_wait(dev, 200) < 0) {
  210. dev_warn(&dev->core, "%s: Notifier timeout\n", __func__);
  211. return -1;
  212. }
  213. return 0;
  214. }
  215. static int ps3vram_download(struct ps3_system_bus_device *dev,
  216. unsigned int src_offset, unsigned int dst_offset,
  217. int len, int count)
  218. {
  219. struct ps3vram_priv *priv = dev->core.driver_data;
  220. ps3vram_begin_ring(priv, DOWNLOAD_SUBCH,
  221. NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
  222. ps3vram_out_ring(priv, src_offset);
  223. ps3vram_out_ring(priv, XDR_IOIF + dst_offset);
  224. ps3vram_out_ring(priv, len);
  225. ps3vram_out_ring(priv, len);
  226. ps3vram_out_ring(priv, len);
  227. ps3vram_out_ring(priv, count);
  228. ps3vram_out_ring(priv, (1 << 8) | 1);
  229. ps3vram_out_ring(priv, 0);
  230. ps3vram_notifier_reset(dev);
  231. ps3vram_begin_ring(priv, DOWNLOAD_SUBCH,
  232. NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY, 1);
  233. ps3vram_out_ring(priv, 0);
  234. ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, 0x100, 1);
  235. ps3vram_out_ring(priv, 0);
  236. ps3vram_fire_ring(dev);
  237. if (ps3vram_notifier_wait(dev, 200) < 0) {
  238. dev_warn(&dev->core, "%s: Notifier timeout\n", __func__);
  239. return -1;
  240. }
  241. return 0;
  242. }
  243. static void ps3vram_cache_evict(struct ps3_system_bus_device *dev, int entry)
  244. {
  245. struct ps3vram_priv *priv = dev->core.driver_data;
  246. struct ps3vram_cache *cache = &priv->cache;
  247. if (!(cache->tags[entry].flags & CACHE_PAGE_DIRTY))
  248. return;
  249. dev_dbg(&dev->core, "Flushing %d: 0x%08x\n", entry,
  250. cache->tags[entry].address);
  251. if (ps3vram_upload(dev, CACHE_OFFSET + entry * cache->page_size,
  252. cache->tags[entry].address, DMA_PAGE_SIZE,
  253. cache->page_size / DMA_PAGE_SIZE) < 0) {
  254. dev_err(&dev->core,
  255. "Failed to upload from 0x%x to " "0x%x size 0x%x\n",
  256. entry * cache->page_size, cache->tags[entry].address,
  257. cache->page_size);
  258. }
  259. cache->tags[entry].flags &= ~CACHE_PAGE_DIRTY;
  260. }
  261. static void ps3vram_cache_load(struct ps3_system_bus_device *dev, int entry,
  262. unsigned int address)
  263. {
  264. struct ps3vram_priv *priv = dev->core.driver_data;
  265. struct ps3vram_cache *cache = &priv->cache;
  266. dev_dbg(&dev->core, "Fetching %d: 0x%08x\n", entry, address);
  267. if (ps3vram_download(dev, address,
  268. CACHE_OFFSET + entry * cache->page_size,
  269. DMA_PAGE_SIZE,
  270. cache->page_size / DMA_PAGE_SIZE) < 0) {
  271. dev_err(&dev->core,
  272. "Failed to download from 0x%x to 0x%x size 0x%x\n",
  273. address, entry * cache->page_size, cache->page_size);
  274. }
  275. cache->tags[entry].address = address;
  276. cache->tags[entry].flags |= CACHE_PAGE_PRESENT;
  277. }
  278. static void ps3vram_cache_flush(struct ps3_system_bus_device *dev)
  279. {
  280. struct ps3vram_priv *priv = dev->core.driver_data;
  281. struct ps3vram_cache *cache = &priv->cache;
  282. int i;
  283. dev_dbg(&dev->core, "FLUSH\n");
  284. for (i = 0; i < cache->page_count; i++) {
  285. ps3vram_cache_evict(dev, i);
  286. cache->tags[i].flags = 0;
  287. }
  288. }
  289. static unsigned int ps3vram_cache_match(struct ps3_system_bus_device *dev,
  290. loff_t address)
  291. {
  292. struct ps3vram_priv *priv = dev->core.driver_data;
  293. struct ps3vram_cache *cache = &priv->cache;
  294. unsigned int base;
  295. unsigned int offset;
  296. int i;
  297. static int counter;
  298. offset = (unsigned int) (address & (cache->page_size - 1));
  299. base = (unsigned int) (address - offset);
  300. /* fully associative check */
  301. for (i = 0; i < cache->page_count; i++) {
  302. if ((cache->tags[i].flags & CACHE_PAGE_PRESENT) &&
  303. cache->tags[i].address == base) {
  304. cache->hit++;
  305. dev_dbg(&dev->core, "Found entry %d: 0x%08x\n", i,
  306. cache->tags[i].address);
  307. return i;
  308. }
  309. }
  310. /* choose a random entry */
  311. i = (jiffies + (counter++)) % cache->page_count;
  312. dev_dbg(&dev->core, "Using entry %d\n", i);
  313. ps3vram_cache_evict(dev, i);
  314. ps3vram_cache_load(dev, i, base);
  315. cache->miss++;
  316. return i;
  317. }
  318. static int ps3vram_cache_init(struct ps3_system_bus_device *dev)
  319. {
  320. struct ps3vram_priv *priv = dev->core.driver_data;
  321. priv->cache.page_count = CACHE_PAGE_COUNT;
  322. priv->cache.page_size = CACHE_PAGE_SIZE;
  323. priv->cache.tags = kzalloc(sizeof(struct ps3vram_tag) *
  324. CACHE_PAGE_COUNT, GFP_KERNEL);
  325. if (priv->cache.tags == NULL) {
  326. dev_err(&dev->core, "Could not allocate cache tags\n");
  327. return -ENOMEM;
  328. }
  329. dev_info(&dev->core, "Created ram cache: %d entries, %d KiB each\n",
  330. CACHE_PAGE_COUNT, CACHE_PAGE_SIZE / 1024);
  331. return 0;
  332. }
  333. static void ps3vram_cache_cleanup(struct ps3_system_bus_device *dev)
  334. {
  335. struct ps3vram_priv *priv = dev->core.driver_data;
  336. ps3vram_cache_flush(dev);
  337. kfree(priv->cache.tags);
  338. }
  339. static int ps3vram_read(struct ps3_system_bus_device *dev, loff_t from,
  340. size_t len, size_t *retlen, u_char *buf)
  341. {
  342. struct ps3vram_priv *priv = dev->core.driver_data;
  343. unsigned int cached, count;
  344. dev_dbg(&dev->core, "%s: from=0x%08x len=0x%zx\n", __func__,
  345. (unsigned int)from, len);
  346. if (from >= priv->size)
  347. return -EIO;
  348. if (len > priv->size - from)
  349. len = priv->size - from;
  350. /* Copy from vram to buf */
  351. count = len;
  352. while (count) {
  353. unsigned int offset, avail;
  354. unsigned int entry;
  355. offset = (unsigned int) (from & (priv->cache.page_size - 1));
  356. avail = priv->cache.page_size - offset;
  357. mutex_lock(&priv->lock);
  358. entry = ps3vram_cache_match(dev, from);
  359. cached = CACHE_OFFSET + entry * priv->cache.page_size + offset;
  360. dev_dbg(&dev->core, "%s: from=%08x cached=%08x offset=%08x "
  361. "avail=%08x count=%08x\n", __func__,
  362. (unsigned int)from, cached, offset, avail, count);
  363. if (avail > count)
  364. avail = count;
  365. memcpy(buf, priv->xdr_buf + cached, avail);
  366. mutex_unlock(&priv->lock);
  367. buf += avail;
  368. count -= avail;
  369. from += avail;
  370. }
  371. *retlen = len;
  372. return 0;
  373. }
  374. static int ps3vram_write(struct ps3_system_bus_device *dev, loff_t to,
  375. size_t len, size_t *retlen, const u_char *buf)
  376. {
  377. struct ps3vram_priv *priv = dev->core.driver_data;
  378. unsigned int cached, count;
  379. if (to >= priv->size)
  380. return -EIO;
  381. if (len > priv->size - to)
  382. len = priv->size - to;
  383. /* Copy from buf to vram */
  384. count = len;
  385. while (count) {
  386. unsigned int offset, avail;
  387. unsigned int entry;
  388. offset = (unsigned int) (to & (priv->cache.page_size - 1));
  389. avail = priv->cache.page_size - offset;
  390. mutex_lock(&priv->lock);
  391. entry = ps3vram_cache_match(dev, to);
  392. cached = CACHE_OFFSET + entry * priv->cache.page_size + offset;
  393. dev_dbg(&dev->core, "%s: to=%08x cached=%08x offset=%08x "
  394. "avail=%08x count=%08x\n", __func__, (unsigned int)to,
  395. cached, offset, avail, count);
  396. if (avail > count)
  397. avail = count;
  398. memcpy(priv->xdr_buf + cached, buf, avail);
  399. priv->cache.tags[entry].flags |= CACHE_PAGE_DIRTY;
  400. mutex_unlock(&priv->lock);
  401. buf += avail;
  402. count -= avail;
  403. to += avail;
  404. }
  405. *retlen = len;
  406. return 0;
  407. }
  408. static int ps3vram_proc_show(struct seq_file *m, void *v)
  409. {
  410. struct ps3vram_priv *priv = m->private;
  411. seq_printf(m, "hit:%u\nmiss:%u\n", priv->cache.hit, priv->cache.miss);
  412. return 0;
  413. }
  414. static int ps3vram_proc_open(struct inode *inode, struct file *file)
  415. {
  416. return single_open(file, ps3vram_proc_show, PDE(inode)->data);
  417. }
  418. static const struct file_operations ps3vram_proc_fops = {
  419. .owner = THIS_MODULE,
  420. .open = ps3vram_proc_open,
  421. .read = seq_read,
  422. .llseek = seq_lseek,
  423. .release = single_release,
  424. };
  425. static void __devinit ps3vram_proc_init(struct ps3_system_bus_device *dev)
  426. {
  427. struct ps3vram_priv *priv = dev->core.driver_data;
  428. struct proc_dir_entry *pde;
  429. pde = proc_create(DEVICE_NAME, 0444, NULL, &ps3vram_proc_fops);
  430. if (!pde) {
  431. dev_warn(&dev->core, "failed to create /proc entry\n");
  432. return;
  433. }
  434. pde->data = priv;
  435. }
  436. static int ps3vram_make_request(struct request_queue *q, struct bio *bio)
  437. {
  438. struct ps3_system_bus_device *dev = q->queuedata;
  439. int write = bio_data_dir(bio) == WRITE;
  440. const char *op = write ? "write" : "read";
  441. loff_t offset = bio->bi_sector << 9;
  442. int error = 0;
  443. struct bio_vec *bvec;
  444. unsigned int i;
  445. dev_dbg(&dev->core, "%s\n", __func__);
  446. bio_for_each_segment(bvec, bio, i) {
  447. /* PS3 is ppc64, so we don't handle highmem */
  448. char *ptr = page_address(bvec->bv_page) + bvec->bv_offset;
  449. size_t len = bvec->bv_len, retlen;
  450. dev_dbg(&dev->core, " %s %zu bytes at offset %llu\n", op,
  451. len, offset);
  452. if (write)
  453. error = ps3vram_write(dev, offset, len, &retlen, ptr);
  454. else
  455. error = ps3vram_read(dev, offset, len, &retlen, ptr);
  456. if (error) {
  457. dev_err(&dev->core, "%s failed\n", op);
  458. goto out;
  459. }
  460. if (retlen != len) {
  461. dev_err(&dev->core, "Short %s\n", op);
  462. goto out;
  463. }
  464. offset += len;
  465. }
  466. dev_dbg(&dev->core, "%s completed\n", op);
  467. out:
  468. bio_endio(bio, error);
  469. return 0;
  470. }
  471. static int __devinit ps3vram_probe(struct ps3_system_bus_device *dev)
  472. {
  473. struct ps3vram_priv *priv;
  474. int error, status;
  475. struct request_queue *queue;
  476. struct gendisk *gendisk;
  477. u64 ddr_lpar, ctrl_lpar, info_lpar, reports_lpar, ddr_size,
  478. reports_size;
  479. char *rest;
  480. priv = kzalloc(sizeof(*priv), GFP_KERNEL);
  481. if (!priv) {
  482. error = -ENOMEM;
  483. goto fail;
  484. }
  485. mutex_init(&priv->lock);
  486. dev->core.driver_data = priv;
  487. priv = dev->core.driver_data;
  488. /* Allocate XDR buffer (1MiB aligned) */
  489. priv->xdr_buf = (void *)__get_free_pages(GFP_KERNEL,
  490. get_order(XDR_BUF_SIZE));
  491. if (priv->xdr_buf == NULL) {
  492. dev_err(&dev->core, "Could not allocate XDR buffer\n");
  493. error = -ENOMEM;
  494. goto fail_free_priv;
  495. }
  496. /* Put FIFO at begginning of XDR buffer */
  497. priv->fifo_base = (u32 *) (priv->xdr_buf + FIFO_OFFSET);
  498. priv->fifo_ptr = priv->fifo_base;
  499. /* XXX: Need to open GPU, in case ps3fb or snd_ps3 aren't loaded */
  500. if (ps3_open_hv_device(dev)) {
  501. dev_err(&dev->core, "ps3_open_hv_device failed\n");
  502. error = -EAGAIN;
  503. goto out_close_gpu;
  504. }
  505. /* Request memory */
  506. status = -1;
  507. ddr_size = ALIGN(memparse(size, &rest), 1024*1024);
  508. if (!ddr_size) {
  509. dev_err(&dev->core, "Specified size is too small\n");
  510. error = -EINVAL;
  511. goto out_close_gpu;
  512. }
  513. while (ddr_size > 0) {
  514. status = lv1_gpu_memory_allocate(ddr_size, 0, 0, 0, 0,
  515. &priv->memory_handle,
  516. &ddr_lpar);
  517. if (!status)
  518. break;
  519. ddr_size -= 1024*1024;
  520. }
  521. if (status) {
  522. dev_err(&dev->core, "lv1_gpu_memory_allocate failed %d\n",
  523. status);
  524. error = -ENOMEM;
  525. goto out_free_xdr_buf;
  526. }
  527. /* Request context */
  528. status = lv1_gpu_context_allocate(priv->memory_handle, 0,
  529. &priv->context_handle, &ctrl_lpar,
  530. &info_lpar, &reports_lpar,
  531. &reports_size);
  532. if (status) {
  533. dev_err(&dev->core, "lv1_gpu_context_allocate failed %d\n",
  534. status);
  535. error = -ENOMEM;
  536. goto out_free_memory;
  537. }
  538. /* Map XDR buffer to RSX */
  539. status = lv1_gpu_context_iomap(priv->context_handle, XDR_IOIF,
  540. ps3_mm_phys_to_lpar(__pa(priv->xdr_buf)),
  541. XDR_BUF_SIZE, 0);
  542. if (status) {
  543. dev_err(&dev->core, "lv1_gpu_context_iomap failed %d\n",
  544. status);
  545. error = -ENOMEM;
  546. goto out_free_context;
  547. }
  548. priv->ddr_base = ioremap_flags(ddr_lpar, ddr_size, _PAGE_NO_CACHE);
  549. if (!priv->ddr_base) {
  550. dev_err(&dev->core, "ioremap DDR failed\n");
  551. error = -ENOMEM;
  552. goto out_free_context;
  553. }
  554. priv->ctrl = ioremap(ctrl_lpar, 64 * 1024);
  555. if (!priv->ctrl) {
  556. dev_err(&dev->core, "ioremap CTRL failed\n");
  557. error = -ENOMEM;
  558. goto out_unmap_vram;
  559. }
  560. priv->reports = ioremap(reports_lpar, reports_size);
  561. if (!priv->reports) {
  562. dev_err(&dev->core, "ioremap REPORTS failed\n");
  563. error = -ENOMEM;
  564. goto out_unmap_ctrl;
  565. }
  566. mutex_lock(&ps3_gpu_mutex);
  567. ps3vram_init_ring(dev);
  568. mutex_unlock(&ps3_gpu_mutex);
  569. priv->size = ddr_size;
  570. ps3vram_bind(dev);
  571. mutex_lock(&ps3_gpu_mutex);
  572. error = ps3vram_wait_ring(dev, 100);
  573. mutex_unlock(&ps3_gpu_mutex);
  574. if (error < 0) {
  575. dev_err(&dev->core, "Failed to initialize channels\n");
  576. error = -ETIMEDOUT;
  577. goto out_unmap_reports;
  578. }
  579. ps3vram_cache_init(dev);
  580. ps3vram_proc_init(dev);
  581. queue = blk_alloc_queue(GFP_KERNEL);
  582. if (!queue) {
  583. dev_err(&dev->core, "blk_alloc_queue failed\n");
  584. error = -ENOMEM;
  585. goto out_cache_cleanup;
  586. }
  587. priv->queue = queue;
  588. queue->queuedata = dev;
  589. blk_queue_make_request(queue, ps3vram_make_request);
  590. blk_queue_max_phys_segments(queue, MAX_PHYS_SEGMENTS);
  591. blk_queue_max_hw_segments(queue, MAX_HW_SEGMENTS);
  592. blk_queue_max_segment_size(queue, MAX_SEGMENT_SIZE);
  593. blk_queue_max_sectors(queue, SAFE_MAX_SECTORS);
  594. gendisk = alloc_disk(1);
  595. if (!gendisk) {
  596. dev_err(&dev->core, "alloc_disk failed\n");
  597. error = -ENOMEM;
  598. goto fail_cleanup_queue;
  599. }
  600. priv->gendisk = gendisk;
  601. gendisk->major = ps3vram_major;
  602. gendisk->first_minor = 0;
  603. gendisk->fops = &ps3vram_fops;
  604. gendisk->queue = queue;
  605. gendisk->private_data = dev;
  606. gendisk->driverfs_dev = &dev->core;
  607. strlcpy(gendisk->disk_name, DEVICE_NAME, sizeof(gendisk->disk_name));
  608. set_capacity(gendisk, priv->size >> 9);
  609. dev_info(&dev->core, "%s: Using %lu MiB of GPU memory\n",
  610. gendisk->disk_name, get_capacity(gendisk) >> 11);
  611. add_disk(gendisk);
  612. return 0;
  613. fail_cleanup_queue:
  614. blk_cleanup_queue(queue);
  615. out_cache_cleanup:
  616. remove_proc_entry(DEVICE_NAME, NULL);
  617. ps3vram_cache_cleanup(dev);
  618. out_unmap_reports:
  619. iounmap(priv->reports);
  620. out_unmap_ctrl:
  621. iounmap(priv->ctrl);
  622. out_unmap_vram:
  623. iounmap(priv->ddr_base);
  624. out_free_context:
  625. lv1_gpu_context_free(priv->context_handle);
  626. out_free_memory:
  627. lv1_gpu_memory_free(priv->memory_handle);
  628. out_close_gpu:
  629. ps3_close_hv_device(dev);
  630. out_free_xdr_buf:
  631. free_pages((unsigned long) priv->xdr_buf, get_order(XDR_BUF_SIZE));
  632. fail_free_priv:
  633. kfree(priv);
  634. dev->core.driver_data = NULL;
  635. fail:
  636. return error;
  637. }
  638. static int ps3vram_remove(struct ps3_system_bus_device *dev)
  639. {
  640. struct ps3vram_priv *priv = dev->core.driver_data;
  641. del_gendisk(priv->gendisk);
  642. put_disk(priv->gendisk);
  643. blk_cleanup_queue(priv->queue);
  644. remove_proc_entry(DEVICE_NAME, NULL);
  645. ps3vram_cache_cleanup(dev);
  646. iounmap(priv->reports);
  647. iounmap(priv->ctrl);
  648. iounmap(priv->ddr_base);
  649. lv1_gpu_context_free(priv->context_handle);
  650. lv1_gpu_memory_free(priv->memory_handle);
  651. ps3_close_hv_device(dev);
  652. free_pages((unsigned long) priv->xdr_buf, get_order(XDR_BUF_SIZE));
  653. kfree(priv);
  654. dev->core.driver_data = NULL;
  655. return 0;
  656. }
  657. static struct ps3_system_bus_driver ps3vram = {
  658. .match_id = PS3_MATCH_ID_GPU,
  659. .match_sub_id = PS3_MATCH_SUB_ID_GPU_RAMDISK,
  660. .core.name = DEVICE_NAME,
  661. .core.owner = THIS_MODULE,
  662. .probe = ps3vram_probe,
  663. .remove = ps3vram_remove,
  664. .shutdown = ps3vram_remove,
  665. };
  666. static int __init ps3vram_init(void)
  667. {
  668. int error;
  669. if (!firmware_has_feature(FW_FEATURE_PS3_LV1))
  670. return -ENODEV;
  671. error = register_blkdev(0, DEVICE_NAME);
  672. if (error <= 0) {
  673. pr_err("%s: register_blkdev failed %d\n", DEVICE_NAME, error);
  674. return error;
  675. }
  676. ps3vram_major = error;
  677. pr_info("%s: registered block device major %d\n", DEVICE_NAME,
  678. ps3vram_major);
  679. error = ps3_system_bus_driver_register(&ps3vram);
  680. if (error)
  681. unregister_blkdev(ps3vram_major, DEVICE_NAME);
  682. return error;
  683. }
  684. static void __exit ps3vram_exit(void)
  685. {
  686. ps3_system_bus_driver_unregister(&ps3vram);
  687. unregister_blkdev(ps3vram_major, DEVICE_NAME);
  688. }
  689. module_init(ps3vram_init);
  690. module_exit(ps3vram_exit);
  691. MODULE_LICENSE("GPL");
  692. MODULE_DESCRIPTION("PS3 Video RAM Storage Driver");
  693. MODULE_AUTHOR("Sony Corporation");
  694. MODULE_ALIAS(PS3_MODULE_ALIAS_GPU_RAMDISK);