sata_mv.c 114 KB

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  1. /*
  2. * sata_mv.c - Marvell SATA support
  3. *
  4. * Copyright 2008-2009: Marvell Corporation, all rights reserved.
  5. * Copyright 2005: EMC Corporation, all rights reserved.
  6. * Copyright 2005 Red Hat, Inc. All rights reserved.
  7. *
  8. * Originally written by Brett Russ.
  9. * Extensive overhaul and enhancement by Mark Lord <mlord@pobox.com>.
  10. *
  11. * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
  12. *
  13. * This program is free software; you can redistribute it and/or modify
  14. * it under the terms of the GNU General Public License as published by
  15. * the Free Software Foundation; version 2 of the License.
  16. *
  17. * This program is distributed in the hope that it will be useful,
  18. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20. * GNU General Public License for more details.
  21. *
  22. * You should have received a copy of the GNU General Public License
  23. * along with this program; if not, write to the Free Software
  24. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  25. *
  26. */
  27. /*
  28. * sata_mv TODO list:
  29. *
  30. * --> Develop a low-power-consumption strategy, and implement it.
  31. *
  32. * --> Add sysfs attributes for per-chip / per-HC IRQ coalescing thresholds.
  33. *
  34. * --> [Experiment, Marvell value added] Is it possible to use target
  35. * mode to cross-connect two Linux boxes with Marvell cards? If so,
  36. * creating LibATA target mode support would be very interesting.
  37. *
  38. * Target mode, for those without docs, is the ability to directly
  39. * connect two SATA ports.
  40. */
  41. /*
  42. * 80x1-B2 errata PCI#11:
  43. *
  44. * Users of the 6041/6081 Rev.B2 chips (current is C0)
  45. * should be careful to insert those cards only onto PCI-X bus #0,
  46. * and only in device slots 0..7, not higher. The chips may not
  47. * work correctly otherwise (note: this is a pretty rare condition).
  48. */
  49. #include <linux/kernel.h>
  50. #include <linux/module.h>
  51. #include <linux/pci.h>
  52. #include <linux/init.h>
  53. #include <linux/blkdev.h>
  54. #include <linux/delay.h>
  55. #include <linux/interrupt.h>
  56. #include <linux/dmapool.h>
  57. #include <linux/dma-mapping.h>
  58. #include <linux/device.h>
  59. #include <linux/platform_device.h>
  60. #include <linux/ata_platform.h>
  61. #include <linux/mbus.h>
  62. #include <linux/bitops.h>
  63. #include <scsi/scsi_host.h>
  64. #include <scsi/scsi_cmnd.h>
  65. #include <scsi/scsi_device.h>
  66. #include <linux/libata.h>
  67. #define DRV_NAME "sata_mv"
  68. #define DRV_VERSION "1.28"
  69. /*
  70. * module options
  71. */
  72. static int msi;
  73. #ifdef CONFIG_PCI
  74. module_param(msi, int, S_IRUGO);
  75. MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)");
  76. #endif
  77. static int irq_coalescing_io_count;
  78. module_param(irq_coalescing_io_count, int, S_IRUGO);
  79. MODULE_PARM_DESC(irq_coalescing_io_count,
  80. "IRQ coalescing I/O count threshold (0..255)");
  81. static int irq_coalescing_usecs;
  82. module_param(irq_coalescing_usecs, int, S_IRUGO);
  83. MODULE_PARM_DESC(irq_coalescing_usecs,
  84. "IRQ coalescing time threshold in usecs");
  85. enum {
  86. /* BAR's are enumerated in terms of pci_resource_start() terms */
  87. MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
  88. MV_IO_BAR = 2, /* offset 0x18: IO space */
  89. MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
  90. MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */
  91. MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
  92. /* For use with both IRQ coalescing methods ("all ports" or "per-HC" */
  93. COAL_CLOCKS_PER_USEC = 150, /* for calculating COAL_TIMEs */
  94. MAX_COAL_TIME_THRESHOLD = ((1 << 24) - 1), /* internal clocks count */
  95. MAX_COAL_IO_COUNT = 255, /* completed I/O count */
  96. MV_PCI_REG_BASE = 0,
  97. /*
  98. * Per-chip ("all ports") interrupt coalescing feature.
  99. * This is only for GEN_II / GEN_IIE hardware.
  100. *
  101. * Coalescing defers the interrupt until either the IO_THRESHOLD
  102. * (count of completed I/Os) is met, or the TIME_THRESHOLD is met.
  103. */
  104. COAL_REG_BASE = 0x18000,
  105. IRQ_COAL_CAUSE = (COAL_REG_BASE + 0x08),
  106. ALL_PORTS_COAL_IRQ = (1 << 4), /* all ports irq event */
  107. IRQ_COAL_IO_THRESHOLD = (COAL_REG_BASE + 0xcc),
  108. IRQ_COAL_TIME_THRESHOLD = (COAL_REG_BASE + 0xd0),
  109. /*
  110. * Registers for the (unused here) transaction coalescing feature:
  111. */
  112. TRAN_COAL_CAUSE_LO = (COAL_REG_BASE + 0x88),
  113. TRAN_COAL_CAUSE_HI = (COAL_REG_BASE + 0x8c),
  114. SATAHC0_REG_BASE = 0x20000,
  115. FLASH_CTL = 0x1046c,
  116. GPIO_PORT_CTL = 0x104f0,
  117. RESET_CFG = 0x180d8,
  118. MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
  119. MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
  120. MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */
  121. MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,
  122. MV_MAX_Q_DEPTH = 32,
  123. MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
  124. /* CRQB needs alignment on a 1KB boundary. Size == 1KB
  125. * CRPB needs alignment on a 256B boundary. Size == 256B
  126. * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
  127. */
  128. MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),
  129. MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),
  130. MV_MAX_SG_CT = 256,
  131. MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
  132. /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */
  133. MV_PORT_HC_SHIFT = 2,
  134. MV_PORTS_PER_HC = (1 << MV_PORT_HC_SHIFT), /* 4 */
  135. /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */
  136. MV_PORT_MASK = (MV_PORTS_PER_HC - 1), /* 3 */
  137. /* Host Flags */
  138. MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
  139. MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
  140. ATA_FLAG_MMIO | ATA_FLAG_PIO_POLLING,
  141. MV_GEN_I_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NO_ATAPI,
  142. MV_GEN_II_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NCQ |
  143. ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA,
  144. MV_GEN_IIE_FLAGS = MV_GEN_II_FLAGS | ATA_FLAG_AN,
  145. CRQB_FLAG_READ = (1 << 0),
  146. CRQB_TAG_SHIFT = 1,
  147. CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */
  148. CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */
  149. CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */
  150. CRQB_CMD_ADDR_SHIFT = 8,
  151. CRQB_CMD_CS = (0x2 << 11),
  152. CRQB_CMD_LAST = (1 << 15),
  153. CRPB_FLAG_STATUS_SHIFT = 8,
  154. CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */
  155. CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */
  156. EPRD_FLAG_END_OF_TBL = (1 << 31),
  157. /* PCI interface registers */
  158. MV_PCI_COMMAND = 0xc00,
  159. MV_PCI_COMMAND_MWRCOM = (1 << 4), /* PCI Master Write Combining */
  160. MV_PCI_COMMAND_MRDTRIG = (1 << 7), /* PCI Master Read Trigger */
  161. PCI_MAIN_CMD_STS = 0xd30,
  162. STOP_PCI_MASTER = (1 << 2),
  163. PCI_MASTER_EMPTY = (1 << 3),
  164. GLOB_SFT_RST = (1 << 4),
  165. MV_PCI_MODE = 0xd00,
  166. MV_PCI_MODE_MASK = 0x30,
  167. MV_PCI_EXP_ROM_BAR_CTL = 0xd2c,
  168. MV_PCI_DISC_TIMER = 0xd04,
  169. MV_PCI_MSI_TRIGGER = 0xc38,
  170. MV_PCI_SERR_MASK = 0xc28,
  171. MV_PCI_XBAR_TMOUT = 0x1d04,
  172. MV_PCI_ERR_LOW_ADDRESS = 0x1d40,
  173. MV_PCI_ERR_HIGH_ADDRESS = 0x1d44,
  174. MV_PCI_ERR_ATTRIBUTE = 0x1d48,
  175. MV_PCI_ERR_COMMAND = 0x1d50,
  176. PCI_IRQ_CAUSE = 0x1d58,
  177. PCI_IRQ_MASK = 0x1d5c,
  178. PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
  179. PCIE_IRQ_CAUSE = 0x1900,
  180. PCIE_IRQ_MASK = 0x1910,
  181. PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */
  182. /* Host Controller Main Interrupt Cause/Mask registers (1 per-chip) */
  183. PCI_HC_MAIN_IRQ_CAUSE = 0x1d60,
  184. PCI_HC_MAIN_IRQ_MASK = 0x1d64,
  185. SOC_HC_MAIN_IRQ_CAUSE = 0x20020,
  186. SOC_HC_MAIN_IRQ_MASK = 0x20024,
  187. ERR_IRQ = (1 << 0), /* shift by (2 * port #) */
  188. DONE_IRQ = (1 << 1), /* shift by (2 * port #) */
  189. HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
  190. HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
  191. DONE_IRQ_0_3 = 0x000000aa, /* DONE_IRQ ports 0,1,2,3 */
  192. DONE_IRQ_4_7 = (DONE_IRQ_0_3 << HC_SHIFT), /* 4,5,6,7 */
  193. PCI_ERR = (1 << 18),
  194. TRAN_COAL_LO_DONE = (1 << 19), /* transaction coalescing */
  195. TRAN_COAL_HI_DONE = (1 << 20), /* transaction coalescing */
  196. PORTS_0_3_COAL_DONE = (1 << 8), /* HC0 IRQ coalescing */
  197. PORTS_4_7_COAL_DONE = (1 << 17), /* HC1 IRQ coalescing */
  198. ALL_PORTS_COAL_DONE = (1 << 21), /* GEN_II(E) IRQ coalescing */
  199. GPIO_INT = (1 << 22),
  200. SELF_INT = (1 << 23),
  201. TWSI_INT = (1 << 24),
  202. HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
  203. HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */
  204. HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */
  205. /* SATAHC registers */
  206. HC_CFG = 0x00,
  207. HC_IRQ_CAUSE = 0x14,
  208. DMA_IRQ = (1 << 0), /* shift by port # */
  209. HC_COAL_IRQ = (1 << 4), /* IRQ coalescing */
  210. DEV_IRQ = (1 << 8), /* shift by port # */
  211. /*
  212. * Per-HC (Host-Controller) interrupt coalescing feature.
  213. * This is present on all chip generations.
  214. *
  215. * Coalescing defers the interrupt until either the IO_THRESHOLD
  216. * (count of completed I/Os) is met, or the TIME_THRESHOLD is met.
  217. */
  218. HC_IRQ_COAL_IO_THRESHOLD = 0x000c,
  219. HC_IRQ_COAL_TIME_THRESHOLD = 0x0010,
  220. SOC_LED_CTRL = 0x2c,
  221. SOC_LED_CTRL_BLINK = (1 << 0), /* Active LED blink */
  222. SOC_LED_CTRL_ACT_PRESENCE = (1 << 2), /* Multiplex dev presence */
  223. /* with dev activity LED */
  224. /* Shadow block registers */
  225. SHD_BLK = 0x100,
  226. SHD_CTL_AST = 0x20, /* ofs from SHD_BLK */
  227. /* SATA registers */
  228. SATA_STATUS = 0x300, /* ctrl, err regs follow status */
  229. SATA_ACTIVE = 0x350,
  230. FIS_IRQ_CAUSE = 0x364,
  231. FIS_IRQ_CAUSE_AN = (1 << 9), /* async notification */
  232. LTMODE = 0x30c, /* requires read-after-write */
  233. LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */
  234. PHY_MODE2 = 0x330,
  235. PHY_MODE3 = 0x310,
  236. PHY_MODE4 = 0x314, /* requires read-after-write */
  237. PHY_MODE4_CFG_MASK = 0x00000003, /* phy internal config field */
  238. PHY_MODE4_CFG_VALUE = 0x00000001, /* phy internal config field */
  239. PHY_MODE4_RSVD_ZEROS = 0x5de3fffa, /* Gen2e always write zeros */
  240. PHY_MODE4_RSVD_ONES = 0x00000005, /* Gen2e always write ones */
  241. SATA_IFCTL = 0x344,
  242. SATA_TESTCTL = 0x348,
  243. SATA_IFSTAT = 0x34c,
  244. VENDOR_UNIQUE_FIS = 0x35c,
  245. FISCFG = 0x360,
  246. FISCFG_WAIT_DEV_ERR = (1 << 8), /* wait for host on DevErr */
  247. FISCFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */
  248. MV5_PHY_MODE = 0x74,
  249. MV5_LTMODE = 0x30,
  250. MV5_PHY_CTL = 0x0C,
  251. SATA_IFCFG = 0x050,
  252. MV_M2_PREAMP_MASK = 0x7e0,
  253. /* Port registers */
  254. EDMA_CFG = 0,
  255. EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */
  256. EDMA_CFG_NCQ = (1 << 5), /* for R/W FPDMA queued */
  257. EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */
  258. EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
  259. EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */
  260. EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */
  261. EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */
  262. EDMA_ERR_IRQ_CAUSE = 0x8,
  263. EDMA_ERR_IRQ_MASK = 0xc,
  264. EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */
  265. EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */
  266. EDMA_ERR_DEV = (1 << 2), /* device error */
  267. EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */
  268. EDMA_ERR_DEV_CON = (1 << 4), /* device connected */
  269. EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */
  270. EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */
  271. EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */
  272. EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */
  273. EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */
  274. EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */
  275. EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */
  276. EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */
  277. EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */
  278. EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */
  279. EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */
  280. EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */
  281. EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */
  282. EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */
  283. EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */
  284. EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */
  285. EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */
  286. EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */
  287. EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */
  288. EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */
  289. EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */
  290. EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */
  291. EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */
  292. EDMA_ERR_OVERRUN_5 = (1 << 5),
  293. EDMA_ERR_UNDERRUN_5 = (1 << 6),
  294. EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 |
  295. EDMA_ERR_LNK_CTRL_RX_1 |
  296. EDMA_ERR_LNK_CTRL_RX_3 |
  297. EDMA_ERR_LNK_CTRL_TX,
  298. EDMA_EH_FREEZE = EDMA_ERR_D_PAR |
  299. EDMA_ERR_PRD_PAR |
  300. EDMA_ERR_DEV_DCON |
  301. EDMA_ERR_DEV_CON |
  302. EDMA_ERR_SERR |
  303. EDMA_ERR_SELF_DIS |
  304. EDMA_ERR_CRQB_PAR |
  305. EDMA_ERR_CRPB_PAR |
  306. EDMA_ERR_INTRL_PAR |
  307. EDMA_ERR_IORDY |
  308. EDMA_ERR_LNK_CTRL_RX_2 |
  309. EDMA_ERR_LNK_DATA_RX |
  310. EDMA_ERR_LNK_DATA_TX |
  311. EDMA_ERR_TRANS_PROTO,
  312. EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR |
  313. EDMA_ERR_PRD_PAR |
  314. EDMA_ERR_DEV_DCON |
  315. EDMA_ERR_DEV_CON |
  316. EDMA_ERR_OVERRUN_5 |
  317. EDMA_ERR_UNDERRUN_5 |
  318. EDMA_ERR_SELF_DIS_5 |
  319. EDMA_ERR_CRQB_PAR |
  320. EDMA_ERR_CRPB_PAR |
  321. EDMA_ERR_INTRL_PAR |
  322. EDMA_ERR_IORDY,
  323. EDMA_REQ_Q_BASE_HI = 0x10,
  324. EDMA_REQ_Q_IN_PTR = 0x14, /* also contains BASE_LO */
  325. EDMA_REQ_Q_OUT_PTR = 0x18,
  326. EDMA_REQ_Q_PTR_SHIFT = 5,
  327. EDMA_RSP_Q_BASE_HI = 0x1c,
  328. EDMA_RSP_Q_IN_PTR = 0x20,
  329. EDMA_RSP_Q_OUT_PTR = 0x24, /* also contains BASE_LO */
  330. EDMA_RSP_Q_PTR_SHIFT = 3,
  331. EDMA_CMD = 0x28, /* EDMA command register */
  332. EDMA_EN = (1 << 0), /* enable EDMA */
  333. EDMA_DS = (1 << 1), /* disable EDMA; self-negated */
  334. EDMA_RESET = (1 << 2), /* reset eng/trans/link/phy */
  335. EDMA_STATUS = 0x30, /* EDMA engine status */
  336. EDMA_STATUS_CACHE_EMPTY = (1 << 6), /* GenIIe command cache empty */
  337. EDMA_STATUS_IDLE = (1 << 7), /* GenIIe EDMA enabled/idle */
  338. EDMA_IORDY_TMOUT = 0x34,
  339. EDMA_ARB_CFG = 0x38,
  340. EDMA_HALTCOND = 0x60, /* GenIIe halt conditions */
  341. EDMA_UNKNOWN_RSVD = 0x6C, /* GenIIe unknown/reserved */
  342. BMDMA_CMD = 0x224, /* bmdma command register */
  343. BMDMA_STATUS = 0x228, /* bmdma status register */
  344. BMDMA_PRD_LOW = 0x22c, /* bmdma PRD addr 31:0 */
  345. BMDMA_PRD_HIGH = 0x230, /* bmdma PRD addr 63:32 */
  346. /* Host private flags (hp_flags) */
  347. MV_HP_FLAG_MSI = (1 << 0),
  348. MV_HP_ERRATA_50XXB0 = (1 << 1),
  349. MV_HP_ERRATA_50XXB2 = (1 << 2),
  350. MV_HP_ERRATA_60X1B2 = (1 << 3),
  351. MV_HP_ERRATA_60X1C0 = (1 << 4),
  352. MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */
  353. MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */
  354. MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */
  355. MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */
  356. MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */
  357. MV_HP_FLAG_SOC = (1 << 11), /* SystemOnChip, no PCI */
  358. MV_HP_QUIRK_LED_BLINK_EN = (1 << 12), /* is led blinking enabled? */
  359. /* Port private flags (pp_flags) */
  360. MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */
  361. MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */
  362. MV_PP_FLAG_FBS_EN = (1 << 2), /* is EDMA set up for FBS? */
  363. MV_PP_FLAG_DELAYED_EH = (1 << 3), /* delayed dev err handling */
  364. MV_PP_FLAG_FAKE_ATA_BUSY = (1 << 4), /* ignore initial ATA_DRDY */
  365. };
  366. #define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I)
  367. #define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II)
  368. #define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
  369. #define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE)
  370. #define IS_SOC(hpriv) ((hpriv)->hp_flags & MV_HP_FLAG_SOC)
  371. #define WINDOW_CTRL(i) (0x20030 + ((i) << 4))
  372. #define WINDOW_BASE(i) (0x20034 + ((i) << 4))
  373. enum {
  374. /* DMA boundary 0xffff is required by the s/g splitting
  375. * we need on /length/ in mv_fill-sg().
  376. */
  377. MV_DMA_BOUNDARY = 0xffffU,
  378. /* mask of register bits containing lower 32 bits
  379. * of EDMA request queue DMA address
  380. */
  381. EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
  382. /* ditto, for response queue */
  383. EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
  384. };
  385. enum chip_type {
  386. chip_504x,
  387. chip_508x,
  388. chip_5080,
  389. chip_604x,
  390. chip_608x,
  391. chip_6042,
  392. chip_7042,
  393. chip_soc,
  394. };
  395. /* Command ReQuest Block: 32B */
  396. struct mv_crqb {
  397. __le32 sg_addr;
  398. __le32 sg_addr_hi;
  399. __le16 ctrl_flags;
  400. __le16 ata_cmd[11];
  401. };
  402. struct mv_crqb_iie {
  403. __le32 addr;
  404. __le32 addr_hi;
  405. __le32 flags;
  406. __le32 len;
  407. __le32 ata_cmd[4];
  408. };
  409. /* Command ResPonse Block: 8B */
  410. struct mv_crpb {
  411. __le16 id;
  412. __le16 flags;
  413. __le32 tmstmp;
  414. };
  415. /* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
  416. struct mv_sg {
  417. __le32 addr;
  418. __le32 flags_size;
  419. __le32 addr_hi;
  420. __le32 reserved;
  421. };
  422. /*
  423. * We keep a local cache of a few frequently accessed port
  424. * registers here, to avoid having to read them (very slow)
  425. * when switching between EDMA and non-EDMA modes.
  426. */
  427. struct mv_cached_regs {
  428. u32 fiscfg;
  429. u32 ltmode;
  430. u32 haltcond;
  431. u32 unknown_rsvd;
  432. };
  433. struct mv_port_priv {
  434. struct mv_crqb *crqb;
  435. dma_addr_t crqb_dma;
  436. struct mv_crpb *crpb;
  437. dma_addr_t crpb_dma;
  438. struct mv_sg *sg_tbl[MV_MAX_Q_DEPTH];
  439. dma_addr_t sg_tbl_dma[MV_MAX_Q_DEPTH];
  440. unsigned int req_idx;
  441. unsigned int resp_idx;
  442. u32 pp_flags;
  443. struct mv_cached_regs cached;
  444. unsigned int delayed_eh_pmp_map;
  445. };
  446. struct mv_port_signal {
  447. u32 amps;
  448. u32 pre;
  449. };
  450. struct mv_host_priv {
  451. u32 hp_flags;
  452. u32 main_irq_mask;
  453. struct mv_port_signal signal[8];
  454. const struct mv_hw_ops *ops;
  455. int n_ports;
  456. void __iomem *base;
  457. void __iomem *main_irq_cause_addr;
  458. void __iomem *main_irq_mask_addr;
  459. u32 irq_cause_offset;
  460. u32 irq_mask_offset;
  461. u32 unmask_all_irqs;
  462. /*
  463. * These consistent DMA memory pools give us guaranteed
  464. * alignment for hardware-accessed data structures,
  465. * and less memory waste in accomplishing the alignment.
  466. */
  467. struct dma_pool *crqb_pool;
  468. struct dma_pool *crpb_pool;
  469. struct dma_pool *sg_tbl_pool;
  470. };
  471. struct mv_hw_ops {
  472. void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
  473. unsigned int port);
  474. void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
  475. void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
  476. void __iomem *mmio);
  477. int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
  478. unsigned int n_hc);
  479. void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
  480. void (*reset_bus)(struct ata_host *host, void __iomem *mmio);
  481. };
  482. static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val);
  483. static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val);
  484. static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val);
  485. static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val);
  486. static int mv_port_start(struct ata_port *ap);
  487. static void mv_port_stop(struct ata_port *ap);
  488. static int mv_qc_defer(struct ata_queued_cmd *qc);
  489. static void mv_qc_prep(struct ata_queued_cmd *qc);
  490. static void mv_qc_prep_iie(struct ata_queued_cmd *qc);
  491. static unsigned int mv_qc_issue(struct ata_queued_cmd *qc);
  492. static int mv_hardreset(struct ata_link *link, unsigned int *class,
  493. unsigned long deadline);
  494. static void mv_eh_freeze(struct ata_port *ap);
  495. static void mv_eh_thaw(struct ata_port *ap);
  496. static void mv6_dev_config(struct ata_device *dev);
  497. static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
  498. unsigned int port);
  499. static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
  500. static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
  501. void __iomem *mmio);
  502. static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
  503. unsigned int n_hc);
  504. static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
  505. static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio);
  506. static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
  507. unsigned int port);
  508. static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
  509. static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
  510. void __iomem *mmio);
  511. static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
  512. unsigned int n_hc);
  513. static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
  514. static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
  515. void __iomem *mmio);
  516. static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
  517. void __iomem *mmio);
  518. static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
  519. void __iomem *mmio, unsigned int n_hc);
  520. static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
  521. void __iomem *mmio);
  522. static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio);
  523. static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio);
  524. static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
  525. unsigned int port_no);
  526. static int mv_stop_edma(struct ata_port *ap);
  527. static int mv_stop_edma_engine(void __iomem *port_mmio);
  528. static void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma);
  529. static void mv_pmp_select(struct ata_port *ap, int pmp);
  530. static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
  531. unsigned long deadline);
  532. static int mv_softreset(struct ata_link *link, unsigned int *class,
  533. unsigned long deadline);
  534. static void mv_pmp_error_handler(struct ata_port *ap);
  535. static void mv_process_crpb_entries(struct ata_port *ap,
  536. struct mv_port_priv *pp);
  537. static void mv_sff_irq_clear(struct ata_port *ap);
  538. static int mv_check_atapi_dma(struct ata_queued_cmd *qc);
  539. static void mv_bmdma_setup(struct ata_queued_cmd *qc);
  540. static void mv_bmdma_start(struct ata_queued_cmd *qc);
  541. static void mv_bmdma_stop(struct ata_queued_cmd *qc);
  542. static u8 mv_bmdma_status(struct ata_port *ap);
  543. static u8 mv_sff_check_status(struct ata_port *ap);
  544. /* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below
  545. * because we have to allow room for worst case splitting of
  546. * PRDs for 64K boundaries in mv_fill_sg().
  547. */
  548. static struct scsi_host_template mv5_sht = {
  549. ATA_BASE_SHT(DRV_NAME),
  550. .sg_tablesize = MV_MAX_SG_CT / 2,
  551. .dma_boundary = MV_DMA_BOUNDARY,
  552. };
  553. static struct scsi_host_template mv6_sht = {
  554. ATA_NCQ_SHT(DRV_NAME),
  555. .can_queue = MV_MAX_Q_DEPTH - 1,
  556. .sg_tablesize = MV_MAX_SG_CT / 2,
  557. .dma_boundary = MV_DMA_BOUNDARY,
  558. };
  559. static struct ata_port_operations mv5_ops = {
  560. .inherits = &ata_sff_port_ops,
  561. .lost_interrupt = ATA_OP_NULL,
  562. .qc_defer = mv_qc_defer,
  563. .qc_prep = mv_qc_prep,
  564. .qc_issue = mv_qc_issue,
  565. .freeze = mv_eh_freeze,
  566. .thaw = mv_eh_thaw,
  567. .hardreset = mv_hardreset,
  568. .error_handler = ata_std_error_handler, /* avoid SFF EH */
  569. .post_internal_cmd = ATA_OP_NULL,
  570. .scr_read = mv5_scr_read,
  571. .scr_write = mv5_scr_write,
  572. .port_start = mv_port_start,
  573. .port_stop = mv_port_stop,
  574. };
  575. static struct ata_port_operations mv6_ops = {
  576. .inherits = &mv5_ops,
  577. .dev_config = mv6_dev_config,
  578. .scr_read = mv_scr_read,
  579. .scr_write = mv_scr_write,
  580. .pmp_hardreset = mv_pmp_hardreset,
  581. .pmp_softreset = mv_softreset,
  582. .softreset = mv_softreset,
  583. .error_handler = mv_pmp_error_handler,
  584. .sff_check_status = mv_sff_check_status,
  585. .sff_irq_clear = mv_sff_irq_clear,
  586. .check_atapi_dma = mv_check_atapi_dma,
  587. .bmdma_setup = mv_bmdma_setup,
  588. .bmdma_start = mv_bmdma_start,
  589. .bmdma_stop = mv_bmdma_stop,
  590. .bmdma_status = mv_bmdma_status,
  591. };
  592. static struct ata_port_operations mv_iie_ops = {
  593. .inherits = &mv6_ops,
  594. .dev_config = ATA_OP_NULL,
  595. .qc_prep = mv_qc_prep_iie,
  596. };
  597. static const struct ata_port_info mv_port_info[] = {
  598. { /* chip_504x */
  599. .flags = MV_GEN_I_FLAGS,
  600. .pio_mask = ATA_PIO4,
  601. .udma_mask = ATA_UDMA6,
  602. .port_ops = &mv5_ops,
  603. },
  604. { /* chip_508x */
  605. .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC,
  606. .pio_mask = ATA_PIO4,
  607. .udma_mask = ATA_UDMA6,
  608. .port_ops = &mv5_ops,
  609. },
  610. { /* chip_5080 */
  611. .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC,
  612. .pio_mask = ATA_PIO4,
  613. .udma_mask = ATA_UDMA6,
  614. .port_ops = &mv5_ops,
  615. },
  616. { /* chip_604x */
  617. .flags = MV_GEN_II_FLAGS,
  618. .pio_mask = ATA_PIO4,
  619. .udma_mask = ATA_UDMA6,
  620. .port_ops = &mv6_ops,
  621. },
  622. { /* chip_608x */
  623. .flags = MV_GEN_II_FLAGS | MV_FLAG_DUAL_HC,
  624. .pio_mask = ATA_PIO4,
  625. .udma_mask = ATA_UDMA6,
  626. .port_ops = &mv6_ops,
  627. },
  628. { /* chip_6042 */
  629. .flags = MV_GEN_IIE_FLAGS,
  630. .pio_mask = ATA_PIO4,
  631. .udma_mask = ATA_UDMA6,
  632. .port_ops = &mv_iie_ops,
  633. },
  634. { /* chip_7042 */
  635. .flags = MV_GEN_IIE_FLAGS,
  636. .pio_mask = ATA_PIO4,
  637. .udma_mask = ATA_UDMA6,
  638. .port_ops = &mv_iie_ops,
  639. },
  640. { /* chip_soc */
  641. .flags = MV_GEN_IIE_FLAGS,
  642. .pio_mask = ATA_PIO4,
  643. .udma_mask = ATA_UDMA6,
  644. .port_ops = &mv_iie_ops,
  645. },
  646. };
  647. static const struct pci_device_id mv_pci_tbl[] = {
  648. { PCI_VDEVICE(MARVELL, 0x5040), chip_504x },
  649. { PCI_VDEVICE(MARVELL, 0x5041), chip_504x },
  650. { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 },
  651. { PCI_VDEVICE(MARVELL, 0x5081), chip_508x },
  652. /* RocketRAID 1720/174x have different identifiers */
  653. { PCI_VDEVICE(TTI, 0x1720), chip_6042 },
  654. { PCI_VDEVICE(TTI, 0x1740), chip_6042 },
  655. { PCI_VDEVICE(TTI, 0x1742), chip_6042 },
  656. { PCI_VDEVICE(MARVELL, 0x6040), chip_604x },
  657. { PCI_VDEVICE(MARVELL, 0x6041), chip_604x },
  658. { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 },
  659. { PCI_VDEVICE(MARVELL, 0x6080), chip_608x },
  660. { PCI_VDEVICE(MARVELL, 0x6081), chip_608x },
  661. { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x },
  662. /* Adaptec 1430SA */
  663. { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 },
  664. /* Marvell 7042 support */
  665. { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 },
  666. /* Highpoint RocketRAID PCIe series */
  667. { PCI_VDEVICE(TTI, 0x2300), chip_7042 },
  668. { PCI_VDEVICE(TTI, 0x2310), chip_7042 },
  669. { } /* terminate list */
  670. };
  671. static const struct mv_hw_ops mv5xxx_ops = {
  672. .phy_errata = mv5_phy_errata,
  673. .enable_leds = mv5_enable_leds,
  674. .read_preamp = mv5_read_preamp,
  675. .reset_hc = mv5_reset_hc,
  676. .reset_flash = mv5_reset_flash,
  677. .reset_bus = mv5_reset_bus,
  678. };
  679. static const struct mv_hw_ops mv6xxx_ops = {
  680. .phy_errata = mv6_phy_errata,
  681. .enable_leds = mv6_enable_leds,
  682. .read_preamp = mv6_read_preamp,
  683. .reset_hc = mv6_reset_hc,
  684. .reset_flash = mv6_reset_flash,
  685. .reset_bus = mv_reset_pci_bus,
  686. };
  687. static const struct mv_hw_ops mv_soc_ops = {
  688. .phy_errata = mv6_phy_errata,
  689. .enable_leds = mv_soc_enable_leds,
  690. .read_preamp = mv_soc_read_preamp,
  691. .reset_hc = mv_soc_reset_hc,
  692. .reset_flash = mv_soc_reset_flash,
  693. .reset_bus = mv_soc_reset_bus,
  694. };
  695. /*
  696. * Functions
  697. */
  698. static inline void writelfl(unsigned long data, void __iomem *addr)
  699. {
  700. writel(data, addr);
  701. (void) readl(addr); /* flush to avoid PCI posted write */
  702. }
  703. static inline unsigned int mv_hc_from_port(unsigned int port)
  704. {
  705. return port >> MV_PORT_HC_SHIFT;
  706. }
  707. static inline unsigned int mv_hardport_from_port(unsigned int port)
  708. {
  709. return port & MV_PORT_MASK;
  710. }
  711. /*
  712. * Consolidate some rather tricky bit shift calculations.
  713. * This is hot-path stuff, so not a function.
  714. * Simple code, with two return values, so macro rather than inline.
  715. *
  716. * port is the sole input, in range 0..7.
  717. * shift is one output, for use with main_irq_cause / main_irq_mask registers.
  718. * hardport is the other output, in range 0..3.
  719. *
  720. * Note that port and hardport may be the same variable in some cases.
  721. */
  722. #define MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport) \
  723. { \
  724. shift = mv_hc_from_port(port) * HC_SHIFT; \
  725. hardport = mv_hardport_from_port(port); \
  726. shift += hardport * 2; \
  727. }
  728. static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
  729. {
  730. return (base + SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
  731. }
  732. static inline void __iomem *mv_hc_base_from_port(void __iomem *base,
  733. unsigned int port)
  734. {
  735. return mv_hc_base(base, mv_hc_from_port(port));
  736. }
  737. static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
  738. {
  739. return mv_hc_base_from_port(base, port) +
  740. MV_SATAHC_ARBTR_REG_SZ +
  741. (mv_hardport_from_port(port) * MV_PORT_REG_SZ);
  742. }
  743. static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
  744. {
  745. void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
  746. unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
  747. return hc_mmio + ofs;
  748. }
  749. static inline void __iomem *mv_host_base(struct ata_host *host)
  750. {
  751. struct mv_host_priv *hpriv = host->private_data;
  752. return hpriv->base;
  753. }
  754. static inline void __iomem *mv_ap_base(struct ata_port *ap)
  755. {
  756. return mv_port_base(mv_host_base(ap->host), ap->port_no);
  757. }
  758. static inline int mv_get_hc_count(unsigned long port_flags)
  759. {
  760. return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
  761. }
  762. /**
  763. * mv_save_cached_regs - (re-)initialize cached port registers
  764. * @ap: the port whose registers we are caching
  765. *
  766. * Initialize the local cache of port registers,
  767. * so that reading them over and over again can
  768. * be avoided on the hotter paths of this driver.
  769. * This saves a few microseconds each time we switch
  770. * to/from EDMA mode to perform (eg.) a drive cache flush.
  771. */
  772. static void mv_save_cached_regs(struct ata_port *ap)
  773. {
  774. void __iomem *port_mmio = mv_ap_base(ap);
  775. struct mv_port_priv *pp = ap->private_data;
  776. pp->cached.fiscfg = readl(port_mmio + FISCFG);
  777. pp->cached.ltmode = readl(port_mmio + LTMODE);
  778. pp->cached.haltcond = readl(port_mmio + EDMA_HALTCOND);
  779. pp->cached.unknown_rsvd = readl(port_mmio + EDMA_UNKNOWN_RSVD);
  780. }
  781. /**
  782. * mv_write_cached_reg - write to a cached port register
  783. * @addr: hardware address of the register
  784. * @old: pointer to cached value of the register
  785. * @new: new value for the register
  786. *
  787. * Write a new value to a cached register,
  788. * but only if the value is different from before.
  789. */
  790. static inline void mv_write_cached_reg(void __iomem *addr, u32 *old, u32 new)
  791. {
  792. if (new != *old) {
  793. unsigned long laddr;
  794. *old = new;
  795. /*
  796. * Workaround for 88SX60x1-B2 FEr SATA#13:
  797. * Read-after-write is needed to prevent generating 64-bit
  798. * write cycles on the PCI bus for SATA interface registers
  799. * at offsets ending in 0x4 or 0xc.
  800. *
  801. * Looks like a lot of fuss, but it avoids an unnecessary
  802. * +1 usec read-after-write delay for unaffected registers.
  803. */
  804. laddr = (long)addr & 0xffff;
  805. if (laddr >= 0x300 && laddr <= 0x33c) {
  806. laddr &= 0x000f;
  807. if (laddr == 0x4 || laddr == 0xc) {
  808. writelfl(new, addr); /* read after write */
  809. return;
  810. }
  811. }
  812. writel(new, addr); /* unaffected by the errata */
  813. }
  814. }
  815. static void mv_set_edma_ptrs(void __iomem *port_mmio,
  816. struct mv_host_priv *hpriv,
  817. struct mv_port_priv *pp)
  818. {
  819. u32 index;
  820. /*
  821. * initialize request queue
  822. */
  823. pp->req_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
  824. index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
  825. WARN_ON(pp->crqb_dma & 0x3ff);
  826. writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI);
  827. writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index,
  828. port_mmio + EDMA_REQ_Q_IN_PTR);
  829. writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR);
  830. /*
  831. * initialize response queue
  832. */
  833. pp->resp_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
  834. index = pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT;
  835. WARN_ON(pp->crpb_dma & 0xff);
  836. writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI);
  837. writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR);
  838. writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index,
  839. port_mmio + EDMA_RSP_Q_OUT_PTR);
  840. }
  841. static void mv_write_main_irq_mask(u32 mask, struct mv_host_priv *hpriv)
  842. {
  843. /*
  844. * When writing to the main_irq_mask in hardware,
  845. * we must ensure exclusivity between the interrupt coalescing bits
  846. * and the corresponding individual port DONE_IRQ bits.
  847. *
  848. * Note that this register is really an "IRQ enable" register,
  849. * not an "IRQ mask" register as Marvell's naming might suggest.
  850. */
  851. if (mask & (ALL_PORTS_COAL_DONE | PORTS_0_3_COAL_DONE))
  852. mask &= ~DONE_IRQ_0_3;
  853. if (mask & (ALL_PORTS_COAL_DONE | PORTS_4_7_COAL_DONE))
  854. mask &= ~DONE_IRQ_4_7;
  855. writelfl(mask, hpriv->main_irq_mask_addr);
  856. }
  857. static void mv_set_main_irq_mask(struct ata_host *host,
  858. u32 disable_bits, u32 enable_bits)
  859. {
  860. struct mv_host_priv *hpriv = host->private_data;
  861. u32 old_mask, new_mask;
  862. old_mask = hpriv->main_irq_mask;
  863. new_mask = (old_mask & ~disable_bits) | enable_bits;
  864. if (new_mask != old_mask) {
  865. hpriv->main_irq_mask = new_mask;
  866. mv_write_main_irq_mask(new_mask, hpriv);
  867. }
  868. }
  869. static void mv_enable_port_irqs(struct ata_port *ap,
  870. unsigned int port_bits)
  871. {
  872. unsigned int shift, hardport, port = ap->port_no;
  873. u32 disable_bits, enable_bits;
  874. MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
  875. disable_bits = (DONE_IRQ | ERR_IRQ) << shift;
  876. enable_bits = port_bits << shift;
  877. mv_set_main_irq_mask(ap->host, disable_bits, enable_bits);
  878. }
  879. static void mv_clear_and_enable_port_irqs(struct ata_port *ap,
  880. void __iomem *port_mmio,
  881. unsigned int port_irqs)
  882. {
  883. struct mv_host_priv *hpriv = ap->host->private_data;
  884. int hardport = mv_hardport_from_port(ap->port_no);
  885. void __iomem *hc_mmio = mv_hc_base_from_port(
  886. mv_host_base(ap->host), ap->port_no);
  887. u32 hc_irq_cause;
  888. /* clear EDMA event indicators, if any */
  889. writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE);
  890. /* clear pending irq events */
  891. hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport);
  892. writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE);
  893. /* clear FIS IRQ Cause */
  894. if (IS_GEN_IIE(hpriv))
  895. writelfl(0, port_mmio + FIS_IRQ_CAUSE);
  896. mv_enable_port_irqs(ap, port_irqs);
  897. }
  898. static void mv_set_irq_coalescing(struct ata_host *host,
  899. unsigned int count, unsigned int usecs)
  900. {
  901. struct mv_host_priv *hpriv = host->private_data;
  902. void __iomem *mmio = hpriv->base, *hc_mmio;
  903. u32 coal_enable = 0;
  904. unsigned long flags;
  905. unsigned int clks, is_dual_hc = hpriv->n_ports > MV_PORTS_PER_HC;
  906. const u32 coal_disable = PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE |
  907. ALL_PORTS_COAL_DONE;
  908. /* Disable IRQ coalescing if either threshold is zero */
  909. if (!usecs || !count) {
  910. clks = count = 0;
  911. } else {
  912. /* Respect maximum limits of the hardware */
  913. clks = usecs * COAL_CLOCKS_PER_USEC;
  914. if (clks > MAX_COAL_TIME_THRESHOLD)
  915. clks = MAX_COAL_TIME_THRESHOLD;
  916. if (count > MAX_COAL_IO_COUNT)
  917. count = MAX_COAL_IO_COUNT;
  918. }
  919. spin_lock_irqsave(&host->lock, flags);
  920. mv_set_main_irq_mask(host, coal_disable, 0);
  921. if (is_dual_hc && !IS_GEN_I(hpriv)) {
  922. /*
  923. * GEN_II/GEN_IIE with dual host controllers:
  924. * one set of global thresholds for the entire chip.
  925. */
  926. writel(clks, mmio + IRQ_COAL_TIME_THRESHOLD);
  927. writel(count, mmio + IRQ_COAL_IO_THRESHOLD);
  928. /* clear leftover coal IRQ bit */
  929. writel(~ALL_PORTS_COAL_IRQ, mmio + IRQ_COAL_CAUSE);
  930. if (count)
  931. coal_enable = ALL_PORTS_COAL_DONE;
  932. clks = count = 0; /* force clearing of regular regs below */
  933. }
  934. /*
  935. * All chips: independent thresholds for each HC on the chip.
  936. */
  937. hc_mmio = mv_hc_base_from_port(mmio, 0);
  938. writel(clks, hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD);
  939. writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD);
  940. writel(~HC_COAL_IRQ, hc_mmio + HC_IRQ_CAUSE);
  941. if (count)
  942. coal_enable |= PORTS_0_3_COAL_DONE;
  943. if (is_dual_hc) {
  944. hc_mmio = mv_hc_base_from_port(mmio, MV_PORTS_PER_HC);
  945. writel(clks, hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD);
  946. writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD);
  947. writel(~HC_COAL_IRQ, hc_mmio + HC_IRQ_CAUSE);
  948. if (count)
  949. coal_enable |= PORTS_4_7_COAL_DONE;
  950. }
  951. mv_set_main_irq_mask(host, 0, coal_enable);
  952. spin_unlock_irqrestore(&host->lock, flags);
  953. }
  954. /**
  955. * mv_start_edma - Enable eDMA engine
  956. * @base: port base address
  957. * @pp: port private data
  958. *
  959. * Verify the local cache of the eDMA state is accurate with a
  960. * WARN_ON.
  961. *
  962. * LOCKING:
  963. * Inherited from caller.
  964. */
  965. static void mv_start_edma(struct ata_port *ap, void __iomem *port_mmio,
  966. struct mv_port_priv *pp, u8 protocol)
  967. {
  968. int want_ncq = (protocol == ATA_PROT_NCQ);
  969. if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
  970. int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0);
  971. if (want_ncq != using_ncq)
  972. mv_stop_edma(ap);
  973. }
  974. if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) {
  975. struct mv_host_priv *hpriv = ap->host->private_data;
  976. mv_edma_cfg(ap, want_ncq, 1);
  977. mv_set_edma_ptrs(port_mmio, hpriv, pp);
  978. mv_clear_and_enable_port_irqs(ap, port_mmio, DONE_IRQ|ERR_IRQ);
  979. writelfl(EDMA_EN, port_mmio + EDMA_CMD);
  980. pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
  981. }
  982. }
  983. static void mv_wait_for_edma_empty_idle(struct ata_port *ap)
  984. {
  985. void __iomem *port_mmio = mv_ap_base(ap);
  986. const u32 empty_idle = (EDMA_STATUS_CACHE_EMPTY | EDMA_STATUS_IDLE);
  987. const int per_loop = 5, timeout = (15 * 1000 / per_loop);
  988. int i;
  989. /*
  990. * Wait for the EDMA engine to finish transactions in progress.
  991. * No idea what a good "timeout" value might be, but measurements
  992. * indicate that it often requires hundreds of microseconds
  993. * with two drives in-use. So we use the 15msec value above
  994. * as a rough guess at what even more drives might require.
  995. */
  996. for (i = 0; i < timeout; ++i) {
  997. u32 edma_stat = readl(port_mmio + EDMA_STATUS);
  998. if ((edma_stat & empty_idle) == empty_idle)
  999. break;
  1000. udelay(per_loop);
  1001. }
  1002. /* ata_port_printk(ap, KERN_INFO, "%s: %u+ usecs\n", __func__, i); */
  1003. }
  1004. /**
  1005. * mv_stop_edma_engine - Disable eDMA engine
  1006. * @port_mmio: io base address
  1007. *
  1008. * LOCKING:
  1009. * Inherited from caller.
  1010. */
  1011. static int mv_stop_edma_engine(void __iomem *port_mmio)
  1012. {
  1013. int i;
  1014. /* Disable eDMA. The disable bit auto clears. */
  1015. writelfl(EDMA_DS, port_mmio + EDMA_CMD);
  1016. /* Wait for the chip to confirm eDMA is off. */
  1017. for (i = 10000; i > 0; i--) {
  1018. u32 reg = readl(port_mmio + EDMA_CMD);
  1019. if (!(reg & EDMA_EN))
  1020. return 0;
  1021. udelay(10);
  1022. }
  1023. return -EIO;
  1024. }
  1025. static int mv_stop_edma(struct ata_port *ap)
  1026. {
  1027. void __iomem *port_mmio = mv_ap_base(ap);
  1028. struct mv_port_priv *pp = ap->private_data;
  1029. int err = 0;
  1030. if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
  1031. return 0;
  1032. pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
  1033. mv_wait_for_edma_empty_idle(ap);
  1034. if (mv_stop_edma_engine(port_mmio)) {
  1035. ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n");
  1036. err = -EIO;
  1037. }
  1038. mv_edma_cfg(ap, 0, 0);
  1039. return err;
  1040. }
  1041. #ifdef ATA_DEBUG
  1042. static void mv_dump_mem(void __iomem *start, unsigned bytes)
  1043. {
  1044. int b, w;
  1045. for (b = 0; b < bytes; ) {
  1046. DPRINTK("%p: ", start + b);
  1047. for (w = 0; b < bytes && w < 4; w++) {
  1048. printk("%08x ", readl(start + b));
  1049. b += sizeof(u32);
  1050. }
  1051. printk("\n");
  1052. }
  1053. }
  1054. #endif
  1055. static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)
  1056. {
  1057. #ifdef ATA_DEBUG
  1058. int b, w;
  1059. u32 dw;
  1060. for (b = 0; b < bytes; ) {
  1061. DPRINTK("%02x: ", b);
  1062. for (w = 0; b < bytes && w < 4; w++) {
  1063. (void) pci_read_config_dword(pdev, b, &dw);
  1064. printk("%08x ", dw);
  1065. b += sizeof(u32);
  1066. }
  1067. printk("\n");
  1068. }
  1069. #endif
  1070. }
  1071. static void mv_dump_all_regs(void __iomem *mmio_base, int port,
  1072. struct pci_dev *pdev)
  1073. {
  1074. #ifdef ATA_DEBUG
  1075. void __iomem *hc_base = mv_hc_base(mmio_base,
  1076. port >> MV_PORT_HC_SHIFT);
  1077. void __iomem *port_base;
  1078. int start_port, num_ports, p, start_hc, num_hcs, hc;
  1079. if (0 > port) {
  1080. start_hc = start_port = 0;
  1081. num_ports = 8; /* shld be benign for 4 port devs */
  1082. num_hcs = 2;
  1083. } else {
  1084. start_hc = port >> MV_PORT_HC_SHIFT;
  1085. start_port = port;
  1086. num_ports = num_hcs = 1;
  1087. }
  1088. DPRINTK("All registers for port(s) %u-%u:\n", start_port,
  1089. num_ports > 1 ? num_ports - 1 : start_port);
  1090. if (NULL != pdev) {
  1091. DPRINTK("PCI config space regs:\n");
  1092. mv_dump_pci_cfg(pdev, 0x68);
  1093. }
  1094. DPRINTK("PCI regs:\n");
  1095. mv_dump_mem(mmio_base+0xc00, 0x3c);
  1096. mv_dump_mem(mmio_base+0xd00, 0x34);
  1097. mv_dump_mem(mmio_base+0xf00, 0x4);
  1098. mv_dump_mem(mmio_base+0x1d00, 0x6c);
  1099. for (hc = start_hc; hc < start_hc + num_hcs; hc++) {
  1100. hc_base = mv_hc_base(mmio_base, hc);
  1101. DPRINTK("HC regs (HC %i):\n", hc);
  1102. mv_dump_mem(hc_base, 0x1c);
  1103. }
  1104. for (p = start_port; p < start_port + num_ports; p++) {
  1105. port_base = mv_port_base(mmio_base, p);
  1106. DPRINTK("EDMA regs (port %i):\n", p);
  1107. mv_dump_mem(port_base, 0x54);
  1108. DPRINTK("SATA regs (port %i):\n", p);
  1109. mv_dump_mem(port_base+0x300, 0x60);
  1110. }
  1111. #endif
  1112. }
  1113. static unsigned int mv_scr_offset(unsigned int sc_reg_in)
  1114. {
  1115. unsigned int ofs;
  1116. switch (sc_reg_in) {
  1117. case SCR_STATUS:
  1118. case SCR_CONTROL:
  1119. case SCR_ERROR:
  1120. ofs = SATA_STATUS + (sc_reg_in * sizeof(u32));
  1121. break;
  1122. case SCR_ACTIVE:
  1123. ofs = SATA_ACTIVE; /* active is not with the others */
  1124. break;
  1125. default:
  1126. ofs = 0xffffffffU;
  1127. break;
  1128. }
  1129. return ofs;
  1130. }
  1131. static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val)
  1132. {
  1133. unsigned int ofs = mv_scr_offset(sc_reg_in);
  1134. if (ofs != 0xffffffffU) {
  1135. *val = readl(mv_ap_base(link->ap) + ofs);
  1136. return 0;
  1137. } else
  1138. return -EINVAL;
  1139. }
  1140. static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val)
  1141. {
  1142. unsigned int ofs = mv_scr_offset(sc_reg_in);
  1143. if (ofs != 0xffffffffU) {
  1144. void __iomem *addr = mv_ap_base(link->ap) + ofs;
  1145. if (sc_reg_in == SCR_CONTROL) {
  1146. /*
  1147. * Workaround for 88SX60x1 FEr SATA#26:
  1148. *
  1149. * COMRESETs have to take care not to accidently
  1150. * put the drive to sleep when writing SCR_CONTROL.
  1151. * Setting bits 12..15 prevents this problem.
  1152. *
  1153. * So if we see an outbound COMMRESET, set those bits.
  1154. * Ditto for the followup write that clears the reset.
  1155. *
  1156. * The proprietary driver does this for
  1157. * all chip versions, and so do we.
  1158. */
  1159. if ((val & 0xf) == 1 || (readl(addr) & 0xf) == 1)
  1160. val |= 0xf000;
  1161. }
  1162. writelfl(val, addr);
  1163. return 0;
  1164. } else
  1165. return -EINVAL;
  1166. }
  1167. static void mv6_dev_config(struct ata_device *adev)
  1168. {
  1169. /*
  1170. * Deal with Gen-II ("mv6") hardware quirks/restrictions:
  1171. *
  1172. * Gen-II does not support NCQ over a port multiplier
  1173. * (no FIS-based switching).
  1174. */
  1175. if (adev->flags & ATA_DFLAG_NCQ) {
  1176. if (sata_pmp_attached(adev->link->ap)) {
  1177. adev->flags &= ~ATA_DFLAG_NCQ;
  1178. ata_dev_printk(adev, KERN_INFO,
  1179. "NCQ disabled for command-based switching\n");
  1180. }
  1181. }
  1182. }
  1183. static int mv_qc_defer(struct ata_queued_cmd *qc)
  1184. {
  1185. struct ata_link *link = qc->dev->link;
  1186. struct ata_port *ap = link->ap;
  1187. struct mv_port_priv *pp = ap->private_data;
  1188. /*
  1189. * Don't allow new commands if we're in a delayed EH state
  1190. * for NCQ and/or FIS-based switching.
  1191. */
  1192. if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
  1193. return ATA_DEFER_PORT;
  1194. /*
  1195. * If the port is completely idle, then allow the new qc.
  1196. */
  1197. if (ap->nr_active_links == 0)
  1198. return 0;
  1199. /*
  1200. * The port is operating in host queuing mode (EDMA) with NCQ
  1201. * enabled, allow multiple NCQ commands. EDMA also allows
  1202. * queueing multiple DMA commands but libata core currently
  1203. * doesn't allow it.
  1204. */
  1205. if ((pp->pp_flags & MV_PP_FLAG_EDMA_EN) &&
  1206. (pp->pp_flags & MV_PP_FLAG_NCQ_EN) && ata_is_ncq(qc->tf.protocol))
  1207. return 0;
  1208. return ATA_DEFER_PORT;
  1209. }
  1210. static void mv_config_fbs(struct ata_port *ap, int want_ncq, int want_fbs)
  1211. {
  1212. struct mv_port_priv *pp = ap->private_data;
  1213. void __iomem *port_mmio;
  1214. u32 fiscfg, *old_fiscfg = &pp->cached.fiscfg;
  1215. u32 ltmode, *old_ltmode = &pp->cached.ltmode;
  1216. u32 haltcond, *old_haltcond = &pp->cached.haltcond;
  1217. ltmode = *old_ltmode & ~LTMODE_BIT8;
  1218. haltcond = *old_haltcond | EDMA_ERR_DEV;
  1219. if (want_fbs) {
  1220. fiscfg = *old_fiscfg | FISCFG_SINGLE_SYNC;
  1221. ltmode = *old_ltmode | LTMODE_BIT8;
  1222. if (want_ncq)
  1223. haltcond &= ~EDMA_ERR_DEV;
  1224. else
  1225. fiscfg |= FISCFG_WAIT_DEV_ERR;
  1226. } else {
  1227. fiscfg = *old_fiscfg & ~(FISCFG_SINGLE_SYNC | FISCFG_WAIT_DEV_ERR);
  1228. }
  1229. port_mmio = mv_ap_base(ap);
  1230. mv_write_cached_reg(port_mmio + FISCFG, old_fiscfg, fiscfg);
  1231. mv_write_cached_reg(port_mmio + LTMODE, old_ltmode, ltmode);
  1232. mv_write_cached_reg(port_mmio + EDMA_HALTCOND, old_haltcond, haltcond);
  1233. }
  1234. static void mv_60x1_errata_sata25(struct ata_port *ap, int want_ncq)
  1235. {
  1236. struct mv_host_priv *hpriv = ap->host->private_data;
  1237. u32 old, new;
  1238. /* workaround for 88SX60x1 FEr SATA#25 (part 1) */
  1239. old = readl(hpriv->base + GPIO_PORT_CTL);
  1240. if (want_ncq)
  1241. new = old | (1 << 22);
  1242. else
  1243. new = old & ~(1 << 22);
  1244. if (new != old)
  1245. writel(new, hpriv->base + GPIO_PORT_CTL);
  1246. }
  1247. /**
  1248. * mv_bmdma_enable - set a magic bit on GEN_IIE to allow bmdma
  1249. * @ap: Port being initialized
  1250. *
  1251. * There are two DMA modes on these chips: basic DMA, and EDMA.
  1252. *
  1253. * Bit-0 of the "EDMA RESERVED" register enables/disables use
  1254. * of basic DMA on the GEN_IIE versions of the chips.
  1255. *
  1256. * This bit survives EDMA resets, and must be set for basic DMA
  1257. * to function, and should be cleared when EDMA is active.
  1258. */
  1259. static void mv_bmdma_enable_iie(struct ata_port *ap, int enable_bmdma)
  1260. {
  1261. struct mv_port_priv *pp = ap->private_data;
  1262. u32 new, *old = &pp->cached.unknown_rsvd;
  1263. if (enable_bmdma)
  1264. new = *old | 1;
  1265. else
  1266. new = *old & ~1;
  1267. mv_write_cached_reg(mv_ap_base(ap) + EDMA_UNKNOWN_RSVD, old, new);
  1268. }
  1269. /*
  1270. * SOC chips have an issue whereby the HDD LEDs don't always blink
  1271. * during I/O when NCQ is enabled. Enabling a special "LED blink" mode
  1272. * of the SOC takes care of it, generating a steady blink rate when
  1273. * any drive on the chip is active.
  1274. *
  1275. * Unfortunately, the blink mode is a global hardware setting for the SOC,
  1276. * so we must use it whenever at least one port on the SOC has NCQ enabled.
  1277. *
  1278. * We turn "LED blink" off when NCQ is not in use anywhere, because the normal
  1279. * LED operation works then, and provides better (more accurate) feedback.
  1280. *
  1281. * Note that this code assumes that an SOC never has more than one HC onboard.
  1282. */
  1283. static void mv_soc_led_blink_enable(struct ata_port *ap)
  1284. {
  1285. struct ata_host *host = ap->host;
  1286. struct mv_host_priv *hpriv = host->private_data;
  1287. void __iomem *hc_mmio;
  1288. u32 led_ctrl;
  1289. if (hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN)
  1290. return;
  1291. hpriv->hp_flags |= MV_HP_QUIRK_LED_BLINK_EN;
  1292. hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no);
  1293. led_ctrl = readl(hc_mmio + SOC_LED_CTRL);
  1294. writel(led_ctrl | SOC_LED_CTRL_BLINK, hc_mmio + SOC_LED_CTRL);
  1295. }
  1296. static void mv_soc_led_blink_disable(struct ata_port *ap)
  1297. {
  1298. struct ata_host *host = ap->host;
  1299. struct mv_host_priv *hpriv = host->private_data;
  1300. void __iomem *hc_mmio;
  1301. u32 led_ctrl;
  1302. unsigned int port;
  1303. if (!(hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN))
  1304. return;
  1305. /* disable led-blink only if no ports are using NCQ */
  1306. for (port = 0; port < hpriv->n_ports; port++) {
  1307. struct ata_port *this_ap = host->ports[port];
  1308. struct mv_port_priv *pp = this_ap->private_data;
  1309. if (pp->pp_flags & MV_PP_FLAG_NCQ_EN)
  1310. return;
  1311. }
  1312. hpriv->hp_flags &= ~MV_HP_QUIRK_LED_BLINK_EN;
  1313. hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no);
  1314. led_ctrl = readl(hc_mmio + SOC_LED_CTRL);
  1315. writel(led_ctrl & ~SOC_LED_CTRL_BLINK, hc_mmio + SOC_LED_CTRL);
  1316. }
  1317. static void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma)
  1318. {
  1319. u32 cfg;
  1320. struct mv_port_priv *pp = ap->private_data;
  1321. struct mv_host_priv *hpriv = ap->host->private_data;
  1322. void __iomem *port_mmio = mv_ap_base(ap);
  1323. /* set up non-NCQ EDMA configuration */
  1324. cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for *all* chips */
  1325. pp->pp_flags &=
  1326. ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN | MV_PP_FLAG_FAKE_ATA_BUSY);
  1327. if (IS_GEN_I(hpriv))
  1328. cfg |= (1 << 8); /* enab config burst size mask */
  1329. else if (IS_GEN_II(hpriv)) {
  1330. cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN;
  1331. mv_60x1_errata_sata25(ap, want_ncq);
  1332. } else if (IS_GEN_IIE(hpriv)) {
  1333. int want_fbs = sata_pmp_attached(ap);
  1334. /*
  1335. * Possible future enhancement:
  1336. *
  1337. * The chip can use FBS with non-NCQ, if we allow it,
  1338. * But first we need to have the error handling in place
  1339. * for this mode (datasheet section 7.3.15.4.2.3).
  1340. * So disallow non-NCQ FBS for now.
  1341. */
  1342. want_fbs &= want_ncq;
  1343. mv_config_fbs(ap, want_ncq, want_fbs);
  1344. if (want_fbs) {
  1345. pp->pp_flags |= MV_PP_FLAG_FBS_EN;
  1346. cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */
  1347. }
  1348. cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */
  1349. if (want_edma) {
  1350. cfg |= (1 << 22); /* enab 4-entry host queue cache */
  1351. if (!IS_SOC(hpriv))
  1352. cfg |= (1 << 18); /* enab early completion */
  1353. }
  1354. if (hpriv->hp_flags & MV_HP_CUT_THROUGH)
  1355. cfg |= (1 << 17); /* enab cut-thru (dis stor&forwrd) */
  1356. mv_bmdma_enable_iie(ap, !want_edma);
  1357. if (IS_SOC(hpriv)) {
  1358. if (want_ncq)
  1359. mv_soc_led_blink_enable(ap);
  1360. else
  1361. mv_soc_led_blink_disable(ap);
  1362. }
  1363. }
  1364. if (want_ncq) {
  1365. cfg |= EDMA_CFG_NCQ;
  1366. pp->pp_flags |= MV_PP_FLAG_NCQ_EN;
  1367. }
  1368. writelfl(cfg, port_mmio + EDMA_CFG);
  1369. }
  1370. static void mv_port_free_dma_mem(struct ata_port *ap)
  1371. {
  1372. struct mv_host_priv *hpriv = ap->host->private_data;
  1373. struct mv_port_priv *pp = ap->private_data;
  1374. int tag;
  1375. if (pp->crqb) {
  1376. dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma);
  1377. pp->crqb = NULL;
  1378. }
  1379. if (pp->crpb) {
  1380. dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma);
  1381. pp->crpb = NULL;
  1382. }
  1383. /*
  1384. * For GEN_I, there's no NCQ, so we have only a single sg_tbl.
  1385. * For later hardware, we have one unique sg_tbl per NCQ tag.
  1386. */
  1387. for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
  1388. if (pp->sg_tbl[tag]) {
  1389. if (tag == 0 || !IS_GEN_I(hpriv))
  1390. dma_pool_free(hpriv->sg_tbl_pool,
  1391. pp->sg_tbl[tag],
  1392. pp->sg_tbl_dma[tag]);
  1393. pp->sg_tbl[tag] = NULL;
  1394. }
  1395. }
  1396. }
  1397. /**
  1398. * mv_port_start - Port specific init/start routine.
  1399. * @ap: ATA channel to manipulate
  1400. *
  1401. * Allocate and point to DMA memory, init port private memory,
  1402. * zero indices.
  1403. *
  1404. * LOCKING:
  1405. * Inherited from caller.
  1406. */
  1407. static int mv_port_start(struct ata_port *ap)
  1408. {
  1409. struct device *dev = ap->host->dev;
  1410. struct mv_host_priv *hpriv = ap->host->private_data;
  1411. struct mv_port_priv *pp;
  1412. unsigned long flags;
  1413. int tag;
  1414. pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
  1415. if (!pp)
  1416. return -ENOMEM;
  1417. ap->private_data = pp;
  1418. pp->crqb = dma_pool_alloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma);
  1419. if (!pp->crqb)
  1420. return -ENOMEM;
  1421. memset(pp->crqb, 0, MV_CRQB_Q_SZ);
  1422. pp->crpb = dma_pool_alloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma);
  1423. if (!pp->crpb)
  1424. goto out_port_free_dma_mem;
  1425. memset(pp->crpb, 0, MV_CRPB_Q_SZ);
  1426. /* 6041/6081 Rev. "C0" (and newer) are okay with async notify */
  1427. if (hpriv->hp_flags & MV_HP_ERRATA_60X1C0)
  1428. ap->flags |= ATA_FLAG_AN;
  1429. /*
  1430. * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl.
  1431. * For later hardware, we need one unique sg_tbl per NCQ tag.
  1432. */
  1433. for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
  1434. if (tag == 0 || !IS_GEN_I(hpriv)) {
  1435. pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool,
  1436. GFP_KERNEL, &pp->sg_tbl_dma[tag]);
  1437. if (!pp->sg_tbl[tag])
  1438. goto out_port_free_dma_mem;
  1439. } else {
  1440. pp->sg_tbl[tag] = pp->sg_tbl[0];
  1441. pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0];
  1442. }
  1443. }
  1444. spin_lock_irqsave(ap->lock, flags);
  1445. mv_save_cached_regs(ap);
  1446. mv_edma_cfg(ap, 0, 0);
  1447. spin_unlock_irqrestore(ap->lock, flags);
  1448. return 0;
  1449. out_port_free_dma_mem:
  1450. mv_port_free_dma_mem(ap);
  1451. return -ENOMEM;
  1452. }
  1453. /**
  1454. * mv_port_stop - Port specific cleanup/stop routine.
  1455. * @ap: ATA channel to manipulate
  1456. *
  1457. * Stop DMA, cleanup port memory.
  1458. *
  1459. * LOCKING:
  1460. * This routine uses the host lock to protect the DMA stop.
  1461. */
  1462. static void mv_port_stop(struct ata_port *ap)
  1463. {
  1464. unsigned long flags;
  1465. spin_lock_irqsave(ap->lock, flags);
  1466. mv_stop_edma(ap);
  1467. mv_enable_port_irqs(ap, 0);
  1468. spin_unlock_irqrestore(ap->lock, flags);
  1469. mv_port_free_dma_mem(ap);
  1470. }
  1471. /**
  1472. * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
  1473. * @qc: queued command whose SG list to source from
  1474. *
  1475. * Populate the SG list and mark the last entry.
  1476. *
  1477. * LOCKING:
  1478. * Inherited from caller.
  1479. */
  1480. static void mv_fill_sg(struct ata_queued_cmd *qc)
  1481. {
  1482. struct mv_port_priv *pp = qc->ap->private_data;
  1483. struct scatterlist *sg;
  1484. struct mv_sg *mv_sg, *last_sg = NULL;
  1485. unsigned int si;
  1486. mv_sg = pp->sg_tbl[qc->tag];
  1487. for_each_sg(qc->sg, sg, qc->n_elem, si) {
  1488. dma_addr_t addr = sg_dma_address(sg);
  1489. u32 sg_len = sg_dma_len(sg);
  1490. while (sg_len) {
  1491. u32 offset = addr & 0xffff;
  1492. u32 len = sg_len;
  1493. if (offset + len > 0x10000)
  1494. len = 0x10000 - offset;
  1495. mv_sg->addr = cpu_to_le32(addr & 0xffffffff);
  1496. mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
  1497. mv_sg->flags_size = cpu_to_le32(len & 0xffff);
  1498. mv_sg->reserved = 0;
  1499. sg_len -= len;
  1500. addr += len;
  1501. last_sg = mv_sg;
  1502. mv_sg++;
  1503. }
  1504. }
  1505. if (likely(last_sg))
  1506. last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL);
  1507. mb(); /* ensure data structure is visible to the chipset */
  1508. }
  1509. static void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last)
  1510. {
  1511. u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
  1512. (last ? CRQB_CMD_LAST : 0);
  1513. *cmdw = cpu_to_le16(tmp);
  1514. }
  1515. /**
  1516. * mv_sff_irq_clear - Clear hardware interrupt after DMA.
  1517. * @ap: Port associated with this ATA transaction.
  1518. *
  1519. * We need this only for ATAPI bmdma transactions,
  1520. * as otherwise we experience spurious interrupts
  1521. * after libata-sff handles the bmdma interrupts.
  1522. */
  1523. static void mv_sff_irq_clear(struct ata_port *ap)
  1524. {
  1525. mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), ERR_IRQ);
  1526. }
  1527. /**
  1528. * mv_check_atapi_dma - Filter ATAPI cmds which are unsuitable for DMA.
  1529. * @qc: queued command to check for chipset/DMA compatibility.
  1530. *
  1531. * The bmdma engines cannot handle speculative data sizes
  1532. * (bytecount under/over flow). So only allow DMA for
  1533. * data transfer commands with known data sizes.
  1534. *
  1535. * LOCKING:
  1536. * Inherited from caller.
  1537. */
  1538. static int mv_check_atapi_dma(struct ata_queued_cmd *qc)
  1539. {
  1540. struct scsi_cmnd *scmd = qc->scsicmd;
  1541. if (scmd) {
  1542. switch (scmd->cmnd[0]) {
  1543. case READ_6:
  1544. case READ_10:
  1545. case READ_12:
  1546. case WRITE_6:
  1547. case WRITE_10:
  1548. case WRITE_12:
  1549. case GPCMD_READ_CD:
  1550. case GPCMD_SEND_DVD_STRUCTURE:
  1551. case GPCMD_SEND_CUE_SHEET:
  1552. return 0; /* DMA is safe */
  1553. }
  1554. }
  1555. return -EOPNOTSUPP; /* use PIO instead */
  1556. }
  1557. /**
  1558. * mv_bmdma_setup - Set up BMDMA transaction
  1559. * @qc: queued command to prepare DMA for.
  1560. *
  1561. * LOCKING:
  1562. * Inherited from caller.
  1563. */
  1564. static void mv_bmdma_setup(struct ata_queued_cmd *qc)
  1565. {
  1566. struct ata_port *ap = qc->ap;
  1567. void __iomem *port_mmio = mv_ap_base(ap);
  1568. struct mv_port_priv *pp = ap->private_data;
  1569. mv_fill_sg(qc);
  1570. /* clear all DMA cmd bits */
  1571. writel(0, port_mmio + BMDMA_CMD);
  1572. /* load PRD table addr. */
  1573. writel((pp->sg_tbl_dma[qc->tag] >> 16) >> 16,
  1574. port_mmio + BMDMA_PRD_HIGH);
  1575. writelfl(pp->sg_tbl_dma[qc->tag],
  1576. port_mmio + BMDMA_PRD_LOW);
  1577. /* issue r/w command */
  1578. ap->ops->sff_exec_command(ap, &qc->tf);
  1579. }
  1580. /**
  1581. * mv_bmdma_start - Start a BMDMA transaction
  1582. * @qc: queued command to start DMA on.
  1583. *
  1584. * LOCKING:
  1585. * Inherited from caller.
  1586. */
  1587. static void mv_bmdma_start(struct ata_queued_cmd *qc)
  1588. {
  1589. struct ata_port *ap = qc->ap;
  1590. void __iomem *port_mmio = mv_ap_base(ap);
  1591. unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
  1592. u32 cmd = (rw ? 0 : ATA_DMA_WR) | ATA_DMA_START;
  1593. /* start host DMA transaction */
  1594. writelfl(cmd, port_mmio + BMDMA_CMD);
  1595. }
  1596. /**
  1597. * mv_bmdma_stop - Stop BMDMA transfer
  1598. * @qc: queued command to stop DMA on.
  1599. *
  1600. * Clears the ATA_DMA_START flag in the bmdma control register
  1601. *
  1602. * LOCKING:
  1603. * Inherited from caller.
  1604. */
  1605. static void mv_bmdma_stop(struct ata_queued_cmd *qc)
  1606. {
  1607. struct ata_port *ap = qc->ap;
  1608. void __iomem *port_mmio = mv_ap_base(ap);
  1609. u32 cmd;
  1610. /* clear start/stop bit */
  1611. cmd = readl(port_mmio + BMDMA_CMD);
  1612. cmd &= ~ATA_DMA_START;
  1613. writelfl(cmd, port_mmio + BMDMA_CMD);
  1614. /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
  1615. ata_sff_dma_pause(ap);
  1616. }
  1617. /**
  1618. * mv_bmdma_status - Read BMDMA status
  1619. * @ap: port for which to retrieve DMA status.
  1620. *
  1621. * Read and return equivalent of the sff BMDMA status register.
  1622. *
  1623. * LOCKING:
  1624. * Inherited from caller.
  1625. */
  1626. static u8 mv_bmdma_status(struct ata_port *ap)
  1627. {
  1628. void __iomem *port_mmio = mv_ap_base(ap);
  1629. u32 reg, status;
  1630. /*
  1631. * Other bits are valid only if ATA_DMA_ACTIVE==0,
  1632. * and the ATA_DMA_INTR bit doesn't exist.
  1633. */
  1634. reg = readl(port_mmio + BMDMA_STATUS);
  1635. if (reg & ATA_DMA_ACTIVE)
  1636. status = ATA_DMA_ACTIVE;
  1637. else
  1638. status = (reg & ATA_DMA_ERR) | ATA_DMA_INTR;
  1639. return status;
  1640. }
  1641. /**
  1642. * mv_qc_prep - Host specific command preparation.
  1643. * @qc: queued command to prepare
  1644. *
  1645. * This routine simply redirects to the general purpose routine
  1646. * if command is not DMA. Else, it handles prep of the CRQB
  1647. * (command request block), does some sanity checking, and calls
  1648. * the SG load routine.
  1649. *
  1650. * LOCKING:
  1651. * Inherited from caller.
  1652. */
  1653. static void mv_qc_prep(struct ata_queued_cmd *qc)
  1654. {
  1655. struct ata_port *ap = qc->ap;
  1656. struct mv_port_priv *pp = ap->private_data;
  1657. __le16 *cw;
  1658. struct ata_taskfile *tf;
  1659. u16 flags = 0;
  1660. unsigned in_index;
  1661. if ((qc->tf.protocol != ATA_PROT_DMA) &&
  1662. (qc->tf.protocol != ATA_PROT_NCQ))
  1663. return;
  1664. /* Fill in command request block
  1665. */
  1666. if (!(qc->tf.flags & ATA_TFLAG_WRITE))
  1667. flags |= CRQB_FLAG_READ;
  1668. WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
  1669. flags |= qc->tag << CRQB_TAG_SHIFT;
  1670. flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
  1671. /* get current queue index from software */
  1672. in_index = pp->req_idx;
  1673. pp->crqb[in_index].sg_addr =
  1674. cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
  1675. pp->crqb[in_index].sg_addr_hi =
  1676. cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
  1677. pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags);
  1678. cw = &pp->crqb[in_index].ata_cmd[0];
  1679. tf = &qc->tf;
  1680. /* Sadly, the CRQB cannot accomodate all registers--there are
  1681. * only 11 bytes...so we must pick and choose required
  1682. * registers based on the command. So, we drop feature and
  1683. * hob_feature for [RW] DMA commands, but they are needed for
  1684. * NCQ. NCQ will drop hob_nsect, which is not needed there
  1685. * (nsect is used only for the tag; feat/hob_feat hold true nsect).
  1686. */
  1687. switch (tf->command) {
  1688. case ATA_CMD_READ:
  1689. case ATA_CMD_READ_EXT:
  1690. case ATA_CMD_WRITE:
  1691. case ATA_CMD_WRITE_EXT:
  1692. case ATA_CMD_WRITE_FUA_EXT:
  1693. mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0);
  1694. break;
  1695. case ATA_CMD_FPDMA_READ:
  1696. case ATA_CMD_FPDMA_WRITE:
  1697. mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
  1698. mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
  1699. break;
  1700. default:
  1701. /* The only other commands EDMA supports in non-queued and
  1702. * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
  1703. * of which are defined/used by Linux. If we get here, this
  1704. * driver needs work.
  1705. *
  1706. * FIXME: modify libata to give qc_prep a return value and
  1707. * return error here.
  1708. */
  1709. BUG_ON(tf->command);
  1710. break;
  1711. }
  1712. mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0);
  1713. mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);
  1714. mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);
  1715. mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0);
  1716. mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0);
  1717. mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0);
  1718. mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0);
  1719. mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);
  1720. mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */
  1721. if (!(qc->flags & ATA_QCFLAG_DMAMAP))
  1722. return;
  1723. mv_fill_sg(qc);
  1724. }
  1725. /**
  1726. * mv_qc_prep_iie - Host specific command preparation.
  1727. * @qc: queued command to prepare
  1728. *
  1729. * This routine simply redirects to the general purpose routine
  1730. * if command is not DMA. Else, it handles prep of the CRQB
  1731. * (command request block), does some sanity checking, and calls
  1732. * the SG load routine.
  1733. *
  1734. * LOCKING:
  1735. * Inherited from caller.
  1736. */
  1737. static void mv_qc_prep_iie(struct ata_queued_cmd *qc)
  1738. {
  1739. struct ata_port *ap = qc->ap;
  1740. struct mv_port_priv *pp = ap->private_data;
  1741. struct mv_crqb_iie *crqb;
  1742. struct ata_taskfile *tf;
  1743. unsigned in_index;
  1744. u32 flags = 0;
  1745. if ((qc->tf.protocol != ATA_PROT_DMA) &&
  1746. (qc->tf.protocol != ATA_PROT_NCQ))
  1747. return;
  1748. /* Fill in Gen IIE command request block */
  1749. if (!(qc->tf.flags & ATA_TFLAG_WRITE))
  1750. flags |= CRQB_FLAG_READ;
  1751. WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
  1752. flags |= qc->tag << CRQB_TAG_SHIFT;
  1753. flags |= qc->tag << CRQB_HOSTQ_SHIFT;
  1754. flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
  1755. /* get current queue index from software */
  1756. in_index = pp->req_idx;
  1757. crqb = (struct mv_crqb_iie *) &pp->crqb[in_index];
  1758. crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
  1759. crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
  1760. crqb->flags = cpu_to_le32(flags);
  1761. tf = &qc->tf;
  1762. crqb->ata_cmd[0] = cpu_to_le32(
  1763. (tf->command << 16) |
  1764. (tf->feature << 24)
  1765. );
  1766. crqb->ata_cmd[1] = cpu_to_le32(
  1767. (tf->lbal << 0) |
  1768. (tf->lbam << 8) |
  1769. (tf->lbah << 16) |
  1770. (tf->device << 24)
  1771. );
  1772. crqb->ata_cmd[2] = cpu_to_le32(
  1773. (tf->hob_lbal << 0) |
  1774. (tf->hob_lbam << 8) |
  1775. (tf->hob_lbah << 16) |
  1776. (tf->hob_feature << 24)
  1777. );
  1778. crqb->ata_cmd[3] = cpu_to_le32(
  1779. (tf->nsect << 0) |
  1780. (tf->hob_nsect << 8)
  1781. );
  1782. if (!(qc->flags & ATA_QCFLAG_DMAMAP))
  1783. return;
  1784. mv_fill_sg(qc);
  1785. }
  1786. /**
  1787. * mv_sff_check_status - fetch device status, if valid
  1788. * @ap: ATA port to fetch status from
  1789. *
  1790. * When using command issue via mv_qc_issue_fis(),
  1791. * the initial ATA_BUSY state does not show up in the
  1792. * ATA status (shadow) register. This can confuse libata!
  1793. *
  1794. * So we have a hook here to fake ATA_BUSY for that situation,
  1795. * until the first time a BUSY, DRQ, or ERR bit is seen.
  1796. *
  1797. * The rest of the time, it simply returns the ATA status register.
  1798. */
  1799. static u8 mv_sff_check_status(struct ata_port *ap)
  1800. {
  1801. u8 stat = ioread8(ap->ioaddr.status_addr);
  1802. struct mv_port_priv *pp = ap->private_data;
  1803. if (pp->pp_flags & MV_PP_FLAG_FAKE_ATA_BUSY) {
  1804. if (stat & (ATA_BUSY | ATA_DRQ | ATA_ERR))
  1805. pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY;
  1806. else
  1807. stat = ATA_BUSY;
  1808. }
  1809. return stat;
  1810. }
  1811. /**
  1812. * mv_send_fis - Send a FIS, using the "Vendor-Unique FIS" register
  1813. * @fis: fis to be sent
  1814. * @nwords: number of 32-bit words in the fis
  1815. */
  1816. static unsigned int mv_send_fis(struct ata_port *ap, u32 *fis, int nwords)
  1817. {
  1818. void __iomem *port_mmio = mv_ap_base(ap);
  1819. u32 ifctl, old_ifctl, ifstat;
  1820. int i, timeout = 200, final_word = nwords - 1;
  1821. /* Initiate FIS transmission mode */
  1822. old_ifctl = readl(port_mmio + SATA_IFCTL);
  1823. ifctl = 0x100 | (old_ifctl & 0xf);
  1824. writelfl(ifctl, port_mmio + SATA_IFCTL);
  1825. /* Send all words of the FIS except for the final word */
  1826. for (i = 0; i < final_word; ++i)
  1827. writel(fis[i], port_mmio + VENDOR_UNIQUE_FIS);
  1828. /* Flag end-of-transmission, and then send the final word */
  1829. writelfl(ifctl | 0x200, port_mmio + SATA_IFCTL);
  1830. writelfl(fis[final_word], port_mmio + VENDOR_UNIQUE_FIS);
  1831. /*
  1832. * Wait for FIS transmission to complete.
  1833. * This typically takes just a single iteration.
  1834. */
  1835. do {
  1836. ifstat = readl(port_mmio + SATA_IFSTAT);
  1837. } while (!(ifstat & 0x1000) && --timeout);
  1838. /* Restore original port configuration */
  1839. writelfl(old_ifctl, port_mmio + SATA_IFCTL);
  1840. /* See if it worked */
  1841. if ((ifstat & 0x3000) != 0x1000) {
  1842. ata_port_printk(ap, KERN_WARNING,
  1843. "%s transmission error, ifstat=%08x\n",
  1844. __func__, ifstat);
  1845. return AC_ERR_OTHER;
  1846. }
  1847. return 0;
  1848. }
  1849. /**
  1850. * mv_qc_issue_fis - Issue a command directly as a FIS
  1851. * @qc: queued command to start
  1852. *
  1853. * Note that the ATA shadow registers are not updated
  1854. * after command issue, so the device will appear "READY"
  1855. * if polled, even while it is BUSY processing the command.
  1856. *
  1857. * So we use a status hook to fake ATA_BUSY until the drive changes state.
  1858. *
  1859. * Note: we don't get updated shadow regs on *completion*
  1860. * of non-data commands. So avoid sending them via this function,
  1861. * as they will appear to have completed immediately.
  1862. *
  1863. * GEN_IIE has special registers that we could get the result tf from,
  1864. * but earlier chipsets do not. For now, we ignore those registers.
  1865. */
  1866. static unsigned int mv_qc_issue_fis(struct ata_queued_cmd *qc)
  1867. {
  1868. struct ata_port *ap = qc->ap;
  1869. struct mv_port_priv *pp = ap->private_data;
  1870. struct ata_link *link = qc->dev->link;
  1871. u32 fis[5];
  1872. int err = 0;
  1873. ata_tf_to_fis(&qc->tf, link->pmp, 1, (void *)fis);
  1874. err = mv_send_fis(ap, fis, sizeof(fis) / sizeof(fis[0]));
  1875. if (err)
  1876. return err;
  1877. switch (qc->tf.protocol) {
  1878. case ATAPI_PROT_PIO:
  1879. pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY;
  1880. /* fall through */
  1881. case ATAPI_PROT_NODATA:
  1882. ap->hsm_task_state = HSM_ST_FIRST;
  1883. break;
  1884. case ATA_PROT_PIO:
  1885. pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY;
  1886. if (qc->tf.flags & ATA_TFLAG_WRITE)
  1887. ap->hsm_task_state = HSM_ST_FIRST;
  1888. else
  1889. ap->hsm_task_state = HSM_ST;
  1890. break;
  1891. default:
  1892. ap->hsm_task_state = HSM_ST_LAST;
  1893. break;
  1894. }
  1895. if (qc->tf.flags & ATA_TFLAG_POLLING)
  1896. ata_pio_queue_task(ap, qc, 0);
  1897. return 0;
  1898. }
  1899. /**
  1900. * mv_qc_issue - Initiate a command to the host
  1901. * @qc: queued command to start
  1902. *
  1903. * This routine simply redirects to the general purpose routine
  1904. * if command is not DMA. Else, it sanity checks our local
  1905. * caches of the request producer/consumer indices then enables
  1906. * DMA and bumps the request producer index.
  1907. *
  1908. * LOCKING:
  1909. * Inherited from caller.
  1910. */
  1911. static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
  1912. {
  1913. static int limit_warnings = 10;
  1914. struct ata_port *ap = qc->ap;
  1915. void __iomem *port_mmio = mv_ap_base(ap);
  1916. struct mv_port_priv *pp = ap->private_data;
  1917. u32 in_index;
  1918. unsigned int port_irqs;
  1919. pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY; /* paranoia */
  1920. switch (qc->tf.protocol) {
  1921. case ATA_PROT_DMA:
  1922. case ATA_PROT_NCQ:
  1923. mv_start_edma(ap, port_mmio, pp, qc->tf.protocol);
  1924. pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK;
  1925. in_index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
  1926. /* Write the request in pointer to kick the EDMA to life */
  1927. writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index,
  1928. port_mmio + EDMA_REQ_Q_IN_PTR);
  1929. return 0;
  1930. case ATA_PROT_PIO:
  1931. /*
  1932. * Errata SATA#16, SATA#24: warn if multiple DRQs expected.
  1933. *
  1934. * Someday, we might implement special polling workarounds
  1935. * for these, but it all seems rather unnecessary since we
  1936. * normally use only DMA for commands which transfer more
  1937. * than a single block of data.
  1938. *
  1939. * Much of the time, this could just work regardless.
  1940. * So for now, just log the incident, and allow the attempt.
  1941. */
  1942. if (limit_warnings > 0 && (qc->nbytes / qc->sect_size) > 1) {
  1943. --limit_warnings;
  1944. ata_link_printk(qc->dev->link, KERN_WARNING, DRV_NAME
  1945. ": attempting PIO w/multiple DRQ: "
  1946. "this may fail due to h/w errata\n");
  1947. }
  1948. /* drop through */
  1949. case ATA_PROT_NODATA:
  1950. case ATAPI_PROT_PIO:
  1951. case ATAPI_PROT_NODATA:
  1952. if (ap->flags & ATA_FLAG_PIO_POLLING)
  1953. qc->tf.flags |= ATA_TFLAG_POLLING;
  1954. break;
  1955. }
  1956. if (qc->tf.flags & ATA_TFLAG_POLLING)
  1957. port_irqs = ERR_IRQ; /* mask device interrupt when polling */
  1958. else
  1959. port_irqs = ERR_IRQ | DONE_IRQ; /* unmask all interrupts */
  1960. /*
  1961. * We're about to send a non-EDMA capable command to the
  1962. * port. Turn off EDMA so there won't be problems accessing
  1963. * shadow block, etc registers.
  1964. */
  1965. mv_stop_edma(ap);
  1966. mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), port_irqs);
  1967. mv_pmp_select(ap, qc->dev->link->pmp);
  1968. if (qc->tf.command == ATA_CMD_READ_LOG_EXT) {
  1969. struct mv_host_priv *hpriv = ap->host->private_data;
  1970. /*
  1971. * Workaround for 88SX60x1 FEr SATA#25 (part 2).
  1972. *
  1973. * After any NCQ error, the READ_LOG_EXT command
  1974. * from libata-eh *must* use mv_qc_issue_fis().
  1975. * Otherwise it might fail, due to chip errata.
  1976. *
  1977. * Rather than special-case it, we'll just *always*
  1978. * use this method here for READ_LOG_EXT, making for
  1979. * easier testing.
  1980. */
  1981. if (IS_GEN_II(hpriv))
  1982. return mv_qc_issue_fis(qc);
  1983. }
  1984. return ata_sff_qc_issue(qc);
  1985. }
  1986. static struct ata_queued_cmd *mv_get_active_qc(struct ata_port *ap)
  1987. {
  1988. struct mv_port_priv *pp = ap->private_data;
  1989. struct ata_queued_cmd *qc;
  1990. if (pp->pp_flags & MV_PP_FLAG_NCQ_EN)
  1991. return NULL;
  1992. qc = ata_qc_from_tag(ap, ap->link.active_tag);
  1993. if (qc) {
  1994. if (qc->tf.flags & ATA_TFLAG_POLLING)
  1995. qc = NULL;
  1996. else if (!(qc->flags & ATA_QCFLAG_ACTIVE))
  1997. qc = NULL;
  1998. }
  1999. return qc;
  2000. }
  2001. static void mv_pmp_error_handler(struct ata_port *ap)
  2002. {
  2003. unsigned int pmp, pmp_map;
  2004. struct mv_port_priv *pp = ap->private_data;
  2005. if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) {
  2006. /*
  2007. * Perform NCQ error analysis on failed PMPs
  2008. * before we freeze the port entirely.
  2009. *
  2010. * The failed PMPs are marked earlier by mv_pmp_eh_prep().
  2011. */
  2012. pmp_map = pp->delayed_eh_pmp_map;
  2013. pp->pp_flags &= ~MV_PP_FLAG_DELAYED_EH;
  2014. for (pmp = 0; pmp_map != 0; pmp++) {
  2015. unsigned int this_pmp = (1 << pmp);
  2016. if (pmp_map & this_pmp) {
  2017. struct ata_link *link = &ap->pmp_link[pmp];
  2018. pmp_map &= ~this_pmp;
  2019. ata_eh_analyze_ncq_error(link);
  2020. }
  2021. }
  2022. ata_port_freeze(ap);
  2023. }
  2024. sata_pmp_error_handler(ap);
  2025. }
  2026. static unsigned int mv_get_err_pmp_map(struct ata_port *ap)
  2027. {
  2028. void __iomem *port_mmio = mv_ap_base(ap);
  2029. return readl(port_mmio + SATA_TESTCTL) >> 16;
  2030. }
  2031. static void mv_pmp_eh_prep(struct ata_port *ap, unsigned int pmp_map)
  2032. {
  2033. struct ata_eh_info *ehi;
  2034. unsigned int pmp;
  2035. /*
  2036. * Initialize EH info for PMPs which saw device errors
  2037. */
  2038. ehi = &ap->link.eh_info;
  2039. for (pmp = 0; pmp_map != 0; pmp++) {
  2040. unsigned int this_pmp = (1 << pmp);
  2041. if (pmp_map & this_pmp) {
  2042. struct ata_link *link = &ap->pmp_link[pmp];
  2043. pmp_map &= ~this_pmp;
  2044. ehi = &link->eh_info;
  2045. ata_ehi_clear_desc(ehi);
  2046. ata_ehi_push_desc(ehi, "dev err");
  2047. ehi->err_mask |= AC_ERR_DEV;
  2048. ehi->action |= ATA_EH_RESET;
  2049. ata_link_abort(link);
  2050. }
  2051. }
  2052. }
  2053. static int mv_req_q_empty(struct ata_port *ap)
  2054. {
  2055. void __iomem *port_mmio = mv_ap_base(ap);
  2056. u32 in_ptr, out_ptr;
  2057. in_ptr = (readl(port_mmio + EDMA_REQ_Q_IN_PTR)
  2058. >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
  2059. out_ptr = (readl(port_mmio + EDMA_REQ_Q_OUT_PTR)
  2060. >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
  2061. return (in_ptr == out_ptr); /* 1 == queue_is_empty */
  2062. }
  2063. static int mv_handle_fbs_ncq_dev_err(struct ata_port *ap)
  2064. {
  2065. struct mv_port_priv *pp = ap->private_data;
  2066. int failed_links;
  2067. unsigned int old_map, new_map;
  2068. /*
  2069. * Device error during FBS+NCQ operation:
  2070. *
  2071. * Set a port flag to prevent further I/O being enqueued.
  2072. * Leave the EDMA running to drain outstanding commands from this port.
  2073. * Perform the post-mortem/EH only when all responses are complete.
  2074. * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.2).
  2075. */
  2076. if (!(pp->pp_flags & MV_PP_FLAG_DELAYED_EH)) {
  2077. pp->pp_flags |= MV_PP_FLAG_DELAYED_EH;
  2078. pp->delayed_eh_pmp_map = 0;
  2079. }
  2080. old_map = pp->delayed_eh_pmp_map;
  2081. new_map = old_map | mv_get_err_pmp_map(ap);
  2082. if (old_map != new_map) {
  2083. pp->delayed_eh_pmp_map = new_map;
  2084. mv_pmp_eh_prep(ap, new_map & ~old_map);
  2085. }
  2086. failed_links = hweight16(new_map);
  2087. ata_port_printk(ap, KERN_INFO, "%s: pmp_map=%04x qc_map=%04x "
  2088. "failed_links=%d nr_active_links=%d\n",
  2089. __func__, pp->delayed_eh_pmp_map,
  2090. ap->qc_active, failed_links,
  2091. ap->nr_active_links);
  2092. if (ap->nr_active_links <= failed_links && mv_req_q_empty(ap)) {
  2093. mv_process_crpb_entries(ap, pp);
  2094. mv_stop_edma(ap);
  2095. mv_eh_freeze(ap);
  2096. ata_port_printk(ap, KERN_INFO, "%s: done\n", __func__);
  2097. return 1; /* handled */
  2098. }
  2099. ata_port_printk(ap, KERN_INFO, "%s: waiting\n", __func__);
  2100. return 1; /* handled */
  2101. }
  2102. static int mv_handle_fbs_non_ncq_dev_err(struct ata_port *ap)
  2103. {
  2104. /*
  2105. * Possible future enhancement:
  2106. *
  2107. * FBS+non-NCQ operation is not yet implemented.
  2108. * See related notes in mv_edma_cfg().
  2109. *
  2110. * Device error during FBS+non-NCQ operation:
  2111. *
  2112. * We need to snapshot the shadow registers for each failed command.
  2113. * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.3).
  2114. */
  2115. return 0; /* not handled */
  2116. }
  2117. static int mv_handle_dev_err(struct ata_port *ap, u32 edma_err_cause)
  2118. {
  2119. struct mv_port_priv *pp = ap->private_data;
  2120. if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
  2121. return 0; /* EDMA was not active: not handled */
  2122. if (!(pp->pp_flags & MV_PP_FLAG_FBS_EN))
  2123. return 0; /* FBS was not active: not handled */
  2124. if (!(edma_err_cause & EDMA_ERR_DEV))
  2125. return 0; /* non DEV error: not handled */
  2126. edma_err_cause &= ~EDMA_ERR_IRQ_TRANSIENT;
  2127. if (edma_err_cause & ~(EDMA_ERR_DEV | EDMA_ERR_SELF_DIS))
  2128. return 0; /* other problems: not handled */
  2129. if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) {
  2130. /*
  2131. * EDMA should NOT have self-disabled for this case.
  2132. * If it did, then something is wrong elsewhere,
  2133. * and we cannot handle it here.
  2134. */
  2135. if (edma_err_cause & EDMA_ERR_SELF_DIS) {
  2136. ata_port_printk(ap, KERN_WARNING,
  2137. "%s: err_cause=0x%x pp_flags=0x%x\n",
  2138. __func__, edma_err_cause, pp->pp_flags);
  2139. return 0; /* not handled */
  2140. }
  2141. return mv_handle_fbs_ncq_dev_err(ap);
  2142. } else {
  2143. /*
  2144. * EDMA should have self-disabled for this case.
  2145. * If it did not, then something is wrong elsewhere,
  2146. * and we cannot handle it here.
  2147. */
  2148. if (!(edma_err_cause & EDMA_ERR_SELF_DIS)) {
  2149. ata_port_printk(ap, KERN_WARNING,
  2150. "%s: err_cause=0x%x pp_flags=0x%x\n",
  2151. __func__, edma_err_cause, pp->pp_flags);
  2152. return 0; /* not handled */
  2153. }
  2154. return mv_handle_fbs_non_ncq_dev_err(ap);
  2155. }
  2156. return 0; /* not handled */
  2157. }
  2158. static void mv_unexpected_intr(struct ata_port *ap, int edma_was_enabled)
  2159. {
  2160. struct ata_eh_info *ehi = &ap->link.eh_info;
  2161. char *when = "idle";
  2162. ata_ehi_clear_desc(ehi);
  2163. if (!ap || (ap->flags & ATA_FLAG_DISABLED)) {
  2164. when = "disabled";
  2165. } else if (edma_was_enabled) {
  2166. when = "EDMA enabled";
  2167. } else {
  2168. struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
  2169. if (qc && (qc->tf.flags & ATA_TFLAG_POLLING))
  2170. when = "polling";
  2171. }
  2172. ata_ehi_push_desc(ehi, "unexpected device interrupt while %s", when);
  2173. ehi->err_mask |= AC_ERR_OTHER;
  2174. ehi->action |= ATA_EH_RESET;
  2175. ata_port_freeze(ap);
  2176. }
  2177. /**
  2178. * mv_err_intr - Handle error interrupts on the port
  2179. * @ap: ATA channel to manipulate
  2180. *
  2181. * Most cases require a full reset of the chip's state machine,
  2182. * which also performs a COMRESET.
  2183. * Also, if the port disabled DMA, update our cached copy to match.
  2184. *
  2185. * LOCKING:
  2186. * Inherited from caller.
  2187. */
  2188. static void mv_err_intr(struct ata_port *ap)
  2189. {
  2190. void __iomem *port_mmio = mv_ap_base(ap);
  2191. u32 edma_err_cause, eh_freeze_mask, serr = 0;
  2192. u32 fis_cause = 0;
  2193. struct mv_port_priv *pp = ap->private_data;
  2194. struct mv_host_priv *hpriv = ap->host->private_data;
  2195. unsigned int action = 0, err_mask = 0;
  2196. struct ata_eh_info *ehi = &ap->link.eh_info;
  2197. struct ata_queued_cmd *qc;
  2198. int abort = 0;
  2199. /*
  2200. * Read and clear the SError and err_cause bits.
  2201. * For GenIIe, if EDMA_ERR_TRANS_IRQ_7 is set, we also must read/clear
  2202. * the FIS_IRQ_CAUSE register before clearing edma_err_cause.
  2203. */
  2204. sata_scr_read(&ap->link, SCR_ERROR, &serr);
  2205. sata_scr_write_flush(&ap->link, SCR_ERROR, serr);
  2206. edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE);
  2207. if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
  2208. fis_cause = readl(port_mmio + FIS_IRQ_CAUSE);
  2209. writelfl(~fis_cause, port_mmio + FIS_IRQ_CAUSE);
  2210. }
  2211. writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE);
  2212. if (edma_err_cause & EDMA_ERR_DEV) {
  2213. /*
  2214. * Device errors during FIS-based switching operation
  2215. * require special handling.
  2216. */
  2217. if (mv_handle_dev_err(ap, edma_err_cause))
  2218. return;
  2219. }
  2220. qc = mv_get_active_qc(ap);
  2221. ata_ehi_clear_desc(ehi);
  2222. ata_ehi_push_desc(ehi, "edma_err_cause=%08x pp_flags=%08x",
  2223. edma_err_cause, pp->pp_flags);
  2224. if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
  2225. ata_ehi_push_desc(ehi, "fis_cause=%08x", fis_cause);
  2226. if (fis_cause & FIS_IRQ_CAUSE_AN) {
  2227. u32 ec = edma_err_cause &
  2228. ~(EDMA_ERR_TRANS_IRQ_7 | EDMA_ERR_IRQ_TRANSIENT);
  2229. sata_async_notification(ap);
  2230. if (!ec)
  2231. return; /* Just an AN; no need for the nukes */
  2232. ata_ehi_push_desc(ehi, "SDB notify");
  2233. }
  2234. }
  2235. /*
  2236. * All generations share these EDMA error cause bits:
  2237. */
  2238. if (edma_err_cause & EDMA_ERR_DEV) {
  2239. err_mask |= AC_ERR_DEV;
  2240. action |= ATA_EH_RESET;
  2241. ata_ehi_push_desc(ehi, "dev error");
  2242. }
  2243. if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
  2244. EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR |
  2245. EDMA_ERR_INTRL_PAR)) {
  2246. err_mask |= AC_ERR_ATA_BUS;
  2247. action |= ATA_EH_RESET;
  2248. ata_ehi_push_desc(ehi, "parity error");
  2249. }
  2250. if (edma_err_cause & (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON)) {
  2251. ata_ehi_hotplugged(ehi);
  2252. ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ?
  2253. "dev disconnect" : "dev connect");
  2254. action |= ATA_EH_RESET;
  2255. }
  2256. /*
  2257. * Gen-I has a different SELF_DIS bit,
  2258. * different FREEZE bits, and no SERR bit:
  2259. */
  2260. if (IS_GEN_I(hpriv)) {
  2261. eh_freeze_mask = EDMA_EH_FREEZE_5;
  2262. if (edma_err_cause & EDMA_ERR_SELF_DIS_5) {
  2263. pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
  2264. ata_ehi_push_desc(ehi, "EDMA self-disable");
  2265. }
  2266. } else {
  2267. eh_freeze_mask = EDMA_EH_FREEZE;
  2268. if (edma_err_cause & EDMA_ERR_SELF_DIS) {
  2269. pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
  2270. ata_ehi_push_desc(ehi, "EDMA self-disable");
  2271. }
  2272. if (edma_err_cause & EDMA_ERR_SERR) {
  2273. ata_ehi_push_desc(ehi, "SError=%08x", serr);
  2274. err_mask |= AC_ERR_ATA_BUS;
  2275. action |= ATA_EH_RESET;
  2276. }
  2277. }
  2278. if (!err_mask) {
  2279. err_mask = AC_ERR_OTHER;
  2280. action |= ATA_EH_RESET;
  2281. }
  2282. ehi->serror |= serr;
  2283. ehi->action |= action;
  2284. if (qc)
  2285. qc->err_mask |= err_mask;
  2286. else
  2287. ehi->err_mask |= err_mask;
  2288. if (err_mask == AC_ERR_DEV) {
  2289. /*
  2290. * Cannot do ata_port_freeze() here,
  2291. * because it would kill PIO access,
  2292. * which is needed for further diagnosis.
  2293. */
  2294. mv_eh_freeze(ap);
  2295. abort = 1;
  2296. } else if (edma_err_cause & eh_freeze_mask) {
  2297. /*
  2298. * Note to self: ata_port_freeze() calls ata_port_abort()
  2299. */
  2300. ata_port_freeze(ap);
  2301. } else {
  2302. abort = 1;
  2303. }
  2304. if (abort) {
  2305. if (qc)
  2306. ata_link_abort(qc->dev->link);
  2307. else
  2308. ata_port_abort(ap);
  2309. }
  2310. }
  2311. static void mv_process_crpb_response(struct ata_port *ap,
  2312. struct mv_crpb *response, unsigned int tag, int ncq_enabled)
  2313. {
  2314. struct ata_queued_cmd *qc = ata_qc_from_tag(ap, tag);
  2315. if (qc) {
  2316. u8 ata_status;
  2317. u16 edma_status = le16_to_cpu(response->flags);
  2318. /*
  2319. * edma_status from a response queue entry:
  2320. * LSB is from EDMA_ERR_IRQ_CAUSE (non-NCQ only).
  2321. * MSB is saved ATA status from command completion.
  2322. */
  2323. if (!ncq_enabled) {
  2324. u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV;
  2325. if (err_cause) {
  2326. /*
  2327. * Error will be seen/handled by mv_err_intr().
  2328. * So do nothing at all here.
  2329. */
  2330. return;
  2331. }
  2332. }
  2333. ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT;
  2334. if (!ac_err_mask(ata_status))
  2335. ata_qc_complete(qc);
  2336. /* else: leave it for mv_err_intr() */
  2337. } else {
  2338. ata_port_printk(ap, KERN_ERR, "%s: no qc for tag=%d\n",
  2339. __func__, tag);
  2340. }
  2341. }
  2342. static void mv_process_crpb_entries(struct ata_port *ap, struct mv_port_priv *pp)
  2343. {
  2344. void __iomem *port_mmio = mv_ap_base(ap);
  2345. struct mv_host_priv *hpriv = ap->host->private_data;
  2346. u32 in_index;
  2347. bool work_done = false;
  2348. int ncq_enabled = (pp->pp_flags & MV_PP_FLAG_NCQ_EN);
  2349. /* Get the hardware queue position index */
  2350. in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR)
  2351. >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
  2352. /* Process new responses from since the last time we looked */
  2353. while (in_index != pp->resp_idx) {
  2354. unsigned int tag;
  2355. struct mv_crpb *response = &pp->crpb[pp->resp_idx];
  2356. pp->resp_idx = (pp->resp_idx + 1) & MV_MAX_Q_DEPTH_MASK;
  2357. if (IS_GEN_I(hpriv)) {
  2358. /* 50xx: no NCQ, only one command active at a time */
  2359. tag = ap->link.active_tag;
  2360. } else {
  2361. /* Gen II/IIE: get command tag from CRPB entry */
  2362. tag = le16_to_cpu(response->id) & 0x1f;
  2363. }
  2364. mv_process_crpb_response(ap, response, tag, ncq_enabled);
  2365. work_done = true;
  2366. }
  2367. /* Update the software queue position index in hardware */
  2368. if (work_done)
  2369. writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) |
  2370. (pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT),
  2371. port_mmio + EDMA_RSP_Q_OUT_PTR);
  2372. }
  2373. static void mv_port_intr(struct ata_port *ap, u32 port_cause)
  2374. {
  2375. struct mv_port_priv *pp;
  2376. int edma_was_enabled;
  2377. if (!ap || (ap->flags & ATA_FLAG_DISABLED)) {
  2378. mv_unexpected_intr(ap, 0);
  2379. return;
  2380. }
  2381. /*
  2382. * Grab a snapshot of the EDMA_EN flag setting,
  2383. * so that we have a consistent view for this port,
  2384. * even if something we call of our routines changes it.
  2385. */
  2386. pp = ap->private_data;
  2387. edma_was_enabled = (pp->pp_flags & MV_PP_FLAG_EDMA_EN);
  2388. /*
  2389. * Process completed CRPB response(s) before other events.
  2390. */
  2391. if (edma_was_enabled && (port_cause & DONE_IRQ)) {
  2392. mv_process_crpb_entries(ap, pp);
  2393. if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
  2394. mv_handle_fbs_ncq_dev_err(ap);
  2395. }
  2396. /*
  2397. * Handle chip-reported errors, or continue on to handle PIO.
  2398. */
  2399. if (unlikely(port_cause & ERR_IRQ)) {
  2400. mv_err_intr(ap);
  2401. } else if (!edma_was_enabled) {
  2402. struct ata_queued_cmd *qc = mv_get_active_qc(ap);
  2403. if (qc)
  2404. ata_sff_host_intr(ap, qc);
  2405. else
  2406. mv_unexpected_intr(ap, edma_was_enabled);
  2407. }
  2408. }
  2409. /**
  2410. * mv_host_intr - Handle all interrupts on the given host controller
  2411. * @host: host specific structure
  2412. * @main_irq_cause: Main interrupt cause register for the chip.
  2413. *
  2414. * LOCKING:
  2415. * Inherited from caller.
  2416. */
  2417. static int mv_host_intr(struct ata_host *host, u32 main_irq_cause)
  2418. {
  2419. struct mv_host_priv *hpriv = host->private_data;
  2420. void __iomem *mmio = hpriv->base, *hc_mmio;
  2421. unsigned int handled = 0, port;
  2422. /* If asserted, clear the "all ports" IRQ coalescing bit */
  2423. if (main_irq_cause & ALL_PORTS_COAL_DONE)
  2424. writel(~ALL_PORTS_COAL_IRQ, mmio + IRQ_COAL_CAUSE);
  2425. for (port = 0; port < hpriv->n_ports; port++) {
  2426. struct ata_port *ap = host->ports[port];
  2427. unsigned int p, shift, hardport, port_cause;
  2428. MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
  2429. /*
  2430. * Each hc within the host has its own hc_irq_cause register,
  2431. * where the interrupting ports bits get ack'd.
  2432. */
  2433. if (hardport == 0) { /* first port on this hc ? */
  2434. u32 hc_cause = (main_irq_cause >> shift) & HC0_IRQ_PEND;
  2435. u32 port_mask, ack_irqs;
  2436. /*
  2437. * Skip this entire hc if nothing pending for any ports
  2438. */
  2439. if (!hc_cause) {
  2440. port += MV_PORTS_PER_HC - 1;
  2441. continue;
  2442. }
  2443. /*
  2444. * We don't need/want to read the hc_irq_cause register,
  2445. * because doing so hurts performance, and
  2446. * main_irq_cause already gives us everything we need.
  2447. *
  2448. * But we do have to *write* to the hc_irq_cause to ack
  2449. * the ports that we are handling this time through.
  2450. *
  2451. * This requires that we create a bitmap for those
  2452. * ports which interrupted us, and use that bitmap
  2453. * to ack (only) those ports via hc_irq_cause.
  2454. */
  2455. ack_irqs = 0;
  2456. if (hc_cause & PORTS_0_3_COAL_DONE)
  2457. ack_irqs = HC_COAL_IRQ;
  2458. for (p = 0; p < MV_PORTS_PER_HC; ++p) {
  2459. if ((port + p) >= hpriv->n_ports)
  2460. break;
  2461. port_mask = (DONE_IRQ | ERR_IRQ) << (p * 2);
  2462. if (hc_cause & port_mask)
  2463. ack_irqs |= (DMA_IRQ | DEV_IRQ) << p;
  2464. }
  2465. hc_mmio = mv_hc_base_from_port(mmio, port);
  2466. writelfl(~ack_irqs, hc_mmio + HC_IRQ_CAUSE);
  2467. handled = 1;
  2468. }
  2469. /*
  2470. * Handle interrupts signalled for this port:
  2471. */
  2472. port_cause = (main_irq_cause >> shift) & (DONE_IRQ | ERR_IRQ);
  2473. if (port_cause)
  2474. mv_port_intr(ap, port_cause);
  2475. }
  2476. return handled;
  2477. }
  2478. static int mv_pci_error(struct ata_host *host, void __iomem *mmio)
  2479. {
  2480. struct mv_host_priv *hpriv = host->private_data;
  2481. struct ata_port *ap;
  2482. struct ata_queued_cmd *qc;
  2483. struct ata_eh_info *ehi;
  2484. unsigned int i, err_mask, printed = 0;
  2485. u32 err_cause;
  2486. err_cause = readl(mmio + hpriv->irq_cause_offset);
  2487. dev_printk(KERN_ERR, host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n",
  2488. err_cause);
  2489. DPRINTK("All regs @ PCI error\n");
  2490. mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev));
  2491. writelfl(0, mmio + hpriv->irq_cause_offset);
  2492. for (i = 0; i < host->n_ports; i++) {
  2493. ap = host->ports[i];
  2494. if (!ata_link_offline(&ap->link)) {
  2495. ehi = &ap->link.eh_info;
  2496. ata_ehi_clear_desc(ehi);
  2497. if (!printed++)
  2498. ata_ehi_push_desc(ehi,
  2499. "PCI err cause 0x%08x", err_cause);
  2500. err_mask = AC_ERR_HOST_BUS;
  2501. ehi->action = ATA_EH_RESET;
  2502. qc = ata_qc_from_tag(ap, ap->link.active_tag);
  2503. if (qc)
  2504. qc->err_mask |= err_mask;
  2505. else
  2506. ehi->err_mask |= err_mask;
  2507. ata_port_freeze(ap);
  2508. }
  2509. }
  2510. return 1; /* handled */
  2511. }
  2512. /**
  2513. * mv_interrupt - Main interrupt event handler
  2514. * @irq: unused
  2515. * @dev_instance: private data; in this case the host structure
  2516. *
  2517. * Read the read only register to determine if any host
  2518. * controllers have pending interrupts. If so, call lower level
  2519. * routine to handle. Also check for PCI errors which are only
  2520. * reported here.
  2521. *
  2522. * LOCKING:
  2523. * This routine holds the host lock while processing pending
  2524. * interrupts.
  2525. */
  2526. static irqreturn_t mv_interrupt(int irq, void *dev_instance)
  2527. {
  2528. struct ata_host *host = dev_instance;
  2529. struct mv_host_priv *hpriv = host->private_data;
  2530. unsigned int handled = 0;
  2531. int using_msi = hpriv->hp_flags & MV_HP_FLAG_MSI;
  2532. u32 main_irq_cause, pending_irqs;
  2533. spin_lock(&host->lock);
  2534. /* for MSI: block new interrupts while in here */
  2535. if (using_msi)
  2536. mv_write_main_irq_mask(0, hpriv);
  2537. main_irq_cause = readl(hpriv->main_irq_cause_addr);
  2538. pending_irqs = main_irq_cause & hpriv->main_irq_mask;
  2539. /*
  2540. * Deal with cases where we either have nothing pending, or have read
  2541. * a bogus register value which can indicate HW removal or PCI fault.
  2542. */
  2543. if (pending_irqs && main_irq_cause != 0xffffffffU) {
  2544. if (unlikely((pending_irqs & PCI_ERR) && !IS_SOC(hpriv)))
  2545. handled = mv_pci_error(host, hpriv->base);
  2546. else
  2547. handled = mv_host_intr(host, pending_irqs);
  2548. }
  2549. /* for MSI: unmask; interrupt cause bits will retrigger now */
  2550. if (using_msi)
  2551. mv_write_main_irq_mask(hpriv->main_irq_mask, hpriv);
  2552. spin_unlock(&host->lock);
  2553. return IRQ_RETVAL(handled);
  2554. }
  2555. static unsigned int mv5_scr_offset(unsigned int sc_reg_in)
  2556. {
  2557. unsigned int ofs;
  2558. switch (sc_reg_in) {
  2559. case SCR_STATUS:
  2560. case SCR_ERROR:
  2561. case SCR_CONTROL:
  2562. ofs = sc_reg_in * sizeof(u32);
  2563. break;
  2564. default:
  2565. ofs = 0xffffffffU;
  2566. break;
  2567. }
  2568. return ofs;
  2569. }
  2570. static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val)
  2571. {
  2572. struct mv_host_priv *hpriv = link->ap->host->private_data;
  2573. void __iomem *mmio = hpriv->base;
  2574. void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no);
  2575. unsigned int ofs = mv5_scr_offset(sc_reg_in);
  2576. if (ofs != 0xffffffffU) {
  2577. *val = readl(addr + ofs);
  2578. return 0;
  2579. } else
  2580. return -EINVAL;
  2581. }
  2582. static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val)
  2583. {
  2584. struct mv_host_priv *hpriv = link->ap->host->private_data;
  2585. void __iomem *mmio = hpriv->base;
  2586. void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no);
  2587. unsigned int ofs = mv5_scr_offset(sc_reg_in);
  2588. if (ofs != 0xffffffffU) {
  2589. writelfl(val, addr + ofs);
  2590. return 0;
  2591. } else
  2592. return -EINVAL;
  2593. }
  2594. static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio)
  2595. {
  2596. struct pci_dev *pdev = to_pci_dev(host->dev);
  2597. int early_5080;
  2598. early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0);
  2599. if (!early_5080) {
  2600. u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
  2601. tmp |= (1 << 0);
  2602. writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
  2603. }
  2604. mv_reset_pci_bus(host, mmio);
  2605. }
  2606. static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
  2607. {
  2608. writel(0x0fcfffff, mmio + FLASH_CTL);
  2609. }
  2610. static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
  2611. void __iomem *mmio)
  2612. {
  2613. void __iomem *phy_mmio = mv5_phy_base(mmio, idx);
  2614. u32 tmp;
  2615. tmp = readl(phy_mmio + MV5_PHY_MODE);
  2616. hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */
  2617. hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */
  2618. }
  2619. static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
  2620. {
  2621. u32 tmp;
  2622. writel(0, mmio + GPIO_PORT_CTL);
  2623. /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
  2624. tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
  2625. tmp |= ~(1 << 0);
  2626. writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
  2627. }
  2628. static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
  2629. unsigned int port)
  2630. {
  2631. void __iomem *phy_mmio = mv5_phy_base(mmio, port);
  2632. const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5);
  2633. u32 tmp;
  2634. int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);
  2635. if (fix_apm_sq) {
  2636. tmp = readl(phy_mmio + MV5_LTMODE);
  2637. tmp |= (1 << 19);
  2638. writel(tmp, phy_mmio + MV5_LTMODE);
  2639. tmp = readl(phy_mmio + MV5_PHY_CTL);
  2640. tmp &= ~0x3;
  2641. tmp |= 0x1;
  2642. writel(tmp, phy_mmio + MV5_PHY_CTL);
  2643. }
  2644. tmp = readl(phy_mmio + MV5_PHY_MODE);
  2645. tmp &= ~mask;
  2646. tmp |= hpriv->signal[port].pre;
  2647. tmp |= hpriv->signal[port].amps;
  2648. writel(tmp, phy_mmio + MV5_PHY_MODE);
  2649. }
  2650. #undef ZERO
  2651. #define ZERO(reg) writel(0, port_mmio + (reg))
  2652. static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
  2653. unsigned int port)
  2654. {
  2655. void __iomem *port_mmio = mv_port_base(mmio, port);
  2656. mv_reset_channel(hpriv, mmio, port);
  2657. ZERO(0x028); /* command */
  2658. writel(0x11f, port_mmio + EDMA_CFG);
  2659. ZERO(0x004); /* timer */
  2660. ZERO(0x008); /* irq err cause */
  2661. ZERO(0x00c); /* irq err mask */
  2662. ZERO(0x010); /* rq bah */
  2663. ZERO(0x014); /* rq inp */
  2664. ZERO(0x018); /* rq outp */
  2665. ZERO(0x01c); /* respq bah */
  2666. ZERO(0x024); /* respq outp */
  2667. ZERO(0x020); /* respq inp */
  2668. ZERO(0x02c); /* test control */
  2669. writel(0xbc, port_mmio + EDMA_IORDY_TMOUT);
  2670. }
  2671. #undef ZERO
  2672. #define ZERO(reg) writel(0, hc_mmio + (reg))
  2673. static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
  2674. unsigned int hc)
  2675. {
  2676. void __iomem *hc_mmio = mv_hc_base(mmio, hc);
  2677. u32 tmp;
  2678. ZERO(0x00c);
  2679. ZERO(0x010);
  2680. ZERO(0x014);
  2681. ZERO(0x018);
  2682. tmp = readl(hc_mmio + 0x20);
  2683. tmp &= 0x1c1c1c1c;
  2684. tmp |= 0x03030303;
  2685. writel(tmp, hc_mmio + 0x20);
  2686. }
  2687. #undef ZERO
  2688. static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
  2689. unsigned int n_hc)
  2690. {
  2691. unsigned int hc, port;
  2692. for (hc = 0; hc < n_hc; hc++) {
  2693. for (port = 0; port < MV_PORTS_PER_HC; port++)
  2694. mv5_reset_hc_port(hpriv, mmio,
  2695. (hc * MV_PORTS_PER_HC) + port);
  2696. mv5_reset_one_hc(hpriv, mmio, hc);
  2697. }
  2698. return 0;
  2699. }
  2700. #undef ZERO
  2701. #define ZERO(reg) writel(0, mmio + (reg))
  2702. static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio)
  2703. {
  2704. struct mv_host_priv *hpriv = host->private_data;
  2705. u32 tmp;
  2706. tmp = readl(mmio + MV_PCI_MODE);
  2707. tmp &= 0xff00ffff;
  2708. writel(tmp, mmio + MV_PCI_MODE);
  2709. ZERO(MV_PCI_DISC_TIMER);
  2710. ZERO(MV_PCI_MSI_TRIGGER);
  2711. writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT);
  2712. ZERO(MV_PCI_SERR_MASK);
  2713. ZERO(hpriv->irq_cause_offset);
  2714. ZERO(hpriv->irq_mask_offset);
  2715. ZERO(MV_PCI_ERR_LOW_ADDRESS);
  2716. ZERO(MV_PCI_ERR_HIGH_ADDRESS);
  2717. ZERO(MV_PCI_ERR_ATTRIBUTE);
  2718. ZERO(MV_PCI_ERR_COMMAND);
  2719. }
  2720. #undef ZERO
  2721. static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
  2722. {
  2723. u32 tmp;
  2724. mv5_reset_flash(hpriv, mmio);
  2725. tmp = readl(mmio + GPIO_PORT_CTL);
  2726. tmp &= 0x3;
  2727. tmp |= (1 << 5) | (1 << 6);
  2728. writel(tmp, mmio + GPIO_PORT_CTL);
  2729. }
  2730. /**
  2731. * mv6_reset_hc - Perform the 6xxx global soft reset
  2732. * @mmio: base address of the HBA
  2733. *
  2734. * This routine only applies to 6xxx parts.
  2735. *
  2736. * LOCKING:
  2737. * Inherited from caller.
  2738. */
  2739. static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
  2740. unsigned int n_hc)
  2741. {
  2742. void __iomem *reg = mmio + PCI_MAIN_CMD_STS;
  2743. int i, rc = 0;
  2744. u32 t;
  2745. /* Following procedure defined in PCI "main command and status
  2746. * register" table.
  2747. */
  2748. t = readl(reg);
  2749. writel(t | STOP_PCI_MASTER, reg);
  2750. for (i = 0; i < 1000; i++) {
  2751. udelay(1);
  2752. t = readl(reg);
  2753. if (PCI_MASTER_EMPTY & t)
  2754. break;
  2755. }
  2756. if (!(PCI_MASTER_EMPTY & t)) {
  2757. printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
  2758. rc = 1;
  2759. goto done;
  2760. }
  2761. /* set reset */
  2762. i = 5;
  2763. do {
  2764. writel(t | GLOB_SFT_RST, reg);
  2765. t = readl(reg);
  2766. udelay(1);
  2767. } while (!(GLOB_SFT_RST & t) && (i-- > 0));
  2768. if (!(GLOB_SFT_RST & t)) {
  2769. printk(KERN_ERR DRV_NAME ": can't set global reset\n");
  2770. rc = 1;
  2771. goto done;
  2772. }
  2773. /* clear reset and *reenable the PCI master* (not mentioned in spec) */
  2774. i = 5;
  2775. do {
  2776. writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
  2777. t = readl(reg);
  2778. udelay(1);
  2779. } while ((GLOB_SFT_RST & t) && (i-- > 0));
  2780. if (GLOB_SFT_RST & t) {
  2781. printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
  2782. rc = 1;
  2783. }
  2784. done:
  2785. return rc;
  2786. }
  2787. static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
  2788. void __iomem *mmio)
  2789. {
  2790. void __iomem *port_mmio;
  2791. u32 tmp;
  2792. tmp = readl(mmio + RESET_CFG);
  2793. if ((tmp & (1 << 0)) == 0) {
  2794. hpriv->signal[idx].amps = 0x7 << 8;
  2795. hpriv->signal[idx].pre = 0x1 << 5;
  2796. return;
  2797. }
  2798. port_mmio = mv_port_base(mmio, idx);
  2799. tmp = readl(port_mmio + PHY_MODE2);
  2800. hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
  2801. hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
  2802. }
  2803. static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
  2804. {
  2805. writel(0x00000060, mmio + GPIO_PORT_CTL);
  2806. }
  2807. static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
  2808. unsigned int port)
  2809. {
  2810. void __iomem *port_mmio = mv_port_base(mmio, port);
  2811. u32 hp_flags = hpriv->hp_flags;
  2812. int fix_phy_mode2 =
  2813. hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
  2814. int fix_phy_mode4 =
  2815. hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
  2816. u32 m2, m3;
  2817. if (fix_phy_mode2) {
  2818. m2 = readl(port_mmio + PHY_MODE2);
  2819. m2 &= ~(1 << 16);
  2820. m2 |= (1 << 31);
  2821. writel(m2, port_mmio + PHY_MODE2);
  2822. udelay(200);
  2823. m2 = readl(port_mmio + PHY_MODE2);
  2824. m2 &= ~((1 << 16) | (1 << 31));
  2825. writel(m2, port_mmio + PHY_MODE2);
  2826. udelay(200);
  2827. }
  2828. /*
  2829. * Gen-II/IIe PHY_MODE3 errata RM#2:
  2830. * Achieves better receiver noise performance than the h/w default:
  2831. */
  2832. m3 = readl(port_mmio + PHY_MODE3);
  2833. m3 = (m3 & 0x1f) | (0x5555601 << 5);
  2834. /* Guideline 88F5182 (GL# SATA-S11) */
  2835. if (IS_SOC(hpriv))
  2836. m3 &= ~0x1c;
  2837. if (fix_phy_mode4) {
  2838. u32 m4 = readl(port_mmio + PHY_MODE4);
  2839. /*
  2840. * Enforce reserved-bit restrictions on GenIIe devices only.
  2841. * For earlier chipsets, force only the internal config field
  2842. * (workaround for errata FEr SATA#10 part 1).
  2843. */
  2844. if (IS_GEN_IIE(hpriv))
  2845. m4 = (m4 & ~PHY_MODE4_RSVD_ZEROS) | PHY_MODE4_RSVD_ONES;
  2846. else
  2847. m4 = (m4 & ~PHY_MODE4_CFG_MASK) | PHY_MODE4_CFG_VALUE;
  2848. writel(m4, port_mmio + PHY_MODE4);
  2849. }
  2850. /*
  2851. * Workaround for 60x1-B2 errata SATA#13:
  2852. * Any write to PHY_MODE4 (above) may corrupt PHY_MODE3,
  2853. * so we must always rewrite PHY_MODE3 after PHY_MODE4.
  2854. * Or ensure we use writelfl() when writing PHY_MODE4.
  2855. */
  2856. writel(m3, port_mmio + PHY_MODE3);
  2857. /* Revert values of pre-emphasis and signal amps to the saved ones */
  2858. m2 = readl(port_mmio + PHY_MODE2);
  2859. m2 &= ~MV_M2_PREAMP_MASK;
  2860. m2 |= hpriv->signal[port].amps;
  2861. m2 |= hpriv->signal[port].pre;
  2862. m2 &= ~(1 << 16);
  2863. /* according to mvSata 3.6.1, some IIE values are fixed */
  2864. if (IS_GEN_IIE(hpriv)) {
  2865. m2 &= ~0xC30FF01F;
  2866. m2 |= 0x0000900F;
  2867. }
  2868. writel(m2, port_mmio + PHY_MODE2);
  2869. }
  2870. /* TODO: use the generic LED interface to configure the SATA Presence */
  2871. /* & Acitivy LEDs on the board */
  2872. static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
  2873. void __iomem *mmio)
  2874. {
  2875. return;
  2876. }
  2877. static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
  2878. void __iomem *mmio)
  2879. {
  2880. void __iomem *port_mmio;
  2881. u32 tmp;
  2882. port_mmio = mv_port_base(mmio, idx);
  2883. tmp = readl(port_mmio + PHY_MODE2);
  2884. hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
  2885. hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
  2886. }
  2887. #undef ZERO
  2888. #define ZERO(reg) writel(0, port_mmio + (reg))
  2889. static void mv_soc_reset_hc_port(struct mv_host_priv *hpriv,
  2890. void __iomem *mmio, unsigned int port)
  2891. {
  2892. void __iomem *port_mmio = mv_port_base(mmio, port);
  2893. mv_reset_channel(hpriv, mmio, port);
  2894. ZERO(0x028); /* command */
  2895. writel(0x101f, port_mmio + EDMA_CFG);
  2896. ZERO(0x004); /* timer */
  2897. ZERO(0x008); /* irq err cause */
  2898. ZERO(0x00c); /* irq err mask */
  2899. ZERO(0x010); /* rq bah */
  2900. ZERO(0x014); /* rq inp */
  2901. ZERO(0x018); /* rq outp */
  2902. ZERO(0x01c); /* respq bah */
  2903. ZERO(0x024); /* respq outp */
  2904. ZERO(0x020); /* respq inp */
  2905. ZERO(0x02c); /* test control */
  2906. writel(0xbc, port_mmio + EDMA_IORDY_TMOUT);
  2907. }
  2908. #undef ZERO
  2909. #define ZERO(reg) writel(0, hc_mmio + (reg))
  2910. static void mv_soc_reset_one_hc(struct mv_host_priv *hpriv,
  2911. void __iomem *mmio)
  2912. {
  2913. void __iomem *hc_mmio = mv_hc_base(mmio, 0);
  2914. ZERO(0x00c);
  2915. ZERO(0x010);
  2916. ZERO(0x014);
  2917. }
  2918. #undef ZERO
  2919. static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
  2920. void __iomem *mmio, unsigned int n_hc)
  2921. {
  2922. unsigned int port;
  2923. for (port = 0; port < hpriv->n_ports; port++)
  2924. mv_soc_reset_hc_port(hpriv, mmio, port);
  2925. mv_soc_reset_one_hc(hpriv, mmio);
  2926. return 0;
  2927. }
  2928. static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
  2929. void __iomem *mmio)
  2930. {
  2931. return;
  2932. }
  2933. static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio)
  2934. {
  2935. return;
  2936. }
  2937. static void mv_setup_ifcfg(void __iomem *port_mmio, int want_gen2i)
  2938. {
  2939. u32 ifcfg = readl(port_mmio + SATA_IFCFG);
  2940. ifcfg = (ifcfg & 0xf7f) | 0x9b1000; /* from chip spec */
  2941. if (want_gen2i)
  2942. ifcfg |= (1 << 7); /* enable gen2i speed */
  2943. writelfl(ifcfg, port_mmio + SATA_IFCFG);
  2944. }
  2945. static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
  2946. unsigned int port_no)
  2947. {
  2948. void __iomem *port_mmio = mv_port_base(mmio, port_no);
  2949. /*
  2950. * The datasheet warns against setting EDMA_RESET when EDMA is active
  2951. * (but doesn't say what the problem might be). So we first try
  2952. * to disable the EDMA engine before doing the EDMA_RESET operation.
  2953. */
  2954. mv_stop_edma_engine(port_mmio);
  2955. writelfl(EDMA_RESET, port_mmio + EDMA_CMD);
  2956. if (!IS_GEN_I(hpriv)) {
  2957. /* Enable 3.0gb/s link speed: this survives EDMA_RESET */
  2958. mv_setup_ifcfg(port_mmio, 1);
  2959. }
  2960. /*
  2961. * Strobing EDMA_RESET here causes a hard reset of the SATA transport,
  2962. * link, and physical layers. It resets all SATA interface registers
  2963. * (except for SATA_IFCFG), and issues a COMRESET to the dev.
  2964. */
  2965. writelfl(EDMA_RESET, port_mmio + EDMA_CMD);
  2966. udelay(25); /* allow reset propagation */
  2967. writelfl(0, port_mmio + EDMA_CMD);
  2968. hpriv->ops->phy_errata(hpriv, mmio, port_no);
  2969. if (IS_GEN_I(hpriv))
  2970. mdelay(1);
  2971. }
  2972. static void mv_pmp_select(struct ata_port *ap, int pmp)
  2973. {
  2974. if (sata_pmp_supported(ap)) {
  2975. void __iomem *port_mmio = mv_ap_base(ap);
  2976. u32 reg = readl(port_mmio + SATA_IFCTL);
  2977. int old = reg & 0xf;
  2978. if (old != pmp) {
  2979. reg = (reg & ~0xf) | pmp;
  2980. writelfl(reg, port_mmio + SATA_IFCTL);
  2981. }
  2982. }
  2983. }
  2984. static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
  2985. unsigned long deadline)
  2986. {
  2987. mv_pmp_select(link->ap, sata_srst_pmp(link));
  2988. return sata_std_hardreset(link, class, deadline);
  2989. }
  2990. static int mv_softreset(struct ata_link *link, unsigned int *class,
  2991. unsigned long deadline)
  2992. {
  2993. mv_pmp_select(link->ap, sata_srst_pmp(link));
  2994. return ata_sff_softreset(link, class, deadline);
  2995. }
  2996. static int mv_hardreset(struct ata_link *link, unsigned int *class,
  2997. unsigned long deadline)
  2998. {
  2999. struct ata_port *ap = link->ap;
  3000. struct mv_host_priv *hpriv = ap->host->private_data;
  3001. struct mv_port_priv *pp = ap->private_data;
  3002. void __iomem *mmio = hpriv->base;
  3003. int rc, attempts = 0, extra = 0;
  3004. u32 sstatus;
  3005. bool online;
  3006. mv_reset_channel(hpriv, mmio, ap->port_no);
  3007. pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
  3008. pp->pp_flags &=
  3009. ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN | MV_PP_FLAG_FAKE_ATA_BUSY);
  3010. /* Workaround for errata FEr SATA#10 (part 2) */
  3011. do {
  3012. const unsigned long *timing =
  3013. sata_ehc_deb_timing(&link->eh_context);
  3014. rc = sata_link_hardreset(link, timing, deadline + extra,
  3015. &online, NULL);
  3016. rc = online ? -EAGAIN : rc;
  3017. if (rc)
  3018. return rc;
  3019. sata_scr_read(link, SCR_STATUS, &sstatus);
  3020. if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) {
  3021. /* Force 1.5gb/s link speed and try again */
  3022. mv_setup_ifcfg(mv_ap_base(ap), 0);
  3023. if (time_after(jiffies + HZ, deadline))
  3024. extra = HZ; /* only extend it once, max */
  3025. }
  3026. } while (sstatus != 0x0 && sstatus != 0x113 && sstatus != 0x123);
  3027. mv_save_cached_regs(ap);
  3028. mv_edma_cfg(ap, 0, 0);
  3029. return rc;
  3030. }
  3031. static void mv_eh_freeze(struct ata_port *ap)
  3032. {
  3033. mv_stop_edma(ap);
  3034. mv_enable_port_irqs(ap, 0);
  3035. }
  3036. static void mv_eh_thaw(struct ata_port *ap)
  3037. {
  3038. struct mv_host_priv *hpriv = ap->host->private_data;
  3039. unsigned int port = ap->port_no;
  3040. unsigned int hardport = mv_hardport_from_port(port);
  3041. void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port);
  3042. void __iomem *port_mmio = mv_ap_base(ap);
  3043. u32 hc_irq_cause;
  3044. /* clear EDMA errors on this port */
  3045. writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE);
  3046. /* clear pending irq events */
  3047. hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport);
  3048. writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE);
  3049. mv_enable_port_irqs(ap, ERR_IRQ);
  3050. }
  3051. /**
  3052. * mv_port_init - Perform some early initialization on a single port.
  3053. * @port: libata data structure storing shadow register addresses
  3054. * @port_mmio: base address of the port
  3055. *
  3056. * Initialize shadow register mmio addresses, clear outstanding
  3057. * interrupts on the port, and unmask interrupts for the future
  3058. * start of the port.
  3059. *
  3060. * LOCKING:
  3061. * Inherited from caller.
  3062. */
  3063. static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
  3064. {
  3065. void __iomem *serr, *shd_base = port_mmio + SHD_BLK;
  3066. /* PIO related setup
  3067. */
  3068. port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
  3069. port->error_addr =
  3070. port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
  3071. port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
  3072. port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
  3073. port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
  3074. port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
  3075. port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
  3076. port->status_addr =
  3077. port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
  3078. /* special case: control/altstatus doesn't have ATA_REG_ address */
  3079. port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST;
  3080. /* unused: */
  3081. port->cmd_addr = port->bmdma_addr = port->scr_addr = NULL;
  3082. /* Clear any currently outstanding port interrupt conditions */
  3083. serr = port_mmio + mv_scr_offset(SCR_ERROR);
  3084. writelfl(readl(serr), serr);
  3085. writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE);
  3086. /* unmask all non-transient EDMA error interrupts */
  3087. writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK);
  3088. VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
  3089. readl(port_mmio + EDMA_CFG),
  3090. readl(port_mmio + EDMA_ERR_IRQ_CAUSE),
  3091. readl(port_mmio + EDMA_ERR_IRQ_MASK));
  3092. }
  3093. static unsigned int mv_in_pcix_mode(struct ata_host *host)
  3094. {
  3095. struct mv_host_priv *hpriv = host->private_data;
  3096. void __iomem *mmio = hpriv->base;
  3097. u32 reg;
  3098. if (IS_SOC(hpriv) || !IS_PCIE(hpriv))
  3099. return 0; /* not PCI-X capable */
  3100. reg = readl(mmio + MV_PCI_MODE);
  3101. if ((reg & MV_PCI_MODE_MASK) == 0)
  3102. return 0; /* conventional PCI mode */
  3103. return 1; /* chip is in PCI-X mode */
  3104. }
  3105. static int mv_pci_cut_through_okay(struct ata_host *host)
  3106. {
  3107. struct mv_host_priv *hpriv = host->private_data;
  3108. void __iomem *mmio = hpriv->base;
  3109. u32 reg;
  3110. if (!mv_in_pcix_mode(host)) {
  3111. reg = readl(mmio + MV_PCI_COMMAND);
  3112. if (reg & MV_PCI_COMMAND_MRDTRIG)
  3113. return 0; /* not okay */
  3114. }
  3115. return 1; /* okay */
  3116. }
  3117. static void mv_60x1b2_errata_pci7(struct ata_host *host)
  3118. {
  3119. struct mv_host_priv *hpriv = host->private_data;
  3120. void __iomem *mmio = hpriv->base;
  3121. /* workaround for 60x1-B2 errata PCI#7 */
  3122. if (mv_in_pcix_mode(host)) {
  3123. u32 reg = readl(mmio + MV_PCI_COMMAND);
  3124. writelfl(reg & ~MV_PCI_COMMAND_MWRCOM, mmio + MV_PCI_COMMAND);
  3125. }
  3126. }
  3127. static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
  3128. {
  3129. struct pci_dev *pdev = to_pci_dev(host->dev);
  3130. struct mv_host_priv *hpriv = host->private_data;
  3131. u32 hp_flags = hpriv->hp_flags;
  3132. switch (board_idx) {
  3133. case chip_5080:
  3134. hpriv->ops = &mv5xxx_ops;
  3135. hp_flags |= MV_HP_GEN_I;
  3136. switch (pdev->revision) {
  3137. case 0x1:
  3138. hp_flags |= MV_HP_ERRATA_50XXB0;
  3139. break;
  3140. case 0x3:
  3141. hp_flags |= MV_HP_ERRATA_50XXB2;
  3142. break;
  3143. default:
  3144. dev_printk(KERN_WARNING, &pdev->dev,
  3145. "Applying 50XXB2 workarounds to unknown rev\n");
  3146. hp_flags |= MV_HP_ERRATA_50XXB2;
  3147. break;
  3148. }
  3149. break;
  3150. case chip_504x:
  3151. case chip_508x:
  3152. hpriv->ops = &mv5xxx_ops;
  3153. hp_flags |= MV_HP_GEN_I;
  3154. switch (pdev->revision) {
  3155. case 0x0:
  3156. hp_flags |= MV_HP_ERRATA_50XXB0;
  3157. break;
  3158. case 0x3:
  3159. hp_flags |= MV_HP_ERRATA_50XXB2;
  3160. break;
  3161. default:
  3162. dev_printk(KERN_WARNING, &pdev->dev,
  3163. "Applying B2 workarounds to unknown rev\n");
  3164. hp_flags |= MV_HP_ERRATA_50XXB2;
  3165. break;
  3166. }
  3167. break;
  3168. case chip_604x:
  3169. case chip_608x:
  3170. hpriv->ops = &mv6xxx_ops;
  3171. hp_flags |= MV_HP_GEN_II;
  3172. switch (pdev->revision) {
  3173. case 0x7:
  3174. mv_60x1b2_errata_pci7(host);
  3175. hp_flags |= MV_HP_ERRATA_60X1B2;
  3176. break;
  3177. case 0x9:
  3178. hp_flags |= MV_HP_ERRATA_60X1C0;
  3179. break;
  3180. default:
  3181. dev_printk(KERN_WARNING, &pdev->dev,
  3182. "Applying B2 workarounds to unknown rev\n");
  3183. hp_flags |= MV_HP_ERRATA_60X1B2;
  3184. break;
  3185. }
  3186. break;
  3187. case chip_7042:
  3188. hp_flags |= MV_HP_PCIE | MV_HP_CUT_THROUGH;
  3189. if (pdev->vendor == PCI_VENDOR_ID_TTI &&
  3190. (pdev->device == 0x2300 || pdev->device == 0x2310))
  3191. {
  3192. /*
  3193. * Highpoint RocketRAID PCIe 23xx series cards:
  3194. *
  3195. * Unconfigured drives are treated as "Legacy"
  3196. * by the BIOS, and it overwrites sector 8 with
  3197. * a "Lgcy" metadata block prior to Linux boot.
  3198. *
  3199. * Configured drives (RAID or JBOD) leave sector 8
  3200. * alone, but instead overwrite a high numbered
  3201. * sector for the RAID metadata. This sector can
  3202. * be determined exactly, by truncating the physical
  3203. * drive capacity to a nice even GB value.
  3204. *
  3205. * RAID metadata is at: (dev->n_sectors & ~0xfffff)
  3206. *
  3207. * Warn the user, lest they think we're just buggy.
  3208. */
  3209. printk(KERN_WARNING DRV_NAME ": Highpoint RocketRAID"
  3210. " BIOS CORRUPTS DATA on all attached drives,"
  3211. " regardless of if/how they are configured."
  3212. " BEWARE!\n");
  3213. printk(KERN_WARNING DRV_NAME ": For data safety, do not"
  3214. " use sectors 8-9 on \"Legacy\" drives,"
  3215. " and avoid the final two gigabytes on"
  3216. " all RocketRAID BIOS initialized drives.\n");
  3217. }
  3218. /* drop through */
  3219. case chip_6042:
  3220. hpriv->ops = &mv6xxx_ops;
  3221. hp_flags |= MV_HP_GEN_IIE;
  3222. if (board_idx == chip_6042 && mv_pci_cut_through_okay(host))
  3223. hp_flags |= MV_HP_CUT_THROUGH;
  3224. switch (pdev->revision) {
  3225. case 0x2: /* Rev.B0: the first/only public release */
  3226. hp_flags |= MV_HP_ERRATA_60X1C0;
  3227. break;
  3228. default:
  3229. dev_printk(KERN_WARNING, &pdev->dev,
  3230. "Applying 60X1C0 workarounds to unknown rev\n");
  3231. hp_flags |= MV_HP_ERRATA_60X1C0;
  3232. break;
  3233. }
  3234. break;
  3235. case chip_soc:
  3236. hpriv->ops = &mv_soc_ops;
  3237. hp_flags |= MV_HP_FLAG_SOC | MV_HP_GEN_IIE |
  3238. MV_HP_ERRATA_60X1C0;
  3239. break;
  3240. default:
  3241. dev_printk(KERN_ERR, host->dev,
  3242. "BUG: invalid board index %u\n", board_idx);
  3243. return 1;
  3244. }
  3245. hpriv->hp_flags = hp_flags;
  3246. if (hp_flags & MV_HP_PCIE) {
  3247. hpriv->irq_cause_offset = PCIE_IRQ_CAUSE;
  3248. hpriv->irq_mask_offset = PCIE_IRQ_MASK;
  3249. hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS;
  3250. } else {
  3251. hpriv->irq_cause_offset = PCI_IRQ_CAUSE;
  3252. hpriv->irq_mask_offset = PCI_IRQ_MASK;
  3253. hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS;
  3254. }
  3255. return 0;
  3256. }
  3257. /**
  3258. * mv_init_host - Perform some early initialization of the host.
  3259. * @host: ATA host to initialize
  3260. * @board_idx: controller index
  3261. *
  3262. * If possible, do an early global reset of the host. Then do
  3263. * our port init and clear/unmask all/relevant host interrupts.
  3264. *
  3265. * LOCKING:
  3266. * Inherited from caller.
  3267. */
  3268. static int mv_init_host(struct ata_host *host, unsigned int board_idx)
  3269. {
  3270. int rc = 0, n_hc, port, hc;
  3271. struct mv_host_priv *hpriv = host->private_data;
  3272. void __iomem *mmio = hpriv->base;
  3273. rc = mv_chip_id(host, board_idx);
  3274. if (rc)
  3275. goto done;
  3276. if (IS_SOC(hpriv)) {
  3277. hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE;
  3278. hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK;
  3279. } else {
  3280. hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE;
  3281. hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK;
  3282. }
  3283. /* initialize shadow irq mask with register's value */
  3284. hpriv->main_irq_mask = readl(hpriv->main_irq_mask_addr);
  3285. /* global interrupt mask: 0 == mask everything */
  3286. mv_set_main_irq_mask(host, ~0, 0);
  3287. n_hc = mv_get_hc_count(host->ports[0]->flags);
  3288. for (port = 0; port < host->n_ports; port++)
  3289. hpriv->ops->read_preamp(hpriv, port, mmio);
  3290. rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
  3291. if (rc)
  3292. goto done;
  3293. hpriv->ops->reset_flash(hpriv, mmio);
  3294. hpriv->ops->reset_bus(host, mmio);
  3295. hpriv->ops->enable_leds(hpriv, mmio);
  3296. for (port = 0; port < host->n_ports; port++) {
  3297. struct ata_port *ap = host->ports[port];
  3298. void __iomem *port_mmio = mv_port_base(mmio, port);
  3299. mv_port_init(&ap->ioaddr, port_mmio);
  3300. #ifdef CONFIG_PCI
  3301. if (!IS_SOC(hpriv)) {
  3302. unsigned int offset = port_mmio - mmio;
  3303. ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio");
  3304. ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port");
  3305. }
  3306. #endif
  3307. }
  3308. for (hc = 0; hc < n_hc; hc++) {
  3309. void __iomem *hc_mmio = mv_hc_base(mmio, hc);
  3310. VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
  3311. "(before clear)=0x%08x\n", hc,
  3312. readl(hc_mmio + HC_CFG),
  3313. readl(hc_mmio + HC_IRQ_CAUSE));
  3314. /* Clear any currently outstanding hc interrupt conditions */
  3315. writelfl(0, hc_mmio + HC_IRQ_CAUSE);
  3316. }
  3317. if (!IS_SOC(hpriv)) {
  3318. /* Clear any currently outstanding host interrupt conditions */
  3319. writelfl(0, mmio + hpriv->irq_cause_offset);
  3320. /* and unmask interrupt generation for host regs */
  3321. writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_offset);
  3322. }
  3323. /*
  3324. * enable only global host interrupts for now.
  3325. * The per-port interrupts get done later as ports are set up.
  3326. */
  3327. mv_set_main_irq_mask(host, 0, PCI_ERR);
  3328. mv_set_irq_coalescing(host, irq_coalescing_io_count,
  3329. irq_coalescing_usecs);
  3330. done:
  3331. return rc;
  3332. }
  3333. static int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev)
  3334. {
  3335. hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ,
  3336. MV_CRQB_Q_SZ, 0);
  3337. if (!hpriv->crqb_pool)
  3338. return -ENOMEM;
  3339. hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ,
  3340. MV_CRPB_Q_SZ, 0);
  3341. if (!hpriv->crpb_pool)
  3342. return -ENOMEM;
  3343. hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ,
  3344. MV_SG_TBL_SZ, 0);
  3345. if (!hpriv->sg_tbl_pool)
  3346. return -ENOMEM;
  3347. return 0;
  3348. }
  3349. static void mv_conf_mbus_windows(struct mv_host_priv *hpriv,
  3350. struct mbus_dram_target_info *dram)
  3351. {
  3352. int i;
  3353. for (i = 0; i < 4; i++) {
  3354. writel(0, hpriv->base + WINDOW_CTRL(i));
  3355. writel(0, hpriv->base + WINDOW_BASE(i));
  3356. }
  3357. for (i = 0; i < dram->num_cs; i++) {
  3358. struct mbus_dram_window *cs = dram->cs + i;
  3359. writel(((cs->size - 1) & 0xffff0000) |
  3360. (cs->mbus_attr << 8) |
  3361. (dram->mbus_dram_target_id << 4) | 1,
  3362. hpriv->base + WINDOW_CTRL(i));
  3363. writel(cs->base, hpriv->base + WINDOW_BASE(i));
  3364. }
  3365. }
  3366. /**
  3367. * mv_platform_probe - handle a positive probe of an soc Marvell
  3368. * host
  3369. * @pdev: platform device found
  3370. *
  3371. * LOCKING:
  3372. * Inherited from caller.
  3373. */
  3374. static int mv_platform_probe(struct platform_device *pdev)
  3375. {
  3376. static int printed_version;
  3377. const struct mv_sata_platform_data *mv_platform_data;
  3378. const struct ata_port_info *ppi[] =
  3379. { &mv_port_info[chip_soc], NULL };
  3380. struct ata_host *host;
  3381. struct mv_host_priv *hpriv;
  3382. struct resource *res;
  3383. int n_ports, rc;
  3384. if (!printed_version++)
  3385. dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
  3386. /*
  3387. * Simple resource validation ..
  3388. */
  3389. if (unlikely(pdev->num_resources != 2)) {
  3390. dev_err(&pdev->dev, "invalid number of resources\n");
  3391. return -EINVAL;
  3392. }
  3393. /*
  3394. * Get the register base first
  3395. */
  3396. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  3397. if (res == NULL)
  3398. return -EINVAL;
  3399. /* allocate host */
  3400. mv_platform_data = pdev->dev.platform_data;
  3401. n_ports = mv_platform_data->n_ports;
  3402. host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
  3403. hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
  3404. if (!host || !hpriv)
  3405. return -ENOMEM;
  3406. host->private_data = hpriv;
  3407. hpriv->n_ports = n_ports;
  3408. host->iomap = NULL;
  3409. hpriv->base = devm_ioremap(&pdev->dev, res->start,
  3410. res->end - res->start + 1);
  3411. hpriv->base -= SATAHC0_REG_BASE;
  3412. /*
  3413. * (Re-)program MBUS remapping windows if we are asked to.
  3414. */
  3415. if (mv_platform_data->dram != NULL)
  3416. mv_conf_mbus_windows(hpriv, mv_platform_data->dram);
  3417. rc = mv_create_dma_pools(hpriv, &pdev->dev);
  3418. if (rc)
  3419. return rc;
  3420. /* initialize adapter */
  3421. rc = mv_init_host(host, chip_soc);
  3422. if (rc)
  3423. return rc;
  3424. dev_printk(KERN_INFO, &pdev->dev,
  3425. "slots %u ports %d\n", (unsigned)MV_MAX_Q_DEPTH,
  3426. host->n_ports);
  3427. return ata_host_activate(host, platform_get_irq(pdev, 0), mv_interrupt,
  3428. IRQF_SHARED, &mv6_sht);
  3429. }
  3430. /*
  3431. *
  3432. * mv_platform_remove - unplug a platform interface
  3433. * @pdev: platform device
  3434. *
  3435. * A platform bus SATA device has been unplugged. Perform the needed
  3436. * cleanup. Also called on module unload for any active devices.
  3437. */
  3438. static int __devexit mv_platform_remove(struct platform_device *pdev)
  3439. {
  3440. struct device *dev = &pdev->dev;
  3441. struct ata_host *host = dev_get_drvdata(dev);
  3442. ata_host_detach(host);
  3443. return 0;
  3444. }
  3445. static struct platform_driver mv_platform_driver = {
  3446. .probe = mv_platform_probe,
  3447. .remove = __devexit_p(mv_platform_remove),
  3448. .driver = {
  3449. .name = DRV_NAME,
  3450. .owner = THIS_MODULE,
  3451. },
  3452. };
  3453. #ifdef CONFIG_PCI
  3454. static int mv_pci_init_one(struct pci_dev *pdev,
  3455. const struct pci_device_id *ent);
  3456. static struct pci_driver mv_pci_driver = {
  3457. .name = DRV_NAME,
  3458. .id_table = mv_pci_tbl,
  3459. .probe = mv_pci_init_one,
  3460. .remove = ata_pci_remove_one,
  3461. };
  3462. /* move to PCI layer or libata core? */
  3463. static int pci_go_64(struct pci_dev *pdev)
  3464. {
  3465. int rc;
  3466. if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
  3467. rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
  3468. if (rc) {
  3469. rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
  3470. if (rc) {
  3471. dev_printk(KERN_ERR, &pdev->dev,
  3472. "64-bit DMA enable failed\n");
  3473. return rc;
  3474. }
  3475. }
  3476. } else {
  3477. rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  3478. if (rc) {
  3479. dev_printk(KERN_ERR, &pdev->dev,
  3480. "32-bit DMA enable failed\n");
  3481. return rc;
  3482. }
  3483. rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
  3484. if (rc) {
  3485. dev_printk(KERN_ERR, &pdev->dev,
  3486. "32-bit consistent DMA enable failed\n");
  3487. return rc;
  3488. }
  3489. }
  3490. return rc;
  3491. }
  3492. /**
  3493. * mv_print_info - Dump key info to kernel log for perusal.
  3494. * @host: ATA host to print info about
  3495. *
  3496. * FIXME: complete this.
  3497. *
  3498. * LOCKING:
  3499. * Inherited from caller.
  3500. */
  3501. static void mv_print_info(struct ata_host *host)
  3502. {
  3503. struct pci_dev *pdev = to_pci_dev(host->dev);
  3504. struct mv_host_priv *hpriv = host->private_data;
  3505. u8 scc;
  3506. const char *scc_s, *gen;
  3507. /* Use this to determine the HW stepping of the chip so we know
  3508. * what errata to workaround
  3509. */
  3510. pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
  3511. if (scc == 0)
  3512. scc_s = "SCSI";
  3513. else if (scc == 0x01)
  3514. scc_s = "RAID";
  3515. else
  3516. scc_s = "?";
  3517. if (IS_GEN_I(hpriv))
  3518. gen = "I";
  3519. else if (IS_GEN_II(hpriv))
  3520. gen = "II";
  3521. else if (IS_GEN_IIE(hpriv))
  3522. gen = "IIE";
  3523. else
  3524. gen = "?";
  3525. dev_printk(KERN_INFO, &pdev->dev,
  3526. "Gen-%s %u slots %u ports %s mode IRQ via %s\n",
  3527. gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports,
  3528. scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
  3529. }
  3530. /**
  3531. * mv_pci_init_one - handle a positive probe of a PCI Marvell host
  3532. * @pdev: PCI device found
  3533. * @ent: PCI device ID entry for the matched host
  3534. *
  3535. * LOCKING:
  3536. * Inherited from caller.
  3537. */
  3538. static int mv_pci_init_one(struct pci_dev *pdev,
  3539. const struct pci_device_id *ent)
  3540. {
  3541. static int printed_version;
  3542. unsigned int board_idx = (unsigned int)ent->driver_data;
  3543. const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL };
  3544. struct ata_host *host;
  3545. struct mv_host_priv *hpriv;
  3546. int n_ports, rc;
  3547. if (!printed_version++)
  3548. dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
  3549. /* allocate host */
  3550. n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC;
  3551. host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
  3552. hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
  3553. if (!host || !hpriv)
  3554. return -ENOMEM;
  3555. host->private_data = hpriv;
  3556. hpriv->n_ports = n_ports;
  3557. /* acquire resources */
  3558. rc = pcim_enable_device(pdev);
  3559. if (rc)
  3560. return rc;
  3561. rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME);
  3562. if (rc == -EBUSY)
  3563. pcim_pin_device(pdev);
  3564. if (rc)
  3565. return rc;
  3566. host->iomap = pcim_iomap_table(pdev);
  3567. hpriv->base = host->iomap[MV_PRIMARY_BAR];
  3568. rc = pci_go_64(pdev);
  3569. if (rc)
  3570. return rc;
  3571. rc = mv_create_dma_pools(hpriv, &pdev->dev);
  3572. if (rc)
  3573. return rc;
  3574. /* initialize adapter */
  3575. rc = mv_init_host(host, board_idx);
  3576. if (rc)
  3577. return rc;
  3578. /* Enable message-switched interrupts, if requested */
  3579. if (msi && pci_enable_msi(pdev) == 0)
  3580. hpriv->hp_flags |= MV_HP_FLAG_MSI;
  3581. mv_dump_pci_cfg(pdev, 0x68);
  3582. mv_print_info(host);
  3583. pci_set_master(pdev);
  3584. pci_try_set_mwi(pdev);
  3585. return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED,
  3586. IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht);
  3587. }
  3588. #endif
  3589. static int mv_platform_probe(struct platform_device *pdev);
  3590. static int __devexit mv_platform_remove(struct platform_device *pdev);
  3591. static int __init mv_init(void)
  3592. {
  3593. int rc = -ENODEV;
  3594. #ifdef CONFIG_PCI
  3595. rc = pci_register_driver(&mv_pci_driver);
  3596. if (rc < 0)
  3597. return rc;
  3598. #endif
  3599. rc = platform_driver_register(&mv_platform_driver);
  3600. #ifdef CONFIG_PCI
  3601. if (rc < 0)
  3602. pci_unregister_driver(&mv_pci_driver);
  3603. #endif
  3604. return rc;
  3605. }
  3606. static void __exit mv_exit(void)
  3607. {
  3608. #ifdef CONFIG_PCI
  3609. pci_unregister_driver(&mv_pci_driver);
  3610. #endif
  3611. platform_driver_unregister(&mv_platform_driver);
  3612. }
  3613. MODULE_AUTHOR("Brett Russ");
  3614. MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
  3615. MODULE_LICENSE("GPL");
  3616. MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
  3617. MODULE_VERSION(DRV_VERSION);
  3618. MODULE_ALIAS("platform:" DRV_NAME);
  3619. module_init(mv_init);
  3620. module_exit(mv_exit);