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asm
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dma-sh.h

dma-sh.h 2.8 KB
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  1. /*
    2. 

  2.  * arch/sh/include/asm/dma-sh.h
    3. 

  3.  *
    4. 

  4.  * Copyright (C) 2000  Takashi YOSHII
    5. 

  5.  * Copyright (C) 2003  Paul Mundt
    6. 

  6.  *
    7. 

  7.  * This file is subject to the terms and conditions of the GNU General Public
    8. 

  8.  * License.  See the file "COPYING" in the main directory of this archive
    9. 

  9.  * for more details.
    10. 

  10.  */
    11. 

  11. #ifndef __DMA_SH_H
    12. 

  12. #define __DMA_SH_H
    13. 

  13. 

  14. #include <asm/dma.h>
    15. 

  15. #include <cpu/dma.h>
    16. 

  16. 

  17. /* DMAOR contorl: The DMAOR access size is different by CPU.*/
    18. 

  18. #if defined(CONFIG_CPU_SUBTYPE_SH7723)	|| \
    19. 

  19.     defined(CONFIG_CPU_SUBTYPE_SH7780)	|| \
    20. 

  20.     defined(CONFIG_CPU_SUBTYPE_SH7785)
    21. 

  21. #define dmaor_read_reg(n) \
    22. 

  22.     (n ? ctrl_inw(SH_DMAC_BASE1 + DMAOR) \
    23. 

  23. 	: ctrl_inw(SH_DMAC_BASE0 + DMAOR))
    24. 

  24. #define dmaor_write_reg(n, data) \
    25. 

  25.     (n ? ctrl_outw(data, SH_DMAC_BASE1 + DMAOR) \
    26. 

  26.     : ctrl_outw(data, SH_DMAC_BASE0 + DMAOR))
    27. 

  27. #else /* Other CPU */
    28. 

  28. #define dmaor_read_reg(n) ctrl_inw(SH_DMAC_BASE0 + DMAOR)
    29. 

  29. #define dmaor_write_reg(n, data) ctrl_outw(data, SH_DMAC_BASE0 + DMAOR)
    30. 

  30. #endif
    31. 

  31. 

  32. static int dmte_irq_map[] __maybe_unused = {
    33. 

  33. #if (MAX_DMA_CHANNELS >= 4)
    34. 

  34.     DMTE0_IRQ,
    35. 

  35.     DMTE0_IRQ + 1,
    36. 

  36.     DMTE0_IRQ + 2,
    37. 

  37.     DMTE0_IRQ + 3,
    38. 

  38. #endif
    39. 

  39. #if (MAX_DMA_CHANNELS >= 6)
    40. 

  40.     DMTE4_IRQ,
    41. 

  41.     DMTE4_IRQ + 1,
    42. 

  42. #endif
    43. 

  43. #if (MAX_DMA_CHANNELS >= 8)
    44. 

  44.     DMTE6_IRQ,
    45. 

  45.     DMTE6_IRQ + 1,
    46. 

  46. #endif
    47. 

  47. #if (MAX_DMA_CHANNELS >= 12)
    48. 

  48.     DMTE8_IRQ,
    49. 

  49.     DMTE9_IRQ,
    50. 

  50.     DMTE10_IRQ,
    51. 

  51.     DMTE11_IRQ,
    52. 

  52. #endif
    53. 

  53. };
    54. 

  54. 

  55. /* Definitions for the SuperH DMAC */
    56. 

  56. #define REQ_L	0x00000000
    57. 

  57. #define REQ_E	0x00080000
    58. 

  58. #define RACK_H	0x00000000
    59. 

  59. #define RACK_L	0x00040000
    60. 

  60. #define ACK_R	0x00000000
    61. 

  61. #define ACK_W	0x00020000
    62. 

  62. #define ACK_H	0x00000000
    63. 

  63. #define ACK_L	0x00010000
    64. 

  64. #define DM_INC	0x00004000
    65. 

  65. #define DM_DEC	0x00008000
    66. 

  66. #define SM_INC	0x00001000
    67. 

  67. #define SM_DEC	0x00002000
    68. 

  68. #define RS_IN	0x00000200
    69. 

  69. #define RS_OUT	0x00000300
    70. 

  70. #define TS_BLK	0x00000040
    71. 

  71. #define TM_BUR	0x00000020
    72. 

  72. #define CHCR_DE 0x00000001
    73. 

  73. #define CHCR_TE 0x00000002
    74. 

  74. #define CHCR_IE 0x00000004
    75. 

  75. 

  76. /* DMAOR definitions */
    77. 

  77. #define DMAOR_AE	0x00000004
    78. 

  78. #define DMAOR_NMIF	0x00000002
    79. 

  79. #define DMAOR_DME	0x00000001
    80. 

  80. 

  81. /*
    82. 

  82.  * Define the default configuration for dual address memory-memory transfer.
    83. 

  83.  * The 0x400 value represents auto-request, external->external.
    84. 

  84.  */
    85. 

  85. #define RS_DUAL	(DM_INC | SM_INC | 0x400 | TS_32)
    86. 

  86. 

  87. /* DMA base address */
    88. 

  88. static u32 dma_base_addr[] __maybe_unused = {
    89. 

  89. #if (MAX_DMA_CHANNELS >= 4)
    90. 

  90. 	SH_DMAC_BASE0 + 0x00,	/* channel 0 */
    91. 

  91. 	SH_DMAC_BASE0 + 0x10,
    92. 

  92. 	SH_DMAC_BASE0 + 0x20,
    93. 

  93. 	SH_DMAC_BASE0 + 0x30,
    94. 

  94. #endif
    95. 

  95. #if (MAX_DMA_CHANNELS >= 6)
    96. 

  96. 	SH_DMAC_BASE0 + 0x50,
    97. 

  97. 	SH_DMAC_BASE0 + 0x60,
    98. 

  98. #endif
    99. 

  99. #if (MAX_DMA_CHANNELS >= 8)
    100. 

  100. 	SH_DMAC_BASE1 + 0x00,
    101. 

  101. 	SH_DMAC_BASE1 + 0x10,
    102. 

  102. #endif
    103. 

  103. #if (MAX_DMA_CHANNELS >= 12)
    104. 

  104. 	SH_DMAC_BASE1 + 0x20,
    105. 

  105. 	SH_DMAC_BASE1 + 0x30,
    106. 

  106. 	SH_DMAC_BASE1 + 0x50,
    107. 

  107. 	SH_DMAC_BASE1 + 0x60, /* channel 11 */
    108. 

  108. #endif
    109. 

  109. };
    110. 

  110. 

  111. /* DMA register */
    112. 

  112. #define SAR     0x00
    113. 

  113. #define DAR     0x04
    114. 

  114. #define TCR     0x08
    115. 

  115. #define CHCR    0x0C
    116. 

  116. #define DMAOR	0x40
    117. 

  117. 

  118. #endif /* __DMA_SH_H */
    119.