ops-sh5.c 2.0 KB

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  1. /*
  2. * Support functions for the SH5 PCI hardware.
  3. *
  4. * Copyright (C) 2001 David J. Mckay (david.mckay@st.com)
  5. * Copyright (C) 2003, 2004 Paul Mundt
  6. * Copyright (C) 2004 Richard Curnow
  7. *
  8. * May be copied or modified under the terms of the GNU General Public
  9. * License. See linux/COPYING for more information.
  10. */
  11. #include <linux/kernel.h>
  12. #include <linux/rwsem.h>
  13. #include <linux/smp.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/init.h>
  16. #include <linux/errno.h>
  17. #include <linux/pci.h>
  18. #include <linux/delay.h>
  19. #include <linux/types.h>
  20. #include <linux/irq.h>
  21. #include <asm/pci.h>
  22. #include <asm/io.h>
  23. #include "pci-sh5.h"
  24. static void __init pci_fixup_ide_bases(struct pci_dev *d)
  25. {
  26. int i;
  27. /*
  28. * PCI IDE controllers use non-standard I/O port decoding, respect it.
  29. */
  30. if ((d->class >> 8) != PCI_CLASS_STORAGE_IDE)
  31. return;
  32. printk("PCI: IDE base address fixup for %s\n", pci_name(d));
  33. for(i=0; i<4; i++) {
  34. struct resource *r = &d->resource[i];
  35. if ((r->start & ~0x80) == 0x374) {
  36. r->start |= 2;
  37. r->end = r->start;
  38. }
  39. }
  40. }
  41. DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases);
  42. char * __devinit pcibios_setup(char *str)
  43. {
  44. return str;
  45. }
  46. static int sh5pci_read(struct pci_bus *bus, unsigned int devfn, int where,
  47. int size, u32 *val)
  48. {
  49. SH5PCI_WRITE(PAR, CONFIG_CMD(bus, devfn, where));
  50. switch (size) {
  51. case 1:
  52. *val = (u8)SH5PCI_READ_BYTE(PDR + (where & 3));
  53. break;
  54. case 2:
  55. *val = (u16)SH5PCI_READ_SHORT(PDR + (where & 2));
  56. break;
  57. case 4:
  58. *val = SH5PCI_READ(PDR);
  59. break;
  60. }
  61. return PCIBIOS_SUCCESSFUL;
  62. }
  63. static int sh5pci_write(struct pci_bus *bus, unsigned int devfn, int where,
  64. int size, u32 val)
  65. {
  66. SH5PCI_WRITE(PAR, CONFIG_CMD(bus, devfn, where));
  67. switch (size) {
  68. case 1:
  69. SH5PCI_WRITE_BYTE(PDR + (where & 3), (u8)val);
  70. break;
  71. case 2:
  72. SH5PCI_WRITE_SHORT(PDR + (where & 2), (u16)val);
  73. break;
  74. case 4:
  75. SH5PCI_WRITE(PDR, val);
  76. break;
  77. }
  78. return PCIBIOS_SUCCESSFUL;
  79. }
  80. struct pci_ops sh5_pci_ops = {
  81. .read = sh5pci_read,
  82. .write = sh5pci_write,
  83. };