cm_bf533.c 10 KB

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  1. /*
  2. * File: arch/blackfin/mach-bf533/boards/cm_bf533.c
  3. * Based on: arch/blackfin/mach-bf533/boards/ezkit.c
  4. * Author: Aidan Williams <aidan@nicta.com.au> Copyright 2005
  5. *
  6. * Created: 2005
  7. * Description: Board description file
  8. *
  9. * Modified:
  10. * Copyright 2004-2006 Analog Devices Inc.
  11. *
  12. * Bugs: Enter bugs at http://blackfin.uclinux.org/
  13. *
  14. * This program is free software; you can redistribute it and/or modify
  15. * it under the terms of the GNU General Public License as published by
  16. * the Free Software Foundation; either version 2 of the License, or
  17. * (at your option) any later version.
  18. *
  19. * This program is distributed in the hope that it will be useful,
  20. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  22. * GNU General Public License for more details.
  23. *
  24. * You should have received a copy of the GNU General Public License
  25. * along with this program; if not, see the file COPYING, or write
  26. * to the Free Software Foundation, Inc.,
  27. * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  28. */
  29. #include <linux/device.h>
  30. #include <linux/platform_device.h>
  31. #include <linux/mtd/mtd.h>
  32. #include <linux/mtd/partitions.h>
  33. #include <linux/spi/spi.h>
  34. #include <linux/spi/flash.h>
  35. #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
  36. #include <linux/usb/isp1362.h>
  37. #endif
  38. #include <linux/irq.h>
  39. #include <asm/dma.h>
  40. #include <asm/bfin5xx_spi.h>
  41. #include <asm/portmux.h>
  42. #include <asm/dpmc.h>
  43. /*
  44. * Name the Board for the /proc/cpuinfo
  45. */
  46. const char bfin_board_name[] = "Bluetechnix CM BF533";
  47. #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
  48. /* all SPI peripherals info goes here */
  49. #if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
  50. static struct mtd_partition bfin_spi_flash_partitions[] = {
  51. {
  52. .name = "bootloader(spi)",
  53. .size = 0x00020000,
  54. .offset = 0,
  55. .mask_flags = MTD_CAP_ROM
  56. }, {
  57. .name = "linux kernel(spi)",
  58. .size = 0xe0000,
  59. .offset = 0x20000
  60. }, {
  61. .name = "file system(spi)",
  62. .size = 0x700000,
  63. .offset = 0x00100000,
  64. }
  65. };
  66. static struct flash_platform_data bfin_spi_flash_data = {
  67. .name = "m25p80",
  68. .parts = bfin_spi_flash_partitions,
  69. .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
  70. .type = "m25p64",
  71. };
  72. /* SPI flash chip (m25p64) */
  73. static struct bfin5xx_spi_chip spi_flash_chip_info = {
  74. .enable_dma = 0, /* use dma transfer with this chip*/
  75. .bits_per_word = 8,
  76. };
  77. #endif
  78. /* SPI ADC chip */
  79. #if defined(CONFIG_SPI_ADC_BF533) || defined(CONFIG_SPI_ADC_BF533_MODULE)
  80. static struct bfin5xx_spi_chip spi_adc_chip_info = {
  81. .enable_dma = 1, /* use dma transfer with this chip*/
  82. .bits_per_word = 16,
  83. };
  84. #endif
  85. #if defined(CONFIG_SND_BLACKFIN_AD1836) || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
  86. static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
  87. .enable_dma = 0,
  88. .bits_per_word = 16,
  89. };
  90. #endif
  91. #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
  92. static struct bfin5xx_spi_chip mmc_spi_chip_info = {
  93. .enable_dma = 0,
  94. .bits_per_word = 8,
  95. };
  96. #endif
  97. static struct spi_board_info bfin_spi_board_info[] __initdata = {
  98. #if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
  99. {
  100. /* the modalias must be the same as spi device driver name */
  101. .modalias = "m25p80", /* Name of spi_driver for this device */
  102. .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
  103. .bus_num = 0, /* Framework bus number */
  104. .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
  105. .platform_data = &bfin_spi_flash_data,
  106. .controller_data = &spi_flash_chip_info,
  107. .mode = SPI_MODE_3,
  108. },
  109. #endif
  110. #if defined(CONFIG_SPI_ADC_BF533) || defined(CONFIG_SPI_ADC_BF533_MODULE)
  111. {
  112. .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
  113. .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
  114. .bus_num = 0, /* Framework bus number */
  115. .chip_select = 2, /* Framework chip select. */
  116. .platform_data = NULL, /* No spi_driver specific config */
  117. .controller_data = &spi_adc_chip_info,
  118. },
  119. #endif
  120. #if defined(CONFIG_SND_BLACKFIN_AD1836) || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
  121. {
  122. .modalias = "ad1836-spi",
  123. .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
  124. .bus_num = 0,
  125. .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT,
  126. .controller_data = &ad1836_spi_chip_info,
  127. },
  128. #endif
  129. #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
  130. {
  131. .modalias = "mmc_spi",
  132. .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
  133. .bus_num = 0,
  134. .chip_select = 5,
  135. .controller_data = &mmc_spi_chip_info,
  136. .mode = SPI_MODE_3,
  137. },
  138. #endif
  139. };
  140. /* SPI (0) */
  141. static struct resource bfin_spi0_resource[] = {
  142. [0] = {
  143. .start = SPI0_REGBASE,
  144. .end = SPI0_REGBASE + 0xFF,
  145. .flags = IORESOURCE_MEM,
  146. },
  147. [1] = {
  148. .start = CH_SPI,
  149. .end = CH_SPI,
  150. .flags = IORESOURCE_IRQ,
  151. }
  152. };
  153. /* SPI controller data */
  154. static struct bfin5xx_spi_master bfin_spi0_info = {
  155. .num_chipselect = 8,
  156. .enable_dma = 1, /* master has the ability to do dma transfer */
  157. .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
  158. };
  159. static struct platform_device bfin_spi0_device = {
  160. .name = "bfin-spi",
  161. .id = 0, /* Bus number */
  162. .num_resources = ARRAY_SIZE(bfin_spi0_resource),
  163. .resource = bfin_spi0_resource,
  164. .dev = {
  165. .platform_data = &bfin_spi0_info, /* Passed to driver */
  166. },
  167. };
  168. #endif /* spi master and devices */
  169. #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
  170. static struct platform_device rtc_device = {
  171. .name = "rtc-bfin",
  172. .id = -1,
  173. };
  174. #endif
  175. #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
  176. static struct resource smc91x_resources[] = {
  177. {
  178. .start = 0x20200300,
  179. .end = 0x20200300 + 16,
  180. .flags = IORESOURCE_MEM,
  181. }, {
  182. .start = IRQ_PF0,
  183. .end = IRQ_PF0,
  184. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
  185. },
  186. };
  187. static struct platform_device smc91x_device = {
  188. .name = "smc91x",
  189. .id = 0,
  190. .num_resources = ARRAY_SIZE(smc91x_resources),
  191. .resource = smc91x_resources,
  192. };
  193. #endif
  194. static struct resource bfin_gpios_resources = {
  195. .start = 0,
  196. .end = MAX_BLACKFIN_GPIOS - 1,
  197. .flags = IORESOURCE_IRQ,
  198. };
  199. static struct platform_device bfin_gpios_device = {
  200. .name = "simple-gpio",
  201. .id = -1,
  202. .num_resources = 1,
  203. .resource = &bfin_gpios_resources,
  204. };
  205. #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
  206. static struct resource bfin_uart_resources[] = {
  207. {
  208. .start = 0xFFC00400,
  209. .end = 0xFFC004FF,
  210. .flags = IORESOURCE_MEM,
  211. },
  212. };
  213. static struct platform_device bfin_uart_device = {
  214. .name = "bfin-uart",
  215. .id = 1,
  216. .num_resources = ARRAY_SIZE(bfin_uart_resources),
  217. .resource = bfin_uart_resources,
  218. };
  219. #endif
  220. #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
  221. #ifdef CONFIG_BFIN_SIR0
  222. static struct resource bfin_sir0_resources[] = {
  223. {
  224. .start = 0xFFC00400,
  225. .end = 0xFFC004FF,
  226. .flags = IORESOURCE_MEM,
  227. },
  228. {
  229. .start = IRQ_UART0_RX,
  230. .end = IRQ_UART0_RX+1,
  231. .flags = IORESOURCE_IRQ,
  232. },
  233. {
  234. .start = CH_UART0_RX,
  235. .end = CH_UART0_RX+1,
  236. .flags = IORESOURCE_DMA,
  237. },
  238. };
  239. static struct platform_device bfin_sir0_device = {
  240. .name = "bfin_sir",
  241. .id = 0,
  242. .num_resources = ARRAY_SIZE(bfin_sir0_resources),
  243. .resource = bfin_sir0_resources,
  244. };
  245. #endif
  246. #endif
  247. #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
  248. static struct platform_device bfin_sport0_uart_device = {
  249. .name = "bfin-sport-uart",
  250. .id = 0,
  251. };
  252. static struct platform_device bfin_sport1_uart_device = {
  253. .name = "bfin-sport-uart",
  254. .id = 1,
  255. };
  256. #endif
  257. #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
  258. static struct resource isp1362_hcd_resources[] = {
  259. {
  260. .start = 0x20308000,
  261. .end = 0x20308000,
  262. .flags = IORESOURCE_MEM,
  263. }, {
  264. .start = 0x20308004,
  265. .end = 0x20308004,
  266. .flags = IORESOURCE_MEM,
  267. }, {
  268. .start = IRQ_PF4,
  269. .end = IRQ_PF4,
  270. .flags = IORESOURCE_IRQ,
  271. },
  272. };
  273. static struct isp1362_platform_data isp1362_priv = {
  274. .sel15Kres = 1,
  275. .clknotstop = 0,
  276. .oc_enable = 0,
  277. .int_act_high = 0,
  278. .int_edge_triggered = 0,
  279. .remote_wakeup_connected = 0,
  280. .no_power_switching = 1,
  281. .power_switching_mode = 0,
  282. };
  283. static struct platform_device isp1362_hcd_device = {
  284. .name = "isp1362-hcd",
  285. .id = 0,
  286. .dev = {
  287. .platform_data = &isp1362_priv,
  288. },
  289. .num_resources = ARRAY_SIZE(isp1362_hcd_resources),
  290. .resource = isp1362_hcd_resources,
  291. };
  292. #endif
  293. static const unsigned int cclk_vlev_datasheet[] =
  294. {
  295. VRPAIR(VLEV_085, 250000000),
  296. VRPAIR(VLEV_090, 376000000),
  297. VRPAIR(VLEV_095, 426000000),
  298. VRPAIR(VLEV_100, 426000000),
  299. VRPAIR(VLEV_105, 476000000),
  300. VRPAIR(VLEV_110, 476000000),
  301. VRPAIR(VLEV_115, 476000000),
  302. VRPAIR(VLEV_120, 600000000),
  303. VRPAIR(VLEV_125, 600000000),
  304. VRPAIR(VLEV_130, 600000000),
  305. };
  306. static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
  307. .tuple_tab = cclk_vlev_datasheet,
  308. .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
  309. .vr_settling_time = 25 /* us */,
  310. };
  311. static struct platform_device bfin_dpmc = {
  312. .name = "bfin dpmc",
  313. .dev = {
  314. .platform_data = &bfin_dmpc_vreg_data,
  315. },
  316. };
  317. static struct platform_device *cm_bf533_devices[] __initdata = {
  318. &bfin_dpmc,
  319. #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
  320. &bfin_uart_device,
  321. #endif
  322. #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
  323. #ifdef CONFIG_BFIN_SIR0
  324. &bfin_sir0_device,
  325. #endif
  326. #endif
  327. #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
  328. &bfin_sport0_uart_device,
  329. &bfin_sport1_uart_device,
  330. #endif
  331. #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
  332. &rtc_device,
  333. #endif
  334. #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
  335. &isp1362_hcd_device,
  336. #endif
  337. #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
  338. &smc91x_device,
  339. #endif
  340. #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
  341. &bfin_spi0_device,
  342. #endif
  343. &bfin_gpios_device,
  344. };
  345. static int __init cm_bf533_init(void)
  346. {
  347. printk(KERN_INFO "%s(): registering device resources\n", __func__);
  348. platform_add_devices(cm_bf533_devices, ARRAY_SIZE(cm_bf533_devices));
  349. #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
  350. spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
  351. #endif
  352. return 0;
  353. }
  354. arch_initcall(cm_bf533_init);