twl4030.c 38 KB

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  1. /*
  2. * ALSA SoC TWL4030 codec driver
  3. *
  4. * Author: Steve Sakoman, <steve@sakoman.com>
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * version 2 as published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  13. * General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  18. * 02110-1301 USA
  19. *
  20. */
  21. #include <linux/module.h>
  22. #include <linux/moduleparam.h>
  23. #include <linux/init.h>
  24. #include <linux/delay.h>
  25. #include <linux/pm.h>
  26. #include <linux/i2c.h>
  27. #include <linux/platform_device.h>
  28. #include <linux/i2c/twl4030.h>
  29. #include <sound/core.h>
  30. #include <sound/pcm.h>
  31. #include <sound/pcm_params.h>
  32. #include <sound/soc.h>
  33. #include <sound/soc-dapm.h>
  34. #include <sound/initval.h>
  35. #include <sound/tlv.h>
  36. #include "twl4030.h"
  37. /*
  38. * twl4030 register cache & default register settings
  39. */
  40. static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
  41. 0x00, /* this register not used */
  42. 0x93, /* REG_CODEC_MODE (0x1) */
  43. 0xc3, /* REG_OPTION (0x2) */
  44. 0x00, /* REG_UNKNOWN (0x3) */
  45. 0x00, /* REG_MICBIAS_CTL (0x4) */
  46. 0x20, /* REG_ANAMICL (0x5) */
  47. 0x00, /* REG_ANAMICR (0x6) */
  48. 0x00, /* REG_AVADC_CTL (0x7) */
  49. 0x00, /* REG_ADCMICSEL (0x8) */
  50. 0x00, /* REG_DIGMIXING (0x9) */
  51. 0x0c, /* REG_ATXL1PGA (0xA) */
  52. 0x0c, /* REG_ATXR1PGA (0xB) */
  53. 0x00, /* REG_AVTXL2PGA (0xC) */
  54. 0x00, /* REG_AVTXR2PGA (0xD) */
  55. 0x01, /* REG_AUDIO_IF (0xE) */
  56. 0x00, /* REG_VOICE_IF (0xF) */
  57. 0x00, /* REG_ARXR1PGA (0x10) */
  58. 0x00, /* REG_ARXL1PGA (0x11) */
  59. 0x6c, /* REG_ARXR2PGA (0x12) */
  60. 0x6c, /* REG_ARXL2PGA (0x13) */
  61. 0x00, /* REG_VRXPGA (0x14) */
  62. 0x00, /* REG_VSTPGA (0x15) */
  63. 0x00, /* REG_VRX2ARXPGA (0x16) */
  64. 0x0c, /* REG_AVDAC_CTL (0x17) */
  65. 0x00, /* REG_ARX2VTXPGA (0x18) */
  66. 0x00, /* REG_ARXL1_APGA_CTL (0x19) */
  67. 0x00, /* REG_ARXR1_APGA_CTL (0x1A) */
  68. 0x4b, /* REG_ARXL2_APGA_CTL (0x1B) */
  69. 0x4b, /* REG_ARXR2_APGA_CTL (0x1C) */
  70. 0x00, /* REG_ATX2ARXPGA (0x1D) */
  71. 0x00, /* REG_BT_IF (0x1E) */
  72. 0x00, /* REG_BTPGA (0x1F) */
  73. 0x00, /* REG_BTSTPGA (0x20) */
  74. 0x00, /* REG_EAR_CTL (0x21) */
  75. 0x24, /* REG_HS_SEL (0x22) */
  76. 0x0a, /* REG_HS_GAIN_SET (0x23) */
  77. 0x00, /* REG_HS_POPN_SET (0x24) */
  78. 0x00, /* REG_PREDL_CTL (0x25) */
  79. 0x00, /* REG_PREDR_CTL (0x26) */
  80. 0x00, /* REG_PRECKL_CTL (0x27) */
  81. 0x00, /* REG_PRECKR_CTL (0x28) */
  82. 0x00, /* REG_HFL_CTL (0x29) */
  83. 0x00, /* REG_HFR_CTL (0x2A) */
  84. 0x00, /* REG_ALC_CTL (0x2B) */
  85. 0x00, /* REG_ALC_SET1 (0x2C) */
  86. 0x00, /* REG_ALC_SET2 (0x2D) */
  87. 0x00, /* REG_BOOST_CTL (0x2E) */
  88. 0x00, /* REG_SOFTVOL_CTL (0x2F) */
  89. 0x00, /* REG_DTMF_FREQSEL (0x30) */
  90. 0x00, /* REG_DTMF_TONEXT1H (0x31) */
  91. 0x00, /* REG_DTMF_TONEXT1L (0x32) */
  92. 0x00, /* REG_DTMF_TONEXT2H (0x33) */
  93. 0x00, /* REG_DTMF_TONEXT2L (0x34) */
  94. 0x00, /* REG_DTMF_TONOFF (0x35) */
  95. 0x00, /* REG_DTMF_WANONOFF (0x36) */
  96. 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
  97. 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
  98. 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
  99. 0x16, /* REG_APLL_CTL (0x3A) */
  100. 0x00, /* REG_DTMF_CTL (0x3B) */
  101. 0x00, /* REG_DTMF_PGA_CTL2 (0x3C) */
  102. 0x00, /* REG_DTMF_PGA_CTL1 (0x3D) */
  103. 0x00, /* REG_MISC_SET_1 (0x3E) */
  104. 0x00, /* REG_PCMBTMUX (0x3F) */
  105. 0x00, /* not used (0x40) */
  106. 0x00, /* not used (0x41) */
  107. 0x00, /* not used (0x42) */
  108. 0x00, /* REG_RX_PATH_SEL (0x43) */
  109. 0x00, /* REG_VDL_APGA_CTL (0x44) */
  110. 0x00, /* REG_VIBRA_CTL (0x45) */
  111. 0x00, /* REG_VIBRA_SET (0x46) */
  112. 0x00, /* REG_VIBRA_PWM_SET (0x47) */
  113. 0x00, /* REG_ANAMIC_GAIN (0x48) */
  114. 0x00, /* REG_MISC_SET_2 (0x49) */
  115. };
  116. /*
  117. * read twl4030 register cache
  118. */
  119. static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
  120. unsigned int reg)
  121. {
  122. u8 *cache = codec->reg_cache;
  123. return cache[reg];
  124. }
  125. /*
  126. * write twl4030 register cache
  127. */
  128. static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
  129. u8 reg, u8 value)
  130. {
  131. u8 *cache = codec->reg_cache;
  132. if (reg >= TWL4030_CACHEREGNUM)
  133. return;
  134. cache[reg] = value;
  135. }
  136. /*
  137. * write to the twl4030 register space
  138. */
  139. static int twl4030_write(struct snd_soc_codec *codec,
  140. unsigned int reg, unsigned int value)
  141. {
  142. twl4030_write_reg_cache(codec, reg, value);
  143. return twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value, reg);
  144. }
  145. static void twl4030_clear_codecpdz(struct snd_soc_codec *codec)
  146. {
  147. u8 mode;
  148. mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
  149. twl4030_write(codec, TWL4030_REG_CODEC_MODE,
  150. mode & ~TWL4030_CODECPDZ);
  151. /* REVISIT: this delay is present in TI sample drivers */
  152. /* but there seems to be no TRM requirement for it */
  153. udelay(10);
  154. }
  155. static void twl4030_set_codecpdz(struct snd_soc_codec *codec)
  156. {
  157. u8 mode;
  158. mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
  159. twl4030_write(codec, TWL4030_REG_CODEC_MODE,
  160. mode | TWL4030_CODECPDZ);
  161. /* REVISIT: this delay is present in TI sample drivers */
  162. /* but there seems to be no TRM requirement for it */
  163. udelay(10);
  164. }
  165. static void twl4030_init_chip(struct snd_soc_codec *codec)
  166. {
  167. int i;
  168. /* clear CODECPDZ prior to setting register defaults */
  169. twl4030_clear_codecpdz(codec);
  170. /* set all audio section registers to reasonable defaults */
  171. for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++)
  172. twl4030_write(codec, i, twl4030_reg[i]);
  173. }
  174. /* Earpiece */
  175. static const char *twl4030_earpiece_texts[] =
  176. {"Off", "DACL1", "DACL2", "Invalid", "DACR1"};
  177. static const struct soc_enum twl4030_earpiece_enum =
  178. SOC_ENUM_SINGLE(TWL4030_REG_EAR_CTL, 1,
  179. ARRAY_SIZE(twl4030_earpiece_texts),
  180. twl4030_earpiece_texts);
  181. static const struct snd_kcontrol_new twl4030_dapm_earpiece_control =
  182. SOC_DAPM_ENUM("Route", twl4030_earpiece_enum);
  183. /* PreDrive Left */
  184. static const char *twl4030_predrivel_texts[] =
  185. {"Off", "DACL1", "DACL2", "Invalid", "DACR2"};
  186. static const struct soc_enum twl4030_predrivel_enum =
  187. SOC_ENUM_SINGLE(TWL4030_REG_PREDL_CTL, 1,
  188. ARRAY_SIZE(twl4030_predrivel_texts),
  189. twl4030_predrivel_texts);
  190. static const struct snd_kcontrol_new twl4030_dapm_predrivel_control =
  191. SOC_DAPM_ENUM("Route", twl4030_predrivel_enum);
  192. /* PreDrive Right */
  193. static const char *twl4030_predriver_texts[] =
  194. {"Off", "DACR1", "DACR2", "Invalid", "DACL2"};
  195. static const struct soc_enum twl4030_predriver_enum =
  196. SOC_ENUM_SINGLE(TWL4030_REG_PREDR_CTL, 1,
  197. ARRAY_SIZE(twl4030_predriver_texts),
  198. twl4030_predriver_texts);
  199. static const struct snd_kcontrol_new twl4030_dapm_predriver_control =
  200. SOC_DAPM_ENUM("Route", twl4030_predriver_enum);
  201. /* Headset Left */
  202. static const char *twl4030_hsol_texts[] =
  203. {"Off", "DACL1", "DACL2"};
  204. static const struct soc_enum twl4030_hsol_enum =
  205. SOC_ENUM_SINGLE(TWL4030_REG_HS_SEL, 1,
  206. ARRAY_SIZE(twl4030_hsol_texts),
  207. twl4030_hsol_texts);
  208. static const struct snd_kcontrol_new twl4030_dapm_hsol_control =
  209. SOC_DAPM_ENUM("Route", twl4030_hsol_enum);
  210. /* Headset Right */
  211. static const char *twl4030_hsor_texts[] =
  212. {"Off", "DACR1", "DACR2"};
  213. static const struct soc_enum twl4030_hsor_enum =
  214. SOC_ENUM_SINGLE(TWL4030_REG_HS_SEL, 4,
  215. ARRAY_SIZE(twl4030_hsor_texts),
  216. twl4030_hsor_texts);
  217. static const struct snd_kcontrol_new twl4030_dapm_hsor_control =
  218. SOC_DAPM_ENUM("Route", twl4030_hsor_enum);
  219. /* Carkit Left */
  220. static const char *twl4030_carkitl_texts[] =
  221. {"Off", "DACL1", "DACL2"};
  222. static const struct soc_enum twl4030_carkitl_enum =
  223. SOC_ENUM_SINGLE(TWL4030_REG_PRECKL_CTL, 1,
  224. ARRAY_SIZE(twl4030_carkitl_texts),
  225. twl4030_carkitl_texts);
  226. static const struct snd_kcontrol_new twl4030_dapm_carkitl_control =
  227. SOC_DAPM_ENUM("Route", twl4030_carkitl_enum);
  228. /* Carkit Right */
  229. static const char *twl4030_carkitr_texts[] =
  230. {"Off", "DACR1", "DACR2"};
  231. static const struct soc_enum twl4030_carkitr_enum =
  232. SOC_ENUM_SINGLE(TWL4030_REG_PRECKR_CTL, 1,
  233. ARRAY_SIZE(twl4030_carkitr_texts),
  234. twl4030_carkitr_texts);
  235. static const struct snd_kcontrol_new twl4030_dapm_carkitr_control =
  236. SOC_DAPM_ENUM("Route", twl4030_carkitr_enum);
  237. /* Handsfree Left */
  238. static const char *twl4030_handsfreel_texts[] =
  239. {"Voice", "DACL1", "DACL2", "DACR2"};
  240. static const struct soc_enum twl4030_handsfreel_enum =
  241. SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0,
  242. ARRAY_SIZE(twl4030_handsfreel_texts),
  243. twl4030_handsfreel_texts);
  244. static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control =
  245. SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum);
  246. /* Handsfree Right */
  247. static const char *twl4030_handsfreer_texts[] =
  248. {"Voice", "DACR1", "DACR2", "DACL2"};
  249. static const struct soc_enum twl4030_handsfreer_enum =
  250. SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0,
  251. ARRAY_SIZE(twl4030_handsfreer_texts),
  252. twl4030_handsfreer_texts);
  253. static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control =
  254. SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum);
  255. /* Left analog microphone selection */
  256. static const char *twl4030_analoglmic_texts[] =
  257. {"Off", "Main mic", "Headset mic", "Invalid", "AUXL",
  258. "Invalid", "Invalid", "Invalid", "Carkit mic"};
  259. static const struct soc_enum twl4030_analoglmic_enum =
  260. SOC_ENUM_SINGLE(TWL4030_REG_ANAMICL, 0,
  261. ARRAY_SIZE(twl4030_analoglmic_texts),
  262. twl4030_analoglmic_texts);
  263. static const struct snd_kcontrol_new twl4030_dapm_analoglmic_control =
  264. SOC_DAPM_ENUM("Route", twl4030_analoglmic_enum);
  265. /* Right analog microphone selection */
  266. static const char *twl4030_analogrmic_texts[] =
  267. {"Off", "Sub mic", "Invalid", "Invalid", "AUXR"};
  268. static const struct soc_enum twl4030_analogrmic_enum =
  269. SOC_ENUM_SINGLE(TWL4030_REG_ANAMICR, 0,
  270. ARRAY_SIZE(twl4030_analogrmic_texts),
  271. twl4030_analogrmic_texts);
  272. static const struct snd_kcontrol_new twl4030_dapm_analogrmic_control =
  273. SOC_DAPM_ENUM("Route", twl4030_analogrmic_enum);
  274. /* TX1 L/R Analog/Digital microphone selection */
  275. static const char *twl4030_micpathtx1_texts[] =
  276. {"Analog", "Digimic0"};
  277. static const struct soc_enum twl4030_micpathtx1_enum =
  278. SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 0,
  279. ARRAY_SIZE(twl4030_micpathtx1_texts),
  280. twl4030_micpathtx1_texts);
  281. static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control =
  282. SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum);
  283. /* TX2 L/R Analog/Digital microphone selection */
  284. static const char *twl4030_micpathtx2_texts[] =
  285. {"Analog", "Digimic1"};
  286. static const struct soc_enum twl4030_micpathtx2_enum =
  287. SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 2,
  288. ARRAY_SIZE(twl4030_micpathtx2_texts),
  289. twl4030_micpathtx2_texts);
  290. static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control =
  291. SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum);
  292. /*
  293. * This function filters out the non valid mux settings, named as "Invalid"
  294. * in the enum texts.
  295. * Just refuse to set an invalid mux mode.
  296. */
  297. static int twl4030_enum_event(struct snd_soc_dapm_widget *w,
  298. struct snd_kcontrol *kcontrol, int event)
  299. {
  300. struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
  301. int ret = 0;
  302. int val;
  303. val = w->value >> e->shift_l;
  304. if (!strcmp("Invalid", e->texts[val])) {
  305. printk(KERN_WARNING "Invalid MUX setting on 0x%02x (%d)\n",
  306. e->reg, val);
  307. ret = -1;
  308. }
  309. return ret;
  310. }
  311. static int micpath_event(struct snd_soc_dapm_widget *w,
  312. struct snd_kcontrol *kcontrol, int event)
  313. {
  314. struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
  315. unsigned char adcmicsel, micbias_ctl;
  316. adcmicsel = twl4030_read_reg_cache(w->codec, TWL4030_REG_ADCMICSEL);
  317. micbias_ctl = twl4030_read_reg_cache(w->codec, TWL4030_REG_MICBIAS_CTL);
  318. /* Prepare the bits for the given TX path:
  319. * shift_l == 0: TX1 microphone path
  320. * shift_l == 2: TX2 microphone path */
  321. if (e->shift_l) {
  322. /* TX2 microphone path */
  323. if (adcmicsel & TWL4030_TX2IN_SEL)
  324. micbias_ctl |= TWL4030_MICBIAS2_CTL; /* digimic */
  325. else
  326. micbias_ctl &= ~TWL4030_MICBIAS2_CTL;
  327. } else {
  328. /* TX1 microphone path */
  329. if (adcmicsel & TWL4030_TX1IN_SEL)
  330. micbias_ctl |= TWL4030_MICBIAS1_CTL; /* digimic */
  331. else
  332. micbias_ctl &= ~TWL4030_MICBIAS1_CTL;
  333. }
  334. twl4030_write(w->codec, TWL4030_REG_MICBIAS_CTL, micbias_ctl);
  335. return 0;
  336. }
  337. static int handsfree_event(struct snd_soc_dapm_widget *w,
  338. struct snd_kcontrol *kcontrol, int event)
  339. {
  340. struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
  341. unsigned char hs_ctl;
  342. hs_ctl = twl4030_read_reg_cache(w->codec, e->reg);
  343. if (hs_ctl & TWL4030_HF_CTL_REF_EN) {
  344. hs_ctl |= TWL4030_HF_CTL_RAMP_EN;
  345. twl4030_write(w->codec, e->reg, hs_ctl);
  346. hs_ctl |= TWL4030_HF_CTL_LOOP_EN;
  347. twl4030_write(w->codec, e->reg, hs_ctl);
  348. hs_ctl |= TWL4030_HF_CTL_HB_EN;
  349. twl4030_write(w->codec, e->reg, hs_ctl);
  350. } else {
  351. hs_ctl &= ~(TWL4030_HF_CTL_RAMP_EN | TWL4030_HF_CTL_LOOP_EN
  352. | TWL4030_HF_CTL_HB_EN);
  353. twl4030_write(w->codec, e->reg, hs_ctl);
  354. }
  355. return 0;
  356. }
  357. /*
  358. * Some of the gain controls in TWL (mostly those which are associated with
  359. * the outputs) are implemented in an interesting way:
  360. * 0x0 : Power down (mute)
  361. * 0x1 : 6dB
  362. * 0x2 : 0 dB
  363. * 0x3 : -6 dB
  364. * Inverting not going to help with these.
  365. * Custom volsw and volsw_2r get/put functions to handle these gain bits.
  366. */
  367. #define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\
  368. xinvert, tlv_array) \
  369. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
  370. .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
  371. SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  372. .tlv.p = (tlv_array), \
  373. .info = snd_soc_info_volsw, \
  374. .get = snd_soc_get_volsw_twl4030, \
  375. .put = snd_soc_put_volsw_twl4030, \
  376. .private_value = (unsigned long)&(struct soc_mixer_control) \
  377. {.reg = xreg, .shift = shift_left, .rshift = shift_right,\
  378. .max = xmax, .invert = xinvert} }
  379. #define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\
  380. xinvert, tlv_array) \
  381. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
  382. .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
  383. SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  384. .tlv.p = (tlv_array), \
  385. .info = snd_soc_info_volsw_2r, \
  386. .get = snd_soc_get_volsw_r2_twl4030,\
  387. .put = snd_soc_put_volsw_r2_twl4030, \
  388. .private_value = (unsigned long)&(struct soc_mixer_control) \
  389. {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
  390. .rshift = xshift, .max = xmax, .invert = xinvert} }
  391. #define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \
  392. SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \
  393. xinvert, tlv_array)
  394. static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
  395. struct snd_ctl_elem_value *ucontrol)
  396. {
  397. struct soc_mixer_control *mc =
  398. (struct soc_mixer_control *)kcontrol->private_value;
  399. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  400. unsigned int reg = mc->reg;
  401. unsigned int shift = mc->shift;
  402. unsigned int rshift = mc->rshift;
  403. int max = mc->max;
  404. int mask = (1 << fls(max)) - 1;
  405. ucontrol->value.integer.value[0] =
  406. (snd_soc_read(codec, reg) >> shift) & mask;
  407. if (ucontrol->value.integer.value[0])
  408. ucontrol->value.integer.value[0] =
  409. max + 1 - ucontrol->value.integer.value[0];
  410. if (shift != rshift) {
  411. ucontrol->value.integer.value[1] =
  412. (snd_soc_read(codec, reg) >> rshift) & mask;
  413. if (ucontrol->value.integer.value[1])
  414. ucontrol->value.integer.value[1] =
  415. max + 1 - ucontrol->value.integer.value[1];
  416. }
  417. return 0;
  418. }
  419. static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
  420. struct snd_ctl_elem_value *ucontrol)
  421. {
  422. struct soc_mixer_control *mc =
  423. (struct soc_mixer_control *)kcontrol->private_value;
  424. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  425. unsigned int reg = mc->reg;
  426. unsigned int shift = mc->shift;
  427. unsigned int rshift = mc->rshift;
  428. int max = mc->max;
  429. int mask = (1 << fls(max)) - 1;
  430. unsigned short val, val2, val_mask;
  431. val = (ucontrol->value.integer.value[0] & mask);
  432. val_mask = mask << shift;
  433. if (val)
  434. val = max + 1 - val;
  435. val = val << shift;
  436. if (shift != rshift) {
  437. val2 = (ucontrol->value.integer.value[1] & mask);
  438. val_mask |= mask << rshift;
  439. if (val2)
  440. val2 = max + 1 - val2;
  441. val |= val2 << rshift;
  442. }
  443. return snd_soc_update_bits(codec, reg, val_mask, val);
  444. }
  445. static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
  446. struct snd_ctl_elem_value *ucontrol)
  447. {
  448. struct soc_mixer_control *mc =
  449. (struct soc_mixer_control *)kcontrol->private_value;
  450. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  451. unsigned int reg = mc->reg;
  452. unsigned int reg2 = mc->rreg;
  453. unsigned int shift = mc->shift;
  454. int max = mc->max;
  455. int mask = (1<<fls(max))-1;
  456. ucontrol->value.integer.value[0] =
  457. (snd_soc_read(codec, reg) >> shift) & mask;
  458. ucontrol->value.integer.value[1] =
  459. (snd_soc_read(codec, reg2) >> shift) & mask;
  460. if (ucontrol->value.integer.value[0])
  461. ucontrol->value.integer.value[0] =
  462. max + 1 - ucontrol->value.integer.value[0];
  463. if (ucontrol->value.integer.value[1])
  464. ucontrol->value.integer.value[1] =
  465. max + 1 - ucontrol->value.integer.value[1];
  466. return 0;
  467. }
  468. static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
  469. struct snd_ctl_elem_value *ucontrol)
  470. {
  471. struct soc_mixer_control *mc =
  472. (struct soc_mixer_control *)kcontrol->private_value;
  473. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  474. unsigned int reg = mc->reg;
  475. unsigned int reg2 = mc->rreg;
  476. unsigned int shift = mc->shift;
  477. int max = mc->max;
  478. int mask = (1 << fls(max)) - 1;
  479. int err;
  480. unsigned short val, val2, val_mask;
  481. val_mask = mask << shift;
  482. val = (ucontrol->value.integer.value[0] & mask);
  483. val2 = (ucontrol->value.integer.value[1] & mask);
  484. if (val)
  485. val = max + 1 - val;
  486. if (val2)
  487. val2 = max + 1 - val2;
  488. val = val << shift;
  489. val2 = val2 << shift;
  490. err = snd_soc_update_bits(codec, reg, val_mask, val);
  491. if (err < 0)
  492. return err;
  493. err = snd_soc_update_bits(codec, reg2, val_mask, val2);
  494. return err;
  495. }
  496. /*
  497. * FGAIN volume control:
  498. * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
  499. */
  500. static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
  501. /*
  502. * CGAIN volume control:
  503. * 0 dB to 12 dB in 6 dB steps
  504. * value 2 and 3 means 12 dB
  505. */
  506. static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
  507. /*
  508. * Analog playback gain
  509. * -24 dB to 12 dB in 2 dB steps
  510. */
  511. static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
  512. /*
  513. * Gain controls tied to outputs
  514. * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
  515. */
  516. static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
  517. /*
  518. * Capture gain after the ADCs
  519. * from 0 dB to 31 dB in 1 dB steps
  520. */
  521. static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
  522. /*
  523. * Gain control for input amplifiers
  524. * 0 dB to 30 dB in 6 dB steps
  525. */
  526. static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
  527. static const struct snd_kcontrol_new twl4030_snd_controls[] = {
  528. /* Common playback gain controls */
  529. SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
  530. TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
  531. 0, 0x3f, 0, digital_fine_tlv),
  532. SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
  533. TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
  534. 0, 0x3f, 0, digital_fine_tlv),
  535. SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
  536. TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
  537. 6, 0x2, 0, digital_coarse_tlv),
  538. SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
  539. TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
  540. 6, 0x2, 0, digital_coarse_tlv),
  541. SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
  542. TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
  543. 3, 0x12, 1, analog_tlv),
  544. SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
  545. TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
  546. 3, 0x12, 1, analog_tlv),
  547. SOC_DOUBLE_R("DAC1 Analog Playback Switch",
  548. TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
  549. 1, 1, 0),
  550. SOC_DOUBLE_R("DAC2 Analog Playback Switch",
  551. TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
  552. 1, 1, 0),
  553. /* Separate output gain controls */
  554. SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume",
  555. TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
  556. 4, 3, 0, output_tvl),
  557. SOC_DOUBLE_TLV_TWL4030("Headset Playback Volume",
  558. TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, output_tvl),
  559. SOC_DOUBLE_R_TLV_TWL4030("Carkit Playback Volume",
  560. TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
  561. 4, 3, 0, output_tvl),
  562. SOC_SINGLE_TLV_TWL4030("Earpiece Playback Volume",
  563. TWL4030_REG_EAR_CTL, 4, 3, 0, output_tvl),
  564. /* Common capture gain controls */
  565. SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume",
  566. TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
  567. 0, 0x1f, 0, digital_capture_tlv),
  568. SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume",
  569. TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA,
  570. 0, 0x1f, 0, digital_capture_tlv),
  571. SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN,
  572. 0, 3, 5, 0, input_gain_tlv),
  573. };
  574. /* add non dapm controls */
  575. static int twl4030_add_controls(struct snd_soc_codec *codec)
  576. {
  577. int err, i;
  578. for (i = 0; i < ARRAY_SIZE(twl4030_snd_controls); i++) {
  579. err = snd_ctl_add(codec->card,
  580. snd_soc_cnew(&twl4030_snd_controls[i],
  581. codec, NULL));
  582. if (err < 0)
  583. return err;
  584. }
  585. return 0;
  586. }
  587. static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
  588. /* Left channel inputs */
  589. SND_SOC_DAPM_INPUT("MAINMIC"),
  590. SND_SOC_DAPM_INPUT("HSMIC"),
  591. SND_SOC_DAPM_INPUT("AUXL"),
  592. SND_SOC_DAPM_INPUT("CARKITMIC"),
  593. /* Right channel inputs */
  594. SND_SOC_DAPM_INPUT("SUBMIC"),
  595. SND_SOC_DAPM_INPUT("AUXR"),
  596. /* Digital microphones (Stereo) */
  597. SND_SOC_DAPM_INPUT("DIGIMIC0"),
  598. SND_SOC_DAPM_INPUT("DIGIMIC1"),
  599. /* Outputs */
  600. SND_SOC_DAPM_OUTPUT("OUTL"),
  601. SND_SOC_DAPM_OUTPUT("OUTR"),
  602. SND_SOC_DAPM_OUTPUT("EARPIECE"),
  603. SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
  604. SND_SOC_DAPM_OUTPUT("PREDRIVER"),
  605. SND_SOC_DAPM_OUTPUT("HSOL"),
  606. SND_SOC_DAPM_OUTPUT("HSOR"),
  607. SND_SOC_DAPM_OUTPUT("CARKITL"),
  608. SND_SOC_DAPM_OUTPUT("CARKITR"),
  609. SND_SOC_DAPM_OUTPUT("HFL"),
  610. SND_SOC_DAPM_OUTPUT("HFR"),
  611. /* DACs */
  612. SND_SOC_DAPM_DAC("DAC Right1", "Right Front Playback",
  613. TWL4030_REG_AVDAC_CTL, 0, 0),
  614. SND_SOC_DAPM_DAC("DAC Left1", "Left Front Playback",
  615. TWL4030_REG_AVDAC_CTL, 1, 0),
  616. SND_SOC_DAPM_DAC("DAC Right2", "Right Rear Playback",
  617. TWL4030_REG_AVDAC_CTL, 2, 0),
  618. SND_SOC_DAPM_DAC("DAC Left2", "Left Rear Playback",
  619. TWL4030_REG_AVDAC_CTL, 3, 0),
  620. /* Analog PGAs */
  621. SND_SOC_DAPM_PGA("ARXR1_APGA", TWL4030_REG_ARXR1_APGA_CTL,
  622. 0, 0, NULL, 0),
  623. SND_SOC_DAPM_PGA("ARXL1_APGA", TWL4030_REG_ARXL1_APGA_CTL,
  624. 0, 0, NULL, 0),
  625. SND_SOC_DAPM_PGA("ARXR2_APGA", TWL4030_REG_ARXR2_APGA_CTL,
  626. 0, 0, NULL, 0),
  627. SND_SOC_DAPM_PGA("ARXL2_APGA", TWL4030_REG_ARXL2_APGA_CTL,
  628. 0, 0, NULL, 0),
  629. /* Output MUX controls */
  630. /* Earpiece */
  631. SND_SOC_DAPM_MUX_E("Earpiece Mux", SND_SOC_NOPM, 0, 0,
  632. &twl4030_dapm_earpiece_control, twl4030_enum_event,
  633. SND_SOC_DAPM_PRE_REG),
  634. /* PreDrivL/R */
  635. SND_SOC_DAPM_MUX_E("PredriveL Mux", SND_SOC_NOPM, 0, 0,
  636. &twl4030_dapm_predrivel_control, twl4030_enum_event,
  637. SND_SOC_DAPM_PRE_REG),
  638. SND_SOC_DAPM_MUX_E("PredriveR Mux", SND_SOC_NOPM, 0, 0,
  639. &twl4030_dapm_predriver_control, twl4030_enum_event,
  640. SND_SOC_DAPM_PRE_REG),
  641. /* HeadsetL/R */
  642. SND_SOC_DAPM_MUX("HeadsetL Mux", SND_SOC_NOPM, 0, 0,
  643. &twl4030_dapm_hsol_control),
  644. SND_SOC_DAPM_MUX("HeadsetR Mux", SND_SOC_NOPM, 0, 0,
  645. &twl4030_dapm_hsor_control),
  646. /* CarkitL/R */
  647. SND_SOC_DAPM_MUX("CarkitL Mux", SND_SOC_NOPM, 0, 0,
  648. &twl4030_dapm_carkitl_control),
  649. SND_SOC_DAPM_MUX("CarkitR Mux", SND_SOC_NOPM, 0, 0,
  650. &twl4030_dapm_carkitr_control),
  651. /* HandsfreeL/R */
  652. SND_SOC_DAPM_MUX_E("HandsfreeL Mux", TWL4030_REG_HFL_CTL, 5, 0,
  653. &twl4030_dapm_handsfreel_control, handsfree_event,
  654. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  655. SND_SOC_DAPM_MUX_E("HandsfreeR Mux", TWL4030_REG_HFR_CTL, 5, 0,
  656. &twl4030_dapm_handsfreer_control, handsfree_event,
  657. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  658. /* Introducing four virtual ADC, since TWL4030 have four channel for
  659. capture */
  660. SND_SOC_DAPM_ADC("ADC Virtual Left1", "Left Front Capture",
  661. SND_SOC_NOPM, 0, 0),
  662. SND_SOC_DAPM_ADC("ADC Virtual Right1", "Right Front Capture",
  663. SND_SOC_NOPM, 0, 0),
  664. SND_SOC_DAPM_ADC("ADC Virtual Left2", "Left Rear Capture",
  665. SND_SOC_NOPM, 0, 0),
  666. SND_SOC_DAPM_ADC("ADC Virtual Right2", "Right Rear Capture",
  667. SND_SOC_NOPM, 0, 0),
  668. /* Analog/Digital mic path selection.
  669. TX1 Left/Right: either analog Left/Right or Digimic0
  670. TX2 Left/Right: either analog Left/Right or Digimic1 */
  671. SND_SOC_DAPM_MUX_E("TX1 Capture Route", SND_SOC_NOPM, 0, 0,
  672. &twl4030_dapm_micpathtx1_control, micpath_event,
  673. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
  674. SND_SOC_DAPM_POST_REG),
  675. SND_SOC_DAPM_MUX_E("TX2 Capture Route", SND_SOC_NOPM, 0, 0,
  676. &twl4030_dapm_micpathtx2_control, micpath_event,
  677. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
  678. SND_SOC_DAPM_POST_REG),
  679. /* Analog input muxes with power switch for the physical ADCL/R */
  680. SND_SOC_DAPM_MUX_E("Analog Left Capture Route",
  681. TWL4030_REG_AVADC_CTL, 3, 0, &twl4030_dapm_analoglmic_control,
  682. twl4030_enum_event, SND_SOC_DAPM_PRE_REG),
  683. SND_SOC_DAPM_MUX_E("Analog Right Capture Route",
  684. TWL4030_REG_AVADC_CTL, 1, 0, &twl4030_dapm_analogrmic_control,
  685. twl4030_enum_event, SND_SOC_DAPM_PRE_REG),
  686. SND_SOC_DAPM_PGA("Analog Left Amplifier",
  687. TWL4030_REG_ANAMICL, 4, 0, NULL, 0),
  688. SND_SOC_DAPM_PGA("Analog Right Amplifier",
  689. TWL4030_REG_ANAMICR, 4, 0, NULL, 0),
  690. SND_SOC_DAPM_PGA("Digimic0 Enable",
  691. TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0),
  692. SND_SOC_DAPM_PGA("Digimic1 Enable",
  693. TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0),
  694. SND_SOC_DAPM_MICBIAS("Mic Bias 1", TWL4030_REG_MICBIAS_CTL, 0, 0),
  695. SND_SOC_DAPM_MICBIAS("Mic Bias 2", TWL4030_REG_MICBIAS_CTL, 1, 0),
  696. SND_SOC_DAPM_MICBIAS("Headset Mic Bias", TWL4030_REG_MICBIAS_CTL, 2, 0),
  697. };
  698. static const struct snd_soc_dapm_route intercon[] = {
  699. {"ARXL1_APGA", NULL, "DAC Left1"},
  700. {"ARXR1_APGA", NULL, "DAC Right1"},
  701. {"ARXL2_APGA", NULL, "DAC Left2"},
  702. {"ARXR2_APGA", NULL, "DAC Right2"},
  703. /* Internal playback routings */
  704. /* Earpiece */
  705. {"Earpiece Mux", "DACL1", "ARXL1_APGA"},
  706. {"Earpiece Mux", "DACL2", "ARXL2_APGA"},
  707. {"Earpiece Mux", "DACR1", "ARXR1_APGA"},
  708. /* PreDrivL */
  709. {"PredriveL Mux", "DACL1", "ARXL1_APGA"},
  710. {"PredriveL Mux", "DACL2", "ARXL2_APGA"},
  711. {"PredriveL Mux", "DACR2", "ARXR2_APGA"},
  712. /* PreDrivR */
  713. {"PredriveR Mux", "DACR1", "ARXR1_APGA"},
  714. {"PredriveR Mux", "DACR2", "ARXR2_APGA"},
  715. {"PredriveR Mux", "DACL2", "ARXL2_APGA"},
  716. /* HeadsetL */
  717. {"HeadsetL Mux", "DACL1", "ARXL1_APGA"},
  718. {"HeadsetL Mux", "DACL2", "ARXL2_APGA"},
  719. /* HeadsetR */
  720. {"HeadsetR Mux", "DACR1", "ARXR1_APGA"},
  721. {"HeadsetR Mux", "DACR2", "ARXR2_APGA"},
  722. /* CarkitL */
  723. {"CarkitL Mux", "DACL1", "ARXL1_APGA"},
  724. {"CarkitL Mux", "DACL2", "ARXL2_APGA"},
  725. /* CarkitR */
  726. {"CarkitR Mux", "DACR1", "ARXR1_APGA"},
  727. {"CarkitR Mux", "DACR2", "ARXR2_APGA"},
  728. /* HandsfreeL */
  729. {"HandsfreeL Mux", "DACL1", "ARXL1_APGA"},
  730. {"HandsfreeL Mux", "DACL2", "ARXL2_APGA"},
  731. {"HandsfreeL Mux", "DACR2", "ARXR2_APGA"},
  732. /* HandsfreeR */
  733. {"HandsfreeR Mux", "DACR1", "ARXR1_APGA"},
  734. {"HandsfreeR Mux", "DACR2", "ARXR2_APGA"},
  735. {"HandsfreeR Mux", "DACL2", "ARXL2_APGA"},
  736. /* outputs */
  737. {"OUTL", NULL, "ARXL2_APGA"},
  738. {"OUTR", NULL, "ARXR2_APGA"},
  739. {"EARPIECE", NULL, "Earpiece Mux"},
  740. {"PREDRIVEL", NULL, "PredriveL Mux"},
  741. {"PREDRIVER", NULL, "PredriveR Mux"},
  742. {"HSOL", NULL, "HeadsetL Mux"},
  743. {"HSOR", NULL, "HeadsetR Mux"},
  744. {"CARKITL", NULL, "CarkitL Mux"},
  745. {"CARKITR", NULL, "CarkitR Mux"},
  746. {"HFL", NULL, "HandsfreeL Mux"},
  747. {"HFR", NULL, "HandsfreeR Mux"},
  748. /* Capture path */
  749. {"Analog Left Capture Route", "Main mic", "MAINMIC"},
  750. {"Analog Left Capture Route", "Headset mic", "HSMIC"},
  751. {"Analog Left Capture Route", "AUXL", "AUXL"},
  752. {"Analog Left Capture Route", "Carkit mic", "CARKITMIC"},
  753. {"Analog Right Capture Route", "Sub mic", "SUBMIC"},
  754. {"Analog Right Capture Route", "AUXR", "AUXR"},
  755. {"Analog Left Amplifier", NULL, "Analog Left Capture Route"},
  756. {"Analog Right Amplifier", NULL, "Analog Right Capture Route"},
  757. {"Digimic0 Enable", NULL, "DIGIMIC0"},
  758. {"Digimic1 Enable", NULL, "DIGIMIC1"},
  759. /* TX1 Left capture path */
  760. {"TX1 Capture Route", "Analog", "Analog Left Amplifier"},
  761. {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
  762. /* TX1 Right capture path */
  763. {"TX1 Capture Route", "Analog", "Analog Right Amplifier"},
  764. {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
  765. /* TX2 Left capture path */
  766. {"TX2 Capture Route", "Analog", "Analog Left Amplifier"},
  767. {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
  768. /* TX2 Right capture path */
  769. {"TX2 Capture Route", "Analog", "Analog Right Amplifier"},
  770. {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
  771. {"ADC Virtual Left1", NULL, "TX1 Capture Route"},
  772. {"ADC Virtual Right1", NULL, "TX1 Capture Route"},
  773. {"ADC Virtual Left2", NULL, "TX2 Capture Route"},
  774. {"ADC Virtual Right2", NULL, "TX2 Capture Route"},
  775. };
  776. static int twl4030_add_widgets(struct snd_soc_codec *codec)
  777. {
  778. snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets,
  779. ARRAY_SIZE(twl4030_dapm_widgets));
  780. snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
  781. snd_soc_dapm_new_widgets(codec);
  782. return 0;
  783. }
  784. static void twl4030_power_up(struct snd_soc_codec *codec)
  785. {
  786. u8 anamicl, regmisc1, byte, popn;
  787. int i = 0;
  788. /* set CODECPDZ to turn on codec */
  789. twl4030_set_codecpdz(codec);
  790. /* initiate offset cancellation */
  791. anamicl = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
  792. twl4030_write(codec, TWL4030_REG_ANAMICL,
  793. anamicl | TWL4030_CNCL_OFFSET_START);
  794. /* wait for offset cancellation to complete */
  795. do {
  796. /* this takes a little while, so don't slam i2c */
  797. udelay(2000);
  798. twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
  799. TWL4030_REG_ANAMICL);
  800. } while ((i++ < 100) &&
  801. ((byte & TWL4030_CNCL_OFFSET_START) ==
  802. TWL4030_CNCL_OFFSET_START));
  803. /* anti-pop when changing analog gain */
  804. regmisc1 = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
  805. twl4030_write(codec, TWL4030_REG_MISC_SET_1,
  806. regmisc1 | TWL4030_SMOOTH_ANAVOL_EN);
  807. /* toggle CODECPDZ as per TRM */
  808. twl4030_clear_codecpdz(codec);
  809. twl4030_set_codecpdz(codec);
  810. /* program anti-pop with bias ramp delay */
  811. popn = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
  812. popn &= TWL4030_RAMP_DELAY;
  813. popn |= TWL4030_RAMP_DELAY_645MS;
  814. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
  815. popn |= TWL4030_VMID_EN;
  816. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
  817. /* enable anti-pop ramp */
  818. popn |= TWL4030_RAMP_EN;
  819. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
  820. }
  821. static void twl4030_power_down(struct snd_soc_codec *codec)
  822. {
  823. u8 popn;
  824. /* disable anti-pop ramp */
  825. popn = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
  826. popn &= ~TWL4030_RAMP_EN;
  827. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
  828. /* disable bias out */
  829. popn &= ~TWL4030_VMID_EN;
  830. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
  831. /* power down */
  832. twl4030_clear_codecpdz(codec);
  833. }
  834. static int twl4030_set_bias_level(struct snd_soc_codec *codec,
  835. enum snd_soc_bias_level level)
  836. {
  837. switch (level) {
  838. case SND_SOC_BIAS_ON:
  839. twl4030_power_up(codec);
  840. break;
  841. case SND_SOC_BIAS_PREPARE:
  842. /* TODO: develop a twl4030_prepare function */
  843. break;
  844. case SND_SOC_BIAS_STANDBY:
  845. /* TODO: develop a twl4030_standby function */
  846. twl4030_power_down(codec);
  847. break;
  848. case SND_SOC_BIAS_OFF:
  849. twl4030_power_down(codec);
  850. break;
  851. }
  852. codec->bias_level = level;
  853. return 0;
  854. }
  855. static int twl4030_hw_params(struct snd_pcm_substream *substream,
  856. struct snd_pcm_hw_params *params,
  857. struct snd_soc_dai *dai)
  858. {
  859. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  860. struct snd_soc_device *socdev = rtd->socdev;
  861. struct snd_soc_codec *codec = socdev->codec;
  862. u8 mode, old_mode, format, old_format;
  863. /* bit rate */
  864. old_mode = twl4030_read_reg_cache(codec,
  865. TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
  866. mode = old_mode & ~TWL4030_APLL_RATE;
  867. switch (params_rate(params)) {
  868. case 8000:
  869. mode |= TWL4030_APLL_RATE_8000;
  870. break;
  871. case 11025:
  872. mode |= TWL4030_APLL_RATE_11025;
  873. break;
  874. case 12000:
  875. mode |= TWL4030_APLL_RATE_12000;
  876. break;
  877. case 16000:
  878. mode |= TWL4030_APLL_RATE_16000;
  879. break;
  880. case 22050:
  881. mode |= TWL4030_APLL_RATE_22050;
  882. break;
  883. case 24000:
  884. mode |= TWL4030_APLL_RATE_24000;
  885. break;
  886. case 32000:
  887. mode |= TWL4030_APLL_RATE_32000;
  888. break;
  889. case 44100:
  890. mode |= TWL4030_APLL_RATE_44100;
  891. break;
  892. case 48000:
  893. mode |= TWL4030_APLL_RATE_48000;
  894. break;
  895. default:
  896. printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n",
  897. params_rate(params));
  898. return -EINVAL;
  899. }
  900. if (mode != old_mode) {
  901. /* change rate and set CODECPDZ */
  902. twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
  903. twl4030_set_codecpdz(codec);
  904. }
  905. /* sample size */
  906. old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  907. format = old_format;
  908. format &= ~TWL4030_DATA_WIDTH;
  909. switch (params_format(params)) {
  910. case SNDRV_PCM_FORMAT_S16_LE:
  911. format |= TWL4030_DATA_WIDTH_16S_16W;
  912. break;
  913. case SNDRV_PCM_FORMAT_S24_LE:
  914. format |= TWL4030_DATA_WIDTH_32S_24W;
  915. break;
  916. default:
  917. printk(KERN_ERR "TWL4030 hw params: unknown format %d\n",
  918. params_format(params));
  919. return -EINVAL;
  920. }
  921. if (format != old_format) {
  922. /* clear CODECPDZ before changing format (codec requirement) */
  923. twl4030_clear_codecpdz(codec);
  924. /* change format */
  925. twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
  926. /* set CODECPDZ afterwards */
  927. twl4030_set_codecpdz(codec);
  928. }
  929. return 0;
  930. }
  931. static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
  932. int clk_id, unsigned int freq, int dir)
  933. {
  934. struct snd_soc_codec *codec = codec_dai->codec;
  935. u8 infreq;
  936. switch (freq) {
  937. case 19200000:
  938. infreq = TWL4030_APLL_INFREQ_19200KHZ;
  939. break;
  940. case 26000000:
  941. infreq = TWL4030_APLL_INFREQ_26000KHZ;
  942. break;
  943. case 38400000:
  944. infreq = TWL4030_APLL_INFREQ_38400KHZ;
  945. break;
  946. default:
  947. printk(KERN_ERR "TWL4030 set sysclk: unknown rate %d\n",
  948. freq);
  949. return -EINVAL;
  950. }
  951. infreq |= TWL4030_APLL_EN;
  952. twl4030_write(codec, TWL4030_REG_APLL_CTL, infreq);
  953. return 0;
  954. }
  955. static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
  956. unsigned int fmt)
  957. {
  958. struct snd_soc_codec *codec = codec_dai->codec;
  959. u8 old_format, format;
  960. /* get format */
  961. old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  962. format = old_format;
  963. /* set master/slave audio interface */
  964. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  965. case SND_SOC_DAIFMT_CBM_CFM:
  966. format &= ~(TWL4030_AIF_SLAVE_EN);
  967. format &= ~(TWL4030_CLK256FS_EN);
  968. break;
  969. case SND_SOC_DAIFMT_CBS_CFS:
  970. format |= TWL4030_AIF_SLAVE_EN;
  971. format |= TWL4030_CLK256FS_EN;
  972. break;
  973. default:
  974. return -EINVAL;
  975. }
  976. /* interface format */
  977. format &= ~TWL4030_AIF_FORMAT;
  978. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  979. case SND_SOC_DAIFMT_I2S:
  980. format |= TWL4030_AIF_FORMAT_CODEC;
  981. break;
  982. default:
  983. return -EINVAL;
  984. }
  985. if (format != old_format) {
  986. /* clear CODECPDZ before changing format (codec requirement) */
  987. twl4030_clear_codecpdz(codec);
  988. /* change format */
  989. twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
  990. /* set CODECPDZ afterwards */
  991. twl4030_set_codecpdz(codec);
  992. }
  993. return 0;
  994. }
  995. #define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
  996. #define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE)
  997. struct snd_soc_dai twl4030_dai = {
  998. .name = "twl4030",
  999. .playback = {
  1000. .stream_name = "Playback",
  1001. .channels_min = 2,
  1002. .channels_max = 2,
  1003. .rates = TWL4030_RATES,
  1004. .formats = TWL4030_FORMATS,},
  1005. .capture = {
  1006. .stream_name = "Capture",
  1007. .channels_min = 2,
  1008. .channels_max = 2,
  1009. .rates = TWL4030_RATES,
  1010. .formats = TWL4030_FORMATS,},
  1011. .ops = {
  1012. .hw_params = twl4030_hw_params,
  1013. .set_sysclk = twl4030_set_dai_sysclk,
  1014. .set_fmt = twl4030_set_dai_fmt,
  1015. }
  1016. };
  1017. EXPORT_SYMBOL_GPL(twl4030_dai);
  1018. static int twl4030_suspend(struct platform_device *pdev, pm_message_t state)
  1019. {
  1020. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1021. struct snd_soc_codec *codec = socdev->codec;
  1022. twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
  1023. return 0;
  1024. }
  1025. static int twl4030_resume(struct platform_device *pdev)
  1026. {
  1027. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1028. struct snd_soc_codec *codec = socdev->codec;
  1029. twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  1030. twl4030_set_bias_level(codec, codec->suspend_bias_level);
  1031. return 0;
  1032. }
  1033. /*
  1034. * initialize the driver
  1035. * register the mixer and dsp interfaces with the kernel
  1036. */
  1037. static int twl4030_init(struct snd_soc_device *socdev)
  1038. {
  1039. struct snd_soc_codec *codec = socdev->codec;
  1040. int ret = 0;
  1041. printk(KERN_INFO "TWL4030 Audio Codec init \n");
  1042. codec->name = "twl4030";
  1043. codec->owner = THIS_MODULE;
  1044. codec->read = twl4030_read_reg_cache;
  1045. codec->write = twl4030_write;
  1046. codec->set_bias_level = twl4030_set_bias_level;
  1047. codec->dai = &twl4030_dai;
  1048. codec->num_dai = 1;
  1049. codec->reg_cache_size = sizeof(twl4030_reg);
  1050. codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg),
  1051. GFP_KERNEL);
  1052. if (codec->reg_cache == NULL)
  1053. return -ENOMEM;
  1054. /* register pcms */
  1055. ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
  1056. if (ret < 0) {
  1057. printk(KERN_ERR "twl4030: failed to create pcms\n");
  1058. goto pcm_err;
  1059. }
  1060. twl4030_init_chip(codec);
  1061. /* power on device */
  1062. twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  1063. twl4030_add_controls(codec);
  1064. twl4030_add_widgets(codec);
  1065. ret = snd_soc_init_card(socdev);
  1066. if (ret < 0) {
  1067. printk(KERN_ERR "twl4030: failed to register card\n");
  1068. goto card_err;
  1069. }
  1070. return ret;
  1071. card_err:
  1072. snd_soc_free_pcms(socdev);
  1073. snd_soc_dapm_free(socdev);
  1074. pcm_err:
  1075. kfree(codec->reg_cache);
  1076. return ret;
  1077. }
  1078. static struct snd_soc_device *twl4030_socdev;
  1079. static int twl4030_probe(struct platform_device *pdev)
  1080. {
  1081. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1082. struct snd_soc_codec *codec;
  1083. codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
  1084. if (codec == NULL)
  1085. return -ENOMEM;
  1086. socdev->codec = codec;
  1087. mutex_init(&codec->mutex);
  1088. INIT_LIST_HEAD(&codec->dapm_widgets);
  1089. INIT_LIST_HEAD(&codec->dapm_paths);
  1090. twl4030_socdev = socdev;
  1091. twl4030_init(socdev);
  1092. return 0;
  1093. }
  1094. static int twl4030_remove(struct platform_device *pdev)
  1095. {
  1096. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1097. struct snd_soc_codec *codec = socdev->codec;
  1098. printk(KERN_INFO "TWL4030 Audio Codec remove\n");
  1099. kfree(codec);
  1100. return 0;
  1101. }
  1102. struct snd_soc_codec_device soc_codec_dev_twl4030 = {
  1103. .probe = twl4030_probe,
  1104. .remove = twl4030_remove,
  1105. .suspend = twl4030_suspend,
  1106. .resume = twl4030_resume,
  1107. };
  1108. EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030);
  1109. static int __init twl4030_modinit(void)
  1110. {
  1111. return snd_soc_register_dai(&twl4030_dai);
  1112. }
  1113. module_init(twl4030_modinit);
  1114. static void __exit twl4030_exit(void)
  1115. {
  1116. snd_soc_unregister_dai(&twl4030_dai);
  1117. }
  1118. module_exit(twl4030_exit);
  1119. MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
  1120. MODULE_AUTHOR("Steve Sakoman");
  1121. MODULE_LICENSE("GPL");