at91sam9g45_devices.c 41 KB

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  1. /*
  2. * On-Chip devices setup code for the AT91SAM9G45 family
  3. *
  4. * Copyright (C) 2009 Atmel Corporation.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. */
  12. #include <asm/mach/arch.h>
  13. #include <asm/mach/map.h>
  14. #include <linux/dma-mapping.h>
  15. #include <linux/gpio.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/i2c-gpio.h>
  18. #include <linux/atmel-mci.h>
  19. #include <linux/fb.h>
  20. #include <video/atmel_lcdc.h>
  21. #include <mach/board.h>
  22. #include <mach/at91sam9g45.h>
  23. #include <mach/at91sam9g45_matrix.h>
  24. #include <mach/at91sam9_smc.h>
  25. #include <mach/at_hdmac.h>
  26. #include <mach/atmel-mci.h>
  27. #include "generic.h"
  28. /* --------------------------------------------------------------------
  29. * HDMAC - AHB DMA Controller
  30. * -------------------------------------------------------------------- */
  31. #if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE)
  32. static u64 hdmac_dmamask = DMA_BIT_MASK(32);
  33. static struct at_dma_platform_data atdma_pdata = {
  34. .nr_channels = 8,
  35. };
  36. static struct resource hdmac_resources[] = {
  37. [0] = {
  38. .start = AT91_BASE_SYS + AT91_DMA,
  39. .end = AT91_BASE_SYS + AT91_DMA + SZ_512 - 1,
  40. .flags = IORESOURCE_MEM,
  41. },
  42. [1] = {
  43. .start = AT91SAM9G45_ID_DMA,
  44. .end = AT91SAM9G45_ID_DMA,
  45. .flags = IORESOURCE_IRQ,
  46. },
  47. };
  48. static struct platform_device at_hdmac_device = {
  49. .name = "at_hdmac",
  50. .id = -1,
  51. .dev = {
  52. .dma_mask = &hdmac_dmamask,
  53. .coherent_dma_mask = DMA_BIT_MASK(32),
  54. .platform_data = &atdma_pdata,
  55. },
  56. .resource = hdmac_resources,
  57. .num_resources = ARRAY_SIZE(hdmac_resources),
  58. };
  59. void __init at91_add_device_hdmac(void)
  60. {
  61. dma_cap_set(DMA_MEMCPY, atdma_pdata.cap_mask);
  62. dma_cap_set(DMA_SLAVE, atdma_pdata.cap_mask);
  63. platform_device_register(&at_hdmac_device);
  64. }
  65. #else
  66. void __init at91_add_device_hdmac(void) {}
  67. #endif
  68. /* --------------------------------------------------------------------
  69. * USB Host (OHCI)
  70. * -------------------------------------------------------------------- */
  71. #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
  72. static u64 ohci_dmamask = DMA_BIT_MASK(32);
  73. static struct at91_usbh_data usbh_ohci_data;
  74. static struct resource usbh_ohci_resources[] = {
  75. [0] = {
  76. .start = AT91SAM9G45_OHCI_BASE,
  77. .end = AT91SAM9G45_OHCI_BASE + SZ_1M - 1,
  78. .flags = IORESOURCE_MEM,
  79. },
  80. [1] = {
  81. .start = AT91SAM9G45_ID_UHPHS,
  82. .end = AT91SAM9G45_ID_UHPHS,
  83. .flags = IORESOURCE_IRQ,
  84. },
  85. };
  86. static struct platform_device at91_usbh_ohci_device = {
  87. .name = "at91_ohci",
  88. .id = -1,
  89. .dev = {
  90. .dma_mask = &ohci_dmamask,
  91. .coherent_dma_mask = DMA_BIT_MASK(32),
  92. .platform_data = &usbh_ohci_data,
  93. },
  94. .resource = usbh_ohci_resources,
  95. .num_resources = ARRAY_SIZE(usbh_ohci_resources),
  96. };
  97. void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data)
  98. {
  99. int i;
  100. if (!data)
  101. return;
  102. /* Enable VBus control for UHP ports */
  103. for (i = 0; i < data->ports; i++) {
  104. if (data->vbus_pin[i])
  105. at91_set_gpio_output(data->vbus_pin[i], 0);
  106. }
  107. /* Enable overcurrent notification */
  108. for (i = 0; i < data->ports; i++) {
  109. if (data->overcurrent_pin[i])
  110. at91_set_gpio_input(data->overcurrent_pin[i], 1);
  111. }
  112. usbh_ohci_data = *data;
  113. platform_device_register(&at91_usbh_ohci_device);
  114. }
  115. #else
  116. void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data) {}
  117. #endif
  118. /* --------------------------------------------------------------------
  119. * USB Host HS (EHCI)
  120. * Needs an OHCI host for low and full speed management
  121. * -------------------------------------------------------------------- */
  122. #if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_EHCI_HCD_MODULE)
  123. static u64 ehci_dmamask = DMA_BIT_MASK(32);
  124. static struct at91_usbh_data usbh_ehci_data;
  125. static struct resource usbh_ehci_resources[] = {
  126. [0] = {
  127. .start = AT91SAM9G45_EHCI_BASE,
  128. .end = AT91SAM9G45_EHCI_BASE + SZ_1M - 1,
  129. .flags = IORESOURCE_MEM,
  130. },
  131. [1] = {
  132. .start = AT91SAM9G45_ID_UHPHS,
  133. .end = AT91SAM9G45_ID_UHPHS,
  134. .flags = IORESOURCE_IRQ,
  135. },
  136. };
  137. static struct platform_device at91_usbh_ehci_device = {
  138. .name = "atmel-ehci",
  139. .id = -1,
  140. .dev = {
  141. .dma_mask = &ehci_dmamask,
  142. .coherent_dma_mask = DMA_BIT_MASK(32),
  143. .platform_data = &usbh_ehci_data,
  144. },
  145. .resource = usbh_ehci_resources,
  146. .num_resources = ARRAY_SIZE(usbh_ehci_resources),
  147. };
  148. void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data)
  149. {
  150. int i;
  151. if (!data)
  152. return;
  153. /* Enable VBus control for UHP ports */
  154. for (i = 0; i < data->ports; i++) {
  155. if (data->vbus_pin[i])
  156. at91_set_gpio_output(data->vbus_pin[i], 0);
  157. }
  158. usbh_ehci_data = *data;
  159. platform_device_register(&at91_usbh_ehci_device);
  160. }
  161. #else
  162. void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data) {}
  163. #endif
  164. /* --------------------------------------------------------------------
  165. * USB HS Device (Gadget)
  166. * -------------------------------------------------------------------- */
  167. #if defined(CONFIG_USB_ATMEL_USBA) || defined(CONFIG_USB_ATMEL_USBA_MODULE)
  168. static struct resource usba_udc_resources[] = {
  169. [0] = {
  170. .start = AT91SAM9G45_UDPHS_FIFO,
  171. .end = AT91SAM9G45_UDPHS_FIFO + SZ_512K - 1,
  172. .flags = IORESOURCE_MEM,
  173. },
  174. [1] = {
  175. .start = AT91SAM9G45_BASE_UDPHS,
  176. .end = AT91SAM9G45_BASE_UDPHS + SZ_1K - 1,
  177. .flags = IORESOURCE_MEM,
  178. },
  179. [2] = {
  180. .start = AT91SAM9G45_ID_UDPHS,
  181. .end = AT91SAM9G45_ID_UDPHS,
  182. .flags = IORESOURCE_IRQ,
  183. },
  184. };
  185. #define EP(nam, idx, maxpkt, maxbk, dma, isoc) \
  186. [idx] = { \
  187. .name = nam, \
  188. .index = idx, \
  189. .fifo_size = maxpkt, \
  190. .nr_banks = maxbk, \
  191. .can_dma = dma, \
  192. .can_isoc = isoc, \
  193. }
  194. static struct usba_ep_data usba_udc_ep[] __initdata = {
  195. EP("ep0", 0, 64, 1, 0, 0),
  196. EP("ep1", 1, 1024, 2, 1, 1),
  197. EP("ep2", 2, 1024, 2, 1, 1),
  198. EP("ep3", 3, 1024, 3, 1, 0),
  199. EP("ep4", 4, 1024, 3, 1, 0),
  200. EP("ep5", 5, 1024, 3, 1, 1),
  201. EP("ep6", 6, 1024, 3, 1, 1),
  202. };
  203. #undef EP
  204. /*
  205. * pdata doesn't have room for any endpoints, so we need to
  206. * append room for the ones we need right after it.
  207. */
  208. static struct {
  209. struct usba_platform_data pdata;
  210. struct usba_ep_data ep[7];
  211. } usba_udc_data;
  212. static struct platform_device at91_usba_udc_device = {
  213. .name = "atmel_usba_udc",
  214. .id = -1,
  215. .dev = {
  216. .platform_data = &usba_udc_data.pdata,
  217. },
  218. .resource = usba_udc_resources,
  219. .num_resources = ARRAY_SIZE(usba_udc_resources),
  220. };
  221. void __init at91_add_device_usba(struct usba_platform_data *data)
  222. {
  223. usba_udc_data.pdata.vbus_pin = -EINVAL;
  224. usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep);
  225. memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep));
  226. if (data && data->vbus_pin > 0) {
  227. at91_set_gpio_input(data->vbus_pin, 0);
  228. at91_set_deglitch(data->vbus_pin, 1);
  229. usba_udc_data.pdata.vbus_pin = data->vbus_pin;
  230. }
  231. /* Pullup pin is handled internally by USB device peripheral */
  232. platform_device_register(&at91_usba_udc_device);
  233. }
  234. #else
  235. void __init at91_add_device_usba(struct usba_platform_data *data) {}
  236. #endif
  237. /* --------------------------------------------------------------------
  238. * Ethernet
  239. * -------------------------------------------------------------------- */
  240. #if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
  241. static u64 eth_dmamask = DMA_BIT_MASK(32);
  242. static struct at91_eth_data eth_data;
  243. static struct resource eth_resources[] = {
  244. [0] = {
  245. .start = AT91SAM9G45_BASE_EMAC,
  246. .end = AT91SAM9G45_BASE_EMAC + SZ_16K - 1,
  247. .flags = IORESOURCE_MEM,
  248. },
  249. [1] = {
  250. .start = AT91SAM9G45_ID_EMAC,
  251. .end = AT91SAM9G45_ID_EMAC,
  252. .flags = IORESOURCE_IRQ,
  253. },
  254. };
  255. static struct platform_device at91sam9g45_eth_device = {
  256. .name = "macb",
  257. .id = -1,
  258. .dev = {
  259. .dma_mask = &eth_dmamask,
  260. .coherent_dma_mask = DMA_BIT_MASK(32),
  261. .platform_data = &eth_data,
  262. },
  263. .resource = eth_resources,
  264. .num_resources = ARRAY_SIZE(eth_resources),
  265. };
  266. void __init at91_add_device_eth(struct at91_eth_data *data)
  267. {
  268. if (!data)
  269. return;
  270. if (data->phy_irq_pin) {
  271. at91_set_gpio_input(data->phy_irq_pin, 0);
  272. at91_set_deglitch(data->phy_irq_pin, 1);
  273. }
  274. /* Pins used for MII and RMII */
  275. at91_set_A_periph(AT91_PIN_PA17, 0); /* ETXCK_EREFCK */
  276. at91_set_A_periph(AT91_PIN_PA15, 0); /* ERXDV */
  277. at91_set_A_periph(AT91_PIN_PA12, 0); /* ERX0 */
  278. at91_set_A_periph(AT91_PIN_PA13, 0); /* ERX1 */
  279. at91_set_A_periph(AT91_PIN_PA16, 0); /* ERXER */
  280. at91_set_A_periph(AT91_PIN_PA14, 0); /* ETXEN */
  281. at91_set_A_periph(AT91_PIN_PA10, 0); /* ETX0 */
  282. at91_set_A_periph(AT91_PIN_PA11, 0); /* ETX1 */
  283. at91_set_A_periph(AT91_PIN_PA19, 0); /* EMDIO */
  284. at91_set_A_periph(AT91_PIN_PA18, 0); /* EMDC */
  285. if (!data->is_rmii) {
  286. at91_set_B_periph(AT91_PIN_PA29, 0); /* ECRS */
  287. at91_set_B_periph(AT91_PIN_PA30, 0); /* ECOL */
  288. at91_set_B_periph(AT91_PIN_PA8, 0); /* ERX2 */
  289. at91_set_B_periph(AT91_PIN_PA9, 0); /* ERX3 */
  290. at91_set_B_periph(AT91_PIN_PA28, 0); /* ERXCK */
  291. at91_set_B_periph(AT91_PIN_PA6, 0); /* ETX2 */
  292. at91_set_B_periph(AT91_PIN_PA7, 0); /* ETX3 */
  293. at91_set_B_periph(AT91_PIN_PA27, 0); /* ETXER */
  294. }
  295. eth_data = *data;
  296. platform_device_register(&at91sam9g45_eth_device);
  297. }
  298. #else
  299. void __init at91_add_device_eth(struct at91_eth_data *data) {}
  300. #endif
  301. /* --------------------------------------------------------------------
  302. * MMC / SD
  303. * -------------------------------------------------------------------- */
  304. #if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE)
  305. static u64 mmc_dmamask = DMA_BIT_MASK(32);
  306. static struct mci_platform_data mmc0_data, mmc1_data;
  307. static struct resource mmc0_resources[] = {
  308. [0] = {
  309. .start = AT91SAM9G45_BASE_MCI0,
  310. .end = AT91SAM9G45_BASE_MCI0 + SZ_16K - 1,
  311. .flags = IORESOURCE_MEM,
  312. },
  313. [1] = {
  314. .start = AT91SAM9G45_ID_MCI0,
  315. .end = AT91SAM9G45_ID_MCI0,
  316. .flags = IORESOURCE_IRQ,
  317. },
  318. };
  319. static struct platform_device at91sam9g45_mmc0_device = {
  320. .name = "atmel_mci",
  321. .id = 0,
  322. .dev = {
  323. .dma_mask = &mmc_dmamask,
  324. .coherent_dma_mask = DMA_BIT_MASK(32),
  325. .platform_data = &mmc0_data,
  326. },
  327. .resource = mmc0_resources,
  328. .num_resources = ARRAY_SIZE(mmc0_resources),
  329. };
  330. static struct resource mmc1_resources[] = {
  331. [0] = {
  332. .start = AT91SAM9G45_BASE_MCI1,
  333. .end = AT91SAM9G45_BASE_MCI1 + SZ_16K - 1,
  334. .flags = IORESOURCE_MEM,
  335. },
  336. [1] = {
  337. .start = AT91SAM9G45_ID_MCI1,
  338. .end = AT91SAM9G45_ID_MCI1,
  339. .flags = IORESOURCE_IRQ,
  340. },
  341. };
  342. static struct platform_device at91sam9g45_mmc1_device = {
  343. .name = "atmel_mci",
  344. .id = 1,
  345. .dev = {
  346. .dma_mask = &mmc_dmamask,
  347. .coherent_dma_mask = DMA_BIT_MASK(32),
  348. .platform_data = &mmc1_data,
  349. },
  350. .resource = mmc1_resources,
  351. .num_resources = ARRAY_SIZE(mmc1_resources),
  352. };
  353. /* Consider only one slot : slot 0 */
  354. void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data)
  355. {
  356. if (!data)
  357. return;
  358. /* Must have at least one usable slot */
  359. if (!data->slot[0].bus_width)
  360. return;
  361. #if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE)
  362. {
  363. struct at_dma_slave *atslave;
  364. struct mci_dma_data *alt_atslave;
  365. alt_atslave = kzalloc(sizeof(struct mci_dma_data), GFP_KERNEL);
  366. atslave = &alt_atslave->sdata;
  367. /* DMA slave channel configuration */
  368. atslave->dma_dev = &at_hdmac_device.dev;
  369. atslave->reg_width = AT_DMA_SLAVE_WIDTH_32BIT;
  370. atslave->cfg = ATC_FIFOCFG_HALFFIFO
  371. | ATC_SRC_H2SEL_HW | ATC_DST_H2SEL_HW;
  372. atslave->ctrla = ATC_SCSIZE_16 | ATC_DCSIZE_16;
  373. if (mmc_id == 0) /* MCI0 */
  374. atslave->cfg |= ATC_SRC_PER(AT_DMA_ID_MCI0)
  375. | ATC_DST_PER(AT_DMA_ID_MCI0);
  376. else /* MCI1 */
  377. atslave->cfg |= ATC_SRC_PER(AT_DMA_ID_MCI1)
  378. | ATC_DST_PER(AT_DMA_ID_MCI1);
  379. data->dma_slave = alt_atslave;
  380. }
  381. #endif
  382. /* input/irq */
  383. if (data->slot[0].detect_pin) {
  384. at91_set_gpio_input(data->slot[0].detect_pin, 1);
  385. at91_set_deglitch(data->slot[0].detect_pin, 1);
  386. }
  387. if (data->slot[0].wp_pin)
  388. at91_set_gpio_input(data->slot[0].wp_pin, 1);
  389. if (mmc_id == 0) { /* MCI0 */
  390. /* CLK */
  391. at91_set_A_periph(AT91_PIN_PA0, 0);
  392. /* CMD */
  393. at91_set_A_periph(AT91_PIN_PA1, 1);
  394. /* DAT0, maybe DAT1..DAT3 and maybe DAT4..DAT7 */
  395. at91_set_A_periph(AT91_PIN_PA2, 1);
  396. if (data->slot[0].bus_width == 4) {
  397. at91_set_A_periph(AT91_PIN_PA3, 1);
  398. at91_set_A_periph(AT91_PIN_PA4, 1);
  399. at91_set_A_periph(AT91_PIN_PA5, 1);
  400. if (data->slot[0].bus_width == 8) {
  401. at91_set_A_periph(AT91_PIN_PA6, 1);
  402. at91_set_A_periph(AT91_PIN_PA7, 1);
  403. at91_set_A_periph(AT91_PIN_PA8, 1);
  404. at91_set_A_periph(AT91_PIN_PA9, 1);
  405. }
  406. }
  407. mmc0_data = *data;
  408. platform_device_register(&at91sam9g45_mmc0_device);
  409. } else { /* MCI1 */
  410. /* CLK */
  411. at91_set_A_periph(AT91_PIN_PA31, 0);
  412. /* CMD */
  413. at91_set_A_periph(AT91_PIN_PA22, 1);
  414. /* DAT0, maybe DAT1..DAT3 and maybe DAT4..DAT7 */
  415. at91_set_A_periph(AT91_PIN_PA23, 1);
  416. if (data->slot[0].bus_width == 4) {
  417. at91_set_A_periph(AT91_PIN_PA24, 1);
  418. at91_set_A_periph(AT91_PIN_PA25, 1);
  419. at91_set_A_periph(AT91_PIN_PA26, 1);
  420. if (data->slot[0].bus_width == 8) {
  421. at91_set_A_periph(AT91_PIN_PA27, 1);
  422. at91_set_A_periph(AT91_PIN_PA28, 1);
  423. at91_set_A_periph(AT91_PIN_PA29, 1);
  424. at91_set_A_periph(AT91_PIN_PA30, 1);
  425. }
  426. }
  427. mmc1_data = *data;
  428. platform_device_register(&at91sam9g45_mmc1_device);
  429. }
  430. }
  431. #else
  432. void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data) {}
  433. #endif
  434. /* --------------------------------------------------------------------
  435. * NAND / SmartMedia
  436. * -------------------------------------------------------------------- */
  437. #if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
  438. static struct atmel_nand_data nand_data;
  439. #define NAND_BASE AT91_CHIPSELECT_3
  440. static struct resource nand_resources[] = {
  441. [0] = {
  442. .start = NAND_BASE,
  443. .end = NAND_BASE + SZ_256M - 1,
  444. .flags = IORESOURCE_MEM,
  445. },
  446. [1] = {
  447. .start = AT91_BASE_SYS + AT91_ECC,
  448. .end = AT91_BASE_SYS + AT91_ECC + SZ_512 - 1,
  449. .flags = IORESOURCE_MEM,
  450. }
  451. };
  452. static struct platform_device at91sam9g45_nand_device = {
  453. .name = "atmel_nand",
  454. .id = -1,
  455. .dev = {
  456. .platform_data = &nand_data,
  457. },
  458. .resource = nand_resources,
  459. .num_resources = ARRAY_SIZE(nand_resources),
  460. };
  461. void __init at91_add_device_nand(struct atmel_nand_data *data)
  462. {
  463. unsigned long csa;
  464. if (!data)
  465. return;
  466. csa = at91_sys_read(AT91_MATRIX_EBICSA);
  467. at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
  468. /* enable pin */
  469. if (data->enable_pin)
  470. at91_set_gpio_output(data->enable_pin, 1);
  471. /* ready/busy pin */
  472. if (data->rdy_pin)
  473. at91_set_gpio_input(data->rdy_pin, 1);
  474. /* card detect pin */
  475. if (data->det_pin)
  476. at91_set_gpio_input(data->det_pin, 1);
  477. nand_data = *data;
  478. platform_device_register(&at91sam9g45_nand_device);
  479. }
  480. #else
  481. void __init at91_add_device_nand(struct atmel_nand_data *data) {}
  482. #endif
  483. /* --------------------------------------------------------------------
  484. * TWI (i2c)
  485. * -------------------------------------------------------------------- */
  486. /*
  487. * Prefer the GPIO code since the TWI controller isn't robust
  488. * (gets overruns and underruns under load) and can only issue
  489. * repeated STARTs in one scenario (the driver doesn't yet handle them).
  490. */
  491. #if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
  492. static struct i2c_gpio_platform_data pdata_i2c0 = {
  493. .sda_pin = AT91_PIN_PA20,
  494. .sda_is_open_drain = 1,
  495. .scl_pin = AT91_PIN_PA21,
  496. .scl_is_open_drain = 1,
  497. .udelay = 5, /* ~100 kHz */
  498. };
  499. static struct platform_device at91sam9g45_twi0_device = {
  500. .name = "i2c-gpio",
  501. .id = 0,
  502. .dev.platform_data = &pdata_i2c0,
  503. };
  504. static struct i2c_gpio_platform_data pdata_i2c1 = {
  505. .sda_pin = AT91_PIN_PB10,
  506. .sda_is_open_drain = 1,
  507. .scl_pin = AT91_PIN_PB11,
  508. .scl_is_open_drain = 1,
  509. .udelay = 5, /* ~100 kHz */
  510. };
  511. static struct platform_device at91sam9g45_twi1_device = {
  512. .name = "i2c-gpio",
  513. .id = 1,
  514. .dev.platform_data = &pdata_i2c1,
  515. };
  516. void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices)
  517. {
  518. i2c_register_board_info(i2c_id, devices, nr_devices);
  519. if (i2c_id == 0) {
  520. at91_set_GPIO_periph(AT91_PIN_PA20, 1); /* TWD (SDA) */
  521. at91_set_multi_drive(AT91_PIN_PA20, 1);
  522. at91_set_GPIO_periph(AT91_PIN_PA21, 1); /* TWCK (SCL) */
  523. at91_set_multi_drive(AT91_PIN_PA21, 1);
  524. platform_device_register(&at91sam9g45_twi0_device);
  525. } else {
  526. at91_set_GPIO_periph(AT91_PIN_PB10, 1); /* TWD (SDA) */
  527. at91_set_multi_drive(AT91_PIN_PB10, 1);
  528. at91_set_GPIO_periph(AT91_PIN_PB11, 1); /* TWCK (SCL) */
  529. at91_set_multi_drive(AT91_PIN_PB11, 1);
  530. platform_device_register(&at91sam9g45_twi1_device);
  531. }
  532. }
  533. #elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
  534. static struct resource twi0_resources[] = {
  535. [0] = {
  536. .start = AT91SAM9G45_BASE_TWI0,
  537. .end = AT91SAM9G45_BASE_TWI0 + SZ_16K - 1,
  538. .flags = IORESOURCE_MEM,
  539. },
  540. [1] = {
  541. .start = AT91SAM9G45_ID_TWI0,
  542. .end = AT91SAM9G45_ID_TWI0,
  543. .flags = IORESOURCE_IRQ,
  544. },
  545. };
  546. static struct platform_device at91sam9g45_twi0_device = {
  547. .name = "at91_i2c",
  548. .id = 0,
  549. .resource = twi0_resources,
  550. .num_resources = ARRAY_SIZE(twi0_resources),
  551. };
  552. static struct resource twi1_resources[] = {
  553. [0] = {
  554. .start = AT91SAM9G45_BASE_TWI1,
  555. .end = AT91SAM9G45_BASE_TWI1 + SZ_16K - 1,
  556. .flags = IORESOURCE_MEM,
  557. },
  558. [1] = {
  559. .start = AT91SAM9G45_ID_TWI1,
  560. .end = AT91SAM9G45_ID_TWI1,
  561. .flags = IORESOURCE_IRQ,
  562. },
  563. };
  564. static struct platform_device at91sam9g45_twi1_device = {
  565. .name = "at91_i2c",
  566. .id = 1,
  567. .resource = twi1_resources,
  568. .num_resources = ARRAY_SIZE(twi1_resources),
  569. };
  570. void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices)
  571. {
  572. i2c_register_board_info(i2c_id, devices, nr_devices);
  573. /* pins used for TWI interface */
  574. if (i2c_id == 0) {
  575. at91_set_A_periph(AT91_PIN_PA20, 0); /* TWD */
  576. at91_set_multi_drive(AT91_PIN_PA20, 1);
  577. at91_set_A_periph(AT91_PIN_PA21, 0); /* TWCK */
  578. at91_set_multi_drive(AT91_PIN_PA21, 1);
  579. platform_device_register(&at91sam9g45_twi0_device);
  580. } else {
  581. at91_set_A_periph(AT91_PIN_PB10, 0); /* TWD */
  582. at91_set_multi_drive(AT91_PIN_PB10, 1);
  583. at91_set_A_periph(AT91_PIN_PB11, 0); /* TWCK */
  584. at91_set_multi_drive(AT91_PIN_PB11, 1);
  585. platform_device_register(&at91sam9g45_twi1_device);
  586. }
  587. }
  588. #else
  589. void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices) {}
  590. #endif
  591. /* --------------------------------------------------------------------
  592. * SPI
  593. * -------------------------------------------------------------------- */
  594. #if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
  595. static u64 spi_dmamask = DMA_BIT_MASK(32);
  596. static struct resource spi0_resources[] = {
  597. [0] = {
  598. .start = AT91SAM9G45_BASE_SPI0,
  599. .end = AT91SAM9G45_BASE_SPI0 + SZ_16K - 1,
  600. .flags = IORESOURCE_MEM,
  601. },
  602. [1] = {
  603. .start = AT91SAM9G45_ID_SPI0,
  604. .end = AT91SAM9G45_ID_SPI0,
  605. .flags = IORESOURCE_IRQ,
  606. },
  607. };
  608. static struct platform_device at91sam9g45_spi0_device = {
  609. .name = "atmel_spi",
  610. .id = 0,
  611. .dev = {
  612. .dma_mask = &spi_dmamask,
  613. .coherent_dma_mask = DMA_BIT_MASK(32),
  614. },
  615. .resource = spi0_resources,
  616. .num_resources = ARRAY_SIZE(spi0_resources),
  617. };
  618. static const unsigned spi0_standard_cs[4] = { AT91_PIN_PB3, AT91_PIN_PB18, AT91_PIN_PB19, AT91_PIN_PD27 };
  619. static struct resource spi1_resources[] = {
  620. [0] = {
  621. .start = AT91SAM9G45_BASE_SPI1,
  622. .end = AT91SAM9G45_BASE_SPI1 + SZ_16K - 1,
  623. .flags = IORESOURCE_MEM,
  624. },
  625. [1] = {
  626. .start = AT91SAM9G45_ID_SPI1,
  627. .end = AT91SAM9G45_ID_SPI1,
  628. .flags = IORESOURCE_IRQ,
  629. },
  630. };
  631. static struct platform_device at91sam9g45_spi1_device = {
  632. .name = "atmel_spi",
  633. .id = 1,
  634. .dev = {
  635. .dma_mask = &spi_dmamask,
  636. .coherent_dma_mask = DMA_BIT_MASK(32),
  637. },
  638. .resource = spi1_resources,
  639. .num_resources = ARRAY_SIZE(spi1_resources),
  640. };
  641. static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB17, AT91_PIN_PD28, AT91_PIN_PD18, AT91_PIN_PD19 };
  642. void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
  643. {
  644. int i;
  645. unsigned long cs_pin;
  646. short enable_spi0 = 0;
  647. short enable_spi1 = 0;
  648. /* Choose SPI chip-selects */
  649. for (i = 0; i < nr_devices; i++) {
  650. if (devices[i].controller_data)
  651. cs_pin = (unsigned long) devices[i].controller_data;
  652. else if (devices[i].bus_num == 0)
  653. cs_pin = spi0_standard_cs[devices[i].chip_select];
  654. else
  655. cs_pin = spi1_standard_cs[devices[i].chip_select];
  656. if (devices[i].bus_num == 0)
  657. enable_spi0 = 1;
  658. else
  659. enable_spi1 = 1;
  660. /* enable chip-select pin */
  661. at91_set_gpio_output(cs_pin, 1);
  662. /* pass chip-select pin to driver */
  663. devices[i].controller_data = (void *) cs_pin;
  664. }
  665. spi_register_board_info(devices, nr_devices);
  666. /* Configure SPI bus(es) */
  667. if (enable_spi0) {
  668. at91_set_A_periph(AT91_PIN_PB0, 0); /* SPI0_MISO */
  669. at91_set_A_periph(AT91_PIN_PB1, 0); /* SPI0_MOSI */
  670. at91_set_A_periph(AT91_PIN_PB2, 0); /* SPI0_SPCK */
  671. platform_device_register(&at91sam9g45_spi0_device);
  672. }
  673. if (enable_spi1) {
  674. at91_set_A_periph(AT91_PIN_PB14, 0); /* SPI1_MISO */
  675. at91_set_A_periph(AT91_PIN_PB15, 0); /* SPI1_MOSI */
  676. at91_set_A_periph(AT91_PIN_PB16, 0); /* SPI1_SPCK */
  677. platform_device_register(&at91sam9g45_spi1_device);
  678. }
  679. }
  680. #else
  681. void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
  682. #endif
  683. /* --------------------------------------------------------------------
  684. * AC97
  685. * -------------------------------------------------------------------- */
  686. #if defined(CONFIG_SND_ATMEL_AC97C) || defined(CONFIG_SND_ATMEL_AC97C_MODULE)
  687. static u64 ac97_dmamask = DMA_BIT_MASK(32);
  688. static struct ac97c_platform_data ac97_data;
  689. static struct resource ac97_resources[] = {
  690. [0] = {
  691. .start = AT91SAM9G45_BASE_AC97C,
  692. .end = AT91SAM9G45_BASE_AC97C + SZ_16K - 1,
  693. .flags = IORESOURCE_MEM,
  694. },
  695. [1] = {
  696. .start = AT91SAM9G45_ID_AC97C,
  697. .end = AT91SAM9G45_ID_AC97C,
  698. .flags = IORESOURCE_IRQ,
  699. },
  700. };
  701. static struct platform_device at91sam9g45_ac97_device = {
  702. .name = "atmel_ac97c",
  703. .id = 0,
  704. .dev = {
  705. .dma_mask = &ac97_dmamask,
  706. .coherent_dma_mask = DMA_BIT_MASK(32),
  707. .platform_data = &ac97_data,
  708. },
  709. .resource = ac97_resources,
  710. .num_resources = ARRAY_SIZE(ac97_resources),
  711. };
  712. void __init at91_add_device_ac97(struct ac97c_platform_data *data)
  713. {
  714. if (!data)
  715. return;
  716. at91_set_A_periph(AT91_PIN_PD8, 0); /* AC97FS */
  717. at91_set_A_periph(AT91_PIN_PD9, 0); /* AC97CK */
  718. at91_set_A_periph(AT91_PIN_PD7, 0); /* AC97TX */
  719. at91_set_A_periph(AT91_PIN_PD6, 0); /* AC97RX */
  720. /* reset */
  721. if (data->reset_pin)
  722. at91_set_gpio_output(data->reset_pin, 0);
  723. ac97_data = *data;
  724. platform_device_register(&at91sam9g45_ac97_device);
  725. }
  726. #else
  727. void __init at91_add_device_ac97(struct ac97c_platform_data *data) {}
  728. #endif
  729. /* --------------------------------------------------------------------
  730. * LCD Controller
  731. * -------------------------------------------------------------------- */
  732. #if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
  733. static u64 lcdc_dmamask = DMA_BIT_MASK(32);
  734. static struct atmel_lcdfb_info lcdc_data;
  735. static struct resource lcdc_resources[] = {
  736. [0] = {
  737. .start = AT91SAM9G45_LCDC_BASE,
  738. .end = AT91SAM9G45_LCDC_BASE + SZ_4K - 1,
  739. .flags = IORESOURCE_MEM,
  740. },
  741. [1] = {
  742. .start = AT91SAM9G45_ID_LCDC,
  743. .end = AT91SAM9G45_ID_LCDC,
  744. .flags = IORESOURCE_IRQ,
  745. },
  746. };
  747. static struct platform_device at91_lcdc_device = {
  748. .name = "atmel_lcdfb",
  749. .id = 0,
  750. .dev = {
  751. .dma_mask = &lcdc_dmamask,
  752. .coherent_dma_mask = DMA_BIT_MASK(32),
  753. .platform_data = &lcdc_data,
  754. },
  755. .resource = lcdc_resources,
  756. .num_resources = ARRAY_SIZE(lcdc_resources),
  757. };
  758. void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
  759. {
  760. if (!data)
  761. return;
  762. at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */
  763. at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */
  764. at91_set_A_periph(AT91_PIN_PE3, 0); /* LCDVSYNC */
  765. at91_set_A_periph(AT91_PIN_PE4, 0); /* LCDHSYNC */
  766. at91_set_A_periph(AT91_PIN_PE5, 0); /* LCDDOTCK */
  767. at91_set_A_periph(AT91_PIN_PE6, 0); /* LCDDEN */
  768. at91_set_A_periph(AT91_PIN_PE7, 0); /* LCDD0 */
  769. at91_set_A_periph(AT91_PIN_PE8, 0); /* LCDD1 */
  770. at91_set_A_periph(AT91_PIN_PE9, 0); /* LCDD2 */
  771. at91_set_A_periph(AT91_PIN_PE10, 0); /* LCDD3 */
  772. at91_set_A_periph(AT91_PIN_PE11, 0); /* LCDD4 */
  773. at91_set_A_periph(AT91_PIN_PE12, 0); /* LCDD5 */
  774. at91_set_A_periph(AT91_PIN_PE13, 0); /* LCDD6 */
  775. at91_set_A_periph(AT91_PIN_PE14, 0); /* LCDD7 */
  776. at91_set_A_periph(AT91_PIN_PE15, 0); /* LCDD8 */
  777. at91_set_A_periph(AT91_PIN_PE16, 0); /* LCDD9 */
  778. at91_set_A_periph(AT91_PIN_PE17, 0); /* LCDD10 */
  779. at91_set_A_periph(AT91_PIN_PE18, 0); /* LCDD11 */
  780. at91_set_A_periph(AT91_PIN_PE19, 0); /* LCDD12 */
  781. at91_set_A_periph(AT91_PIN_PE20, 0); /* LCDD13 */
  782. at91_set_A_periph(AT91_PIN_PE21, 0); /* LCDD14 */
  783. at91_set_A_periph(AT91_PIN_PE22, 0); /* LCDD15 */
  784. at91_set_A_periph(AT91_PIN_PE23, 0); /* LCDD16 */
  785. at91_set_A_periph(AT91_PIN_PE24, 0); /* LCDD17 */
  786. at91_set_A_periph(AT91_PIN_PE25, 0); /* LCDD18 */
  787. at91_set_A_periph(AT91_PIN_PE26, 0); /* LCDD19 */
  788. at91_set_A_periph(AT91_PIN_PE27, 0); /* LCDD20 */
  789. at91_set_A_periph(AT91_PIN_PE28, 0); /* LCDD21 */
  790. at91_set_A_periph(AT91_PIN_PE29, 0); /* LCDD22 */
  791. at91_set_A_periph(AT91_PIN_PE30, 0); /* LCDD23 */
  792. lcdc_data = *data;
  793. platform_device_register(&at91_lcdc_device);
  794. }
  795. #else
  796. void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
  797. #endif
  798. /* --------------------------------------------------------------------
  799. * Timer/Counter block
  800. * -------------------------------------------------------------------- */
  801. #ifdef CONFIG_ATMEL_TCLIB
  802. static struct resource tcb0_resources[] = {
  803. [0] = {
  804. .start = AT91SAM9G45_BASE_TCB0,
  805. .end = AT91SAM9G45_BASE_TCB0 + SZ_16K - 1,
  806. .flags = IORESOURCE_MEM,
  807. },
  808. [1] = {
  809. .start = AT91SAM9G45_ID_TCB,
  810. .end = AT91SAM9G45_ID_TCB,
  811. .flags = IORESOURCE_IRQ,
  812. },
  813. };
  814. static struct platform_device at91sam9g45_tcb0_device = {
  815. .name = "atmel_tcb",
  816. .id = 0,
  817. .resource = tcb0_resources,
  818. .num_resources = ARRAY_SIZE(tcb0_resources),
  819. };
  820. /* TCB1 begins with TC3 */
  821. static struct resource tcb1_resources[] = {
  822. [0] = {
  823. .start = AT91SAM9G45_BASE_TCB1,
  824. .end = AT91SAM9G45_BASE_TCB1 + SZ_16K - 1,
  825. .flags = IORESOURCE_MEM,
  826. },
  827. [1] = {
  828. .start = AT91SAM9G45_ID_TCB,
  829. .end = AT91SAM9G45_ID_TCB,
  830. .flags = IORESOURCE_IRQ,
  831. },
  832. };
  833. static struct platform_device at91sam9g45_tcb1_device = {
  834. .name = "atmel_tcb",
  835. .id = 1,
  836. .resource = tcb1_resources,
  837. .num_resources = ARRAY_SIZE(tcb1_resources),
  838. };
  839. static void __init at91_add_device_tc(void)
  840. {
  841. platform_device_register(&at91sam9g45_tcb0_device);
  842. platform_device_register(&at91sam9g45_tcb1_device);
  843. }
  844. #else
  845. static void __init at91_add_device_tc(void) { }
  846. #endif
  847. /* --------------------------------------------------------------------
  848. * RTC
  849. * -------------------------------------------------------------------- */
  850. #if defined(CONFIG_RTC_DRV_AT91RM9200) || defined(CONFIG_RTC_DRV_AT91RM9200_MODULE)
  851. static struct platform_device at91sam9g45_rtc_device = {
  852. .name = "at91_rtc",
  853. .id = -1,
  854. .num_resources = 0,
  855. };
  856. static void __init at91_add_device_rtc(void)
  857. {
  858. platform_device_register(&at91sam9g45_rtc_device);
  859. }
  860. #else
  861. static void __init at91_add_device_rtc(void) {}
  862. #endif
  863. /* --------------------------------------------------------------------
  864. * Touchscreen
  865. * -------------------------------------------------------------------- */
  866. #if defined(CONFIG_TOUCHSCREEN_ATMEL_TSADCC) || defined(CONFIG_TOUCHSCREEN_ATMEL_TSADCC_MODULE)
  867. static u64 tsadcc_dmamask = DMA_BIT_MASK(32);
  868. static struct at91_tsadcc_data tsadcc_data;
  869. static struct resource tsadcc_resources[] = {
  870. [0] = {
  871. .start = AT91SAM9G45_BASE_TSC,
  872. .end = AT91SAM9G45_BASE_TSC + SZ_16K - 1,
  873. .flags = IORESOURCE_MEM,
  874. },
  875. [1] = {
  876. .start = AT91SAM9G45_ID_TSC,
  877. .end = AT91SAM9G45_ID_TSC,
  878. .flags = IORESOURCE_IRQ,
  879. }
  880. };
  881. static struct platform_device at91sam9g45_tsadcc_device = {
  882. .name = "atmel_tsadcc",
  883. .id = -1,
  884. .dev = {
  885. .dma_mask = &tsadcc_dmamask,
  886. .coherent_dma_mask = DMA_BIT_MASK(32),
  887. .platform_data = &tsadcc_data,
  888. },
  889. .resource = tsadcc_resources,
  890. .num_resources = ARRAY_SIZE(tsadcc_resources),
  891. };
  892. void __init at91_add_device_tsadcc(struct at91_tsadcc_data *data)
  893. {
  894. if (!data)
  895. return;
  896. at91_set_gpio_input(AT91_PIN_PD20, 0); /* AD0_XR */
  897. at91_set_gpio_input(AT91_PIN_PD21, 0); /* AD1_XL */
  898. at91_set_gpio_input(AT91_PIN_PD22, 0); /* AD2_YT */
  899. at91_set_gpio_input(AT91_PIN_PD23, 0); /* AD3_TB */
  900. tsadcc_data = *data;
  901. platform_device_register(&at91sam9g45_tsadcc_device);
  902. }
  903. #else
  904. void __init at91_add_device_tsadcc(struct at91_tsadcc_data *data) {}
  905. #endif
  906. /* --------------------------------------------------------------------
  907. * RTT
  908. * -------------------------------------------------------------------- */
  909. static struct resource rtt_resources[] = {
  910. {
  911. .start = AT91_BASE_SYS + AT91_RTT,
  912. .end = AT91_BASE_SYS + AT91_RTT + SZ_16 - 1,
  913. .flags = IORESOURCE_MEM,
  914. }
  915. };
  916. static struct platform_device at91sam9g45_rtt_device = {
  917. .name = "at91_rtt",
  918. .id = 0,
  919. .resource = rtt_resources,
  920. .num_resources = ARRAY_SIZE(rtt_resources),
  921. };
  922. static void __init at91_add_device_rtt(void)
  923. {
  924. platform_device_register(&at91sam9g45_rtt_device);
  925. }
  926. /* --------------------------------------------------------------------
  927. * TRNG
  928. * -------------------------------------------------------------------- */
  929. #if defined(CONFIG_HW_RANDOM_ATMEL) || defined(CONFIG_HW_RANDOM_ATMEL_MODULE)
  930. static struct resource trng_resources[] = {
  931. {
  932. .start = AT91SAM9G45_BASE_TRNG,
  933. .end = AT91SAM9G45_BASE_TRNG + SZ_16K - 1,
  934. .flags = IORESOURCE_MEM,
  935. },
  936. };
  937. static struct platform_device at91sam9g45_trng_device = {
  938. .name = "atmel-trng",
  939. .id = -1,
  940. .resource = trng_resources,
  941. .num_resources = ARRAY_SIZE(trng_resources),
  942. };
  943. static void __init at91_add_device_trng(void)
  944. {
  945. platform_device_register(&at91sam9g45_trng_device);
  946. }
  947. #else
  948. static void __init at91_add_device_trng(void) {}
  949. #endif
  950. /* --------------------------------------------------------------------
  951. * Watchdog
  952. * -------------------------------------------------------------------- */
  953. #if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
  954. static struct platform_device at91sam9g45_wdt_device = {
  955. .name = "at91_wdt",
  956. .id = -1,
  957. .num_resources = 0,
  958. };
  959. static void __init at91_add_device_watchdog(void)
  960. {
  961. platform_device_register(&at91sam9g45_wdt_device);
  962. }
  963. #else
  964. static void __init at91_add_device_watchdog(void) {}
  965. #endif
  966. /* --------------------------------------------------------------------
  967. * PWM
  968. * --------------------------------------------------------------------*/
  969. #if defined(CONFIG_ATMEL_PWM) || defined(CONFIG_ATMEL_PWM_MODULE)
  970. static u32 pwm_mask;
  971. static struct resource pwm_resources[] = {
  972. [0] = {
  973. .start = AT91SAM9G45_BASE_PWMC,
  974. .end = AT91SAM9G45_BASE_PWMC + SZ_16K - 1,
  975. .flags = IORESOURCE_MEM,
  976. },
  977. [1] = {
  978. .start = AT91SAM9G45_ID_PWMC,
  979. .end = AT91SAM9G45_ID_PWMC,
  980. .flags = IORESOURCE_IRQ,
  981. },
  982. };
  983. static struct platform_device at91sam9g45_pwm0_device = {
  984. .name = "atmel_pwm",
  985. .id = -1,
  986. .dev = {
  987. .platform_data = &pwm_mask,
  988. },
  989. .resource = pwm_resources,
  990. .num_resources = ARRAY_SIZE(pwm_resources),
  991. };
  992. void __init at91_add_device_pwm(u32 mask)
  993. {
  994. if (mask & (1 << AT91_PWM0))
  995. at91_set_B_periph(AT91_PIN_PD24, 1); /* enable PWM0 */
  996. if (mask & (1 << AT91_PWM1))
  997. at91_set_B_periph(AT91_PIN_PD31, 1); /* enable PWM1 */
  998. if (mask & (1 << AT91_PWM2))
  999. at91_set_B_periph(AT91_PIN_PD26, 1); /* enable PWM2 */
  1000. if (mask & (1 << AT91_PWM3))
  1001. at91_set_B_periph(AT91_PIN_PD0, 1); /* enable PWM3 */
  1002. pwm_mask = mask;
  1003. platform_device_register(&at91sam9g45_pwm0_device);
  1004. }
  1005. #else
  1006. void __init at91_add_device_pwm(u32 mask) {}
  1007. #endif
  1008. /* --------------------------------------------------------------------
  1009. * SSC -- Synchronous Serial Controller
  1010. * -------------------------------------------------------------------- */
  1011. #if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
  1012. static u64 ssc0_dmamask = DMA_BIT_MASK(32);
  1013. static struct resource ssc0_resources[] = {
  1014. [0] = {
  1015. .start = AT91SAM9G45_BASE_SSC0,
  1016. .end = AT91SAM9G45_BASE_SSC0 + SZ_16K - 1,
  1017. .flags = IORESOURCE_MEM,
  1018. },
  1019. [1] = {
  1020. .start = AT91SAM9G45_ID_SSC0,
  1021. .end = AT91SAM9G45_ID_SSC0,
  1022. .flags = IORESOURCE_IRQ,
  1023. },
  1024. };
  1025. static struct platform_device at91sam9g45_ssc0_device = {
  1026. .name = "ssc",
  1027. .id = 0,
  1028. .dev = {
  1029. .dma_mask = &ssc0_dmamask,
  1030. .coherent_dma_mask = DMA_BIT_MASK(32),
  1031. },
  1032. .resource = ssc0_resources,
  1033. .num_resources = ARRAY_SIZE(ssc0_resources),
  1034. };
  1035. static inline void configure_ssc0_pins(unsigned pins)
  1036. {
  1037. if (pins & ATMEL_SSC_TF)
  1038. at91_set_A_periph(AT91_PIN_PD1, 1);
  1039. if (pins & ATMEL_SSC_TK)
  1040. at91_set_A_periph(AT91_PIN_PD0, 1);
  1041. if (pins & ATMEL_SSC_TD)
  1042. at91_set_A_periph(AT91_PIN_PD2, 1);
  1043. if (pins & ATMEL_SSC_RD)
  1044. at91_set_A_periph(AT91_PIN_PD3, 1);
  1045. if (pins & ATMEL_SSC_RK)
  1046. at91_set_A_periph(AT91_PIN_PD4, 1);
  1047. if (pins & ATMEL_SSC_RF)
  1048. at91_set_A_periph(AT91_PIN_PD5, 1);
  1049. }
  1050. static u64 ssc1_dmamask = DMA_BIT_MASK(32);
  1051. static struct resource ssc1_resources[] = {
  1052. [0] = {
  1053. .start = AT91SAM9G45_BASE_SSC1,
  1054. .end = AT91SAM9G45_BASE_SSC1 + SZ_16K - 1,
  1055. .flags = IORESOURCE_MEM,
  1056. },
  1057. [1] = {
  1058. .start = AT91SAM9G45_ID_SSC1,
  1059. .end = AT91SAM9G45_ID_SSC1,
  1060. .flags = IORESOURCE_IRQ,
  1061. },
  1062. };
  1063. static struct platform_device at91sam9g45_ssc1_device = {
  1064. .name = "ssc",
  1065. .id = 1,
  1066. .dev = {
  1067. .dma_mask = &ssc1_dmamask,
  1068. .coherent_dma_mask = DMA_BIT_MASK(32),
  1069. },
  1070. .resource = ssc1_resources,
  1071. .num_resources = ARRAY_SIZE(ssc1_resources),
  1072. };
  1073. static inline void configure_ssc1_pins(unsigned pins)
  1074. {
  1075. if (pins & ATMEL_SSC_TF)
  1076. at91_set_A_periph(AT91_PIN_PD14, 1);
  1077. if (pins & ATMEL_SSC_TK)
  1078. at91_set_A_periph(AT91_PIN_PD12, 1);
  1079. if (pins & ATMEL_SSC_TD)
  1080. at91_set_A_periph(AT91_PIN_PD10, 1);
  1081. if (pins & ATMEL_SSC_RD)
  1082. at91_set_A_periph(AT91_PIN_PD11, 1);
  1083. if (pins & ATMEL_SSC_RK)
  1084. at91_set_A_periph(AT91_PIN_PD13, 1);
  1085. if (pins & ATMEL_SSC_RF)
  1086. at91_set_A_periph(AT91_PIN_PD15, 1);
  1087. }
  1088. /*
  1089. * SSC controllers are accessed through library code, instead of any
  1090. * kind of all-singing/all-dancing driver. For example one could be
  1091. * used by a particular I2S audio codec's driver, while another one
  1092. * on the same system might be used by a custom data capture driver.
  1093. */
  1094. void __init at91_add_device_ssc(unsigned id, unsigned pins)
  1095. {
  1096. struct platform_device *pdev;
  1097. /*
  1098. * NOTE: caller is responsible for passing information matching
  1099. * "pins" to whatever will be using each particular controller.
  1100. */
  1101. switch (id) {
  1102. case AT91SAM9G45_ID_SSC0:
  1103. pdev = &at91sam9g45_ssc0_device;
  1104. configure_ssc0_pins(pins);
  1105. break;
  1106. case AT91SAM9G45_ID_SSC1:
  1107. pdev = &at91sam9g45_ssc1_device;
  1108. configure_ssc1_pins(pins);
  1109. break;
  1110. default:
  1111. return;
  1112. }
  1113. platform_device_register(pdev);
  1114. }
  1115. #else
  1116. void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
  1117. #endif
  1118. /* --------------------------------------------------------------------
  1119. * UART
  1120. * -------------------------------------------------------------------- */
  1121. #if defined(CONFIG_SERIAL_ATMEL)
  1122. static struct resource dbgu_resources[] = {
  1123. [0] = {
  1124. .start = AT91_BASE_SYS + AT91_DBGU,
  1125. .end = AT91_BASE_SYS + AT91_DBGU + SZ_512 - 1,
  1126. .flags = IORESOURCE_MEM,
  1127. },
  1128. [1] = {
  1129. .start = AT91_ID_SYS,
  1130. .end = AT91_ID_SYS,
  1131. .flags = IORESOURCE_IRQ,
  1132. },
  1133. };
  1134. static struct atmel_uart_data dbgu_data = {
  1135. .use_dma_tx = 0,
  1136. .use_dma_rx = 0,
  1137. };
  1138. static u64 dbgu_dmamask = DMA_BIT_MASK(32);
  1139. static struct platform_device at91sam9g45_dbgu_device = {
  1140. .name = "atmel_usart",
  1141. .id = 0,
  1142. .dev = {
  1143. .dma_mask = &dbgu_dmamask,
  1144. .coherent_dma_mask = DMA_BIT_MASK(32),
  1145. .platform_data = &dbgu_data,
  1146. },
  1147. .resource = dbgu_resources,
  1148. .num_resources = ARRAY_SIZE(dbgu_resources),
  1149. };
  1150. static inline void configure_dbgu_pins(void)
  1151. {
  1152. at91_set_A_periph(AT91_PIN_PB12, 0); /* DRXD */
  1153. at91_set_A_periph(AT91_PIN_PB13, 1); /* DTXD */
  1154. }
  1155. static struct resource uart0_resources[] = {
  1156. [0] = {
  1157. .start = AT91SAM9G45_BASE_US0,
  1158. .end = AT91SAM9G45_BASE_US0 + SZ_16K - 1,
  1159. .flags = IORESOURCE_MEM,
  1160. },
  1161. [1] = {
  1162. .start = AT91SAM9G45_ID_US0,
  1163. .end = AT91SAM9G45_ID_US0,
  1164. .flags = IORESOURCE_IRQ,
  1165. },
  1166. };
  1167. static struct atmel_uart_data uart0_data = {
  1168. .use_dma_tx = 1,
  1169. .use_dma_rx = 1,
  1170. };
  1171. static u64 uart0_dmamask = DMA_BIT_MASK(32);
  1172. static struct platform_device at91sam9g45_uart0_device = {
  1173. .name = "atmel_usart",
  1174. .id = 1,
  1175. .dev = {
  1176. .dma_mask = &uart0_dmamask,
  1177. .coherent_dma_mask = DMA_BIT_MASK(32),
  1178. .platform_data = &uart0_data,
  1179. },
  1180. .resource = uart0_resources,
  1181. .num_resources = ARRAY_SIZE(uart0_resources),
  1182. };
  1183. static inline void configure_usart0_pins(unsigned pins)
  1184. {
  1185. at91_set_A_periph(AT91_PIN_PB19, 1); /* TXD0 */
  1186. at91_set_A_periph(AT91_PIN_PB18, 0); /* RXD0 */
  1187. if (pins & ATMEL_UART_RTS)
  1188. at91_set_B_periph(AT91_PIN_PB17, 0); /* RTS0 */
  1189. if (pins & ATMEL_UART_CTS)
  1190. at91_set_B_periph(AT91_PIN_PB15, 0); /* CTS0 */
  1191. }
  1192. static struct resource uart1_resources[] = {
  1193. [0] = {
  1194. .start = AT91SAM9G45_BASE_US1,
  1195. .end = AT91SAM9G45_BASE_US1 + SZ_16K - 1,
  1196. .flags = IORESOURCE_MEM,
  1197. },
  1198. [1] = {
  1199. .start = AT91SAM9G45_ID_US1,
  1200. .end = AT91SAM9G45_ID_US1,
  1201. .flags = IORESOURCE_IRQ,
  1202. },
  1203. };
  1204. static struct atmel_uart_data uart1_data = {
  1205. .use_dma_tx = 1,
  1206. .use_dma_rx = 1,
  1207. };
  1208. static u64 uart1_dmamask = DMA_BIT_MASK(32);
  1209. static struct platform_device at91sam9g45_uart1_device = {
  1210. .name = "atmel_usart",
  1211. .id = 2,
  1212. .dev = {
  1213. .dma_mask = &uart1_dmamask,
  1214. .coherent_dma_mask = DMA_BIT_MASK(32),
  1215. .platform_data = &uart1_data,
  1216. },
  1217. .resource = uart1_resources,
  1218. .num_resources = ARRAY_SIZE(uart1_resources),
  1219. };
  1220. static inline void configure_usart1_pins(unsigned pins)
  1221. {
  1222. at91_set_A_periph(AT91_PIN_PB4, 1); /* TXD1 */
  1223. at91_set_A_periph(AT91_PIN_PB5, 0); /* RXD1 */
  1224. if (pins & ATMEL_UART_RTS)
  1225. at91_set_A_periph(AT91_PIN_PD16, 0); /* RTS1 */
  1226. if (pins & ATMEL_UART_CTS)
  1227. at91_set_A_periph(AT91_PIN_PD17, 0); /* CTS1 */
  1228. }
  1229. static struct resource uart2_resources[] = {
  1230. [0] = {
  1231. .start = AT91SAM9G45_BASE_US2,
  1232. .end = AT91SAM9G45_BASE_US2 + SZ_16K - 1,
  1233. .flags = IORESOURCE_MEM,
  1234. },
  1235. [1] = {
  1236. .start = AT91SAM9G45_ID_US2,
  1237. .end = AT91SAM9G45_ID_US2,
  1238. .flags = IORESOURCE_IRQ,
  1239. },
  1240. };
  1241. static struct atmel_uart_data uart2_data = {
  1242. .use_dma_tx = 1,
  1243. .use_dma_rx = 1,
  1244. };
  1245. static u64 uart2_dmamask = DMA_BIT_MASK(32);
  1246. static struct platform_device at91sam9g45_uart2_device = {
  1247. .name = "atmel_usart",
  1248. .id = 3,
  1249. .dev = {
  1250. .dma_mask = &uart2_dmamask,
  1251. .coherent_dma_mask = DMA_BIT_MASK(32),
  1252. .platform_data = &uart2_data,
  1253. },
  1254. .resource = uart2_resources,
  1255. .num_resources = ARRAY_SIZE(uart2_resources),
  1256. };
  1257. static inline void configure_usart2_pins(unsigned pins)
  1258. {
  1259. at91_set_A_periph(AT91_PIN_PB6, 1); /* TXD2 */
  1260. at91_set_A_periph(AT91_PIN_PB7, 0); /* RXD2 */
  1261. if (pins & ATMEL_UART_RTS)
  1262. at91_set_B_periph(AT91_PIN_PC9, 0); /* RTS2 */
  1263. if (pins & ATMEL_UART_CTS)
  1264. at91_set_B_periph(AT91_PIN_PC11, 0); /* CTS2 */
  1265. }
  1266. static struct resource uart3_resources[] = {
  1267. [0] = {
  1268. .start = AT91SAM9G45_BASE_US3,
  1269. .end = AT91SAM9G45_BASE_US3 + SZ_16K - 1,
  1270. .flags = IORESOURCE_MEM,
  1271. },
  1272. [1] = {
  1273. .start = AT91SAM9G45_ID_US3,
  1274. .end = AT91SAM9G45_ID_US3,
  1275. .flags = IORESOURCE_IRQ,
  1276. },
  1277. };
  1278. static struct atmel_uart_data uart3_data = {
  1279. .use_dma_tx = 1,
  1280. .use_dma_rx = 1,
  1281. };
  1282. static u64 uart3_dmamask = DMA_BIT_MASK(32);
  1283. static struct platform_device at91sam9g45_uart3_device = {
  1284. .name = "atmel_usart",
  1285. .id = 4,
  1286. .dev = {
  1287. .dma_mask = &uart3_dmamask,
  1288. .coherent_dma_mask = DMA_BIT_MASK(32),
  1289. .platform_data = &uart3_data,
  1290. },
  1291. .resource = uart3_resources,
  1292. .num_resources = ARRAY_SIZE(uart3_resources),
  1293. };
  1294. static inline void configure_usart3_pins(unsigned pins)
  1295. {
  1296. at91_set_A_periph(AT91_PIN_PB8, 1); /* TXD3 */
  1297. at91_set_A_periph(AT91_PIN_PB9, 0); /* RXD3 */
  1298. if (pins & ATMEL_UART_RTS)
  1299. at91_set_B_periph(AT91_PIN_PA23, 0); /* RTS3 */
  1300. if (pins & ATMEL_UART_CTS)
  1301. at91_set_B_periph(AT91_PIN_PA24, 0); /* CTS3 */
  1302. }
  1303. static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
  1304. struct platform_device *atmel_default_console_device; /* the serial console device */
  1305. void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
  1306. {
  1307. struct platform_device *pdev;
  1308. struct atmel_uart_data *pdata;
  1309. switch (id) {
  1310. case 0: /* DBGU */
  1311. pdev = &at91sam9g45_dbgu_device;
  1312. configure_dbgu_pins();
  1313. break;
  1314. case AT91SAM9G45_ID_US0:
  1315. pdev = &at91sam9g45_uart0_device;
  1316. configure_usart0_pins(pins);
  1317. break;
  1318. case AT91SAM9G45_ID_US1:
  1319. pdev = &at91sam9g45_uart1_device;
  1320. configure_usart1_pins(pins);
  1321. break;
  1322. case AT91SAM9G45_ID_US2:
  1323. pdev = &at91sam9g45_uart2_device;
  1324. configure_usart2_pins(pins);
  1325. break;
  1326. case AT91SAM9G45_ID_US3:
  1327. pdev = &at91sam9g45_uart3_device;
  1328. configure_usart3_pins(pins);
  1329. break;
  1330. default:
  1331. return;
  1332. }
  1333. pdata = pdev->dev.platform_data;
  1334. pdata->num = portnr; /* update to mapped ID */
  1335. if (portnr < ATMEL_MAX_UART)
  1336. at91_uarts[portnr] = pdev;
  1337. }
  1338. void __init at91_set_serial_console(unsigned portnr)
  1339. {
  1340. if (portnr < ATMEL_MAX_UART) {
  1341. atmel_default_console_device = at91_uarts[portnr];
  1342. at91sam9g45_set_console_clock(at91_uarts[portnr]->id);
  1343. }
  1344. }
  1345. void __init at91_add_device_serial(void)
  1346. {
  1347. int i;
  1348. for (i = 0; i < ATMEL_MAX_UART; i++) {
  1349. if (at91_uarts[i])
  1350. platform_device_register(at91_uarts[i]);
  1351. }
  1352. if (!atmel_default_console_device)
  1353. printk(KERN_INFO "AT91: No default serial console defined.\n");
  1354. }
  1355. #else
  1356. void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
  1357. void __init at91_set_serial_console(unsigned portnr) {}
  1358. void __init at91_add_device_serial(void) {}
  1359. #endif
  1360. /* -------------------------------------------------------------------- */
  1361. /*
  1362. * These devices are always present and don't need any board-specific
  1363. * setup.
  1364. */
  1365. static int __init at91_add_standard_devices(void)
  1366. {
  1367. at91_add_device_hdmac();
  1368. at91_add_device_rtc();
  1369. at91_add_device_rtt();
  1370. at91_add_device_trng();
  1371. at91_add_device_watchdog();
  1372. at91_add_device_tc();
  1373. return 0;
  1374. }
  1375. arch_initcall(at91_add_standard_devices);