spi-davinci.c 27 KB

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  1. /*
  2. * Copyright (C) 2009 Texas Instruments.
  3. * Copyright (C) 2010 EF Johnson Technologies
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation; either version 2 of the License, or
  8. * (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  18. */
  19. #include <linux/interrupt.h>
  20. #include <linux/io.h>
  21. #include <linux/gpio.h>
  22. #include <linux/module.h>
  23. #include <linux/delay.h>
  24. #include <linux/platform_device.h>
  25. #include <linux/err.h>
  26. #include <linux/clk.h>
  27. #include <linux/dmaengine.h>
  28. #include <linux/dma-mapping.h>
  29. #include <linux/edma.h>
  30. #include <linux/of.h>
  31. #include <linux/of_device.h>
  32. #include <linux/spi/spi.h>
  33. #include <linux/spi/spi_bitbang.h>
  34. #include <linux/slab.h>
  35. #include <linux/platform_data/spi-davinci.h>
  36. #define SPI_NO_RESOURCE ((resource_size_t)-1)
  37. #define SPI_MAX_CHIPSELECT 2
  38. #define CS_DEFAULT 0xFF
  39. #define SPIFMT_PHASE_MASK BIT(16)
  40. #define SPIFMT_POLARITY_MASK BIT(17)
  41. #define SPIFMT_DISTIMER_MASK BIT(18)
  42. #define SPIFMT_SHIFTDIR_MASK BIT(20)
  43. #define SPIFMT_WAITENA_MASK BIT(21)
  44. #define SPIFMT_PARITYENA_MASK BIT(22)
  45. #define SPIFMT_ODD_PARITY_MASK BIT(23)
  46. #define SPIFMT_WDELAY_MASK 0x3f000000u
  47. #define SPIFMT_WDELAY_SHIFT 24
  48. #define SPIFMT_PRESCALE_SHIFT 8
  49. /* SPIPC0 */
  50. #define SPIPC0_DIFUN_MASK BIT(11) /* MISO */
  51. #define SPIPC0_DOFUN_MASK BIT(10) /* MOSI */
  52. #define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */
  53. #define SPIPC0_SPIENA_MASK BIT(8) /* nREADY */
  54. #define SPIINT_MASKALL 0x0101035F
  55. #define SPIINT_MASKINT 0x0000015F
  56. #define SPI_INTLVL_1 0x000001FF
  57. #define SPI_INTLVL_0 0x00000000
  58. /* SPIDAT1 (upper 16 bit defines) */
  59. #define SPIDAT1_CSHOLD_MASK BIT(12)
  60. /* SPIGCR1 */
  61. #define SPIGCR1_CLKMOD_MASK BIT(1)
  62. #define SPIGCR1_MASTER_MASK BIT(0)
  63. #define SPIGCR1_POWERDOWN_MASK BIT(8)
  64. #define SPIGCR1_LOOPBACK_MASK BIT(16)
  65. #define SPIGCR1_SPIENA_MASK BIT(24)
  66. /* SPIBUF */
  67. #define SPIBUF_TXFULL_MASK BIT(29)
  68. #define SPIBUF_RXEMPTY_MASK BIT(31)
  69. /* SPIDELAY */
  70. #define SPIDELAY_C2TDELAY_SHIFT 24
  71. #define SPIDELAY_C2TDELAY_MASK (0xFF << SPIDELAY_C2TDELAY_SHIFT)
  72. #define SPIDELAY_T2CDELAY_SHIFT 16
  73. #define SPIDELAY_T2CDELAY_MASK (0xFF << SPIDELAY_T2CDELAY_SHIFT)
  74. #define SPIDELAY_T2EDELAY_SHIFT 8
  75. #define SPIDELAY_T2EDELAY_MASK (0xFF << SPIDELAY_T2EDELAY_SHIFT)
  76. #define SPIDELAY_C2EDELAY_SHIFT 0
  77. #define SPIDELAY_C2EDELAY_MASK 0xFF
  78. /* Error Masks */
  79. #define SPIFLG_DLEN_ERR_MASK BIT(0)
  80. #define SPIFLG_TIMEOUT_MASK BIT(1)
  81. #define SPIFLG_PARERR_MASK BIT(2)
  82. #define SPIFLG_DESYNC_MASK BIT(3)
  83. #define SPIFLG_BITERR_MASK BIT(4)
  84. #define SPIFLG_OVRRUN_MASK BIT(6)
  85. #define SPIFLG_BUF_INIT_ACTIVE_MASK BIT(24)
  86. #define SPIFLG_ERROR_MASK (SPIFLG_DLEN_ERR_MASK \
  87. | SPIFLG_TIMEOUT_MASK | SPIFLG_PARERR_MASK \
  88. | SPIFLG_DESYNC_MASK | SPIFLG_BITERR_MASK \
  89. | SPIFLG_OVRRUN_MASK)
  90. #define SPIINT_DMA_REQ_EN BIT(16)
  91. /* SPI Controller registers */
  92. #define SPIGCR0 0x00
  93. #define SPIGCR1 0x04
  94. #define SPIINT 0x08
  95. #define SPILVL 0x0c
  96. #define SPIFLG 0x10
  97. #define SPIPC0 0x14
  98. #define SPIDAT1 0x3c
  99. #define SPIBUF 0x40
  100. #define SPIDELAY 0x48
  101. #define SPIDEF 0x4c
  102. #define SPIFMT0 0x50
  103. /* SPI Controller driver's private data. */
  104. struct davinci_spi {
  105. struct spi_bitbang bitbang;
  106. struct clk *clk;
  107. u8 version;
  108. resource_size_t pbase;
  109. void __iomem *base;
  110. u32 irq;
  111. struct completion done;
  112. const void *tx;
  113. void *rx;
  114. int rcount;
  115. int wcount;
  116. struct dma_chan *dma_rx;
  117. struct dma_chan *dma_tx;
  118. int dma_rx_chnum;
  119. int dma_tx_chnum;
  120. struct davinci_spi_platform_data pdata;
  121. void (*get_rx)(u32 rx_data, struct davinci_spi *);
  122. u32 (*get_tx)(struct davinci_spi *);
  123. u8 bytes_per_word[SPI_MAX_CHIPSELECT];
  124. };
  125. static struct davinci_spi_config davinci_spi_default_cfg;
  126. static void davinci_spi_rx_buf_u8(u32 data, struct davinci_spi *dspi)
  127. {
  128. if (dspi->rx) {
  129. u8 *rx = dspi->rx;
  130. *rx++ = (u8)data;
  131. dspi->rx = rx;
  132. }
  133. }
  134. static void davinci_spi_rx_buf_u16(u32 data, struct davinci_spi *dspi)
  135. {
  136. if (dspi->rx) {
  137. u16 *rx = dspi->rx;
  138. *rx++ = (u16)data;
  139. dspi->rx = rx;
  140. }
  141. }
  142. static u32 davinci_spi_tx_buf_u8(struct davinci_spi *dspi)
  143. {
  144. u32 data = 0;
  145. if (dspi->tx) {
  146. const u8 *tx = dspi->tx;
  147. data = *tx++;
  148. dspi->tx = tx;
  149. }
  150. return data;
  151. }
  152. static u32 davinci_spi_tx_buf_u16(struct davinci_spi *dspi)
  153. {
  154. u32 data = 0;
  155. if (dspi->tx) {
  156. const u16 *tx = dspi->tx;
  157. data = *tx++;
  158. dspi->tx = tx;
  159. }
  160. return data;
  161. }
  162. static inline void set_io_bits(void __iomem *addr, u32 bits)
  163. {
  164. u32 v = ioread32(addr);
  165. v |= bits;
  166. iowrite32(v, addr);
  167. }
  168. static inline void clear_io_bits(void __iomem *addr, u32 bits)
  169. {
  170. u32 v = ioread32(addr);
  171. v &= ~bits;
  172. iowrite32(v, addr);
  173. }
  174. /*
  175. * Interface to control the chip select signal
  176. */
  177. static void davinci_spi_chipselect(struct spi_device *spi, int value)
  178. {
  179. struct davinci_spi *dspi;
  180. struct davinci_spi_platform_data *pdata;
  181. u8 chip_sel = spi->chip_select;
  182. u16 spidat1 = CS_DEFAULT;
  183. bool gpio_chipsel = false;
  184. dspi = spi_master_get_devdata(spi->master);
  185. pdata = &dspi->pdata;
  186. if (pdata->chip_sel && chip_sel < pdata->num_chipselect &&
  187. pdata->chip_sel[chip_sel] != SPI_INTERN_CS)
  188. gpio_chipsel = true;
  189. /*
  190. * Board specific chip select logic decides the polarity and cs
  191. * line for the controller
  192. */
  193. if (gpio_chipsel) {
  194. if (value == BITBANG_CS_ACTIVE)
  195. gpio_set_value(pdata->chip_sel[chip_sel], 0);
  196. else
  197. gpio_set_value(pdata->chip_sel[chip_sel], 1);
  198. } else {
  199. if (value == BITBANG_CS_ACTIVE) {
  200. spidat1 |= SPIDAT1_CSHOLD_MASK;
  201. spidat1 &= ~(0x1 << chip_sel);
  202. }
  203. iowrite16(spidat1, dspi->base + SPIDAT1 + 2);
  204. }
  205. }
  206. /**
  207. * davinci_spi_get_prescale - Calculates the correct prescale value
  208. * @maxspeed_hz: the maximum rate the SPI clock can run at
  209. *
  210. * This function calculates the prescale value that generates a clock rate
  211. * less than or equal to the specified maximum.
  212. *
  213. * Returns: calculated prescale - 1 for easy programming into SPI registers
  214. * or negative error number if valid prescalar cannot be updated.
  215. */
  216. static inline int davinci_spi_get_prescale(struct davinci_spi *dspi,
  217. u32 max_speed_hz)
  218. {
  219. int ret;
  220. ret = DIV_ROUND_UP(clk_get_rate(dspi->clk), max_speed_hz);
  221. if (ret < 3 || ret > 256)
  222. return -EINVAL;
  223. return ret - 1;
  224. }
  225. /**
  226. * davinci_spi_setup_transfer - This functions will determine transfer method
  227. * @spi: spi device on which data transfer to be done
  228. * @t: spi transfer in which transfer info is filled
  229. *
  230. * This function determines data transfer method (8/16/32 bit transfer).
  231. * It will also set the SPI Clock Control register according to
  232. * SPI slave device freq.
  233. */
  234. static int davinci_spi_setup_transfer(struct spi_device *spi,
  235. struct spi_transfer *t)
  236. {
  237. struct davinci_spi *dspi;
  238. struct davinci_spi_config *spicfg;
  239. u8 bits_per_word = 0;
  240. u32 hz = 0, spifmt = 0, prescale = 0;
  241. dspi = spi_master_get_devdata(spi->master);
  242. spicfg = (struct davinci_spi_config *)spi->controller_data;
  243. if (!spicfg)
  244. spicfg = &davinci_spi_default_cfg;
  245. if (t) {
  246. bits_per_word = t->bits_per_word;
  247. hz = t->speed_hz;
  248. }
  249. /* if bits_per_word is not set then set it default */
  250. if (!bits_per_word)
  251. bits_per_word = spi->bits_per_word;
  252. /*
  253. * Assign function pointer to appropriate transfer method
  254. * 8bit, 16bit or 32bit transfer
  255. */
  256. if (bits_per_word <= 8 && bits_per_word >= 2) {
  257. dspi->get_rx = davinci_spi_rx_buf_u8;
  258. dspi->get_tx = davinci_spi_tx_buf_u8;
  259. dspi->bytes_per_word[spi->chip_select] = 1;
  260. } else if (bits_per_word <= 16 && bits_per_word >= 2) {
  261. dspi->get_rx = davinci_spi_rx_buf_u16;
  262. dspi->get_tx = davinci_spi_tx_buf_u16;
  263. dspi->bytes_per_word[spi->chip_select] = 2;
  264. } else
  265. return -EINVAL;
  266. if (!hz)
  267. hz = spi->max_speed_hz;
  268. /* Set up SPIFMTn register, unique to this chipselect. */
  269. prescale = davinci_spi_get_prescale(dspi, hz);
  270. if (prescale < 0)
  271. return prescale;
  272. spifmt = (prescale << SPIFMT_PRESCALE_SHIFT) | (bits_per_word & 0x1f);
  273. if (spi->mode & SPI_LSB_FIRST)
  274. spifmt |= SPIFMT_SHIFTDIR_MASK;
  275. if (spi->mode & SPI_CPOL)
  276. spifmt |= SPIFMT_POLARITY_MASK;
  277. if (!(spi->mode & SPI_CPHA))
  278. spifmt |= SPIFMT_PHASE_MASK;
  279. /*
  280. * Version 1 hardware supports two basic SPI modes:
  281. * - Standard SPI mode uses 4 pins, with chipselect
  282. * - 3 pin SPI is a 4 pin variant without CS (SPI_NO_CS)
  283. * (distinct from SPI_3WIRE, with just one data wire;
  284. * or similar variants without MOSI or without MISO)
  285. *
  286. * Version 2 hardware supports an optional handshaking signal,
  287. * so it can support two more modes:
  288. * - 5 pin SPI variant is standard SPI plus SPI_READY
  289. * - 4 pin with enable is (SPI_READY | SPI_NO_CS)
  290. */
  291. if (dspi->version == SPI_VERSION_2) {
  292. u32 delay = 0;
  293. spifmt |= ((spicfg->wdelay << SPIFMT_WDELAY_SHIFT)
  294. & SPIFMT_WDELAY_MASK);
  295. if (spicfg->odd_parity)
  296. spifmt |= SPIFMT_ODD_PARITY_MASK;
  297. if (spicfg->parity_enable)
  298. spifmt |= SPIFMT_PARITYENA_MASK;
  299. if (spicfg->timer_disable) {
  300. spifmt |= SPIFMT_DISTIMER_MASK;
  301. } else {
  302. delay |= (spicfg->c2tdelay << SPIDELAY_C2TDELAY_SHIFT)
  303. & SPIDELAY_C2TDELAY_MASK;
  304. delay |= (spicfg->t2cdelay << SPIDELAY_T2CDELAY_SHIFT)
  305. & SPIDELAY_T2CDELAY_MASK;
  306. }
  307. if (spi->mode & SPI_READY) {
  308. spifmt |= SPIFMT_WAITENA_MASK;
  309. delay |= (spicfg->t2edelay << SPIDELAY_T2EDELAY_SHIFT)
  310. & SPIDELAY_T2EDELAY_MASK;
  311. delay |= (spicfg->c2edelay << SPIDELAY_C2EDELAY_SHIFT)
  312. & SPIDELAY_C2EDELAY_MASK;
  313. }
  314. iowrite32(delay, dspi->base + SPIDELAY);
  315. }
  316. iowrite32(spifmt, dspi->base + SPIFMT0);
  317. return 0;
  318. }
  319. /**
  320. * davinci_spi_setup - This functions will set default transfer method
  321. * @spi: spi device on which data transfer to be done
  322. *
  323. * This functions sets the default transfer method.
  324. */
  325. static int davinci_spi_setup(struct spi_device *spi)
  326. {
  327. int retval = 0;
  328. struct davinci_spi *dspi;
  329. struct davinci_spi_platform_data *pdata;
  330. dspi = spi_master_get_devdata(spi->master);
  331. pdata = &dspi->pdata;
  332. /* if bits per word length is zero then set it default 8 */
  333. if (!spi->bits_per_word)
  334. spi->bits_per_word = 8;
  335. if (!(spi->mode & SPI_NO_CS)) {
  336. if ((pdata->chip_sel == NULL) ||
  337. (pdata->chip_sel[spi->chip_select] == SPI_INTERN_CS))
  338. set_io_bits(dspi->base + SPIPC0, 1 << spi->chip_select);
  339. }
  340. if (spi->mode & SPI_READY)
  341. set_io_bits(dspi->base + SPIPC0, SPIPC0_SPIENA_MASK);
  342. if (spi->mode & SPI_LOOP)
  343. set_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK);
  344. else
  345. clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK);
  346. return retval;
  347. }
  348. static int davinci_spi_check_error(struct davinci_spi *dspi, int int_status)
  349. {
  350. struct device *sdev = dspi->bitbang.master->dev.parent;
  351. if (int_status & SPIFLG_TIMEOUT_MASK) {
  352. dev_dbg(sdev, "SPI Time-out Error\n");
  353. return -ETIMEDOUT;
  354. }
  355. if (int_status & SPIFLG_DESYNC_MASK) {
  356. dev_dbg(sdev, "SPI Desynchronization Error\n");
  357. return -EIO;
  358. }
  359. if (int_status & SPIFLG_BITERR_MASK) {
  360. dev_dbg(sdev, "SPI Bit error\n");
  361. return -EIO;
  362. }
  363. if (dspi->version == SPI_VERSION_2) {
  364. if (int_status & SPIFLG_DLEN_ERR_MASK) {
  365. dev_dbg(sdev, "SPI Data Length Error\n");
  366. return -EIO;
  367. }
  368. if (int_status & SPIFLG_PARERR_MASK) {
  369. dev_dbg(sdev, "SPI Parity Error\n");
  370. return -EIO;
  371. }
  372. if (int_status & SPIFLG_OVRRUN_MASK) {
  373. dev_dbg(sdev, "SPI Data Overrun error\n");
  374. return -EIO;
  375. }
  376. if (int_status & SPIFLG_BUF_INIT_ACTIVE_MASK) {
  377. dev_dbg(sdev, "SPI Buffer Init Active\n");
  378. return -EBUSY;
  379. }
  380. }
  381. return 0;
  382. }
  383. /**
  384. * davinci_spi_process_events - check for and handle any SPI controller events
  385. * @dspi: the controller data
  386. *
  387. * This function will check the SPIFLG register and handle any events that are
  388. * detected there
  389. */
  390. static int davinci_spi_process_events(struct davinci_spi *dspi)
  391. {
  392. u32 buf, status, errors = 0, spidat1;
  393. buf = ioread32(dspi->base + SPIBUF);
  394. if (dspi->rcount > 0 && !(buf & SPIBUF_RXEMPTY_MASK)) {
  395. dspi->get_rx(buf & 0xFFFF, dspi);
  396. dspi->rcount--;
  397. }
  398. status = ioread32(dspi->base + SPIFLG);
  399. if (unlikely(status & SPIFLG_ERROR_MASK)) {
  400. errors = status & SPIFLG_ERROR_MASK;
  401. goto out;
  402. }
  403. if (dspi->wcount > 0 && !(buf & SPIBUF_TXFULL_MASK)) {
  404. spidat1 = ioread32(dspi->base + SPIDAT1);
  405. dspi->wcount--;
  406. spidat1 &= ~0xFFFF;
  407. spidat1 |= 0xFFFF & dspi->get_tx(dspi);
  408. iowrite32(spidat1, dspi->base + SPIDAT1);
  409. }
  410. out:
  411. return errors;
  412. }
  413. static void davinci_spi_dma_rx_callback(void *data)
  414. {
  415. struct davinci_spi *dspi = (struct davinci_spi *)data;
  416. dspi->rcount = 0;
  417. if (!dspi->wcount && !dspi->rcount)
  418. complete(&dspi->done);
  419. }
  420. static void davinci_spi_dma_tx_callback(void *data)
  421. {
  422. struct davinci_spi *dspi = (struct davinci_spi *)data;
  423. dspi->wcount = 0;
  424. if (!dspi->wcount && !dspi->rcount)
  425. complete(&dspi->done);
  426. }
  427. /**
  428. * davinci_spi_bufs - functions which will handle transfer data
  429. * @spi: spi device on which data transfer to be done
  430. * @t: spi transfer in which transfer info is filled
  431. *
  432. * This function will put data to be transferred into data register
  433. * of SPI controller and then wait until the completion will be marked
  434. * by the IRQ Handler.
  435. */
  436. static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t)
  437. {
  438. struct davinci_spi *dspi;
  439. int data_type, ret = -ENOMEM;
  440. u32 tx_data, spidat1;
  441. u32 errors = 0;
  442. struct davinci_spi_config *spicfg;
  443. struct davinci_spi_platform_data *pdata;
  444. unsigned uninitialized_var(rx_buf_count);
  445. void *dummy_buf = NULL;
  446. struct scatterlist sg_rx, sg_tx;
  447. dspi = spi_master_get_devdata(spi->master);
  448. pdata = &dspi->pdata;
  449. spicfg = (struct davinci_spi_config *)spi->controller_data;
  450. if (!spicfg)
  451. spicfg = &davinci_spi_default_cfg;
  452. /* convert len to words based on bits_per_word */
  453. data_type = dspi->bytes_per_word[spi->chip_select];
  454. dspi->tx = t->tx_buf;
  455. dspi->rx = t->rx_buf;
  456. dspi->wcount = t->len / data_type;
  457. dspi->rcount = dspi->wcount;
  458. spidat1 = ioread32(dspi->base + SPIDAT1);
  459. clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
  460. set_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
  461. INIT_COMPLETION(dspi->done);
  462. if (spicfg->io_type == SPI_IO_TYPE_INTR)
  463. set_io_bits(dspi->base + SPIINT, SPIINT_MASKINT);
  464. if (spicfg->io_type != SPI_IO_TYPE_DMA) {
  465. /* start the transfer */
  466. dspi->wcount--;
  467. tx_data = dspi->get_tx(dspi);
  468. spidat1 &= 0xFFFF0000;
  469. spidat1 |= tx_data & 0xFFFF;
  470. iowrite32(spidat1, dspi->base + SPIDAT1);
  471. } else {
  472. struct dma_slave_config dma_rx_conf = {
  473. .direction = DMA_DEV_TO_MEM,
  474. .src_addr = (unsigned long)dspi->pbase + SPIBUF,
  475. .src_addr_width = data_type,
  476. .src_maxburst = 1,
  477. };
  478. struct dma_slave_config dma_tx_conf = {
  479. .direction = DMA_MEM_TO_DEV,
  480. .dst_addr = (unsigned long)dspi->pbase + SPIDAT1,
  481. .dst_addr_width = data_type,
  482. .dst_maxburst = 1,
  483. };
  484. struct dma_async_tx_descriptor *rxdesc;
  485. struct dma_async_tx_descriptor *txdesc;
  486. void *buf;
  487. dummy_buf = kzalloc(t->len, GFP_KERNEL);
  488. if (!dummy_buf)
  489. goto err_alloc_dummy_buf;
  490. dmaengine_slave_config(dspi->dma_rx, &dma_rx_conf);
  491. dmaengine_slave_config(dspi->dma_tx, &dma_tx_conf);
  492. sg_init_table(&sg_rx, 1);
  493. if (!t->rx_buf)
  494. buf = dummy_buf;
  495. else
  496. buf = t->rx_buf;
  497. t->rx_dma = dma_map_single(&spi->dev, buf,
  498. t->len, DMA_FROM_DEVICE);
  499. if (!t->rx_dma) {
  500. ret = -EFAULT;
  501. goto err_rx_map;
  502. }
  503. sg_dma_address(&sg_rx) = t->rx_dma;
  504. sg_dma_len(&sg_rx) = t->len;
  505. sg_init_table(&sg_tx, 1);
  506. if (!t->tx_buf)
  507. buf = dummy_buf;
  508. else
  509. buf = (void *)t->tx_buf;
  510. t->tx_dma = dma_map_single(&spi->dev, buf,
  511. t->len, DMA_FROM_DEVICE);
  512. if (!t->tx_dma) {
  513. ret = -EFAULT;
  514. goto err_tx_map;
  515. }
  516. sg_dma_address(&sg_tx) = t->tx_dma;
  517. sg_dma_len(&sg_tx) = t->len;
  518. rxdesc = dmaengine_prep_slave_sg(dspi->dma_rx,
  519. &sg_rx, 1, DMA_DEV_TO_MEM,
  520. DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
  521. if (!rxdesc)
  522. goto err_desc;
  523. txdesc = dmaengine_prep_slave_sg(dspi->dma_tx,
  524. &sg_tx, 1, DMA_MEM_TO_DEV,
  525. DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
  526. if (!txdesc)
  527. goto err_desc;
  528. rxdesc->callback = davinci_spi_dma_rx_callback;
  529. rxdesc->callback_param = (void *)dspi;
  530. txdesc->callback = davinci_spi_dma_tx_callback;
  531. txdesc->callback_param = (void *)dspi;
  532. if (pdata->cshold_bug)
  533. iowrite16(spidat1 >> 16, dspi->base + SPIDAT1 + 2);
  534. dmaengine_submit(rxdesc);
  535. dmaengine_submit(txdesc);
  536. dma_async_issue_pending(dspi->dma_rx);
  537. dma_async_issue_pending(dspi->dma_tx);
  538. set_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN);
  539. }
  540. /* Wait for the transfer to complete */
  541. if (spicfg->io_type != SPI_IO_TYPE_POLL) {
  542. wait_for_completion_interruptible(&(dspi->done));
  543. } else {
  544. while (dspi->rcount > 0 || dspi->wcount > 0) {
  545. errors = davinci_spi_process_events(dspi);
  546. if (errors)
  547. break;
  548. cpu_relax();
  549. }
  550. }
  551. clear_io_bits(dspi->base + SPIINT, SPIINT_MASKALL);
  552. if (spicfg->io_type == SPI_IO_TYPE_DMA) {
  553. clear_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN);
  554. dma_unmap_single(&spi->dev, t->rx_dma,
  555. t->len, DMA_FROM_DEVICE);
  556. dma_unmap_single(&spi->dev, t->tx_dma,
  557. t->len, DMA_TO_DEVICE);
  558. kfree(dummy_buf);
  559. }
  560. clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
  561. set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
  562. /*
  563. * Check for bit error, desync error,parity error,timeout error and
  564. * receive overflow errors
  565. */
  566. if (errors) {
  567. ret = davinci_spi_check_error(dspi, errors);
  568. WARN(!ret, "%s: error reported but no error found!\n",
  569. dev_name(&spi->dev));
  570. return ret;
  571. }
  572. if (dspi->rcount != 0 || dspi->wcount != 0) {
  573. dev_err(&spi->dev, "SPI data transfer error\n");
  574. return -EIO;
  575. }
  576. return t->len;
  577. err_desc:
  578. dma_unmap_single(&spi->dev, t->tx_dma, t->len, DMA_TO_DEVICE);
  579. err_tx_map:
  580. dma_unmap_single(&spi->dev, t->rx_dma, t->len, DMA_FROM_DEVICE);
  581. err_rx_map:
  582. kfree(dummy_buf);
  583. err_alloc_dummy_buf:
  584. return ret;
  585. }
  586. /**
  587. * davinci_spi_irq - Interrupt handler for SPI Master Controller
  588. * @irq: IRQ number for this SPI Master
  589. * @context_data: structure for SPI Master controller davinci_spi
  590. *
  591. * ISR will determine that interrupt arrives either for READ or WRITE command.
  592. * According to command it will do the appropriate action. It will check
  593. * transfer length and if it is not zero then dispatch transfer command again.
  594. * If transfer length is zero then it will indicate the COMPLETION so that
  595. * davinci_spi_bufs function can go ahead.
  596. */
  597. static irqreturn_t davinci_spi_irq(s32 irq, void *data)
  598. {
  599. struct davinci_spi *dspi = data;
  600. int status;
  601. status = davinci_spi_process_events(dspi);
  602. if (unlikely(status != 0))
  603. clear_io_bits(dspi->base + SPIINT, SPIINT_MASKINT);
  604. if ((!dspi->rcount && !dspi->wcount) || status)
  605. complete(&dspi->done);
  606. return IRQ_HANDLED;
  607. }
  608. static int davinci_spi_request_dma(struct davinci_spi *dspi)
  609. {
  610. dma_cap_mask_t mask;
  611. struct device *sdev = dspi->bitbang.master->dev.parent;
  612. int r;
  613. dma_cap_zero(mask);
  614. dma_cap_set(DMA_SLAVE, mask);
  615. dspi->dma_rx = dma_request_channel(mask, edma_filter_fn,
  616. &dspi->dma_rx_chnum);
  617. if (!dspi->dma_rx) {
  618. dev_err(sdev, "request RX DMA channel failed\n");
  619. r = -ENODEV;
  620. goto rx_dma_failed;
  621. }
  622. dspi->dma_tx = dma_request_channel(mask, edma_filter_fn,
  623. &dspi->dma_tx_chnum);
  624. if (!dspi->dma_tx) {
  625. dev_err(sdev, "request TX DMA channel failed\n");
  626. r = -ENODEV;
  627. goto tx_dma_failed;
  628. }
  629. return 0;
  630. tx_dma_failed:
  631. dma_release_channel(dspi->dma_rx);
  632. rx_dma_failed:
  633. return r;
  634. }
  635. #if defined(CONFIG_OF)
  636. static const struct of_device_id davinci_spi_of_match[] = {
  637. {
  638. .compatible = "ti,dm644x-spi",
  639. },
  640. {
  641. .compatible = "ti,da8xx-spi",
  642. .data = (void *)SPI_VERSION_2,
  643. },
  644. { },
  645. };
  646. MODULE_DEVICE_TABLE(of, davini_spi_of_match);
  647. /**
  648. * spi_davinci_get_pdata - Get platform data from DTS binding
  649. * @pdev: ptr to platform data
  650. * @dspi: ptr to driver data
  651. *
  652. * Parses and populates pdata in dspi from device tree bindings.
  653. *
  654. * NOTE: Not all platform data params are supported currently.
  655. */
  656. static int spi_davinci_get_pdata(struct platform_device *pdev,
  657. struct davinci_spi *dspi)
  658. {
  659. struct device_node *node = pdev->dev.of_node;
  660. struct davinci_spi_platform_data *pdata;
  661. unsigned int num_cs, intr_line = 0;
  662. const struct of_device_id *match;
  663. pdata = &dspi->pdata;
  664. pdata->version = SPI_VERSION_1;
  665. match = of_match_device(of_match_ptr(davinci_spi_of_match),
  666. &pdev->dev);
  667. if (!match)
  668. return -ENODEV;
  669. /* match data has the SPI version number for SPI_VERSION_2 */
  670. if (match->data == (void *)SPI_VERSION_2)
  671. pdata->version = SPI_VERSION_2;
  672. /*
  673. * default num_cs is 1 and all chipsel are internal to the chip
  674. * indicated by chip_sel being NULL. GPIO based CS is not
  675. * supported yet in DT bindings.
  676. */
  677. num_cs = 1;
  678. of_property_read_u32(node, "num-cs", &num_cs);
  679. pdata->num_chipselect = num_cs;
  680. of_property_read_u32(node, "ti,davinci-spi-intr-line", &intr_line);
  681. pdata->intr_line = intr_line;
  682. return 0;
  683. }
  684. #else
  685. #define davinci_spi_of_match NULL
  686. static struct davinci_spi_platform_data
  687. *spi_davinci_get_pdata(struct platform_device *pdev,
  688. struct davinci_spi *dspi)
  689. {
  690. return -ENODEV;
  691. }
  692. #endif
  693. /**
  694. * davinci_spi_probe - probe function for SPI Master Controller
  695. * @pdev: platform_device structure which contains plateform specific data
  696. *
  697. * According to Linux Device Model this function will be invoked by Linux
  698. * with platform_device struct which contains the device specific info.
  699. * This function will map the SPI controller's memory, register IRQ,
  700. * Reset SPI controller and setting its registers to default value.
  701. * It will invoke spi_bitbang_start to create work queue so that client driver
  702. * can register transfer method to work queue.
  703. */
  704. static int davinci_spi_probe(struct platform_device *pdev)
  705. {
  706. struct spi_master *master;
  707. struct davinci_spi *dspi;
  708. struct davinci_spi_platform_data *pdata;
  709. struct resource *r, *mem;
  710. resource_size_t dma_rx_chan = SPI_NO_RESOURCE;
  711. resource_size_t dma_tx_chan = SPI_NO_RESOURCE;
  712. int i = 0, ret = 0;
  713. u32 spipc0;
  714. master = spi_alloc_master(&pdev->dev, sizeof(struct davinci_spi));
  715. if (master == NULL) {
  716. ret = -ENOMEM;
  717. goto err;
  718. }
  719. dev_set_drvdata(&pdev->dev, master);
  720. dspi = spi_master_get_devdata(master);
  721. if (dspi == NULL) {
  722. ret = -ENOENT;
  723. goto free_master;
  724. }
  725. if (pdev->dev.platform_data) {
  726. pdata = pdev->dev.platform_data;
  727. dspi->pdata = *pdata;
  728. } else {
  729. /* update dspi pdata with that from the DT */
  730. ret = spi_davinci_get_pdata(pdev, dspi);
  731. if (ret < 0)
  732. goto free_master;
  733. }
  734. /* pdata in dspi is now updated and point pdata to that */
  735. pdata = &dspi->pdata;
  736. r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  737. if (r == NULL) {
  738. ret = -ENOENT;
  739. goto free_master;
  740. }
  741. dspi->pbase = r->start;
  742. mem = request_mem_region(r->start, resource_size(r), pdev->name);
  743. if (mem == NULL) {
  744. ret = -EBUSY;
  745. goto free_master;
  746. }
  747. dspi->base = ioremap(r->start, resource_size(r));
  748. if (dspi->base == NULL) {
  749. ret = -ENOMEM;
  750. goto release_region;
  751. }
  752. dspi->irq = platform_get_irq(pdev, 0);
  753. if (dspi->irq <= 0) {
  754. ret = -EINVAL;
  755. goto unmap_io;
  756. }
  757. ret = request_irq(dspi->irq, davinci_spi_irq, 0, dev_name(&pdev->dev),
  758. dspi);
  759. if (ret)
  760. goto unmap_io;
  761. dspi->bitbang.master = spi_master_get(master);
  762. if (dspi->bitbang.master == NULL) {
  763. ret = -ENODEV;
  764. goto irq_free;
  765. }
  766. dspi->clk = clk_get(&pdev->dev, NULL);
  767. if (IS_ERR(dspi->clk)) {
  768. ret = -ENODEV;
  769. goto put_master;
  770. }
  771. clk_prepare_enable(dspi->clk);
  772. master->dev.of_node = pdev->dev.of_node;
  773. master->bus_num = pdev->id;
  774. master->num_chipselect = pdata->num_chipselect;
  775. master->setup = davinci_spi_setup;
  776. dspi->bitbang.chipselect = davinci_spi_chipselect;
  777. dspi->bitbang.setup_transfer = davinci_spi_setup_transfer;
  778. dspi->version = pdata->version;
  779. dspi->bitbang.flags = SPI_NO_CS | SPI_LSB_FIRST | SPI_LOOP;
  780. if (dspi->version == SPI_VERSION_2)
  781. dspi->bitbang.flags |= SPI_READY;
  782. r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
  783. if (r)
  784. dma_rx_chan = r->start;
  785. r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
  786. if (r)
  787. dma_tx_chan = r->start;
  788. dspi->bitbang.txrx_bufs = davinci_spi_bufs;
  789. if (dma_rx_chan != SPI_NO_RESOURCE &&
  790. dma_tx_chan != SPI_NO_RESOURCE) {
  791. dspi->dma_rx_chnum = dma_rx_chan;
  792. dspi->dma_tx_chnum = dma_tx_chan;
  793. ret = davinci_spi_request_dma(dspi);
  794. if (ret)
  795. goto free_clk;
  796. dev_info(&pdev->dev, "DMA: supported\n");
  797. dev_info(&pdev->dev, "DMA: RX channel: %d, TX channel: %d, "
  798. "event queue: %d\n", dma_rx_chan, dma_tx_chan,
  799. pdata->dma_event_q);
  800. }
  801. dspi->get_rx = davinci_spi_rx_buf_u8;
  802. dspi->get_tx = davinci_spi_tx_buf_u8;
  803. init_completion(&dspi->done);
  804. /* Reset In/OUT SPI module */
  805. iowrite32(0, dspi->base + SPIGCR0);
  806. udelay(100);
  807. iowrite32(1, dspi->base + SPIGCR0);
  808. /* Set up SPIPC0. CS and ENA init is done in davinci_spi_setup */
  809. spipc0 = SPIPC0_DIFUN_MASK | SPIPC0_DOFUN_MASK | SPIPC0_CLKFUN_MASK;
  810. iowrite32(spipc0, dspi->base + SPIPC0);
  811. /* initialize chip selects */
  812. if (pdata->chip_sel) {
  813. for (i = 0; i < pdata->num_chipselect; i++) {
  814. if (pdata->chip_sel[i] != SPI_INTERN_CS)
  815. gpio_direction_output(pdata->chip_sel[i], 1);
  816. }
  817. }
  818. if (pdata->intr_line)
  819. iowrite32(SPI_INTLVL_1, dspi->base + SPILVL);
  820. else
  821. iowrite32(SPI_INTLVL_0, dspi->base + SPILVL);
  822. iowrite32(CS_DEFAULT, dspi->base + SPIDEF);
  823. /* master mode default */
  824. set_io_bits(dspi->base + SPIGCR1, SPIGCR1_CLKMOD_MASK);
  825. set_io_bits(dspi->base + SPIGCR1, SPIGCR1_MASTER_MASK);
  826. set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
  827. ret = spi_bitbang_start(&dspi->bitbang);
  828. if (ret)
  829. goto free_dma;
  830. dev_info(&pdev->dev, "Controller at 0x%p\n", dspi->base);
  831. return ret;
  832. free_dma:
  833. dma_release_channel(dspi->dma_rx);
  834. dma_release_channel(dspi->dma_tx);
  835. free_clk:
  836. clk_disable_unprepare(dspi->clk);
  837. clk_put(dspi->clk);
  838. put_master:
  839. spi_master_put(master);
  840. irq_free:
  841. free_irq(dspi->irq, dspi);
  842. unmap_io:
  843. iounmap(dspi->base);
  844. release_region:
  845. release_mem_region(dspi->pbase, resource_size(r));
  846. free_master:
  847. kfree(master);
  848. err:
  849. return ret;
  850. }
  851. /**
  852. * davinci_spi_remove - remove function for SPI Master Controller
  853. * @pdev: platform_device structure which contains plateform specific data
  854. *
  855. * This function will do the reverse action of davinci_spi_probe function
  856. * It will free the IRQ and SPI controller's memory region.
  857. * It will also call spi_bitbang_stop to destroy the work queue which was
  858. * created by spi_bitbang_start.
  859. */
  860. static int davinci_spi_remove(struct platform_device *pdev)
  861. {
  862. struct davinci_spi *dspi;
  863. struct spi_master *master;
  864. struct resource *r;
  865. master = dev_get_drvdata(&pdev->dev);
  866. dspi = spi_master_get_devdata(master);
  867. spi_bitbang_stop(&dspi->bitbang);
  868. clk_disable_unprepare(dspi->clk);
  869. clk_put(dspi->clk);
  870. spi_master_put(master);
  871. free_irq(dspi->irq, dspi);
  872. iounmap(dspi->base);
  873. r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  874. release_mem_region(dspi->pbase, resource_size(r));
  875. return 0;
  876. }
  877. static struct platform_driver davinci_spi_driver = {
  878. .driver = {
  879. .name = "spi_davinci",
  880. .owner = THIS_MODULE,
  881. .of_match_table = davinci_spi_of_match,
  882. },
  883. .probe = davinci_spi_probe,
  884. .remove = davinci_spi_remove,
  885. };
  886. module_platform_driver(davinci_spi_driver);
  887. MODULE_DESCRIPTION("TI DaVinci SPI Master Controller Driver");
  888. MODULE_LICENSE("GPL");