bnad.c 79 KB

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  1. /*
  2. * Linux network driver for Brocade Converged Network Adapter.
  3. *
  4. * This program is free software; you can redistribute it and/or modify it
  5. * under the terms of the GNU General Public License (GPL) Version 2 as
  6. * published by the Free Software Foundation
  7. *
  8. * This program is distributed in the hope that it will be useful, but
  9. * WITHOUT ANY WARRANTY; without even the implied warranty of
  10. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  11. * General Public License for more details.
  12. */
  13. /*
  14. * Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
  15. * All rights reserved
  16. * www.brocade.com
  17. */
  18. #include <linux/netdevice.h>
  19. #include <linux/skbuff.h>
  20. #include <linux/etherdevice.h>
  21. #include <linux/in.h>
  22. #include <linux/ethtool.h>
  23. #include <linux/if_vlan.h>
  24. #include <linux/if_ether.h>
  25. #include <linux/ip.h>
  26. #include "bnad.h"
  27. #include "bna.h"
  28. #include "cna.h"
  29. static DEFINE_MUTEX(bnad_fwimg_mutex);
  30. /*
  31. * Module params
  32. */
  33. static uint bnad_msix_disable;
  34. module_param(bnad_msix_disable, uint, 0444);
  35. MODULE_PARM_DESC(bnad_msix_disable, "Disable MSIX mode");
  36. static uint bnad_ioc_auto_recover = 1;
  37. module_param(bnad_ioc_auto_recover, uint, 0444);
  38. MODULE_PARM_DESC(bnad_ioc_auto_recover, "Enable / Disable auto recovery");
  39. /*
  40. * Global variables
  41. */
  42. u32 bnad_rxqs_per_cq = 2;
  43. static const u8 bnad_bcast_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
  44. /*
  45. * Local MACROS
  46. */
  47. #define BNAD_TX_UNMAPQ_DEPTH (bnad->txq_depth * 2)
  48. #define BNAD_RX_UNMAPQ_DEPTH (bnad->rxq_depth)
  49. #define BNAD_GET_MBOX_IRQ(_bnad) \
  50. (((_bnad)->cfg_flags & BNAD_CF_MSIX) ? \
  51. ((_bnad)->msix_table[(_bnad)->msix_num - 1].vector) : \
  52. ((_bnad)->pcidev->irq))
  53. #define BNAD_FILL_UNMAPQ_MEM_REQ(_res_info, _num, _depth) \
  54. do { \
  55. (_res_info)->res_type = BNA_RES_T_MEM; \
  56. (_res_info)->res_u.mem_info.mem_type = BNA_MEM_T_KVA; \
  57. (_res_info)->res_u.mem_info.num = (_num); \
  58. (_res_info)->res_u.mem_info.len = \
  59. sizeof(struct bnad_unmap_q) + \
  60. (sizeof(struct bnad_skb_unmap) * ((_depth) - 1)); \
  61. } while (0)
  62. #define BNAD_TXRX_SYNC_MDELAY 250 /* 250 msecs */
  63. /*
  64. * Reinitialize completions in CQ, once Rx is taken down
  65. */
  66. static void
  67. bnad_cq_cmpl_init(struct bnad *bnad, struct bna_ccb *ccb)
  68. {
  69. struct bna_cq_entry *cmpl, *next_cmpl;
  70. unsigned int wi_range, wis = 0, ccb_prod = 0;
  71. int i;
  72. BNA_CQ_QPGE_PTR_GET(ccb_prod, ccb->sw_qpt, cmpl,
  73. wi_range);
  74. for (i = 0; i < ccb->q_depth; i++) {
  75. wis++;
  76. if (likely(--wi_range))
  77. next_cmpl = cmpl + 1;
  78. else {
  79. BNA_QE_INDX_ADD(ccb_prod, wis, ccb->q_depth);
  80. wis = 0;
  81. BNA_CQ_QPGE_PTR_GET(ccb_prod, ccb->sw_qpt,
  82. next_cmpl, wi_range);
  83. }
  84. cmpl->valid = 0;
  85. cmpl = next_cmpl;
  86. }
  87. }
  88. /*
  89. * Frees all pending Tx Bufs
  90. * At this point no activity is expected on the Q,
  91. * so DMA unmap & freeing is fine.
  92. */
  93. static void
  94. bnad_free_all_txbufs(struct bnad *bnad,
  95. struct bna_tcb *tcb)
  96. {
  97. u32 unmap_cons;
  98. struct bnad_unmap_q *unmap_q = tcb->unmap_q;
  99. struct bnad_skb_unmap *unmap_array;
  100. struct sk_buff *skb = NULL;
  101. int i;
  102. unmap_array = unmap_q->unmap_array;
  103. unmap_cons = 0;
  104. while (unmap_cons < unmap_q->q_depth) {
  105. skb = unmap_array[unmap_cons].skb;
  106. if (!skb) {
  107. unmap_cons++;
  108. continue;
  109. }
  110. unmap_array[unmap_cons].skb = NULL;
  111. pci_unmap_single(bnad->pcidev,
  112. pci_unmap_addr(&unmap_array[unmap_cons],
  113. dma_addr), skb_headlen(skb),
  114. PCI_DMA_TODEVICE);
  115. pci_unmap_addr_set(&unmap_array[unmap_cons], dma_addr, 0);
  116. if (++unmap_cons >= unmap_q->q_depth)
  117. break;
  118. for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
  119. pci_unmap_page(bnad->pcidev,
  120. pci_unmap_addr(&unmap_array[unmap_cons],
  121. dma_addr),
  122. skb_shinfo(skb)->frags[i].size,
  123. PCI_DMA_TODEVICE);
  124. pci_unmap_addr_set(&unmap_array[unmap_cons], dma_addr,
  125. 0);
  126. if (++unmap_cons >= unmap_q->q_depth)
  127. break;
  128. }
  129. dev_kfree_skb_any(skb);
  130. }
  131. }
  132. /* Data Path Handlers */
  133. /*
  134. * bnad_free_txbufs : Frees the Tx bufs on Tx completion
  135. * Can be called in a) Interrupt context
  136. * b) Sending context
  137. * c) Tasklet context
  138. */
  139. static u32
  140. bnad_free_txbufs(struct bnad *bnad,
  141. struct bna_tcb *tcb)
  142. {
  143. u32 sent_packets = 0, sent_bytes = 0;
  144. u16 wis, unmap_cons, updated_hw_cons;
  145. struct bnad_unmap_q *unmap_q = tcb->unmap_q;
  146. struct bnad_skb_unmap *unmap_array;
  147. struct sk_buff *skb;
  148. int i;
  149. /*
  150. * Just return if TX is stopped. This check is useful
  151. * when bnad_free_txbufs() runs out of a tasklet scheduled
  152. * before bnad_cb_tx_cleanup() cleared BNAD_TXQ_TX_STARTED bit
  153. * but this routine runs actually after the cleanup has been
  154. * executed.
  155. */
  156. if (!test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags))
  157. return 0;
  158. updated_hw_cons = *(tcb->hw_consumer_index);
  159. wis = BNA_Q_INDEX_CHANGE(tcb->consumer_index,
  160. updated_hw_cons, tcb->q_depth);
  161. BUG_ON(!(wis <= BNA_QE_IN_USE_CNT(tcb, tcb->q_depth)));
  162. unmap_array = unmap_q->unmap_array;
  163. unmap_cons = unmap_q->consumer_index;
  164. prefetch(&unmap_array[unmap_cons + 1]);
  165. while (wis) {
  166. skb = unmap_array[unmap_cons].skb;
  167. unmap_array[unmap_cons].skb = NULL;
  168. sent_packets++;
  169. sent_bytes += skb->len;
  170. wis -= BNA_TXQ_WI_NEEDED(1 + skb_shinfo(skb)->nr_frags);
  171. pci_unmap_single(bnad->pcidev,
  172. pci_unmap_addr(&unmap_array[unmap_cons],
  173. dma_addr), skb_headlen(skb),
  174. PCI_DMA_TODEVICE);
  175. pci_unmap_addr_set(&unmap_array[unmap_cons], dma_addr, 0);
  176. BNA_QE_INDX_ADD(unmap_cons, 1, unmap_q->q_depth);
  177. prefetch(&unmap_array[unmap_cons + 1]);
  178. for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
  179. prefetch(&unmap_array[unmap_cons + 1]);
  180. pci_unmap_page(bnad->pcidev,
  181. pci_unmap_addr(&unmap_array[unmap_cons],
  182. dma_addr),
  183. skb_shinfo(skb)->frags[i].size,
  184. PCI_DMA_TODEVICE);
  185. pci_unmap_addr_set(&unmap_array[unmap_cons], dma_addr,
  186. 0);
  187. BNA_QE_INDX_ADD(unmap_cons, 1, unmap_q->q_depth);
  188. }
  189. dev_kfree_skb_any(skb);
  190. }
  191. /* Update consumer pointers. */
  192. tcb->consumer_index = updated_hw_cons;
  193. unmap_q->consumer_index = unmap_cons;
  194. tcb->txq->tx_packets += sent_packets;
  195. tcb->txq->tx_bytes += sent_bytes;
  196. return sent_packets;
  197. }
  198. /* Tx Free Tasklet function */
  199. /* Frees for all the tcb's in all the Tx's */
  200. /*
  201. * Scheduled from sending context, so that
  202. * the fat Tx lock is not held for too long
  203. * in the sending context.
  204. */
  205. static void
  206. bnad_tx_free_tasklet(unsigned long bnad_ptr)
  207. {
  208. struct bnad *bnad = (struct bnad *)bnad_ptr;
  209. struct bna_tcb *tcb;
  210. u32 acked = 0;
  211. int i, j;
  212. for (i = 0; i < bnad->num_tx; i++) {
  213. for (j = 0; j < bnad->num_txq_per_tx; j++) {
  214. tcb = bnad->tx_info[i].tcb[j];
  215. if (!tcb)
  216. continue;
  217. if (((u16) (*tcb->hw_consumer_index) !=
  218. tcb->consumer_index) &&
  219. (!test_and_set_bit(BNAD_TXQ_FREE_SENT,
  220. &tcb->flags))) {
  221. acked = bnad_free_txbufs(bnad, tcb);
  222. if (likely(test_bit(BNAD_TXQ_TX_STARTED,
  223. &tcb->flags)))
  224. bna_ib_ack(tcb->i_dbell, acked);
  225. smp_mb__before_clear_bit();
  226. clear_bit(BNAD_TXQ_FREE_SENT, &tcb->flags);
  227. }
  228. if (unlikely(!test_bit(BNAD_TXQ_TX_STARTED,
  229. &tcb->flags)))
  230. continue;
  231. if (netif_queue_stopped(bnad->netdev)) {
  232. if (acked && netif_carrier_ok(bnad->netdev) &&
  233. BNA_QE_FREE_CNT(tcb, tcb->q_depth) >=
  234. BNAD_NETIF_WAKE_THRESHOLD) {
  235. netif_wake_queue(bnad->netdev);
  236. /* TODO */
  237. /* Counters for individual TxQs? */
  238. BNAD_UPDATE_CTR(bnad,
  239. netif_queue_wakeup);
  240. }
  241. }
  242. }
  243. }
  244. }
  245. static u32
  246. bnad_tx(struct bnad *bnad, struct bna_tcb *tcb)
  247. {
  248. struct net_device *netdev = bnad->netdev;
  249. u32 sent = 0;
  250. if (test_and_set_bit(BNAD_TXQ_FREE_SENT, &tcb->flags))
  251. return 0;
  252. sent = bnad_free_txbufs(bnad, tcb);
  253. if (sent) {
  254. if (netif_queue_stopped(netdev) &&
  255. netif_carrier_ok(netdev) &&
  256. BNA_QE_FREE_CNT(tcb, tcb->q_depth) >=
  257. BNAD_NETIF_WAKE_THRESHOLD) {
  258. if (test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags)) {
  259. netif_wake_queue(netdev);
  260. BNAD_UPDATE_CTR(bnad, netif_queue_wakeup);
  261. }
  262. }
  263. }
  264. if (likely(test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags)))
  265. bna_ib_ack(tcb->i_dbell, sent);
  266. smp_mb__before_clear_bit();
  267. clear_bit(BNAD_TXQ_FREE_SENT, &tcb->flags);
  268. return sent;
  269. }
  270. /* MSIX Tx Completion Handler */
  271. static irqreturn_t
  272. bnad_msix_tx(int irq, void *data)
  273. {
  274. struct bna_tcb *tcb = (struct bna_tcb *)data;
  275. struct bnad *bnad = tcb->bnad;
  276. bnad_tx(bnad, tcb);
  277. return IRQ_HANDLED;
  278. }
  279. static void
  280. bnad_reset_rcb(struct bnad *bnad, struct bna_rcb *rcb)
  281. {
  282. struct bnad_unmap_q *unmap_q = rcb->unmap_q;
  283. rcb->producer_index = 0;
  284. rcb->consumer_index = 0;
  285. unmap_q->producer_index = 0;
  286. unmap_q->consumer_index = 0;
  287. }
  288. static void
  289. bnad_free_all_rxbufs(struct bnad *bnad, struct bna_rcb *rcb)
  290. {
  291. struct bnad_unmap_q *unmap_q;
  292. struct sk_buff *skb;
  293. int unmap_cons;
  294. unmap_q = rcb->unmap_q;
  295. for (unmap_cons = 0; unmap_cons < unmap_q->q_depth; unmap_cons++) {
  296. skb = unmap_q->unmap_array[unmap_cons].skb;
  297. if (!skb)
  298. continue;
  299. unmap_q->unmap_array[unmap_cons].skb = NULL;
  300. pci_unmap_single(bnad->pcidev, pci_unmap_addr(&unmap_q->
  301. unmap_array[unmap_cons],
  302. dma_addr), rcb->rxq->buffer_size,
  303. PCI_DMA_FROMDEVICE);
  304. dev_kfree_skb(skb);
  305. }
  306. bnad_reset_rcb(bnad, rcb);
  307. }
  308. static void
  309. bnad_alloc_n_post_rxbufs(struct bnad *bnad, struct bna_rcb *rcb)
  310. {
  311. u16 to_alloc, alloced, unmap_prod, wi_range;
  312. struct bnad_unmap_q *unmap_q = rcb->unmap_q;
  313. struct bnad_skb_unmap *unmap_array;
  314. struct bna_rxq_entry *rxent;
  315. struct sk_buff *skb;
  316. dma_addr_t dma_addr;
  317. alloced = 0;
  318. to_alloc =
  319. BNA_QE_FREE_CNT(unmap_q, unmap_q->q_depth);
  320. unmap_array = unmap_q->unmap_array;
  321. unmap_prod = unmap_q->producer_index;
  322. BNA_RXQ_QPGE_PTR_GET(unmap_prod, rcb->sw_qpt, rxent, wi_range);
  323. while (to_alloc--) {
  324. if (!wi_range) {
  325. BNA_RXQ_QPGE_PTR_GET(unmap_prod, rcb->sw_qpt, rxent,
  326. wi_range);
  327. }
  328. skb = alloc_skb(rcb->rxq->buffer_size + NET_IP_ALIGN,
  329. GFP_ATOMIC);
  330. if (unlikely(!skb)) {
  331. BNAD_UPDATE_CTR(bnad, rxbuf_alloc_failed);
  332. goto finishing;
  333. }
  334. skb->dev = bnad->netdev;
  335. skb_reserve(skb, NET_IP_ALIGN);
  336. unmap_array[unmap_prod].skb = skb;
  337. dma_addr = pci_map_single(bnad->pcidev, skb->data,
  338. rcb->rxq->buffer_size, PCI_DMA_FROMDEVICE);
  339. pci_unmap_addr_set(&unmap_array[unmap_prod], dma_addr,
  340. dma_addr);
  341. BNA_SET_DMA_ADDR(dma_addr, &rxent->host_addr);
  342. BNA_QE_INDX_ADD(unmap_prod, 1, unmap_q->q_depth);
  343. rxent++;
  344. wi_range--;
  345. alloced++;
  346. }
  347. finishing:
  348. if (likely(alloced)) {
  349. unmap_q->producer_index = unmap_prod;
  350. rcb->producer_index = unmap_prod;
  351. smp_mb();
  352. if (likely(test_bit(BNAD_RXQ_STARTED, &rcb->flags)))
  353. bna_rxq_prod_indx_doorbell(rcb);
  354. }
  355. }
  356. static inline void
  357. bnad_refill_rxq(struct bnad *bnad, struct bna_rcb *rcb)
  358. {
  359. struct bnad_unmap_q *unmap_q = rcb->unmap_q;
  360. if (!test_and_set_bit(BNAD_RXQ_REFILL, &rcb->flags)) {
  361. if (BNA_QE_FREE_CNT(unmap_q, unmap_q->q_depth)
  362. >> BNAD_RXQ_REFILL_THRESHOLD_SHIFT)
  363. bnad_alloc_n_post_rxbufs(bnad, rcb);
  364. smp_mb__before_clear_bit();
  365. clear_bit(BNAD_RXQ_REFILL, &rcb->flags);
  366. }
  367. }
  368. static u32
  369. bnad_poll_cq(struct bnad *bnad, struct bna_ccb *ccb, int budget)
  370. {
  371. struct bna_cq_entry *cmpl, *next_cmpl;
  372. struct bna_rcb *rcb = NULL;
  373. unsigned int wi_range, packets = 0, wis = 0;
  374. struct bnad_unmap_q *unmap_q;
  375. struct sk_buff *skb;
  376. u32 flags;
  377. u32 qid0 = ccb->rcb[0]->rxq->rxq_id;
  378. struct bna_pkt_rate *pkt_rt = &ccb->pkt_rate;
  379. if (!test_bit(BNAD_RXQ_STARTED, &ccb->rcb[0]->flags))
  380. return 0;
  381. prefetch(bnad->netdev);
  382. BNA_CQ_QPGE_PTR_GET(ccb->producer_index, ccb->sw_qpt, cmpl,
  383. wi_range);
  384. BUG_ON(!(wi_range <= ccb->q_depth));
  385. while (cmpl->valid && packets < budget) {
  386. packets++;
  387. BNA_UPDATE_PKT_CNT(pkt_rt, ntohs(cmpl->length));
  388. if (qid0 == cmpl->rxq_id)
  389. rcb = ccb->rcb[0];
  390. else
  391. rcb = ccb->rcb[1];
  392. unmap_q = rcb->unmap_q;
  393. skb = unmap_q->unmap_array[unmap_q->consumer_index].skb;
  394. BUG_ON(!(skb));
  395. unmap_q->unmap_array[unmap_q->consumer_index].skb = NULL;
  396. pci_unmap_single(bnad->pcidev,
  397. pci_unmap_addr(&unmap_q->
  398. unmap_array[unmap_q->
  399. consumer_index],
  400. dma_addr),
  401. rcb->rxq->buffer_size,
  402. PCI_DMA_FROMDEVICE);
  403. BNA_QE_INDX_ADD(unmap_q->consumer_index, 1, unmap_q->q_depth);
  404. /* Should be more efficient ? Performance ? */
  405. BNA_QE_INDX_ADD(rcb->consumer_index, 1, rcb->q_depth);
  406. wis++;
  407. if (likely(--wi_range))
  408. next_cmpl = cmpl + 1;
  409. else {
  410. BNA_QE_INDX_ADD(ccb->producer_index, wis, ccb->q_depth);
  411. wis = 0;
  412. BNA_CQ_QPGE_PTR_GET(ccb->producer_index, ccb->sw_qpt,
  413. next_cmpl, wi_range);
  414. BUG_ON(!(wi_range <= ccb->q_depth));
  415. }
  416. prefetch(next_cmpl);
  417. flags = ntohl(cmpl->flags);
  418. if (unlikely
  419. (flags &
  420. (BNA_CQ_EF_MAC_ERROR | BNA_CQ_EF_FCS_ERROR |
  421. BNA_CQ_EF_TOO_LONG))) {
  422. dev_kfree_skb_any(skb);
  423. rcb->rxq->rx_packets_with_error++;
  424. goto next;
  425. }
  426. skb_put(skb, ntohs(cmpl->length));
  427. if (likely
  428. (bnad->rx_csum &&
  429. (((flags & BNA_CQ_EF_IPV4) &&
  430. (flags & BNA_CQ_EF_L3_CKSUM_OK)) ||
  431. (flags & BNA_CQ_EF_IPV6)) &&
  432. (flags & (BNA_CQ_EF_TCP | BNA_CQ_EF_UDP)) &&
  433. (flags & BNA_CQ_EF_L4_CKSUM_OK)))
  434. skb->ip_summed = CHECKSUM_UNNECESSARY;
  435. else
  436. skb_checksum_none_assert(skb);
  437. rcb->rxq->rx_packets++;
  438. rcb->rxq->rx_bytes += skb->len;
  439. skb->protocol = eth_type_trans(skb, bnad->netdev);
  440. if (bnad->vlan_grp && (flags & BNA_CQ_EF_VLAN)) {
  441. struct bnad_rx_ctrl *rx_ctrl =
  442. (struct bnad_rx_ctrl *)ccb->ctrl;
  443. if (skb->ip_summed == CHECKSUM_UNNECESSARY)
  444. vlan_gro_receive(&rx_ctrl->napi, bnad->vlan_grp,
  445. ntohs(cmpl->vlan_tag), skb);
  446. else
  447. vlan_hwaccel_receive_skb(skb,
  448. bnad->vlan_grp,
  449. ntohs(cmpl->vlan_tag));
  450. } else { /* Not VLAN tagged/stripped */
  451. struct bnad_rx_ctrl *rx_ctrl =
  452. (struct bnad_rx_ctrl *)ccb->ctrl;
  453. if (skb->ip_summed == CHECKSUM_UNNECESSARY)
  454. napi_gro_receive(&rx_ctrl->napi, skb);
  455. else
  456. netif_receive_skb(skb);
  457. }
  458. next:
  459. cmpl->valid = 0;
  460. cmpl = next_cmpl;
  461. }
  462. BNA_QE_INDX_ADD(ccb->producer_index, wis, ccb->q_depth);
  463. if (likely(ccb)) {
  464. if (likely(test_bit(BNAD_RXQ_STARTED, &ccb->rcb[0]->flags)))
  465. bna_ib_ack(ccb->i_dbell, packets);
  466. bnad_refill_rxq(bnad, ccb->rcb[0]);
  467. if (ccb->rcb[1])
  468. bnad_refill_rxq(bnad, ccb->rcb[1]);
  469. } else {
  470. if (likely(test_bit(BNAD_RXQ_STARTED, &ccb->rcb[0]->flags)))
  471. bna_ib_ack(ccb->i_dbell, 0);
  472. }
  473. return packets;
  474. }
  475. static void
  476. bnad_disable_rx_irq(struct bnad *bnad, struct bna_ccb *ccb)
  477. {
  478. if (unlikely(!test_bit(BNAD_RXQ_STARTED, &ccb->rcb[0]->flags)))
  479. return;
  480. bna_ib_coalescing_timer_set(ccb->i_dbell, 0);
  481. bna_ib_ack(ccb->i_dbell, 0);
  482. }
  483. static void
  484. bnad_enable_rx_irq(struct bnad *bnad, struct bna_ccb *ccb)
  485. {
  486. unsigned long flags;
  487. /* Because of polling context */
  488. spin_lock_irqsave(&bnad->bna_lock, flags);
  489. bnad_enable_rx_irq_unsafe(ccb);
  490. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  491. }
  492. static void
  493. bnad_netif_rx_schedule_poll(struct bnad *bnad, struct bna_ccb *ccb)
  494. {
  495. struct bnad_rx_ctrl *rx_ctrl = (struct bnad_rx_ctrl *)(ccb->ctrl);
  496. struct napi_struct *napi = &rx_ctrl->napi;
  497. if (likely(napi_schedule_prep(napi))) {
  498. bnad_disable_rx_irq(bnad, ccb);
  499. __napi_schedule(napi);
  500. }
  501. BNAD_UPDATE_CTR(bnad, netif_rx_schedule);
  502. }
  503. /* MSIX Rx Path Handler */
  504. static irqreturn_t
  505. bnad_msix_rx(int irq, void *data)
  506. {
  507. struct bna_ccb *ccb = (struct bna_ccb *)data;
  508. struct bnad *bnad = ccb->bnad;
  509. bnad_netif_rx_schedule_poll(bnad, ccb);
  510. return IRQ_HANDLED;
  511. }
  512. /* Interrupt handlers */
  513. /* Mbox Interrupt Handlers */
  514. static irqreturn_t
  515. bnad_msix_mbox_handler(int irq, void *data)
  516. {
  517. u32 intr_status;
  518. unsigned long flags;
  519. struct bnad *bnad = (struct bnad *)data;
  520. if (unlikely(test_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags)))
  521. return IRQ_HANDLED;
  522. spin_lock_irqsave(&bnad->bna_lock, flags);
  523. bna_intr_status_get(&bnad->bna, intr_status);
  524. if (BNA_IS_MBOX_ERR_INTR(intr_status))
  525. bna_mbox_handler(&bnad->bna, intr_status);
  526. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  527. return IRQ_HANDLED;
  528. }
  529. static irqreturn_t
  530. bnad_isr(int irq, void *data)
  531. {
  532. int i, j;
  533. u32 intr_status;
  534. unsigned long flags;
  535. struct bnad *bnad = (struct bnad *)data;
  536. struct bnad_rx_info *rx_info;
  537. struct bnad_rx_ctrl *rx_ctrl;
  538. if (unlikely(test_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags)))
  539. return IRQ_NONE;
  540. bna_intr_status_get(&bnad->bna, intr_status);
  541. if (unlikely(!intr_status))
  542. return IRQ_NONE;
  543. spin_lock_irqsave(&bnad->bna_lock, flags);
  544. if (BNA_IS_MBOX_ERR_INTR(intr_status))
  545. bna_mbox_handler(&bnad->bna, intr_status);
  546. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  547. if (!BNA_IS_INTX_DATA_INTR(intr_status))
  548. return IRQ_HANDLED;
  549. /* Process data interrupts */
  550. /* Tx processing */
  551. for (i = 0; i < bnad->num_tx; i++) {
  552. for (j = 0; j < bnad->num_txq_per_tx; j++)
  553. bnad_tx(bnad, bnad->tx_info[i].tcb[j]);
  554. }
  555. /* Rx processing */
  556. for (i = 0; i < bnad->num_rx; i++) {
  557. rx_info = &bnad->rx_info[i];
  558. if (!rx_info->rx)
  559. continue;
  560. for (j = 0; j < bnad->num_rxp_per_rx; j++) {
  561. rx_ctrl = &rx_info->rx_ctrl[j];
  562. if (rx_ctrl->ccb)
  563. bnad_netif_rx_schedule_poll(bnad,
  564. rx_ctrl->ccb);
  565. }
  566. }
  567. return IRQ_HANDLED;
  568. }
  569. /*
  570. * Called in interrupt / callback context
  571. * with bna_lock held, so cfg_flags access is OK
  572. */
  573. static void
  574. bnad_enable_mbox_irq(struct bnad *bnad)
  575. {
  576. clear_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags);
  577. BNAD_UPDATE_CTR(bnad, mbox_intr_enabled);
  578. }
  579. /*
  580. * Called with bnad->bna_lock held b'cos of
  581. * bnad->cfg_flags access.
  582. */
  583. static void
  584. bnad_disable_mbox_irq(struct bnad *bnad)
  585. {
  586. set_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags);
  587. BNAD_UPDATE_CTR(bnad, mbox_intr_disabled);
  588. }
  589. static void
  590. bnad_set_netdev_perm_addr(struct bnad *bnad)
  591. {
  592. struct net_device *netdev = bnad->netdev;
  593. memcpy(netdev->perm_addr, &bnad->perm_addr, netdev->addr_len);
  594. if (is_zero_ether_addr(netdev->dev_addr))
  595. memcpy(netdev->dev_addr, &bnad->perm_addr, netdev->addr_len);
  596. }
  597. /* Control Path Handlers */
  598. /* Callbacks */
  599. void
  600. bnad_cb_device_enable_mbox_intr(struct bnad *bnad)
  601. {
  602. bnad_enable_mbox_irq(bnad);
  603. }
  604. void
  605. bnad_cb_device_disable_mbox_intr(struct bnad *bnad)
  606. {
  607. bnad_disable_mbox_irq(bnad);
  608. }
  609. void
  610. bnad_cb_device_enabled(struct bnad *bnad, enum bna_cb_status status)
  611. {
  612. complete(&bnad->bnad_completions.ioc_comp);
  613. bnad->bnad_completions.ioc_comp_status = status;
  614. }
  615. void
  616. bnad_cb_device_disabled(struct bnad *bnad, enum bna_cb_status status)
  617. {
  618. complete(&bnad->bnad_completions.ioc_comp);
  619. bnad->bnad_completions.ioc_comp_status = status;
  620. }
  621. static void
  622. bnad_cb_port_disabled(void *arg, enum bna_cb_status status)
  623. {
  624. struct bnad *bnad = (struct bnad *)arg;
  625. complete(&bnad->bnad_completions.port_comp);
  626. netif_carrier_off(bnad->netdev);
  627. }
  628. void
  629. bnad_cb_port_link_status(struct bnad *bnad,
  630. enum bna_link_status link_status)
  631. {
  632. bool link_up = 0;
  633. link_up = (link_status == BNA_LINK_UP) || (link_status == BNA_CEE_UP);
  634. if (link_status == BNA_CEE_UP) {
  635. set_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags);
  636. BNAD_UPDATE_CTR(bnad, cee_up);
  637. } else
  638. clear_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags);
  639. if (link_up) {
  640. if (!netif_carrier_ok(bnad->netdev)) {
  641. struct bna_tcb *tcb = bnad->tx_info[0].tcb[0];
  642. if (!tcb)
  643. return;
  644. pr_warn("bna: %s link up\n",
  645. bnad->netdev->name);
  646. netif_carrier_on(bnad->netdev);
  647. BNAD_UPDATE_CTR(bnad, link_toggle);
  648. if (test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags)) {
  649. /* Force an immediate Transmit Schedule */
  650. pr_info("bna: %s TX_STARTED\n",
  651. bnad->netdev->name);
  652. netif_wake_queue(bnad->netdev);
  653. BNAD_UPDATE_CTR(bnad, netif_queue_wakeup);
  654. } else {
  655. netif_stop_queue(bnad->netdev);
  656. BNAD_UPDATE_CTR(bnad, netif_queue_stop);
  657. }
  658. }
  659. } else {
  660. if (netif_carrier_ok(bnad->netdev)) {
  661. pr_warn("bna: %s link down\n",
  662. bnad->netdev->name);
  663. netif_carrier_off(bnad->netdev);
  664. BNAD_UPDATE_CTR(bnad, link_toggle);
  665. }
  666. }
  667. }
  668. static void
  669. bnad_cb_tx_disabled(void *arg, struct bna_tx *tx,
  670. enum bna_cb_status status)
  671. {
  672. struct bnad *bnad = (struct bnad *)arg;
  673. complete(&bnad->bnad_completions.tx_comp);
  674. }
  675. static void
  676. bnad_cb_tcb_setup(struct bnad *bnad, struct bna_tcb *tcb)
  677. {
  678. struct bnad_tx_info *tx_info =
  679. (struct bnad_tx_info *)tcb->txq->tx->priv;
  680. struct bnad_unmap_q *unmap_q = tcb->unmap_q;
  681. tx_info->tcb[tcb->id] = tcb;
  682. unmap_q->producer_index = 0;
  683. unmap_q->consumer_index = 0;
  684. unmap_q->q_depth = BNAD_TX_UNMAPQ_DEPTH;
  685. }
  686. static void
  687. bnad_cb_tcb_destroy(struct bnad *bnad, struct bna_tcb *tcb)
  688. {
  689. struct bnad_tx_info *tx_info =
  690. (struct bnad_tx_info *)tcb->txq->tx->priv;
  691. struct bnad_unmap_q *unmap_q = tcb->unmap_q;
  692. while (test_and_set_bit(BNAD_TXQ_FREE_SENT, &tcb->flags))
  693. cpu_relax();
  694. bnad_free_all_txbufs(bnad, tcb);
  695. unmap_q->producer_index = 0;
  696. unmap_q->consumer_index = 0;
  697. smp_mb__before_clear_bit();
  698. clear_bit(BNAD_TXQ_FREE_SENT, &tcb->flags);
  699. tx_info->tcb[tcb->id] = NULL;
  700. }
  701. static void
  702. bnad_cb_rcb_setup(struct bnad *bnad, struct bna_rcb *rcb)
  703. {
  704. struct bnad_unmap_q *unmap_q = rcb->unmap_q;
  705. unmap_q->producer_index = 0;
  706. unmap_q->consumer_index = 0;
  707. unmap_q->q_depth = BNAD_RX_UNMAPQ_DEPTH;
  708. }
  709. static void
  710. bnad_cb_rcb_destroy(struct bnad *bnad, struct bna_rcb *rcb)
  711. {
  712. bnad_free_all_rxbufs(bnad, rcb);
  713. }
  714. static void
  715. bnad_cb_ccb_setup(struct bnad *bnad, struct bna_ccb *ccb)
  716. {
  717. struct bnad_rx_info *rx_info =
  718. (struct bnad_rx_info *)ccb->cq->rx->priv;
  719. rx_info->rx_ctrl[ccb->id].ccb = ccb;
  720. ccb->ctrl = &rx_info->rx_ctrl[ccb->id];
  721. }
  722. static void
  723. bnad_cb_ccb_destroy(struct bnad *bnad, struct bna_ccb *ccb)
  724. {
  725. struct bnad_rx_info *rx_info =
  726. (struct bnad_rx_info *)ccb->cq->rx->priv;
  727. rx_info->rx_ctrl[ccb->id].ccb = NULL;
  728. }
  729. static void
  730. bnad_cb_tx_stall(struct bnad *bnad, struct bna_tcb *tcb)
  731. {
  732. struct bnad_tx_info *tx_info =
  733. (struct bnad_tx_info *)tcb->txq->tx->priv;
  734. if (tx_info != &bnad->tx_info[0])
  735. return;
  736. clear_bit(BNAD_TXQ_TX_STARTED, &tcb->flags);
  737. netif_stop_queue(bnad->netdev);
  738. pr_info("bna: %s TX_STOPPED\n", bnad->netdev->name);
  739. }
  740. static void
  741. bnad_cb_tx_resume(struct bnad *bnad, struct bna_tcb *tcb)
  742. {
  743. struct bnad_unmap_q *unmap_q = tcb->unmap_q;
  744. if (test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags))
  745. return;
  746. clear_bit(BNAD_RF_TX_SHUTDOWN_DELAYED, &bnad->run_flags);
  747. while (test_and_set_bit(BNAD_TXQ_FREE_SENT, &tcb->flags))
  748. cpu_relax();
  749. bnad_free_all_txbufs(bnad, tcb);
  750. unmap_q->producer_index = 0;
  751. unmap_q->consumer_index = 0;
  752. smp_mb__before_clear_bit();
  753. clear_bit(BNAD_TXQ_FREE_SENT, &tcb->flags);
  754. /*
  755. * Workaround for first device enable failure & we
  756. * get a 0 MAC address. We try to get the MAC address
  757. * again here.
  758. */
  759. if (is_zero_ether_addr(&bnad->perm_addr.mac[0])) {
  760. bna_port_mac_get(&bnad->bna.port, &bnad->perm_addr);
  761. bnad_set_netdev_perm_addr(bnad);
  762. }
  763. set_bit(BNAD_TXQ_TX_STARTED, &tcb->flags);
  764. if (netif_carrier_ok(bnad->netdev)) {
  765. pr_info("bna: %s TX_STARTED\n", bnad->netdev->name);
  766. netif_wake_queue(bnad->netdev);
  767. BNAD_UPDATE_CTR(bnad, netif_queue_wakeup);
  768. }
  769. }
  770. static void
  771. bnad_cb_tx_cleanup(struct bnad *bnad, struct bna_tcb *tcb)
  772. {
  773. /* Delay only once for the whole Tx Path Shutdown */
  774. if (!test_and_set_bit(BNAD_RF_TX_SHUTDOWN_DELAYED, &bnad->run_flags))
  775. mdelay(BNAD_TXRX_SYNC_MDELAY);
  776. }
  777. static void
  778. bnad_cb_rx_cleanup(struct bnad *bnad,
  779. struct bna_ccb *ccb)
  780. {
  781. clear_bit(BNAD_RXQ_STARTED, &ccb->rcb[0]->flags);
  782. if (ccb->rcb[1])
  783. clear_bit(BNAD_RXQ_STARTED, &ccb->rcb[1]->flags);
  784. if (!test_and_set_bit(BNAD_RF_RX_SHUTDOWN_DELAYED, &bnad->run_flags))
  785. mdelay(BNAD_TXRX_SYNC_MDELAY);
  786. }
  787. static void
  788. bnad_cb_rx_post(struct bnad *bnad, struct bna_rcb *rcb)
  789. {
  790. struct bnad_unmap_q *unmap_q = rcb->unmap_q;
  791. clear_bit(BNAD_RF_RX_SHUTDOWN_DELAYED, &bnad->run_flags);
  792. if (rcb == rcb->cq->ccb->rcb[0])
  793. bnad_cq_cmpl_init(bnad, rcb->cq->ccb);
  794. bnad_free_all_rxbufs(bnad, rcb);
  795. set_bit(BNAD_RXQ_STARTED, &rcb->flags);
  796. /* Now allocate & post buffers for this RCB */
  797. /* !!Allocation in callback context */
  798. if (!test_and_set_bit(BNAD_RXQ_REFILL, &rcb->flags)) {
  799. if (BNA_QE_FREE_CNT(unmap_q, unmap_q->q_depth)
  800. >> BNAD_RXQ_REFILL_THRESHOLD_SHIFT)
  801. bnad_alloc_n_post_rxbufs(bnad, rcb);
  802. smp_mb__before_clear_bit();
  803. clear_bit(BNAD_RXQ_REFILL, &rcb->flags);
  804. }
  805. }
  806. static void
  807. bnad_cb_rx_disabled(void *arg, struct bna_rx *rx,
  808. enum bna_cb_status status)
  809. {
  810. struct bnad *bnad = (struct bnad *)arg;
  811. complete(&bnad->bnad_completions.rx_comp);
  812. }
  813. static void
  814. bnad_cb_rx_mcast_add(struct bnad *bnad, struct bna_rx *rx,
  815. enum bna_cb_status status)
  816. {
  817. bnad->bnad_completions.mcast_comp_status = status;
  818. complete(&bnad->bnad_completions.mcast_comp);
  819. }
  820. void
  821. bnad_cb_stats_get(struct bnad *bnad, enum bna_cb_status status,
  822. struct bna_stats *stats)
  823. {
  824. if (status == BNA_CB_SUCCESS)
  825. BNAD_UPDATE_CTR(bnad, hw_stats_updates);
  826. if (!netif_running(bnad->netdev) ||
  827. !test_bit(BNAD_RF_STATS_TIMER_RUNNING, &bnad->run_flags))
  828. return;
  829. mod_timer(&bnad->stats_timer,
  830. jiffies + msecs_to_jiffies(BNAD_STATS_TIMER_FREQ));
  831. }
  832. /* Resource allocation, free functions */
  833. static void
  834. bnad_mem_free(struct bnad *bnad,
  835. struct bna_mem_info *mem_info)
  836. {
  837. int i;
  838. dma_addr_t dma_pa;
  839. if (mem_info->mdl == NULL)
  840. return;
  841. for (i = 0; i < mem_info->num; i++) {
  842. if (mem_info->mdl[i].kva != NULL) {
  843. if (mem_info->mem_type == BNA_MEM_T_DMA) {
  844. BNA_GET_DMA_ADDR(&(mem_info->mdl[i].dma),
  845. dma_pa);
  846. pci_free_consistent(bnad->pcidev,
  847. mem_info->mdl[i].len,
  848. mem_info->mdl[i].kva, dma_pa);
  849. } else
  850. kfree(mem_info->mdl[i].kva);
  851. }
  852. }
  853. kfree(mem_info->mdl);
  854. mem_info->mdl = NULL;
  855. }
  856. static int
  857. bnad_mem_alloc(struct bnad *bnad,
  858. struct bna_mem_info *mem_info)
  859. {
  860. int i;
  861. dma_addr_t dma_pa;
  862. if ((mem_info->num == 0) || (mem_info->len == 0)) {
  863. mem_info->mdl = NULL;
  864. return 0;
  865. }
  866. mem_info->mdl = kcalloc(mem_info->num, sizeof(struct bna_mem_descr),
  867. GFP_KERNEL);
  868. if (mem_info->mdl == NULL)
  869. return -ENOMEM;
  870. if (mem_info->mem_type == BNA_MEM_T_DMA) {
  871. for (i = 0; i < mem_info->num; i++) {
  872. mem_info->mdl[i].len = mem_info->len;
  873. mem_info->mdl[i].kva =
  874. pci_alloc_consistent(bnad->pcidev,
  875. mem_info->len, &dma_pa);
  876. if (mem_info->mdl[i].kva == NULL)
  877. goto err_return;
  878. BNA_SET_DMA_ADDR(dma_pa,
  879. &(mem_info->mdl[i].dma));
  880. }
  881. } else {
  882. for (i = 0; i < mem_info->num; i++) {
  883. mem_info->mdl[i].len = mem_info->len;
  884. mem_info->mdl[i].kva = kzalloc(mem_info->len,
  885. GFP_KERNEL);
  886. if (mem_info->mdl[i].kva == NULL)
  887. goto err_return;
  888. }
  889. }
  890. return 0;
  891. err_return:
  892. bnad_mem_free(bnad, mem_info);
  893. return -ENOMEM;
  894. }
  895. /* Free IRQ for Mailbox */
  896. static void
  897. bnad_mbox_irq_free(struct bnad *bnad,
  898. struct bna_intr_info *intr_info)
  899. {
  900. int irq;
  901. unsigned long flags;
  902. if (intr_info->idl == NULL)
  903. return;
  904. spin_lock_irqsave(&bnad->bna_lock, flags);
  905. bnad_disable_mbox_irq(bnad);
  906. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  907. irq = BNAD_GET_MBOX_IRQ(bnad);
  908. free_irq(irq, bnad);
  909. kfree(intr_info->idl);
  910. }
  911. /*
  912. * Allocates IRQ for Mailbox, but keep it disabled
  913. * This will be enabled once we get the mbox enable callback
  914. * from bna
  915. */
  916. static int
  917. bnad_mbox_irq_alloc(struct bnad *bnad,
  918. struct bna_intr_info *intr_info)
  919. {
  920. int err = 0;
  921. unsigned long flags;
  922. u32 irq;
  923. irq_handler_t irq_handler;
  924. /* Mbox should use only 1 vector */
  925. intr_info->idl = kzalloc(sizeof(*(intr_info->idl)), GFP_KERNEL);
  926. if (!intr_info->idl)
  927. return -ENOMEM;
  928. spin_lock_irqsave(&bnad->bna_lock, flags);
  929. if (bnad->cfg_flags & BNAD_CF_MSIX) {
  930. irq_handler = (irq_handler_t)bnad_msix_mbox_handler;
  931. irq = bnad->msix_table[bnad->msix_num - 1].vector;
  932. flags = 0;
  933. intr_info->intr_type = BNA_INTR_T_MSIX;
  934. intr_info->idl[0].vector = bnad->msix_num - 1;
  935. } else {
  936. irq_handler = (irq_handler_t)bnad_isr;
  937. irq = bnad->pcidev->irq;
  938. flags = IRQF_SHARED;
  939. intr_info->intr_type = BNA_INTR_T_INTX;
  940. /* intr_info->idl.vector = 0 ? */
  941. }
  942. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  943. sprintf(bnad->mbox_irq_name, "%s", BNAD_NAME);
  944. /*
  945. * Set the Mbox IRQ disable flag, so that the IRQ handler
  946. * called from request_irq() for SHARED IRQs do not execute
  947. */
  948. set_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags);
  949. BNAD_UPDATE_CTR(bnad, mbox_intr_disabled);
  950. err = request_irq(irq, irq_handler, flags,
  951. bnad->mbox_irq_name, bnad);
  952. if (err) {
  953. kfree(intr_info->idl);
  954. intr_info->idl = NULL;
  955. }
  956. return err;
  957. }
  958. static void
  959. bnad_txrx_irq_free(struct bnad *bnad, struct bna_intr_info *intr_info)
  960. {
  961. kfree(intr_info->idl);
  962. intr_info->idl = NULL;
  963. }
  964. /* Allocates Interrupt Descriptor List for MSIX/INT-X vectors */
  965. static int
  966. bnad_txrx_irq_alloc(struct bnad *bnad, enum bnad_intr_source src,
  967. uint txrx_id, struct bna_intr_info *intr_info)
  968. {
  969. int i, vector_start = 0;
  970. u32 cfg_flags;
  971. unsigned long flags;
  972. spin_lock_irqsave(&bnad->bna_lock, flags);
  973. cfg_flags = bnad->cfg_flags;
  974. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  975. if (cfg_flags & BNAD_CF_MSIX) {
  976. intr_info->intr_type = BNA_INTR_T_MSIX;
  977. intr_info->idl = kcalloc(intr_info->num,
  978. sizeof(struct bna_intr_descr),
  979. GFP_KERNEL);
  980. if (!intr_info->idl)
  981. return -ENOMEM;
  982. switch (src) {
  983. case BNAD_INTR_TX:
  984. vector_start = txrx_id;
  985. break;
  986. case BNAD_INTR_RX:
  987. vector_start = bnad->num_tx * bnad->num_txq_per_tx +
  988. txrx_id;
  989. break;
  990. default:
  991. BUG();
  992. }
  993. for (i = 0; i < intr_info->num; i++)
  994. intr_info->idl[i].vector = vector_start + i;
  995. } else {
  996. intr_info->intr_type = BNA_INTR_T_INTX;
  997. intr_info->num = 1;
  998. intr_info->idl = kcalloc(intr_info->num,
  999. sizeof(struct bna_intr_descr),
  1000. GFP_KERNEL);
  1001. if (!intr_info->idl)
  1002. return -ENOMEM;
  1003. switch (src) {
  1004. case BNAD_INTR_TX:
  1005. intr_info->idl[0].vector = 0x1; /* Bit mask : Tx IB */
  1006. break;
  1007. case BNAD_INTR_RX:
  1008. intr_info->idl[0].vector = 0x2; /* Bit mask : Rx IB */
  1009. break;
  1010. }
  1011. }
  1012. return 0;
  1013. }
  1014. /**
  1015. * NOTE: Should be called for MSIX only
  1016. * Unregisters Tx MSIX vector(s) from the kernel
  1017. */
  1018. static void
  1019. bnad_tx_msix_unregister(struct bnad *bnad, struct bnad_tx_info *tx_info,
  1020. int num_txqs)
  1021. {
  1022. int i;
  1023. int vector_num;
  1024. for (i = 0; i < num_txqs; i++) {
  1025. if (tx_info->tcb[i] == NULL)
  1026. continue;
  1027. vector_num = tx_info->tcb[i]->intr_vector;
  1028. free_irq(bnad->msix_table[vector_num].vector, tx_info->tcb[i]);
  1029. }
  1030. }
  1031. /**
  1032. * NOTE: Should be called for MSIX only
  1033. * Registers Tx MSIX vector(s) and ISR(s), cookie with the kernel
  1034. */
  1035. static int
  1036. bnad_tx_msix_register(struct bnad *bnad, struct bnad_tx_info *tx_info,
  1037. uint tx_id, int num_txqs)
  1038. {
  1039. int i;
  1040. int err;
  1041. int vector_num;
  1042. for (i = 0; i < num_txqs; i++) {
  1043. vector_num = tx_info->tcb[i]->intr_vector;
  1044. sprintf(tx_info->tcb[i]->name, "%s TXQ %d", bnad->netdev->name,
  1045. tx_id + tx_info->tcb[i]->id);
  1046. err = request_irq(bnad->msix_table[vector_num].vector,
  1047. (irq_handler_t)bnad_msix_tx, 0,
  1048. tx_info->tcb[i]->name,
  1049. tx_info->tcb[i]);
  1050. if (err)
  1051. goto err_return;
  1052. }
  1053. return 0;
  1054. err_return:
  1055. if (i > 0)
  1056. bnad_tx_msix_unregister(bnad, tx_info, (i - 1));
  1057. return -1;
  1058. }
  1059. /**
  1060. * NOTE: Should be called for MSIX only
  1061. * Unregisters Rx MSIX vector(s) from the kernel
  1062. */
  1063. static void
  1064. bnad_rx_msix_unregister(struct bnad *bnad, struct bnad_rx_info *rx_info,
  1065. int num_rxps)
  1066. {
  1067. int i;
  1068. int vector_num;
  1069. for (i = 0; i < num_rxps; i++) {
  1070. if (rx_info->rx_ctrl[i].ccb == NULL)
  1071. continue;
  1072. vector_num = rx_info->rx_ctrl[i].ccb->intr_vector;
  1073. free_irq(bnad->msix_table[vector_num].vector,
  1074. rx_info->rx_ctrl[i].ccb);
  1075. }
  1076. }
  1077. /**
  1078. * NOTE: Should be called for MSIX only
  1079. * Registers Tx MSIX vector(s) and ISR(s), cookie with the kernel
  1080. */
  1081. static int
  1082. bnad_rx_msix_register(struct bnad *bnad, struct bnad_rx_info *rx_info,
  1083. uint rx_id, int num_rxps)
  1084. {
  1085. int i;
  1086. int err;
  1087. int vector_num;
  1088. for (i = 0; i < num_rxps; i++) {
  1089. vector_num = rx_info->rx_ctrl[i].ccb->intr_vector;
  1090. sprintf(rx_info->rx_ctrl[i].ccb->name, "%s CQ %d",
  1091. bnad->netdev->name,
  1092. rx_id + rx_info->rx_ctrl[i].ccb->id);
  1093. err = request_irq(bnad->msix_table[vector_num].vector,
  1094. (irq_handler_t)bnad_msix_rx, 0,
  1095. rx_info->rx_ctrl[i].ccb->name,
  1096. rx_info->rx_ctrl[i].ccb);
  1097. if (err)
  1098. goto err_return;
  1099. }
  1100. return 0;
  1101. err_return:
  1102. if (i > 0)
  1103. bnad_rx_msix_unregister(bnad, rx_info, (i - 1));
  1104. return -1;
  1105. }
  1106. /* Free Tx object Resources */
  1107. static void
  1108. bnad_tx_res_free(struct bnad *bnad, struct bna_res_info *res_info)
  1109. {
  1110. int i;
  1111. for (i = 0; i < BNA_TX_RES_T_MAX; i++) {
  1112. if (res_info[i].res_type == BNA_RES_T_MEM)
  1113. bnad_mem_free(bnad, &res_info[i].res_u.mem_info);
  1114. else if (res_info[i].res_type == BNA_RES_T_INTR)
  1115. bnad_txrx_irq_free(bnad, &res_info[i].res_u.intr_info);
  1116. }
  1117. }
  1118. /* Allocates memory and interrupt resources for Tx object */
  1119. static int
  1120. bnad_tx_res_alloc(struct bnad *bnad, struct bna_res_info *res_info,
  1121. uint tx_id)
  1122. {
  1123. int i, err = 0;
  1124. for (i = 0; i < BNA_TX_RES_T_MAX; i++) {
  1125. if (res_info[i].res_type == BNA_RES_T_MEM)
  1126. err = bnad_mem_alloc(bnad,
  1127. &res_info[i].res_u.mem_info);
  1128. else if (res_info[i].res_type == BNA_RES_T_INTR)
  1129. err = bnad_txrx_irq_alloc(bnad, BNAD_INTR_TX, tx_id,
  1130. &res_info[i].res_u.intr_info);
  1131. if (err)
  1132. goto err_return;
  1133. }
  1134. return 0;
  1135. err_return:
  1136. bnad_tx_res_free(bnad, res_info);
  1137. return err;
  1138. }
  1139. /* Free Rx object Resources */
  1140. static void
  1141. bnad_rx_res_free(struct bnad *bnad, struct bna_res_info *res_info)
  1142. {
  1143. int i;
  1144. for (i = 0; i < BNA_RX_RES_T_MAX; i++) {
  1145. if (res_info[i].res_type == BNA_RES_T_MEM)
  1146. bnad_mem_free(bnad, &res_info[i].res_u.mem_info);
  1147. else if (res_info[i].res_type == BNA_RES_T_INTR)
  1148. bnad_txrx_irq_free(bnad, &res_info[i].res_u.intr_info);
  1149. }
  1150. }
  1151. /* Allocates memory and interrupt resources for Rx object */
  1152. static int
  1153. bnad_rx_res_alloc(struct bnad *bnad, struct bna_res_info *res_info,
  1154. uint rx_id)
  1155. {
  1156. int i, err = 0;
  1157. /* All memory needs to be allocated before setup_ccbs */
  1158. for (i = 0; i < BNA_RX_RES_T_MAX; i++) {
  1159. if (res_info[i].res_type == BNA_RES_T_MEM)
  1160. err = bnad_mem_alloc(bnad,
  1161. &res_info[i].res_u.mem_info);
  1162. else if (res_info[i].res_type == BNA_RES_T_INTR)
  1163. err = bnad_txrx_irq_alloc(bnad, BNAD_INTR_RX, rx_id,
  1164. &res_info[i].res_u.intr_info);
  1165. if (err)
  1166. goto err_return;
  1167. }
  1168. return 0;
  1169. err_return:
  1170. bnad_rx_res_free(bnad, res_info);
  1171. return err;
  1172. }
  1173. /* Timer callbacks */
  1174. /* a) IOC timer */
  1175. static void
  1176. bnad_ioc_timeout(unsigned long data)
  1177. {
  1178. struct bnad *bnad = (struct bnad *)data;
  1179. unsigned long flags;
  1180. spin_lock_irqsave(&bnad->bna_lock, flags);
  1181. bfa_nw_ioc_timeout((void *) &bnad->bna.device.ioc);
  1182. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  1183. }
  1184. static void
  1185. bnad_ioc_hb_check(unsigned long data)
  1186. {
  1187. struct bnad *bnad = (struct bnad *)data;
  1188. unsigned long flags;
  1189. spin_lock_irqsave(&bnad->bna_lock, flags);
  1190. bfa_nw_ioc_hb_check((void *) &bnad->bna.device.ioc);
  1191. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  1192. }
  1193. static void
  1194. bnad_ioc_sem_timeout(unsigned long data)
  1195. {
  1196. struct bnad *bnad = (struct bnad *)data;
  1197. unsigned long flags;
  1198. spin_lock_irqsave(&bnad->bna_lock, flags);
  1199. bfa_nw_ioc_sem_timeout((void *) &bnad->bna.device.ioc);
  1200. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  1201. }
  1202. /*
  1203. * All timer routines use bnad->bna_lock to protect against
  1204. * the following race, which may occur in case of no locking:
  1205. * Time CPU m CPU n
  1206. * 0 1 = test_bit
  1207. * 1 clear_bit
  1208. * 2 del_timer_sync
  1209. * 3 mod_timer
  1210. */
  1211. /* b) Dynamic Interrupt Moderation Timer */
  1212. static void
  1213. bnad_dim_timeout(unsigned long data)
  1214. {
  1215. struct bnad *bnad = (struct bnad *)data;
  1216. struct bnad_rx_info *rx_info;
  1217. struct bnad_rx_ctrl *rx_ctrl;
  1218. int i, j;
  1219. unsigned long flags;
  1220. if (!netif_carrier_ok(bnad->netdev))
  1221. return;
  1222. spin_lock_irqsave(&bnad->bna_lock, flags);
  1223. for (i = 0; i < bnad->num_rx; i++) {
  1224. rx_info = &bnad->rx_info[i];
  1225. if (!rx_info->rx)
  1226. continue;
  1227. for (j = 0; j < bnad->num_rxp_per_rx; j++) {
  1228. rx_ctrl = &rx_info->rx_ctrl[j];
  1229. if (!rx_ctrl->ccb)
  1230. continue;
  1231. bna_rx_dim_update(rx_ctrl->ccb);
  1232. }
  1233. }
  1234. /* Check for BNAD_CF_DIM_ENABLED, does not eleminate a race */
  1235. if (test_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags))
  1236. mod_timer(&bnad->dim_timer,
  1237. jiffies + msecs_to_jiffies(BNAD_DIM_TIMER_FREQ));
  1238. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  1239. }
  1240. /* c) Statistics Timer */
  1241. static void
  1242. bnad_stats_timeout(unsigned long data)
  1243. {
  1244. struct bnad *bnad = (struct bnad *)data;
  1245. unsigned long flags;
  1246. if (!netif_running(bnad->netdev) ||
  1247. !test_bit(BNAD_RF_STATS_TIMER_RUNNING, &bnad->run_flags))
  1248. return;
  1249. spin_lock_irqsave(&bnad->bna_lock, flags);
  1250. bna_stats_get(&bnad->bna);
  1251. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  1252. }
  1253. /*
  1254. * Set up timer for DIM
  1255. * Called with bnad->bna_lock held
  1256. */
  1257. void
  1258. bnad_dim_timer_start(struct bnad *bnad)
  1259. {
  1260. if (bnad->cfg_flags & BNAD_CF_DIM_ENABLED &&
  1261. !test_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags)) {
  1262. setup_timer(&bnad->dim_timer, bnad_dim_timeout,
  1263. (unsigned long)bnad);
  1264. set_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags);
  1265. mod_timer(&bnad->dim_timer,
  1266. jiffies + msecs_to_jiffies(BNAD_DIM_TIMER_FREQ));
  1267. }
  1268. }
  1269. /*
  1270. * Set up timer for statistics
  1271. * Called with mutex_lock(&bnad->conf_mutex) held
  1272. */
  1273. static void
  1274. bnad_stats_timer_start(struct bnad *bnad)
  1275. {
  1276. unsigned long flags;
  1277. spin_lock_irqsave(&bnad->bna_lock, flags);
  1278. if (!test_and_set_bit(BNAD_RF_STATS_TIMER_RUNNING, &bnad->run_flags)) {
  1279. setup_timer(&bnad->stats_timer, bnad_stats_timeout,
  1280. (unsigned long)bnad);
  1281. mod_timer(&bnad->stats_timer,
  1282. jiffies + msecs_to_jiffies(BNAD_STATS_TIMER_FREQ));
  1283. }
  1284. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  1285. }
  1286. /*
  1287. * Stops the stats timer
  1288. * Called with mutex_lock(&bnad->conf_mutex) held
  1289. */
  1290. static void
  1291. bnad_stats_timer_stop(struct bnad *bnad)
  1292. {
  1293. int to_del = 0;
  1294. unsigned long flags;
  1295. spin_lock_irqsave(&bnad->bna_lock, flags);
  1296. if (test_and_clear_bit(BNAD_RF_STATS_TIMER_RUNNING, &bnad->run_flags))
  1297. to_del = 1;
  1298. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  1299. if (to_del)
  1300. del_timer_sync(&bnad->stats_timer);
  1301. }
  1302. /* Utilities */
  1303. static void
  1304. bnad_netdev_mc_list_get(struct net_device *netdev, u8 *mc_list)
  1305. {
  1306. int i = 1; /* Index 0 has broadcast address */
  1307. struct netdev_hw_addr *mc_addr;
  1308. netdev_for_each_mc_addr(mc_addr, netdev) {
  1309. memcpy(&mc_list[i * ETH_ALEN], &mc_addr->addr[0],
  1310. ETH_ALEN);
  1311. i++;
  1312. }
  1313. }
  1314. static int
  1315. bnad_napi_poll_rx(struct napi_struct *napi, int budget)
  1316. {
  1317. struct bnad_rx_ctrl *rx_ctrl =
  1318. container_of(napi, struct bnad_rx_ctrl, napi);
  1319. struct bna_ccb *ccb;
  1320. struct bnad *bnad;
  1321. int rcvd = 0;
  1322. ccb = rx_ctrl->ccb;
  1323. bnad = ccb->bnad;
  1324. if (!netif_carrier_ok(bnad->netdev))
  1325. goto poll_exit;
  1326. rcvd = bnad_poll_cq(bnad, ccb, budget);
  1327. if (rcvd == budget)
  1328. return rcvd;
  1329. poll_exit:
  1330. napi_complete((napi));
  1331. BNAD_UPDATE_CTR(bnad, netif_rx_complete);
  1332. bnad_enable_rx_irq(bnad, ccb);
  1333. return rcvd;
  1334. }
  1335. static void
  1336. bnad_napi_enable(struct bnad *bnad, u32 rx_id)
  1337. {
  1338. struct bnad_rx_ctrl *rx_ctrl;
  1339. int i;
  1340. /* Initialize & enable NAPI */
  1341. for (i = 0; i < bnad->num_rxp_per_rx; i++) {
  1342. rx_ctrl = &bnad->rx_info[rx_id].rx_ctrl[i];
  1343. netif_napi_add(bnad->netdev, &rx_ctrl->napi,
  1344. bnad_napi_poll_rx, 64);
  1345. napi_enable(&rx_ctrl->napi);
  1346. }
  1347. }
  1348. static void
  1349. bnad_napi_disable(struct bnad *bnad, u32 rx_id)
  1350. {
  1351. int i;
  1352. /* First disable and then clean up */
  1353. for (i = 0; i < bnad->num_rxp_per_rx; i++) {
  1354. napi_disable(&bnad->rx_info[rx_id].rx_ctrl[i].napi);
  1355. netif_napi_del(&bnad->rx_info[rx_id].rx_ctrl[i].napi);
  1356. }
  1357. }
  1358. /* Should be held with conf_lock held */
  1359. void
  1360. bnad_cleanup_tx(struct bnad *bnad, uint tx_id)
  1361. {
  1362. struct bnad_tx_info *tx_info = &bnad->tx_info[tx_id];
  1363. struct bna_res_info *res_info = &bnad->tx_res_info[tx_id].res_info[0];
  1364. unsigned long flags;
  1365. if (!tx_info->tx)
  1366. return;
  1367. init_completion(&bnad->bnad_completions.tx_comp);
  1368. spin_lock_irqsave(&bnad->bna_lock, flags);
  1369. bna_tx_disable(tx_info->tx, BNA_HARD_CLEANUP, bnad_cb_tx_disabled);
  1370. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  1371. wait_for_completion(&bnad->bnad_completions.tx_comp);
  1372. if (tx_info->tcb[0]->intr_type == BNA_INTR_T_MSIX)
  1373. bnad_tx_msix_unregister(bnad, tx_info,
  1374. bnad->num_txq_per_tx);
  1375. spin_lock_irqsave(&bnad->bna_lock, flags);
  1376. bna_tx_destroy(tx_info->tx);
  1377. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  1378. tx_info->tx = NULL;
  1379. if (0 == tx_id)
  1380. tasklet_kill(&bnad->tx_free_tasklet);
  1381. bnad_tx_res_free(bnad, res_info);
  1382. }
  1383. /* Should be held with conf_lock held */
  1384. int
  1385. bnad_setup_tx(struct bnad *bnad, uint tx_id)
  1386. {
  1387. int err;
  1388. struct bnad_tx_info *tx_info = &bnad->tx_info[tx_id];
  1389. struct bna_res_info *res_info = &bnad->tx_res_info[tx_id].res_info[0];
  1390. struct bna_intr_info *intr_info =
  1391. &res_info[BNA_TX_RES_INTR_T_TXCMPL].res_u.intr_info;
  1392. struct bna_tx_config *tx_config = &bnad->tx_config[tx_id];
  1393. struct bna_tx_event_cbfn tx_cbfn;
  1394. struct bna_tx *tx;
  1395. unsigned long flags;
  1396. /* Initialize the Tx object configuration */
  1397. tx_config->num_txq = bnad->num_txq_per_tx;
  1398. tx_config->txq_depth = bnad->txq_depth;
  1399. tx_config->tx_type = BNA_TX_T_REGULAR;
  1400. /* Initialize the tx event handlers */
  1401. tx_cbfn.tcb_setup_cbfn = bnad_cb_tcb_setup;
  1402. tx_cbfn.tcb_destroy_cbfn = bnad_cb_tcb_destroy;
  1403. tx_cbfn.tx_stall_cbfn = bnad_cb_tx_stall;
  1404. tx_cbfn.tx_resume_cbfn = bnad_cb_tx_resume;
  1405. tx_cbfn.tx_cleanup_cbfn = bnad_cb_tx_cleanup;
  1406. /* Get BNA's resource requirement for one tx object */
  1407. spin_lock_irqsave(&bnad->bna_lock, flags);
  1408. bna_tx_res_req(bnad->num_txq_per_tx,
  1409. bnad->txq_depth, res_info);
  1410. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  1411. /* Fill Unmap Q memory requirements */
  1412. BNAD_FILL_UNMAPQ_MEM_REQ(
  1413. &res_info[BNA_TX_RES_MEM_T_UNMAPQ],
  1414. bnad->num_txq_per_tx,
  1415. BNAD_TX_UNMAPQ_DEPTH);
  1416. /* Allocate resources */
  1417. err = bnad_tx_res_alloc(bnad, res_info, tx_id);
  1418. if (err)
  1419. return err;
  1420. /* Ask BNA to create one Tx object, supplying required resources */
  1421. spin_lock_irqsave(&bnad->bna_lock, flags);
  1422. tx = bna_tx_create(&bnad->bna, bnad, tx_config, &tx_cbfn, res_info,
  1423. tx_info);
  1424. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  1425. if (!tx)
  1426. goto err_return;
  1427. tx_info->tx = tx;
  1428. /* Register ISR for the Tx object */
  1429. if (intr_info->intr_type == BNA_INTR_T_MSIX) {
  1430. err = bnad_tx_msix_register(bnad, tx_info,
  1431. tx_id, bnad->num_txq_per_tx);
  1432. if (err)
  1433. goto err_return;
  1434. }
  1435. spin_lock_irqsave(&bnad->bna_lock, flags);
  1436. bna_tx_enable(tx);
  1437. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  1438. return 0;
  1439. err_return:
  1440. bnad_tx_res_free(bnad, res_info);
  1441. return err;
  1442. }
  1443. /* Setup the rx config for bna_rx_create */
  1444. /* bnad decides the configuration */
  1445. static void
  1446. bnad_init_rx_config(struct bnad *bnad, struct bna_rx_config *rx_config)
  1447. {
  1448. rx_config->rx_type = BNA_RX_T_REGULAR;
  1449. rx_config->num_paths = bnad->num_rxp_per_rx;
  1450. if (bnad->num_rxp_per_rx > 1) {
  1451. rx_config->rss_status = BNA_STATUS_T_ENABLED;
  1452. rx_config->rss_config.hash_type =
  1453. (BFI_RSS_T_V4_TCP |
  1454. BFI_RSS_T_V6_TCP |
  1455. BFI_RSS_T_V4_IP |
  1456. BFI_RSS_T_V6_IP);
  1457. rx_config->rss_config.hash_mask =
  1458. bnad->num_rxp_per_rx - 1;
  1459. get_random_bytes(rx_config->rss_config.toeplitz_hash_key,
  1460. sizeof(rx_config->rss_config.toeplitz_hash_key));
  1461. } else {
  1462. rx_config->rss_status = BNA_STATUS_T_DISABLED;
  1463. memset(&rx_config->rss_config, 0,
  1464. sizeof(rx_config->rss_config));
  1465. }
  1466. rx_config->rxp_type = BNA_RXP_SLR;
  1467. rx_config->q_depth = bnad->rxq_depth;
  1468. rx_config->small_buff_size = BFI_SMALL_RXBUF_SIZE;
  1469. rx_config->vlan_strip_status = BNA_STATUS_T_ENABLED;
  1470. }
  1471. /* Called with mutex_lock(&bnad->conf_mutex) held */
  1472. void
  1473. bnad_cleanup_rx(struct bnad *bnad, uint rx_id)
  1474. {
  1475. struct bnad_rx_info *rx_info = &bnad->rx_info[rx_id];
  1476. struct bna_rx_config *rx_config = &bnad->rx_config[rx_id];
  1477. struct bna_res_info *res_info = &bnad->rx_res_info[rx_id].res_info[0];
  1478. unsigned long flags;
  1479. int dim_timer_del = 0;
  1480. if (!rx_info->rx)
  1481. return;
  1482. if (0 == rx_id) {
  1483. spin_lock_irqsave(&bnad->bna_lock, flags);
  1484. dim_timer_del = bnad_dim_timer_running(bnad);
  1485. if (dim_timer_del)
  1486. clear_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags);
  1487. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  1488. if (dim_timer_del)
  1489. del_timer_sync(&bnad->dim_timer);
  1490. }
  1491. bnad_napi_disable(bnad, rx_id);
  1492. init_completion(&bnad->bnad_completions.rx_comp);
  1493. spin_lock_irqsave(&bnad->bna_lock, flags);
  1494. bna_rx_disable(rx_info->rx, BNA_HARD_CLEANUP, bnad_cb_rx_disabled);
  1495. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  1496. wait_for_completion(&bnad->bnad_completions.rx_comp);
  1497. if (rx_info->rx_ctrl[0].ccb->intr_type == BNA_INTR_T_MSIX)
  1498. bnad_rx_msix_unregister(bnad, rx_info, rx_config->num_paths);
  1499. spin_lock_irqsave(&bnad->bna_lock, flags);
  1500. bna_rx_destroy(rx_info->rx);
  1501. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  1502. rx_info->rx = NULL;
  1503. bnad_rx_res_free(bnad, res_info);
  1504. }
  1505. /* Called with mutex_lock(&bnad->conf_mutex) held */
  1506. int
  1507. bnad_setup_rx(struct bnad *bnad, uint rx_id)
  1508. {
  1509. int err;
  1510. struct bnad_rx_info *rx_info = &bnad->rx_info[rx_id];
  1511. struct bna_res_info *res_info = &bnad->rx_res_info[rx_id].res_info[0];
  1512. struct bna_intr_info *intr_info =
  1513. &res_info[BNA_RX_RES_T_INTR].res_u.intr_info;
  1514. struct bna_rx_config *rx_config = &bnad->rx_config[rx_id];
  1515. struct bna_rx_event_cbfn rx_cbfn;
  1516. struct bna_rx *rx;
  1517. unsigned long flags;
  1518. /* Initialize the Rx object configuration */
  1519. bnad_init_rx_config(bnad, rx_config);
  1520. /* Initialize the Rx event handlers */
  1521. rx_cbfn.rcb_setup_cbfn = bnad_cb_rcb_setup;
  1522. rx_cbfn.rcb_destroy_cbfn = bnad_cb_rcb_destroy;
  1523. rx_cbfn.rcb_destroy_cbfn = NULL;
  1524. rx_cbfn.ccb_setup_cbfn = bnad_cb_ccb_setup;
  1525. rx_cbfn.ccb_destroy_cbfn = bnad_cb_ccb_destroy;
  1526. rx_cbfn.rx_cleanup_cbfn = bnad_cb_rx_cleanup;
  1527. rx_cbfn.rx_post_cbfn = bnad_cb_rx_post;
  1528. /* Get BNA's resource requirement for one Rx object */
  1529. spin_lock_irqsave(&bnad->bna_lock, flags);
  1530. bna_rx_res_req(rx_config, res_info);
  1531. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  1532. /* Fill Unmap Q memory requirements */
  1533. BNAD_FILL_UNMAPQ_MEM_REQ(
  1534. &res_info[BNA_RX_RES_MEM_T_UNMAPQ],
  1535. rx_config->num_paths +
  1536. ((rx_config->rxp_type == BNA_RXP_SINGLE) ? 0 :
  1537. rx_config->num_paths), BNAD_RX_UNMAPQ_DEPTH);
  1538. /* Allocate resource */
  1539. err = bnad_rx_res_alloc(bnad, res_info, rx_id);
  1540. if (err)
  1541. return err;
  1542. /* Ask BNA to create one Rx object, supplying required resources */
  1543. spin_lock_irqsave(&bnad->bna_lock, flags);
  1544. rx = bna_rx_create(&bnad->bna, bnad, rx_config, &rx_cbfn, res_info,
  1545. rx_info);
  1546. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  1547. if (!rx)
  1548. goto err_return;
  1549. rx_info->rx = rx;
  1550. /* Register ISR for the Rx object */
  1551. if (intr_info->intr_type == BNA_INTR_T_MSIX) {
  1552. err = bnad_rx_msix_register(bnad, rx_info, rx_id,
  1553. rx_config->num_paths);
  1554. if (err)
  1555. goto err_return;
  1556. }
  1557. /* Enable NAPI */
  1558. bnad_napi_enable(bnad, rx_id);
  1559. spin_lock_irqsave(&bnad->bna_lock, flags);
  1560. if (0 == rx_id) {
  1561. /* Set up Dynamic Interrupt Moderation Vector */
  1562. if (bnad->cfg_flags & BNAD_CF_DIM_ENABLED)
  1563. bna_rx_dim_reconfig(&bnad->bna, bna_napi_dim_vector);
  1564. /* Enable VLAN filtering only on the default Rx */
  1565. bna_rx_vlanfilter_enable(rx);
  1566. /* Start the DIM timer */
  1567. bnad_dim_timer_start(bnad);
  1568. }
  1569. bna_rx_enable(rx);
  1570. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  1571. return 0;
  1572. err_return:
  1573. bnad_cleanup_rx(bnad, rx_id);
  1574. return err;
  1575. }
  1576. /* Called with conf_lock & bnad->bna_lock held */
  1577. void
  1578. bnad_tx_coalescing_timeo_set(struct bnad *bnad)
  1579. {
  1580. struct bnad_tx_info *tx_info;
  1581. tx_info = &bnad->tx_info[0];
  1582. if (!tx_info->tx)
  1583. return;
  1584. bna_tx_coalescing_timeo_set(tx_info->tx, bnad->tx_coalescing_timeo);
  1585. }
  1586. /* Called with conf_lock & bnad->bna_lock held */
  1587. void
  1588. bnad_rx_coalescing_timeo_set(struct bnad *bnad)
  1589. {
  1590. struct bnad_rx_info *rx_info;
  1591. int i;
  1592. for (i = 0; i < bnad->num_rx; i++) {
  1593. rx_info = &bnad->rx_info[i];
  1594. if (!rx_info->rx)
  1595. continue;
  1596. bna_rx_coalescing_timeo_set(rx_info->rx,
  1597. bnad->rx_coalescing_timeo);
  1598. }
  1599. }
  1600. /*
  1601. * Called with bnad->bna_lock held
  1602. */
  1603. static int
  1604. bnad_mac_addr_set_locked(struct bnad *bnad, u8 *mac_addr)
  1605. {
  1606. int ret;
  1607. if (!is_valid_ether_addr(mac_addr))
  1608. return -EADDRNOTAVAIL;
  1609. /* If datapath is down, pretend everything went through */
  1610. if (!bnad->rx_info[0].rx)
  1611. return 0;
  1612. ret = bna_rx_ucast_set(bnad->rx_info[0].rx, mac_addr, NULL);
  1613. if (ret != BNA_CB_SUCCESS)
  1614. return -EADDRNOTAVAIL;
  1615. return 0;
  1616. }
  1617. /* Should be called with conf_lock held */
  1618. static int
  1619. bnad_enable_default_bcast(struct bnad *bnad)
  1620. {
  1621. struct bnad_rx_info *rx_info = &bnad->rx_info[0];
  1622. int ret;
  1623. unsigned long flags;
  1624. init_completion(&bnad->bnad_completions.mcast_comp);
  1625. spin_lock_irqsave(&bnad->bna_lock, flags);
  1626. ret = bna_rx_mcast_add(rx_info->rx, (u8 *)bnad_bcast_addr,
  1627. bnad_cb_rx_mcast_add);
  1628. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  1629. if (ret == BNA_CB_SUCCESS)
  1630. wait_for_completion(&bnad->bnad_completions.mcast_comp);
  1631. else
  1632. return -ENODEV;
  1633. if (bnad->bnad_completions.mcast_comp_status != BNA_CB_SUCCESS)
  1634. return -ENODEV;
  1635. return 0;
  1636. }
  1637. /* Called with bnad_conf_lock() held */
  1638. static void
  1639. bnad_restore_vlans(struct bnad *bnad, u32 rx_id)
  1640. {
  1641. u16 vlan_id;
  1642. unsigned long flags;
  1643. if (!bnad->vlan_grp)
  1644. return;
  1645. BUG_ON(!(VLAN_N_VID == (BFI_MAX_VLAN + 1)));
  1646. for (vlan_id = 0; vlan_id < VLAN_N_VID; vlan_id++) {
  1647. if (!vlan_group_get_device(bnad->vlan_grp, vlan_id))
  1648. continue;
  1649. spin_lock_irqsave(&bnad->bna_lock, flags);
  1650. bna_rx_vlan_add(bnad->rx_info[rx_id].rx, vlan_id);
  1651. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  1652. }
  1653. }
  1654. /* Statistics utilities */
  1655. void
  1656. bnad_netdev_qstats_fill(struct bnad *bnad, struct rtnl_link_stats64 *stats)
  1657. {
  1658. int i, j;
  1659. for (i = 0; i < bnad->num_rx; i++) {
  1660. for (j = 0; j < bnad->num_rxp_per_rx; j++) {
  1661. if (bnad->rx_info[i].rx_ctrl[j].ccb) {
  1662. stats->rx_packets += bnad->rx_info[i].
  1663. rx_ctrl[j].ccb->rcb[0]->rxq->rx_packets;
  1664. stats->rx_bytes += bnad->rx_info[i].
  1665. rx_ctrl[j].ccb->rcb[0]->rxq->rx_bytes;
  1666. if (bnad->rx_info[i].rx_ctrl[j].ccb->rcb[1] &&
  1667. bnad->rx_info[i].rx_ctrl[j].ccb->
  1668. rcb[1]->rxq) {
  1669. stats->rx_packets +=
  1670. bnad->rx_info[i].rx_ctrl[j].
  1671. ccb->rcb[1]->rxq->rx_packets;
  1672. stats->rx_bytes +=
  1673. bnad->rx_info[i].rx_ctrl[j].
  1674. ccb->rcb[1]->rxq->rx_bytes;
  1675. }
  1676. }
  1677. }
  1678. }
  1679. for (i = 0; i < bnad->num_tx; i++) {
  1680. for (j = 0; j < bnad->num_txq_per_tx; j++) {
  1681. if (bnad->tx_info[i].tcb[j]) {
  1682. stats->tx_packets +=
  1683. bnad->tx_info[i].tcb[j]->txq->tx_packets;
  1684. stats->tx_bytes +=
  1685. bnad->tx_info[i].tcb[j]->txq->tx_bytes;
  1686. }
  1687. }
  1688. }
  1689. }
  1690. /*
  1691. * Must be called with the bna_lock held.
  1692. */
  1693. void
  1694. bnad_netdev_hwstats_fill(struct bnad *bnad, struct rtnl_link_stats64 *stats)
  1695. {
  1696. struct bfi_ll_stats_mac *mac_stats;
  1697. u64 bmap;
  1698. int i;
  1699. mac_stats = &bnad->stats.bna_stats->hw_stats->mac_stats;
  1700. stats->rx_errors =
  1701. mac_stats->rx_fcs_error + mac_stats->rx_alignment_error +
  1702. mac_stats->rx_frame_length_error + mac_stats->rx_code_error +
  1703. mac_stats->rx_undersize;
  1704. stats->tx_errors = mac_stats->tx_fcs_error +
  1705. mac_stats->tx_undersize;
  1706. stats->rx_dropped = mac_stats->rx_drop;
  1707. stats->tx_dropped = mac_stats->tx_drop;
  1708. stats->multicast = mac_stats->rx_multicast;
  1709. stats->collisions = mac_stats->tx_total_collision;
  1710. stats->rx_length_errors = mac_stats->rx_frame_length_error;
  1711. /* receive ring buffer overflow ?? */
  1712. stats->rx_crc_errors = mac_stats->rx_fcs_error;
  1713. stats->rx_frame_errors = mac_stats->rx_alignment_error;
  1714. /* recv'r fifo overrun */
  1715. bmap = (u64)bnad->stats.bna_stats->rxf_bmap[0] |
  1716. ((u64)bnad->stats.bna_stats->rxf_bmap[1] << 32);
  1717. for (i = 0; bmap && (i < BFI_LL_RXF_ID_MAX); i++) {
  1718. if (bmap & 1) {
  1719. stats->rx_fifo_errors +=
  1720. bnad->stats.bna_stats->
  1721. hw_stats->rxf_stats[i].frame_drops;
  1722. break;
  1723. }
  1724. bmap >>= 1;
  1725. }
  1726. }
  1727. static void
  1728. bnad_mbox_irq_sync(struct bnad *bnad)
  1729. {
  1730. u32 irq;
  1731. unsigned long flags;
  1732. spin_lock_irqsave(&bnad->bna_lock, flags);
  1733. if (bnad->cfg_flags & BNAD_CF_MSIX)
  1734. irq = bnad->msix_table[bnad->msix_num - 1].vector;
  1735. else
  1736. irq = bnad->pcidev->irq;
  1737. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  1738. synchronize_irq(irq);
  1739. }
  1740. /* Utility used by bnad_start_xmit, for doing TSO */
  1741. static int
  1742. bnad_tso_prepare(struct bnad *bnad, struct sk_buff *skb)
  1743. {
  1744. int err;
  1745. /* SKB_GSO_TCPV4 and SKB_GSO_TCPV6 is defined since 2.6.18. */
  1746. BUG_ON(!(skb_shinfo(skb)->gso_type == SKB_GSO_TCPV4 ||
  1747. skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6));
  1748. if (skb_header_cloned(skb)) {
  1749. err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
  1750. if (err) {
  1751. BNAD_UPDATE_CTR(bnad, tso_err);
  1752. return err;
  1753. }
  1754. }
  1755. /*
  1756. * For TSO, the TCP checksum field is seeded with pseudo-header sum
  1757. * excluding the length field.
  1758. */
  1759. if (skb->protocol == htons(ETH_P_IP)) {
  1760. struct iphdr *iph = ip_hdr(skb);
  1761. /* Do we really need these? */
  1762. iph->tot_len = 0;
  1763. iph->check = 0;
  1764. tcp_hdr(skb)->check =
  1765. ~csum_tcpudp_magic(iph->saddr, iph->daddr, 0,
  1766. IPPROTO_TCP, 0);
  1767. BNAD_UPDATE_CTR(bnad, tso4);
  1768. } else {
  1769. struct ipv6hdr *ipv6h = ipv6_hdr(skb);
  1770. BUG_ON(!(skb->protocol == htons(ETH_P_IPV6)));
  1771. ipv6h->payload_len = 0;
  1772. tcp_hdr(skb)->check =
  1773. ~csum_ipv6_magic(&ipv6h->saddr, &ipv6h->daddr, 0,
  1774. IPPROTO_TCP, 0);
  1775. BNAD_UPDATE_CTR(bnad, tso6);
  1776. }
  1777. return 0;
  1778. }
  1779. /*
  1780. * Initialize Q numbers depending on Rx Paths
  1781. * Called with bnad->bna_lock held, because of cfg_flags
  1782. * access.
  1783. */
  1784. static void
  1785. bnad_q_num_init(struct bnad *bnad)
  1786. {
  1787. int rxps;
  1788. rxps = min((uint)num_online_cpus(),
  1789. (uint)(BNAD_MAX_RXS * BNAD_MAX_RXPS_PER_RX));
  1790. if (!(bnad->cfg_flags & BNAD_CF_MSIX))
  1791. rxps = 1; /* INTx */
  1792. bnad->num_rx = 1;
  1793. bnad->num_tx = 1;
  1794. bnad->num_rxp_per_rx = rxps;
  1795. bnad->num_txq_per_tx = BNAD_TXQ_NUM;
  1796. }
  1797. /*
  1798. * Adjusts the Q numbers, given a number of msix vectors
  1799. * Give preference to RSS as opposed to Tx priority Queues,
  1800. * in such a case, just use 1 Tx Q
  1801. * Called with bnad->bna_lock held b'cos of cfg_flags access
  1802. */
  1803. static void
  1804. bnad_q_num_adjust(struct bnad *bnad, int msix_vectors)
  1805. {
  1806. bnad->num_txq_per_tx = 1;
  1807. if ((msix_vectors >= (bnad->num_tx * bnad->num_txq_per_tx) +
  1808. bnad_rxqs_per_cq + BNAD_MAILBOX_MSIX_VECTORS) &&
  1809. (bnad->cfg_flags & BNAD_CF_MSIX)) {
  1810. bnad->num_rxp_per_rx = msix_vectors -
  1811. (bnad->num_tx * bnad->num_txq_per_tx) -
  1812. BNAD_MAILBOX_MSIX_VECTORS;
  1813. } else
  1814. bnad->num_rxp_per_rx = 1;
  1815. }
  1816. /* Enable / disable device */
  1817. static void
  1818. bnad_device_disable(struct bnad *bnad)
  1819. {
  1820. unsigned long flags;
  1821. init_completion(&bnad->bnad_completions.ioc_comp);
  1822. spin_lock_irqsave(&bnad->bna_lock, flags);
  1823. bna_device_disable(&bnad->bna.device, BNA_HARD_CLEANUP);
  1824. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  1825. wait_for_completion(&bnad->bnad_completions.ioc_comp);
  1826. }
  1827. static int
  1828. bnad_device_enable(struct bnad *bnad)
  1829. {
  1830. int err = 0;
  1831. unsigned long flags;
  1832. init_completion(&bnad->bnad_completions.ioc_comp);
  1833. spin_lock_irqsave(&bnad->bna_lock, flags);
  1834. bna_device_enable(&bnad->bna.device);
  1835. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  1836. wait_for_completion(&bnad->bnad_completions.ioc_comp);
  1837. if (bnad->bnad_completions.ioc_comp_status)
  1838. err = bnad->bnad_completions.ioc_comp_status;
  1839. return err;
  1840. }
  1841. /* Free BNA resources */
  1842. static void
  1843. bnad_res_free(struct bnad *bnad)
  1844. {
  1845. int i;
  1846. struct bna_res_info *res_info = &bnad->res_info[0];
  1847. for (i = 0; i < BNA_RES_T_MAX; i++) {
  1848. if (res_info[i].res_type == BNA_RES_T_MEM)
  1849. bnad_mem_free(bnad, &res_info[i].res_u.mem_info);
  1850. else
  1851. bnad_mbox_irq_free(bnad, &res_info[i].res_u.intr_info);
  1852. }
  1853. }
  1854. /* Allocates memory and interrupt resources for BNA */
  1855. static int
  1856. bnad_res_alloc(struct bnad *bnad)
  1857. {
  1858. int i, err;
  1859. struct bna_res_info *res_info = &bnad->res_info[0];
  1860. for (i = 0; i < BNA_RES_T_MAX; i++) {
  1861. if (res_info[i].res_type == BNA_RES_T_MEM)
  1862. err = bnad_mem_alloc(bnad, &res_info[i].res_u.mem_info);
  1863. else
  1864. err = bnad_mbox_irq_alloc(bnad,
  1865. &res_info[i].res_u.intr_info);
  1866. if (err)
  1867. goto err_return;
  1868. }
  1869. return 0;
  1870. err_return:
  1871. bnad_res_free(bnad);
  1872. return err;
  1873. }
  1874. /* Interrupt enable / disable */
  1875. static void
  1876. bnad_enable_msix(struct bnad *bnad)
  1877. {
  1878. int i, ret;
  1879. unsigned long flags;
  1880. spin_lock_irqsave(&bnad->bna_lock, flags);
  1881. if (!(bnad->cfg_flags & BNAD_CF_MSIX)) {
  1882. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  1883. return;
  1884. }
  1885. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  1886. if (bnad->msix_table)
  1887. return;
  1888. bnad->msix_table =
  1889. kcalloc(bnad->msix_num, sizeof(struct msix_entry), GFP_KERNEL);
  1890. if (!bnad->msix_table)
  1891. goto intx_mode;
  1892. for (i = 0; i < bnad->msix_num; i++)
  1893. bnad->msix_table[i].entry = i;
  1894. ret = pci_enable_msix(bnad->pcidev, bnad->msix_table, bnad->msix_num);
  1895. if (ret > 0) {
  1896. /* Not enough MSI-X vectors. */
  1897. spin_lock_irqsave(&bnad->bna_lock, flags);
  1898. /* ret = #of vectors that we got */
  1899. bnad_q_num_adjust(bnad, ret);
  1900. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  1901. bnad->msix_num = (bnad->num_tx * bnad->num_txq_per_tx)
  1902. + (bnad->num_rx
  1903. * bnad->num_rxp_per_rx) +
  1904. BNAD_MAILBOX_MSIX_VECTORS;
  1905. /* Try once more with adjusted numbers */
  1906. /* If this fails, fall back to INTx */
  1907. ret = pci_enable_msix(bnad->pcidev, bnad->msix_table,
  1908. bnad->msix_num);
  1909. if (ret)
  1910. goto intx_mode;
  1911. } else if (ret < 0)
  1912. goto intx_mode;
  1913. return;
  1914. intx_mode:
  1915. kfree(bnad->msix_table);
  1916. bnad->msix_table = NULL;
  1917. bnad->msix_num = 0;
  1918. spin_lock_irqsave(&bnad->bna_lock, flags);
  1919. bnad->cfg_flags &= ~BNAD_CF_MSIX;
  1920. bnad_q_num_init(bnad);
  1921. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  1922. }
  1923. static void
  1924. bnad_disable_msix(struct bnad *bnad)
  1925. {
  1926. u32 cfg_flags;
  1927. unsigned long flags;
  1928. spin_lock_irqsave(&bnad->bna_lock, flags);
  1929. cfg_flags = bnad->cfg_flags;
  1930. if (bnad->cfg_flags & BNAD_CF_MSIX)
  1931. bnad->cfg_flags &= ~BNAD_CF_MSIX;
  1932. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  1933. if (cfg_flags & BNAD_CF_MSIX) {
  1934. pci_disable_msix(bnad->pcidev);
  1935. kfree(bnad->msix_table);
  1936. bnad->msix_table = NULL;
  1937. }
  1938. }
  1939. /* Netdev entry points */
  1940. static int
  1941. bnad_open(struct net_device *netdev)
  1942. {
  1943. int err;
  1944. struct bnad *bnad = netdev_priv(netdev);
  1945. struct bna_pause_config pause_config;
  1946. int mtu;
  1947. unsigned long flags;
  1948. mutex_lock(&bnad->conf_mutex);
  1949. /* Tx */
  1950. err = bnad_setup_tx(bnad, 0);
  1951. if (err)
  1952. goto err_return;
  1953. /* Rx */
  1954. err = bnad_setup_rx(bnad, 0);
  1955. if (err)
  1956. goto cleanup_tx;
  1957. /* Port */
  1958. pause_config.tx_pause = 0;
  1959. pause_config.rx_pause = 0;
  1960. mtu = ETH_HLEN + bnad->netdev->mtu + ETH_FCS_LEN;
  1961. spin_lock_irqsave(&bnad->bna_lock, flags);
  1962. bna_port_mtu_set(&bnad->bna.port, mtu, NULL);
  1963. bna_port_pause_config(&bnad->bna.port, &pause_config, NULL);
  1964. bna_port_enable(&bnad->bna.port);
  1965. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  1966. /* Enable broadcast */
  1967. bnad_enable_default_bcast(bnad);
  1968. /* Restore VLANs, if any */
  1969. bnad_restore_vlans(bnad, 0);
  1970. /* Set the UCAST address */
  1971. spin_lock_irqsave(&bnad->bna_lock, flags);
  1972. bnad_mac_addr_set_locked(bnad, netdev->dev_addr);
  1973. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  1974. /* Start the stats timer */
  1975. bnad_stats_timer_start(bnad);
  1976. mutex_unlock(&bnad->conf_mutex);
  1977. return 0;
  1978. cleanup_tx:
  1979. bnad_cleanup_tx(bnad, 0);
  1980. err_return:
  1981. mutex_unlock(&bnad->conf_mutex);
  1982. return err;
  1983. }
  1984. static int
  1985. bnad_stop(struct net_device *netdev)
  1986. {
  1987. struct bnad *bnad = netdev_priv(netdev);
  1988. unsigned long flags;
  1989. mutex_lock(&bnad->conf_mutex);
  1990. /* Stop the stats timer */
  1991. bnad_stats_timer_stop(bnad);
  1992. init_completion(&bnad->bnad_completions.port_comp);
  1993. spin_lock_irqsave(&bnad->bna_lock, flags);
  1994. bna_port_disable(&bnad->bna.port, BNA_HARD_CLEANUP,
  1995. bnad_cb_port_disabled);
  1996. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  1997. wait_for_completion(&bnad->bnad_completions.port_comp);
  1998. bnad_cleanup_tx(bnad, 0);
  1999. bnad_cleanup_rx(bnad, 0);
  2000. /* Synchronize mailbox IRQ */
  2001. bnad_mbox_irq_sync(bnad);
  2002. mutex_unlock(&bnad->conf_mutex);
  2003. return 0;
  2004. }
  2005. /* TX */
  2006. /*
  2007. * bnad_start_xmit : Netdev entry point for Transmit
  2008. * Called under lock held by net_device
  2009. */
  2010. static netdev_tx_t
  2011. bnad_start_xmit(struct sk_buff *skb, struct net_device *netdev)
  2012. {
  2013. struct bnad *bnad = netdev_priv(netdev);
  2014. u16 txq_prod, vlan_tag = 0;
  2015. u32 unmap_prod, wis, wis_used, wi_range;
  2016. u32 vectors, vect_id, i, acked;
  2017. u32 tx_id;
  2018. int err;
  2019. struct bnad_tx_info *tx_info;
  2020. struct bna_tcb *tcb;
  2021. struct bnad_unmap_q *unmap_q;
  2022. dma_addr_t dma_addr;
  2023. struct bna_txq_entry *txqent;
  2024. bna_txq_wi_ctrl_flag_t flags;
  2025. if (unlikely
  2026. (skb->len <= ETH_HLEN || skb->len > BFI_TX_MAX_DATA_PER_PKT)) {
  2027. dev_kfree_skb(skb);
  2028. return NETDEV_TX_OK;
  2029. }
  2030. tx_id = 0;
  2031. tx_info = &bnad->tx_info[tx_id];
  2032. tcb = tx_info->tcb[tx_id];
  2033. unmap_q = tcb->unmap_q;
  2034. /*
  2035. * Takes care of the Tx that is scheduled between clearing the flag
  2036. * and the netif_stop_queue() call.
  2037. */
  2038. if (unlikely(!test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags))) {
  2039. dev_kfree_skb(skb);
  2040. return NETDEV_TX_OK;
  2041. }
  2042. vectors = 1 + skb_shinfo(skb)->nr_frags;
  2043. if (vectors > BFI_TX_MAX_VECTORS_PER_PKT) {
  2044. dev_kfree_skb(skb);
  2045. return NETDEV_TX_OK;
  2046. }
  2047. wis = BNA_TXQ_WI_NEEDED(vectors); /* 4 vectors per work item */
  2048. acked = 0;
  2049. if (unlikely
  2050. (wis > BNA_QE_FREE_CNT(tcb, tcb->q_depth) ||
  2051. vectors > BNA_QE_FREE_CNT(unmap_q, unmap_q->q_depth))) {
  2052. if ((u16) (*tcb->hw_consumer_index) !=
  2053. tcb->consumer_index &&
  2054. !test_and_set_bit(BNAD_TXQ_FREE_SENT, &tcb->flags)) {
  2055. acked = bnad_free_txbufs(bnad, tcb);
  2056. if (likely(test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags)))
  2057. bna_ib_ack(tcb->i_dbell, acked);
  2058. smp_mb__before_clear_bit();
  2059. clear_bit(BNAD_TXQ_FREE_SENT, &tcb->flags);
  2060. } else {
  2061. netif_stop_queue(netdev);
  2062. BNAD_UPDATE_CTR(bnad, netif_queue_stop);
  2063. }
  2064. smp_mb();
  2065. /*
  2066. * Check again to deal with race condition between
  2067. * netif_stop_queue here, and netif_wake_queue in
  2068. * interrupt handler which is not inside netif tx lock.
  2069. */
  2070. if (likely
  2071. (wis > BNA_QE_FREE_CNT(tcb, tcb->q_depth) ||
  2072. vectors > BNA_QE_FREE_CNT(unmap_q, unmap_q->q_depth))) {
  2073. BNAD_UPDATE_CTR(bnad, netif_queue_stop);
  2074. return NETDEV_TX_BUSY;
  2075. } else {
  2076. netif_wake_queue(netdev);
  2077. BNAD_UPDATE_CTR(bnad, netif_queue_wakeup);
  2078. }
  2079. }
  2080. unmap_prod = unmap_q->producer_index;
  2081. wis_used = 1;
  2082. vect_id = 0;
  2083. flags = 0;
  2084. txq_prod = tcb->producer_index;
  2085. BNA_TXQ_QPGE_PTR_GET(txq_prod, tcb->sw_qpt, txqent, wi_range);
  2086. BUG_ON(!(wi_range <= tcb->q_depth));
  2087. txqent->hdr.wi.reserved = 0;
  2088. txqent->hdr.wi.num_vectors = vectors;
  2089. txqent->hdr.wi.opcode =
  2090. htons((skb_is_gso(skb) ? BNA_TXQ_WI_SEND_LSO :
  2091. BNA_TXQ_WI_SEND));
  2092. if (vlan_tx_tag_present(skb)) {
  2093. vlan_tag = (u16) vlan_tx_tag_get(skb);
  2094. flags |= (BNA_TXQ_WI_CF_INS_PRIO | BNA_TXQ_WI_CF_INS_VLAN);
  2095. }
  2096. if (test_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags)) {
  2097. vlan_tag =
  2098. (tcb->priority & 0x7) << 13 | (vlan_tag & 0x1fff);
  2099. flags |= (BNA_TXQ_WI_CF_INS_PRIO | BNA_TXQ_WI_CF_INS_VLAN);
  2100. }
  2101. txqent->hdr.wi.vlan_tag = htons(vlan_tag);
  2102. if (skb_is_gso(skb)) {
  2103. err = bnad_tso_prepare(bnad, skb);
  2104. if (err) {
  2105. dev_kfree_skb(skb);
  2106. return NETDEV_TX_OK;
  2107. }
  2108. txqent->hdr.wi.lso_mss = htons(skb_is_gso(skb));
  2109. flags |= (BNA_TXQ_WI_CF_IP_CKSUM | BNA_TXQ_WI_CF_TCP_CKSUM);
  2110. txqent->hdr.wi.l4_hdr_size_n_offset =
  2111. htons(BNA_TXQ_WI_L4_HDR_N_OFFSET
  2112. (tcp_hdrlen(skb) >> 2,
  2113. skb_transport_offset(skb)));
  2114. } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
  2115. u8 proto = 0;
  2116. txqent->hdr.wi.lso_mss = 0;
  2117. if (skb->protocol == htons(ETH_P_IP))
  2118. proto = ip_hdr(skb)->protocol;
  2119. else if (skb->protocol == htons(ETH_P_IPV6)) {
  2120. /* nexthdr may not be TCP immediately. */
  2121. proto = ipv6_hdr(skb)->nexthdr;
  2122. }
  2123. if (proto == IPPROTO_TCP) {
  2124. flags |= BNA_TXQ_WI_CF_TCP_CKSUM;
  2125. txqent->hdr.wi.l4_hdr_size_n_offset =
  2126. htons(BNA_TXQ_WI_L4_HDR_N_OFFSET
  2127. (0, skb_transport_offset(skb)));
  2128. BNAD_UPDATE_CTR(bnad, tcpcsum_offload);
  2129. BUG_ON(!(skb_headlen(skb) >=
  2130. skb_transport_offset(skb) + tcp_hdrlen(skb)));
  2131. } else if (proto == IPPROTO_UDP) {
  2132. flags |= BNA_TXQ_WI_CF_UDP_CKSUM;
  2133. txqent->hdr.wi.l4_hdr_size_n_offset =
  2134. htons(BNA_TXQ_WI_L4_HDR_N_OFFSET
  2135. (0, skb_transport_offset(skb)));
  2136. BNAD_UPDATE_CTR(bnad, udpcsum_offload);
  2137. BUG_ON(!(skb_headlen(skb) >=
  2138. skb_transport_offset(skb) +
  2139. sizeof(struct udphdr)));
  2140. } else {
  2141. err = skb_checksum_help(skb);
  2142. BNAD_UPDATE_CTR(bnad, csum_help);
  2143. if (err) {
  2144. dev_kfree_skb(skb);
  2145. BNAD_UPDATE_CTR(bnad, csum_help_err);
  2146. return NETDEV_TX_OK;
  2147. }
  2148. }
  2149. } else {
  2150. txqent->hdr.wi.lso_mss = 0;
  2151. txqent->hdr.wi.l4_hdr_size_n_offset = 0;
  2152. }
  2153. txqent->hdr.wi.flags = htons(flags);
  2154. txqent->hdr.wi.frame_length = htonl(skb->len);
  2155. unmap_q->unmap_array[unmap_prod].skb = skb;
  2156. BUG_ON(!(skb_headlen(skb) <= BFI_TX_MAX_DATA_PER_VECTOR));
  2157. txqent->vector[vect_id].length = htons(skb_headlen(skb));
  2158. dma_addr = pci_map_single(bnad->pcidev, skb->data, skb_headlen(skb),
  2159. PCI_DMA_TODEVICE);
  2160. pci_unmap_addr_set(&unmap_q->unmap_array[unmap_prod], dma_addr,
  2161. dma_addr);
  2162. BNA_SET_DMA_ADDR(dma_addr, &txqent->vector[vect_id].host_addr);
  2163. BNA_QE_INDX_ADD(unmap_prod, 1, unmap_q->q_depth);
  2164. for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
  2165. struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
  2166. u32 size = frag->size;
  2167. if (++vect_id == BFI_TX_MAX_VECTORS_PER_WI) {
  2168. vect_id = 0;
  2169. if (--wi_range)
  2170. txqent++;
  2171. else {
  2172. BNA_QE_INDX_ADD(txq_prod, wis_used,
  2173. tcb->q_depth);
  2174. wis_used = 0;
  2175. BNA_TXQ_QPGE_PTR_GET(txq_prod, tcb->sw_qpt,
  2176. txqent, wi_range);
  2177. BUG_ON(!(wi_range <= tcb->q_depth));
  2178. }
  2179. wis_used++;
  2180. txqent->hdr.wi_ext.opcode = htons(BNA_TXQ_WI_EXTENSION);
  2181. }
  2182. BUG_ON(!(size <= BFI_TX_MAX_DATA_PER_VECTOR));
  2183. txqent->vector[vect_id].length = htons(size);
  2184. dma_addr =
  2185. pci_map_page(bnad->pcidev, frag->page,
  2186. frag->page_offset, size,
  2187. PCI_DMA_TODEVICE);
  2188. pci_unmap_addr_set(&unmap_q->unmap_array[unmap_prod], dma_addr,
  2189. dma_addr);
  2190. BNA_SET_DMA_ADDR(dma_addr, &txqent->vector[vect_id].host_addr);
  2191. BNA_QE_INDX_ADD(unmap_prod, 1, unmap_q->q_depth);
  2192. }
  2193. unmap_q->producer_index = unmap_prod;
  2194. BNA_QE_INDX_ADD(txq_prod, wis_used, tcb->q_depth);
  2195. tcb->producer_index = txq_prod;
  2196. smp_mb();
  2197. if (unlikely(!test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags)))
  2198. return NETDEV_TX_OK;
  2199. bna_txq_prod_indx_doorbell(tcb);
  2200. if ((u16) (*tcb->hw_consumer_index) != tcb->consumer_index)
  2201. tasklet_schedule(&bnad->tx_free_tasklet);
  2202. return NETDEV_TX_OK;
  2203. }
  2204. /*
  2205. * Used spin_lock to synchronize reading of stats structures, which
  2206. * is written by BNA under the same lock.
  2207. */
  2208. static struct rtnl_link_stats64 *
  2209. bnad_get_stats64(struct net_device *netdev, struct rtnl_link_stats64 *stats)
  2210. {
  2211. struct bnad *bnad = netdev_priv(netdev);
  2212. unsigned long flags;
  2213. spin_lock_irqsave(&bnad->bna_lock, flags);
  2214. bnad_netdev_qstats_fill(bnad, stats);
  2215. bnad_netdev_hwstats_fill(bnad, stats);
  2216. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  2217. return stats;
  2218. }
  2219. static void
  2220. bnad_set_rx_mode(struct net_device *netdev)
  2221. {
  2222. struct bnad *bnad = netdev_priv(netdev);
  2223. u32 new_mask, valid_mask;
  2224. unsigned long flags;
  2225. spin_lock_irqsave(&bnad->bna_lock, flags);
  2226. new_mask = valid_mask = 0;
  2227. if (netdev->flags & IFF_PROMISC) {
  2228. if (!(bnad->cfg_flags & BNAD_CF_PROMISC)) {
  2229. new_mask = BNAD_RXMODE_PROMISC_DEFAULT;
  2230. valid_mask = BNAD_RXMODE_PROMISC_DEFAULT;
  2231. bnad->cfg_flags |= BNAD_CF_PROMISC;
  2232. }
  2233. } else {
  2234. if (bnad->cfg_flags & BNAD_CF_PROMISC) {
  2235. new_mask = ~BNAD_RXMODE_PROMISC_DEFAULT;
  2236. valid_mask = BNAD_RXMODE_PROMISC_DEFAULT;
  2237. bnad->cfg_flags &= ~BNAD_CF_PROMISC;
  2238. }
  2239. }
  2240. if (netdev->flags & IFF_ALLMULTI) {
  2241. if (!(bnad->cfg_flags & BNAD_CF_ALLMULTI)) {
  2242. new_mask |= BNA_RXMODE_ALLMULTI;
  2243. valid_mask |= BNA_RXMODE_ALLMULTI;
  2244. bnad->cfg_flags |= BNAD_CF_ALLMULTI;
  2245. }
  2246. } else {
  2247. if (bnad->cfg_flags & BNAD_CF_ALLMULTI) {
  2248. new_mask &= ~BNA_RXMODE_ALLMULTI;
  2249. valid_mask |= BNA_RXMODE_ALLMULTI;
  2250. bnad->cfg_flags &= ~BNAD_CF_ALLMULTI;
  2251. }
  2252. }
  2253. bna_rx_mode_set(bnad->rx_info[0].rx, new_mask, valid_mask, NULL);
  2254. if (!netdev_mc_empty(netdev)) {
  2255. u8 *mcaddr_list;
  2256. int mc_count = netdev_mc_count(netdev);
  2257. /* Index 0 holds the broadcast address */
  2258. mcaddr_list =
  2259. kzalloc((mc_count + 1) * ETH_ALEN,
  2260. GFP_ATOMIC);
  2261. if (!mcaddr_list)
  2262. goto unlock;
  2263. memcpy(&mcaddr_list[0], &bnad_bcast_addr[0], ETH_ALEN);
  2264. /* Copy rest of the MC addresses */
  2265. bnad_netdev_mc_list_get(netdev, mcaddr_list);
  2266. bna_rx_mcast_listset(bnad->rx_info[0].rx, mc_count + 1,
  2267. mcaddr_list, NULL);
  2268. /* Should we enable BNAD_CF_ALLMULTI for err != 0 ? */
  2269. kfree(mcaddr_list);
  2270. }
  2271. unlock:
  2272. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  2273. }
  2274. /*
  2275. * bna_lock is used to sync writes to netdev->addr
  2276. * conf_lock cannot be used since this call may be made
  2277. * in a non-blocking context.
  2278. */
  2279. static int
  2280. bnad_set_mac_address(struct net_device *netdev, void *mac_addr)
  2281. {
  2282. int err;
  2283. struct bnad *bnad = netdev_priv(netdev);
  2284. struct sockaddr *sa = (struct sockaddr *)mac_addr;
  2285. unsigned long flags;
  2286. spin_lock_irqsave(&bnad->bna_lock, flags);
  2287. err = bnad_mac_addr_set_locked(bnad, sa->sa_data);
  2288. if (!err)
  2289. memcpy(netdev->dev_addr, sa->sa_data, netdev->addr_len);
  2290. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  2291. return err;
  2292. }
  2293. static int
  2294. bnad_change_mtu(struct net_device *netdev, int new_mtu)
  2295. {
  2296. int mtu, err = 0;
  2297. unsigned long flags;
  2298. struct bnad *bnad = netdev_priv(netdev);
  2299. if (new_mtu + ETH_HLEN < ETH_ZLEN || new_mtu > BNAD_JUMBO_MTU)
  2300. return -EINVAL;
  2301. mutex_lock(&bnad->conf_mutex);
  2302. netdev->mtu = new_mtu;
  2303. mtu = ETH_HLEN + new_mtu + ETH_FCS_LEN;
  2304. spin_lock_irqsave(&bnad->bna_lock, flags);
  2305. bna_port_mtu_set(&bnad->bna.port, mtu, NULL);
  2306. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  2307. mutex_unlock(&bnad->conf_mutex);
  2308. return err;
  2309. }
  2310. static void
  2311. bnad_vlan_rx_register(struct net_device *netdev,
  2312. struct vlan_group *vlan_grp)
  2313. {
  2314. struct bnad *bnad = netdev_priv(netdev);
  2315. mutex_lock(&bnad->conf_mutex);
  2316. bnad->vlan_grp = vlan_grp;
  2317. mutex_unlock(&bnad->conf_mutex);
  2318. }
  2319. static void
  2320. bnad_vlan_rx_add_vid(struct net_device *netdev,
  2321. unsigned short vid)
  2322. {
  2323. struct bnad *bnad = netdev_priv(netdev);
  2324. unsigned long flags;
  2325. if (!bnad->rx_info[0].rx)
  2326. return;
  2327. mutex_lock(&bnad->conf_mutex);
  2328. spin_lock_irqsave(&bnad->bna_lock, flags);
  2329. bna_rx_vlan_add(bnad->rx_info[0].rx, vid);
  2330. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  2331. mutex_unlock(&bnad->conf_mutex);
  2332. }
  2333. static void
  2334. bnad_vlan_rx_kill_vid(struct net_device *netdev,
  2335. unsigned short vid)
  2336. {
  2337. struct bnad *bnad = netdev_priv(netdev);
  2338. unsigned long flags;
  2339. if (!bnad->rx_info[0].rx)
  2340. return;
  2341. mutex_lock(&bnad->conf_mutex);
  2342. spin_lock_irqsave(&bnad->bna_lock, flags);
  2343. bna_rx_vlan_del(bnad->rx_info[0].rx, vid);
  2344. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  2345. mutex_unlock(&bnad->conf_mutex);
  2346. }
  2347. #ifdef CONFIG_NET_POLL_CONTROLLER
  2348. static void
  2349. bnad_netpoll(struct net_device *netdev)
  2350. {
  2351. struct bnad *bnad = netdev_priv(netdev);
  2352. struct bnad_rx_info *rx_info;
  2353. struct bnad_rx_ctrl *rx_ctrl;
  2354. u32 curr_mask;
  2355. int i, j;
  2356. if (!(bnad->cfg_flags & BNAD_CF_MSIX)) {
  2357. bna_intx_disable(&bnad->bna, curr_mask);
  2358. bnad_isr(bnad->pcidev->irq, netdev);
  2359. bna_intx_enable(&bnad->bna, curr_mask);
  2360. } else {
  2361. for (i = 0; i < bnad->num_rx; i++) {
  2362. rx_info = &bnad->rx_info[i];
  2363. if (!rx_info->rx)
  2364. continue;
  2365. for (j = 0; j < bnad->num_rxp_per_rx; j++) {
  2366. rx_ctrl = &rx_info->rx_ctrl[j];
  2367. if (rx_ctrl->ccb) {
  2368. bnad_disable_rx_irq(bnad,
  2369. rx_ctrl->ccb);
  2370. bnad_netif_rx_schedule_poll(bnad,
  2371. rx_ctrl->ccb);
  2372. }
  2373. }
  2374. }
  2375. }
  2376. }
  2377. #endif
  2378. static const struct net_device_ops bnad_netdev_ops = {
  2379. .ndo_open = bnad_open,
  2380. .ndo_stop = bnad_stop,
  2381. .ndo_start_xmit = bnad_start_xmit,
  2382. .ndo_get_stats64 = bnad_get_stats64,
  2383. .ndo_set_rx_mode = bnad_set_rx_mode,
  2384. .ndo_set_multicast_list = bnad_set_rx_mode,
  2385. .ndo_validate_addr = eth_validate_addr,
  2386. .ndo_set_mac_address = bnad_set_mac_address,
  2387. .ndo_change_mtu = bnad_change_mtu,
  2388. .ndo_vlan_rx_register = bnad_vlan_rx_register,
  2389. .ndo_vlan_rx_add_vid = bnad_vlan_rx_add_vid,
  2390. .ndo_vlan_rx_kill_vid = bnad_vlan_rx_kill_vid,
  2391. #ifdef CONFIG_NET_POLL_CONTROLLER
  2392. .ndo_poll_controller = bnad_netpoll
  2393. #endif
  2394. };
  2395. static void
  2396. bnad_netdev_init(struct bnad *bnad, bool using_dac)
  2397. {
  2398. struct net_device *netdev = bnad->netdev;
  2399. netdev->features |= NETIF_F_IPV6_CSUM;
  2400. netdev->features |= NETIF_F_TSO;
  2401. netdev->features |= NETIF_F_TSO6;
  2402. netdev->features |= NETIF_F_GRO;
  2403. pr_warn("bna: GRO enabled, using kernel stack GRO\n");
  2404. netdev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
  2405. if (using_dac)
  2406. netdev->features |= NETIF_F_HIGHDMA;
  2407. netdev->features |=
  2408. NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX |
  2409. NETIF_F_HW_VLAN_FILTER;
  2410. netdev->vlan_features = netdev->features;
  2411. netdev->mem_start = bnad->mmio_start;
  2412. netdev->mem_end = bnad->mmio_start + bnad->mmio_len - 1;
  2413. netdev->netdev_ops = &bnad_netdev_ops;
  2414. bnad_set_ethtool_ops(netdev);
  2415. }
  2416. /*
  2417. * 1. Initialize the bnad structure
  2418. * 2. Setup netdev pointer in pci_dev
  2419. * 3. Initialze Tx free tasklet
  2420. * 4. Initialize no. of TxQ & CQs & MSIX vectors
  2421. */
  2422. static int
  2423. bnad_init(struct bnad *bnad,
  2424. struct pci_dev *pdev, struct net_device *netdev)
  2425. {
  2426. unsigned long flags;
  2427. SET_NETDEV_DEV(netdev, &pdev->dev);
  2428. pci_set_drvdata(pdev, netdev);
  2429. bnad->netdev = netdev;
  2430. bnad->pcidev = pdev;
  2431. bnad->mmio_start = pci_resource_start(pdev, 0);
  2432. bnad->mmio_len = pci_resource_len(pdev, 0);
  2433. bnad->bar0 = ioremap_nocache(bnad->mmio_start, bnad->mmio_len);
  2434. if (!bnad->bar0) {
  2435. dev_err(&pdev->dev, "ioremap for bar0 failed\n");
  2436. pci_set_drvdata(pdev, NULL);
  2437. return -ENOMEM;
  2438. }
  2439. pr_info("bar0 mapped to %p, len %llu\n", bnad->bar0,
  2440. (unsigned long long) bnad->mmio_len);
  2441. spin_lock_irqsave(&bnad->bna_lock, flags);
  2442. if (!bnad_msix_disable)
  2443. bnad->cfg_flags = BNAD_CF_MSIX;
  2444. bnad->cfg_flags |= BNAD_CF_DIM_ENABLED;
  2445. bnad_q_num_init(bnad);
  2446. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  2447. bnad->msix_num = (bnad->num_tx * bnad->num_txq_per_tx) +
  2448. (bnad->num_rx * bnad->num_rxp_per_rx) +
  2449. BNAD_MAILBOX_MSIX_VECTORS;
  2450. bnad->txq_depth = BNAD_TXQ_DEPTH;
  2451. bnad->rxq_depth = BNAD_RXQ_DEPTH;
  2452. bnad->rx_csum = true;
  2453. bnad->tx_coalescing_timeo = BFI_TX_COALESCING_TIMEO;
  2454. bnad->rx_coalescing_timeo = BFI_RX_COALESCING_TIMEO;
  2455. tasklet_init(&bnad->tx_free_tasklet, bnad_tx_free_tasklet,
  2456. (unsigned long)bnad);
  2457. return 0;
  2458. }
  2459. /*
  2460. * Must be called after bnad_pci_uninit()
  2461. * so that iounmap() and pci_set_drvdata(NULL)
  2462. * happens only after PCI uninitialization.
  2463. */
  2464. static void
  2465. bnad_uninit(struct bnad *bnad)
  2466. {
  2467. if (bnad->bar0)
  2468. iounmap(bnad->bar0);
  2469. pci_set_drvdata(bnad->pcidev, NULL);
  2470. }
  2471. /*
  2472. * Initialize locks
  2473. a) Per device mutes used for serializing configuration
  2474. changes from OS interface
  2475. b) spin lock used to protect bna state machine
  2476. */
  2477. static void
  2478. bnad_lock_init(struct bnad *bnad)
  2479. {
  2480. spin_lock_init(&bnad->bna_lock);
  2481. mutex_init(&bnad->conf_mutex);
  2482. }
  2483. static void
  2484. bnad_lock_uninit(struct bnad *bnad)
  2485. {
  2486. mutex_destroy(&bnad->conf_mutex);
  2487. }
  2488. /* PCI Initialization */
  2489. static int
  2490. bnad_pci_init(struct bnad *bnad,
  2491. struct pci_dev *pdev, bool *using_dac)
  2492. {
  2493. int err;
  2494. err = pci_enable_device(pdev);
  2495. if (err)
  2496. return err;
  2497. err = pci_request_regions(pdev, BNAD_NAME);
  2498. if (err)
  2499. goto disable_device;
  2500. if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
  2501. !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
  2502. *using_dac = 1;
  2503. } else {
  2504. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  2505. if (err) {
  2506. err = pci_set_consistent_dma_mask(pdev,
  2507. DMA_BIT_MASK(32));
  2508. if (err)
  2509. goto release_regions;
  2510. }
  2511. *using_dac = 0;
  2512. }
  2513. pci_set_master(pdev);
  2514. return 0;
  2515. release_regions:
  2516. pci_release_regions(pdev);
  2517. disable_device:
  2518. pci_disable_device(pdev);
  2519. return err;
  2520. }
  2521. static void
  2522. bnad_pci_uninit(struct pci_dev *pdev)
  2523. {
  2524. pci_release_regions(pdev);
  2525. pci_disable_device(pdev);
  2526. }
  2527. static int __devinit
  2528. bnad_pci_probe(struct pci_dev *pdev,
  2529. const struct pci_device_id *pcidev_id)
  2530. {
  2531. bool using_dac = false;
  2532. int err;
  2533. struct bnad *bnad;
  2534. struct bna *bna;
  2535. struct net_device *netdev;
  2536. struct bfa_pcidev pcidev_info;
  2537. unsigned long flags;
  2538. pr_info("bnad_pci_probe : (0x%p, 0x%p) PCI Func : (%d)\n",
  2539. pdev, pcidev_id, PCI_FUNC(pdev->devfn));
  2540. mutex_lock(&bnad_fwimg_mutex);
  2541. if (!cna_get_firmware_buf(pdev)) {
  2542. mutex_unlock(&bnad_fwimg_mutex);
  2543. pr_warn("Failed to load Firmware Image!\n");
  2544. return -ENODEV;
  2545. }
  2546. mutex_unlock(&bnad_fwimg_mutex);
  2547. /*
  2548. * Allocates sizeof(struct net_device + struct bnad)
  2549. * bnad = netdev->priv
  2550. */
  2551. netdev = alloc_etherdev(sizeof(struct bnad));
  2552. if (!netdev) {
  2553. dev_err(&pdev->dev, "alloc_etherdev failed\n");
  2554. err = -ENOMEM;
  2555. return err;
  2556. }
  2557. bnad = netdev_priv(netdev);
  2558. /*
  2559. * PCI initialization
  2560. * Output : using_dac = 1 for 64 bit DMA
  2561. * = 0 for 32 bit DMA
  2562. */
  2563. err = bnad_pci_init(bnad, pdev, &using_dac);
  2564. if (err)
  2565. goto free_netdev;
  2566. bnad_lock_init(bnad);
  2567. /*
  2568. * Initialize bnad structure
  2569. * Setup relation between pci_dev & netdev
  2570. * Init Tx free tasklet
  2571. */
  2572. err = bnad_init(bnad, pdev, netdev);
  2573. if (err)
  2574. goto pci_uninit;
  2575. /* Initialize netdev structure, set up ethtool ops */
  2576. bnad_netdev_init(bnad, using_dac);
  2577. /* Set link to down state */
  2578. netif_carrier_off(netdev);
  2579. bnad_enable_msix(bnad);
  2580. /* Get resource requirement form bna */
  2581. bna_res_req(&bnad->res_info[0]);
  2582. /* Allocate resources from bna */
  2583. err = bnad_res_alloc(bnad);
  2584. if (err)
  2585. goto free_netdev;
  2586. bna = &bnad->bna;
  2587. /* Setup pcidev_info for bna_init() */
  2588. pcidev_info.pci_slot = PCI_SLOT(bnad->pcidev->devfn);
  2589. pcidev_info.pci_func = PCI_FUNC(bnad->pcidev->devfn);
  2590. pcidev_info.device_id = bnad->pcidev->device;
  2591. pcidev_info.pci_bar_kva = bnad->bar0;
  2592. mutex_lock(&bnad->conf_mutex);
  2593. spin_lock_irqsave(&bnad->bna_lock, flags);
  2594. bna_init(bna, bnad, &pcidev_info, &bnad->res_info[0]);
  2595. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  2596. bnad->stats.bna_stats = &bna->stats;
  2597. /* Set up timers */
  2598. setup_timer(&bnad->bna.device.ioc.ioc_timer, bnad_ioc_timeout,
  2599. ((unsigned long)bnad));
  2600. setup_timer(&bnad->bna.device.ioc.hb_timer, bnad_ioc_hb_check,
  2601. ((unsigned long)bnad));
  2602. setup_timer(&bnad->bna.device.ioc.sem_timer, bnad_ioc_sem_timeout,
  2603. ((unsigned long)bnad));
  2604. /* Now start the timer before calling IOC */
  2605. mod_timer(&bnad->bna.device.ioc.ioc_timer,
  2606. jiffies + msecs_to_jiffies(BNA_IOC_TIMER_FREQ));
  2607. /*
  2608. * Start the chip
  2609. * Don't care even if err != 0, bna state machine will
  2610. * deal with it
  2611. */
  2612. err = bnad_device_enable(bnad);
  2613. /* Get the burnt-in mac */
  2614. spin_lock_irqsave(&bnad->bna_lock, flags);
  2615. bna_port_mac_get(&bna->port, &bnad->perm_addr);
  2616. bnad_set_netdev_perm_addr(bnad);
  2617. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  2618. mutex_unlock(&bnad->conf_mutex);
  2619. /* Finally, reguister with net_device layer */
  2620. err = register_netdev(netdev);
  2621. if (err) {
  2622. pr_err("BNA : Registering with netdev failed\n");
  2623. goto disable_device;
  2624. }
  2625. return 0;
  2626. disable_device:
  2627. mutex_lock(&bnad->conf_mutex);
  2628. bnad_device_disable(bnad);
  2629. del_timer_sync(&bnad->bna.device.ioc.ioc_timer);
  2630. del_timer_sync(&bnad->bna.device.ioc.sem_timer);
  2631. del_timer_sync(&bnad->bna.device.ioc.hb_timer);
  2632. spin_lock_irqsave(&bnad->bna_lock, flags);
  2633. bna_uninit(bna);
  2634. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  2635. mutex_unlock(&bnad->conf_mutex);
  2636. bnad_res_free(bnad);
  2637. bnad_disable_msix(bnad);
  2638. pci_uninit:
  2639. bnad_pci_uninit(pdev);
  2640. bnad_lock_uninit(bnad);
  2641. bnad_uninit(bnad);
  2642. free_netdev:
  2643. free_netdev(netdev);
  2644. return err;
  2645. }
  2646. static void __devexit
  2647. bnad_pci_remove(struct pci_dev *pdev)
  2648. {
  2649. struct net_device *netdev = pci_get_drvdata(pdev);
  2650. struct bnad *bnad;
  2651. struct bna *bna;
  2652. unsigned long flags;
  2653. if (!netdev)
  2654. return;
  2655. pr_info("%s bnad_pci_remove\n", netdev->name);
  2656. bnad = netdev_priv(netdev);
  2657. bna = &bnad->bna;
  2658. unregister_netdev(netdev);
  2659. mutex_lock(&bnad->conf_mutex);
  2660. bnad_device_disable(bnad);
  2661. del_timer_sync(&bnad->bna.device.ioc.ioc_timer);
  2662. del_timer_sync(&bnad->bna.device.ioc.sem_timer);
  2663. del_timer_sync(&bnad->bna.device.ioc.hb_timer);
  2664. spin_lock_irqsave(&bnad->bna_lock, flags);
  2665. bna_uninit(bna);
  2666. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  2667. mutex_unlock(&bnad->conf_mutex);
  2668. bnad_res_free(bnad);
  2669. bnad_disable_msix(bnad);
  2670. bnad_pci_uninit(pdev);
  2671. bnad_lock_uninit(bnad);
  2672. bnad_uninit(bnad);
  2673. free_netdev(netdev);
  2674. }
  2675. static const struct pci_device_id bnad_pci_id_table[] = {
  2676. {
  2677. PCI_DEVICE(PCI_VENDOR_ID_BROCADE,
  2678. PCI_DEVICE_ID_BROCADE_CT),
  2679. .class = PCI_CLASS_NETWORK_ETHERNET << 8,
  2680. .class_mask = 0xffff00
  2681. }, {0, }
  2682. };
  2683. MODULE_DEVICE_TABLE(pci, bnad_pci_id_table);
  2684. static struct pci_driver bnad_pci_driver = {
  2685. .name = BNAD_NAME,
  2686. .id_table = bnad_pci_id_table,
  2687. .probe = bnad_pci_probe,
  2688. .remove = __devexit_p(bnad_pci_remove),
  2689. };
  2690. static int __init
  2691. bnad_module_init(void)
  2692. {
  2693. int err;
  2694. pr_info("Brocade 10G Ethernet driver\n");
  2695. bfa_nw_ioc_auto_recover(bnad_ioc_auto_recover);
  2696. err = pci_register_driver(&bnad_pci_driver);
  2697. if (err < 0) {
  2698. pr_err("bna : PCI registration failed in module init "
  2699. "(%d)\n", err);
  2700. return err;
  2701. }
  2702. return 0;
  2703. }
  2704. static void __exit
  2705. bnad_module_exit(void)
  2706. {
  2707. pci_unregister_driver(&bnad_pci_driver);
  2708. if (bfi_fw)
  2709. release_firmware(bfi_fw);
  2710. }
  2711. module_init(bnad_module_init);
  2712. module_exit(bnad_module_exit);
  2713. MODULE_AUTHOR("Brocade");
  2714. MODULE_LICENSE("GPL");
  2715. MODULE_DESCRIPTION("Brocade 10G PCIe Ethernet driver");
  2716. MODULE_VERSION(BNAD_VERSION);
  2717. MODULE_FIRMWARE(CNA_FW_FILE_CT);