mr.c 22 KB

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  1. /*
  2. * Copyright (c) 2013, Mellanox Technologies inc. All rights reserved.
  3. *
  4. * This software is available to you under a choice of one of two
  5. * licenses. You may choose to be licensed under the terms of the GNU
  6. * General Public License (GPL) Version 2, available from the file
  7. * COPYING in the main directory of this source tree, or the
  8. * OpenIB.org BSD license below:
  9. *
  10. * Redistribution and use in source and binary forms, with or
  11. * without modification, are permitted provided that the following
  12. * conditions are met:
  13. *
  14. * - Redistributions of source code must retain the above
  15. * copyright notice, this list of conditions and the following
  16. * disclaimer.
  17. *
  18. * - Redistributions in binary form must reproduce the above
  19. * copyright notice, this list of conditions and the following
  20. * disclaimer in the documentation and/or other materials
  21. * provided with the distribution.
  22. *
  23. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30. * SOFTWARE.
  31. */
  32. #include <linux/kref.h>
  33. #include <linux/random.h>
  34. #include <linux/debugfs.h>
  35. #include <linux/export.h>
  36. #include <rdma/ib_umem.h>
  37. #include "mlx5_ib.h"
  38. enum {
  39. DEF_CACHE_SIZE = 10,
  40. };
  41. enum {
  42. MLX5_UMR_ALIGN = 2048
  43. };
  44. static __be64 *mr_align(__be64 *ptr, int align)
  45. {
  46. unsigned long mask = align - 1;
  47. return (__be64 *)(((unsigned long)ptr + mask) & ~mask);
  48. }
  49. static int order2idx(struct mlx5_ib_dev *dev, int order)
  50. {
  51. struct mlx5_mr_cache *cache = &dev->cache;
  52. if (order < cache->ent[0].order)
  53. return 0;
  54. else
  55. return order - cache->ent[0].order;
  56. }
  57. static int add_keys(struct mlx5_ib_dev *dev, int c, int num)
  58. {
  59. struct mlx5_mr_cache *cache = &dev->cache;
  60. struct mlx5_cache_ent *ent = &cache->ent[c];
  61. struct mlx5_create_mkey_mbox_in *in;
  62. struct mlx5_ib_mr *mr;
  63. int npages = 1 << ent->order;
  64. int err = 0;
  65. int i;
  66. in = kzalloc(sizeof(*in), GFP_KERNEL);
  67. if (!in)
  68. return -ENOMEM;
  69. for (i = 0; i < num; i++) {
  70. mr = kzalloc(sizeof(*mr), GFP_KERNEL);
  71. if (!mr) {
  72. err = -ENOMEM;
  73. goto out;
  74. }
  75. mr->order = ent->order;
  76. mr->umred = 1;
  77. in->seg.status = 1 << 6;
  78. in->seg.xlt_oct_size = cpu_to_be32((npages + 1) / 2);
  79. in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
  80. in->seg.flags = MLX5_ACCESS_MODE_MTT | MLX5_PERM_UMR_EN;
  81. in->seg.log2_page_size = 12;
  82. err = mlx5_core_create_mkey(&dev->mdev, &mr->mmr, in,
  83. sizeof(*in));
  84. if (err) {
  85. mlx5_ib_warn(dev, "create mkey failed %d\n", err);
  86. kfree(mr);
  87. goto out;
  88. }
  89. cache->last_add = jiffies;
  90. spin_lock(&ent->lock);
  91. list_add_tail(&mr->list, &ent->head);
  92. ent->cur++;
  93. ent->size++;
  94. spin_unlock(&ent->lock);
  95. }
  96. out:
  97. kfree(in);
  98. return err;
  99. }
  100. static void remove_keys(struct mlx5_ib_dev *dev, int c, int num)
  101. {
  102. struct mlx5_mr_cache *cache = &dev->cache;
  103. struct mlx5_cache_ent *ent = &cache->ent[c];
  104. struct mlx5_ib_mr *mr;
  105. int err;
  106. int i;
  107. for (i = 0; i < num; i++) {
  108. spin_lock(&ent->lock);
  109. if (list_empty(&ent->head)) {
  110. spin_unlock(&ent->lock);
  111. return;
  112. }
  113. mr = list_first_entry(&ent->head, struct mlx5_ib_mr, list);
  114. list_del(&mr->list);
  115. ent->cur--;
  116. ent->size--;
  117. spin_unlock(&ent->lock);
  118. err = mlx5_core_destroy_mkey(&dev->mdev, &mr->mmr);
  119. if (err)
  120. mlx5_ib_warn(dev, "failed destroy mkey\n");
  121. else
  122. kfree(mr);
  123. }
  124. }
  125. static ssize_t size_write(struct file *filp, const char __user *buf,
  126. size_t count, loff_t *pos)
  127. {
  128. struct mlx5_cache_ent *ent = filp->private_data;
  129. struct mlx5_ib_dev *dev = ent->dev;
  130. char lbuf[20];
  131. u32 var;
  132. int err;
  133. int c;
  134. if (copy_from_user(lbuf, buf, sizeof(lbuf)))
  135. return -EFAULT;
  136. c = order2idx(dev, ent->order);
  137. lbuf[sizeof(lbuf) - 1] = 0;
  138. if (sscanf(lbuf, "%u", &var) != 1)
  139. return -EINVAL;
  140. if (var < ent->limit)
  141. return -EINVAL;
  142. if (var > ent->size) {
  143. err = add_keys(dev, c, var - ent->size);
  144. if (err)
  145. return err;
  146. } else if (var < ent->size) {
  147. remove_keys(dev, c, ent->size - var);
  148. }
  149. return count;
  150. }
  151. static ssize_t size_read(struct file *filp, char __user *buf, size_t count,
  152. loff_t *pos)
  153. {
  154. struct mlx5_cache_ent *ent = filp->private_data;
  155. char lbuf[20];
  156. int err;
  157. if (*pos)
  158. return 0;
  159. err = snprintf(lbuf, sizeof(lbuf), "%d\n", ent->size);
  160. if (err < 0)
  161. return err;
  162. if (copy_to_user(buf, lbuf, err))
  163. return -EFAULT;
  164. *pos += err;
  165. return err;
  166. }
  167. static const struct file_operations size_fops = {
  168. .owner = THIS_MODULE,
  169. .open = simple_open,
  170. .write = size_write,
  171. .read = size_read,
  172. };
  173. static ssize_t limit_write(struct file *filp, const char __user *buf,
  174. size_t count, loff_t *pos)
  175. {
  176. struct mlx5_cache_ent *ent = filp->private_data;
  177. struct mlx5_ib_dev *dev = ent->dev;
  178. char lbuf[20];
  179. u32 var;
  180. int err;
  181. int c;
  182. if (copy_from_user(lbuf, buf, sizeof(lbuf)))
  183. return -EFAULT;
  184. c = order2idx(dev, ent->order);
  185. lbuf[sizeof(lbuf) - 1] = 0;
  186. if (sscanf(lbuf, "%u", &var) != 1)
  187. return -EINVAL;
  188. if (var > ent->size)
  189. return -EINVAL;
  190. ent->limit = var;
  191. if (ent->cur < ent->limit) {
  192. err = add_keys(dev, c, 2 * ent->limit - ent->cur);
  193. if (err)
  194. return err;
  195. }
  196. return count;
  197. }
  198. static ssize_t limit_read(struct file *filp, char __user *buf, size_t count,
  199. loff_t *pos)
  200. {
  201. struct mlx5_cache_ent *ent = filp->private_data;
  202. char lbuf[20];
  203. int err;
  204. if (*pos)
  205. return 0;
  206. err = snprintf(lbuf, sizeof(lbuf), "%d\n", ent->limit);
  207. if (err < 0)
  208. return err;
  209. if (copy_to_user(buf, lbuf, err))
  210. return -EFAULT;
  211. *pos += err;
  212. return err;
  213. }
  214. static const struct file_operations limit_fops = {
  215. .owner = THIS_MODULE,
  216. .open = simple_open,
  217. .write = limit_write,
  218. .read = limit_read,
  219. };
  220. static int someone_adding(struct mlx5_mr_cache *cache)
  221. {
  222. int i;
  223. for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) {
  224. if (cache->ent[i].cur < cache->ent[i].limit)
  225. return 1;
  226. }
  227. return 0;
  228. }
  229. static void __cache_work_func(struct mlx5_cache_ent *ent)
  230. {
  231. struct mlx5_ib_dev *dev = ent->dev;
  232. struct mlx5_mr_cache *cache = &dev->cache;
  233. int i = order2idx(dev, ent->order);
  234. if (cache->stopped)
  235. return;
  236. ent = &dev->cache.ent[i];
  237. if (ent->cur < 2 * ent->limit) {
  238. add_keys(dev, i, 1);
  239. if (ent->cur < 2 * ent->limit)
  240. queue_work(cache->wq, &ent->work);
  241. } else if (ent->cur > 2 * ent->limit) {
  242. if (!someone_adding(cache) &&
  243. time_after(jiffies, cache->last_add + 60 * HZ)) {
  244. remove_keys(dev, i, 1);
  245. if (ent->cur > ent->limit)
  246. queue_work(cache->wq, &ent->work);
  247. } else {
  248. queue_delayed_work(cache->wq, &ent->dwork, 60 * HZ);
  249. }
  250. }
  251. }
  252. static void delayed_cache_work_func(struct work_struct *work)
  253. {
  254. struct mlx5_cache_ent *ent;
  255. ent = container_of(work, struct mlx5_cache_ent, dwork.work);
  256. __cache_work_func(ent);
  257. }
  258. static void cache_work_func(struct work_struct *work)
  259. {
  260. struct mlx5_cache_ent *ent;
  261. ent = container_of(work, struct mlx5_cache_ent, work);
  262. __cache_work_func(ent);
  263. }
  264. static struct mlx5_ib_mr *alloc_cached_mr(struct mlx5_ib_dev *dev, int order)
  265. {
  266. struct mlx5_mr_cache *cache = &dev->cache;
  267. struct mlx5_ib_mr *mr = NULL;
  268. struct mlx5_cache_ent *ent;
  269. int c;
  270. int i;
  271. c = order2idx(dev, order);
  272. if (c < 0 || c >= MAX_MR_CACHE_ENTRIES) {
  273. mlx5_ib_warn(dev, "order %d, cache index %d\n", order, c);
  274. return NULL;
  275. }
  276. for (i = c; i < MAX_MR_CACHE_ENTRIES; i++) {
  277. ent = &cache->ent[i];
  278. mlx5_ib_dbg(dev, "order %d, cache index %d\n", ent->order, i);
  279. spin_lock(&ent->lock);
  280. if (!list_empty(&ent->head)) {
  281. mr = list_first_entry(&ent->head, struct mlx5_ib_mr,
  282. list);
  283. list_del(&mr->list);
  284. ent->cur--;
  285. spin_unlock(&ent->lock);
  286. if (ent->cur < ent->limit)
  287. queue_work(cache->wq, &ent->work);
  288. break;
  289. }
  290. spin_unlock(&ent->lock);
  291. queue_work(cache->wq, &ent->work);
  292. if (mr)
  293. break;
  294. }
  295. if (!mr)
  296. cache->ent[c].miss++;
  297. return mr;
  298. }
  299. static void free_cached_mr(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr)
  300. {
  301. struct mlx5_mr_cache *cache = &dev->cache;
  302. struct mlx5_cache_ent *ent;
  303. int shrink = 0;
  304. int c;
  305. c = order2idx(dev, mr->order);
  306. if (c < 0 || c >= MAX_MR_CACHE_ENTRIES) {
  307. mlx5_ib_warn(dev, "order %d, cache index %d\n", mr->order, c);
  308. return;
  309. }
  310. ent = &cache->ent[c];
  311. spin_lock(&ent->lock);
  312. list_add_tail(&mr->list, &ent->head);
  313. ent->cur++;
  314. if (ent->cur > 2 * ent->limit)
  315. shrink = 1;
  316. spin_unlock(&ent->lock);
  317. if (shrink)
  318. queue_work(cache->wq, &ent->work);
  319. }
  320. static void clean_keys(struct mlx5_ib_dev *dev, int c)
  321. {
  322. struct mlx5_mr_cache *cache = &dev->cache;
  323. struct mlx5_cache_ent *ent = &cache->ent[c];
  324. struct mlx5_ib_mr *mr;
  325. int err;
  326. cancel_delayed_work(&ent->dwork);
  327. while (1) {
  328. spin_lock(&ent->lock);
  329. if (list_empty(&ent->head)) {
  330. spin_unlock(&ent->lock);
  331. return;
  332. }
  333. mr = list_first_entry(&ent->head, struct mlx5_ib_mr, list);
  334. list_del(&mr->list);
  335. ent->cur--;
  336. ent->size--;
  337. spin_unlock(&ent->lock);
  338. err = mlx5_core_destroy_mkey(&dev->mdev, &mr->mmr);
  339. if (err)
  340. mlx5_ib_warn(dev, "failed destroy mkey\n");
  341. else
  342. kfree(mr);
  343. }
  344. }
  345. static int mlx5_mr_cache_debugfs_init(struct mlx5_ib_dev *dev)
  346. {
  347. struct mlx5_mr_cache *cache = &dev->cache;
  348. struct mlx5_cache_ent *ent;
  349. int i;
  350. if (!mlx5_debugfs_root)
  351. return 0;
  352. cache->root = debugfs_create_dir("mr_cache", dev->mdev.priv.dbg_root);
  353. if (!cache->root)
  354. return -ENOMEM;
  355. for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) {
  356. ent = &cache->ent[i];
  357. sprintf(ent->name, "%d", ent->order);
  358. ent->dir = debugfs_create_dir(ent->name, cache->root);
  359. if (!ent->dir)
  360. return -ENOMEM;
  361. ent->fsize = debugfs_create_file("size", 0600, ent->dir, ent,
  362. &size_fops);
  363. if (!ent->fsize)
  364. return -ENOMEM;
  365. ent->flimit = debugfs_create_file("limit", 0600, ent->dir, ent,
  366. &limit_fops);
  367. if (!ent->flimit)
  368. return -ENOMEM;
  369. ent->fcur = debugfs_create_u32("cur", 0400, ent->dir,
  370. &ent->cur);
  371. if (!ent->fcur)
  372. return -ENOMEM;
  373. ent->fmiss = debugfs_create_u32("miss", 0600, ent->dir,
  374. &ent->miss);
  375. if (!ent->fmiss)
  376. return -ENOMEM;
  377. }
  378. return 0;
  379. }
  380. static void mlx5_mr_cache_debugfs_cleanup(struct mlx5_ib_dev *dev)
  381. {
  382. if (!mlx5_debugfs_root)
  383. return;
  384. debugfs_remove_recursive(dev->cache.root);
  385. }
  386. int mlx5_mr_cache_init(struct mlx5_ib_dev *dev)
  387. {
  388. struct mlx5_mr_cache *cache = &dev->cache;
  389. struct mlx5_cache_ent *ent;
  390. int limit;
  391. int size;
  392. int err;
  393. int i;
  394. cache->wq = create_singlethread_workqueue("mkey_cache");
  395. if (!cache->wq) {
  396. mlx5_ib_warn(dev, "failed to create work queue\n");
  397. return -ENOMEM;
  398. }
  399. for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) {
  400. INIT_LIST_HEAD(&cache->ent[i].head);
  401. spin_lock_init(&cache->ent[i].lock);
  402. ent = &cache->ent[i];
  403. INIT_LIST_HEAD(&ent->head);
  404. spin_lock_init(&ent->lock);
  405. ent->order = i + 2;
  406. ent->dev = dev;
  407. if (dev->mdev.profile->mask & MLX5_PROF_MASK_MR_CACHE) {
  408. size = dev->mdev.profile->mr_cache[i].size;
  409. limit = dev->mdev.profile->mr_cache[i].limit;
  410. } else {
  411. size = DEF_CACHE_SIZE;
  412. limit = 0;
  413. }
  414. INIT_WORK(&ent->work, cache_work_func);
  415. INIT_DELAYED_WORK(&ent->dwork, delayed_cache_work_func);
  416. ent->limit = limit;
  417. queue_work(cache->wq, &ent->work);
  418. }
  419. err = mlx5_mr_cache_debugfs_init(dev);
  420. if (err)
  421. mlx5_ib_warn(dev, "cache debugfs failure\n");
  422. return 0;
  423. }
  424. int mlx5_mr_cache_cleanup(struct mlx5_ib_dev *dev)
  425. {
  426. int i;
  427. dev->cache.stopped = 1;
  428. flush_workqueue(dev->cache.wq);
  429. mlx5_mr_cache_debugfs_cleanup(dev);
  430. for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++)
  431. clean_keys(dev, i);
  432. destroy_workqueue(dev->cache.wq);
  433. return 0;
  434. }
  435. struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc)
  436. {
  437. struct mlx5_ib_dev *dev = to_mdev(pd->device);
  438. struct mlx5_core_dev *mdev = &dev->mdev;
  439. struct mlx5_create_mkey_mbox_in *in;
  440. struct mlx5_mkey_seg *seg;
  441. struct mlx5_ib_mr *mr;
  442. int err;
  443. mr = kzalloc(sizeof(*mr), GFP_KERNEL);
  444. if (!mr)
  445. return ERR_PTR(-ENOMEM);
  446. in = kzalloc(sizeof(*in), GFP_KERNEL);
  447. if (!in) {
  448. err = -ENOMEM;
  449. goto err_free;
  450. }
  451. seg = &in->seg;
  452. seg->flags = convert_access(acc) | MLX5_ACCESS_MODE_PA;
  453. seg->flags_pd = cpu_to_be32(to_mpd(pd)->pdn | MLX5_MKEY_LEN64);
  454. seg->qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
  455. seg->start_addr = 0;
  456. err = mlx5_core_create_mkey(mdev, &mr->mmr, in, sizeof(*in));
  457. if (err)
  458. goto err_in;
  459. kfree(in);
  460. mr->ibmr.lkey = mr->mmr.key;
  461. mr->ibmr.rkey = mr->mmr.key;
  462. mr->umem = NULL;
  463. return &mr->ibmr;
  464. err_in:
  465. kfree(in);
  466. err_free:
  467. kfree(mr);
  468. return ERR_PTR(err);
  469. }
  470. static int get_octo_len(u64 addr, u64 len, int page_size)
  471. {
  472. u64 offset;
  473. int npages;
  474. offset = addr & (page_size - 1);
  475. npages = ALIGN(len + offset, page_size) >> ilog2(page_size);
  476. return (npages + 1) / 2;
  477. }
  478. static int use_umr(int order)
  479. {
  480. return order <= 17;
  481. }
  482. static void prep_umr_reg_wqe(struct ib_pd *pd, struct ib_send_wr *wr,
  483. struct ib_sge *sg, u64 dma, int n, u32 key,
  484. int page_shift, u64 virt_addr, u64 len,
  485. int access_flags)
  486. {
  487. struct mlx5_ib_dev *dev = to_mdev(pd->device);
  488. struct ib_mr *mr = dev->umrc.mr;
  489. sg->addr = dma;
  490. sg->length = ALIGN(sizeof(u64) * n, 64);
  491. sg->lkey = mr->lkey;
  492. wr->next = NULL;
  493. wr->send_flags = 0;
  494. wr->sg_list = sg;
  495. if (n)
  496. wr->num_sge = 1;
  497. else
  498. wr->num_sge = 0;
  499. wr->opcode = MLX5_IB_WR_UMR;
  500. wr->wr.fast_reg.page_list_len = n;
  501. wr->wr.fast_reg.page_shift = page_shift;
  502. wr->wr.fast_reg.rkey = key;
  503. wr->wr.fast_reg.iova_start = virt_addr;
  504. wr->wr.fast_reg.length = len;
  505. wr->wr.fast_reg.access_flags = access_flags;
  506. wr->wr.fast_reg.page_list = (struct ib_fast_reg_page_list *)pd;
  507. }
  508. static void prep_umr_unreg_wqe(struct mlx5_ib_dev *dev,
  509. struct ib_send_wr *wr, u32 key)
  510. {
  511. wr->send_flags = MLX5_IB_SEND_UMR_UNREG;
  512. wr->opcode = MLX5_IB_WR_UMR;
  513. wr->wr.fast_reg.rkey = key;
  514. }
  515. void mlx5_umr_cq_handler(struct ib_cq *cq, void *cq_context)
  516. {
  517. struct mlx5_ib_mr *mr;
  518. struct ib_wc wc;
  519. int err;
  520. while (1) {
  521. err = ib_poll_cq(cq, 1, &wc);
  522. if (err < 0) {
  523. pr_warn("poll cq error %d\n", err);
  524. return;
  525. }
  526. if (err == 0)
  527. break;
  528. mr = (struct mlx5_ib_mr *)(unsigned long)wc.wr_id;
  529. mr->status = wc.status;
  530. complete(&mr->done);
  531. }
  532. ib_req_notify_cq(cq, IB_CQ_NEXT_COMP);
  533. }
  534. static struct mlx5_ib_mr *reg_umr(struct ib_pd *pd, struct ib_umem *umem,
  535. u64 virt_addr, u64 len, int npages,
  536. int page_shift, int order, int access_flags)
  537. {
  538. struct mlx5_ib_dev *dev = to_mdev(pd->device);
  539. struct device *ddev = dev->ib_dev.dma_device;
  540. struct umr_common *umrc = &dev->umrc;
  541. struct ib_send_wr wr, *bad;
  542. struct mlx5_ib_mr *mr;
  543. struct ib_sge sg;
  544. int size = sizeof(u64) * npages;
  545. int err;
  546. int i;
  547. for (i = 0; i < 10; i++) {
  548. mr = alloc_cached_mr(dev, order);
  549. if (mr)
  550. break;
  551. err = add_keys(dev, order2idx(dev, order), 1);
  552. if (err) {
  553. mlx5_ib_warn(dev, "add_keys failed\n");
  554. break;
  555. }
  556. }
  557. if (!mr)
  558. return ERR_PTR(-EAGAIN);
  559. mr->pas = kmalloc(size + MLX5_UMR_ALIGN - 1, GFP_KERNEL);
  560. if (!mr->pas) {
  561. err = -ENOMEM;
  562. goto error;
  563. }
  564. mlx5_ib_populate_pas(dev, umem, page_shift,
  565. mr_align(mr->pas, MLX5_UMR_ALIGN), 1);
  566. mr->dma = dma_map_single(ddev, mr_align(mr->pas, MLX5_UMR_ALIGN), size,
  567. DMA_TO_DEVICE);
  568. if (dma_mapping_error(ddev, mr->dma)) {
  569. kfree(mr->pas);
  570. err = -ENOMEM;
  571. goto error;
  572. }
  573. memset(&wr, 0, sizeof(wr));
  574. wr.wr_id = (u64)(unsigned long)mr;
  575. prep_umr_reg_wqe(pd, &wr, &sg, mr->dma, npages, mr->mmr.key, page_shift, virt_addr, len, access_flags);
  576. /* We serialize polls so one process does not kidnap another's
  577. * completion. This is not a problem since wr is completed in
  578. * around 1 usec
  579. */
  580. down(&umrc->sem);
  581. init_completion(&mr->done);
  582. err = ib_post_send(umrc->qp, &wr, &bad);
  583. if (err) {
  584. mlx5_ib_warn(dev, "post send failed, err %d\n", err);
  585. up(&umrc->sem);
  586. goto error;
  587. }
  588. wait_for_completion(&mr->done);
  589. up(&umrc->sem);
  590. dma_unmap_single(ddev, mr->dma, size, DMA_TO_DEVICE);
  591. kfree(mr->pas);
  592. if (mr->status != IB_WC_SUCCESS) {
  593. mlx5_ib_warn(dev, "reg umr failed\n");
  594. err = -EFAULT;
  595. goto error;
  596. }
  597. return mr;
  598. error:
  599. free_cached_mr(dev, mr);
  600. return ERR_PTR(err);
  601. }
  602. static struct mlx5_ib_mr *reg_create(struct ib_pd *pd, u64 virt_addr,
  603. u64 length, struct ib_umem *umem,
  604. int npages, int page_shift,
  605. int access_flags)
  606. {
  607. struct mlx5_ib_dev *dev = to_mdev(pd->device);
  608. struct mlx5_create_mkey_mbox_in *in;
  609. struct mlx5_ib_mr *mr;
  610. int inlen;
  611. int err;
  612. mr = kzalloc(sizeof(*mr), GFP_KERNEL);
  613. if (!mr)
  614. return ERR_PTR(-ENOMEM);
  615. inlen = sizeof(*in) + sizeof(*in->pas) * ((npages + 1) / 2) * 2;
  616. in = mlx5_vzalloc(inlen);
  617. if (!in) {
  618. err = -ENOMEM;
  619. goto err_1;
  620. }
  621. mlx5_ib_populate_pas(dev, umem, page_shift, in->pas, 0);
  622. in->seg.flags = convert_access(access_flags) |
  623. MLX5_ACCESS_MODE_MTT;
  624. in->seg.flags_pd = cpu_to_be32(to_mpd(pd)->pdn);
  625. in->seg.start_addr = cpu_to_be64(virt_addr);
  626. in->seg.len = cpu_to_be64(length);
  627. in->seg.bsfs_octo_size = 0;
  628. in->seg.xlt_oct_size = cpu_to_be32(get_octo_len(virt_addr, length, 1 << page_shift));
  629. in->seg.log2_page_size = page_shift;
  630. in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
  631. in->xlat_oct_act_size = cpu_to_be32(get_octo_len(virt_addr, length, 1 << page_shift));
  632. err = mlx5_core_create_mkey(&dev->mdev, &mr->mmr, in, inlen);
  633. if (err) {
  634. mlx5_ib_warn(dev, "create mkey failed\n");
  635. goto err_2;
  636. }
  637. mr->umem = umem;
  638. mlx5_vfree(in);
  639. mlx5_ib_dbg(dev, "mkey = 0x%x\n", mr->mmr.key);
  640. return mr;
  641. err_2:
  642. mlx5_vfree(in);
  643. err_1:
  644. kfree(mr);
  645. return ERR_PTR(err);
  646. }
  647. struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
  648. u64 virt_addr, int access_flags,
  649. struct ib_udata *udata)
  650. {
  651. struct mlx5_ib_dev *dev = to_mdev(pd->device);
  652. struct mlx5_ib_mr *mr = NULL;
  653. struct ib_umem *umem;
  654. int page_shift;
  655. int npages;
  656. int ncont;
  657. int order;
  658. int err;
  659. mlx5_ib_dbg(dev, "start 0x%llx, virt_addr 0x%llx, length 0x%llx\n",
  660. start, virt_addr, length);
  661. umem = ib_umem_get(pd->uobject->context, start, length, access_flags,
  662. 0);
  663. if (IS_ERR(umem)) {
  664. mlx5_ib_dbg(dev, "umem get failed\n");
  665. return (void *)umem;
  666. }
  667. mlx5_ib_cont_pages(umem, start, &npages, &page_shift, &ncont, &order);
  668. if (!npages) {
  669. mlx5_ib_warn(dev, "avoid zero region\n");
  670. err = -EINVAL;
  671. goto error;
  672. }
  673. mlx5_ib_dbg(dev, "npages %d, ncont %d, order %d, page_shift %d\n",
  674. npages, ncont, order, page_shift);
  675. if (use_umr(order)) {
  676. mr = reg_umr(pd, umem, virt_addr, length, ncont, page_shift,
  677. order, access_flags);
  678. if (PTR_ERR(mr) == -EAGAIN) {
  679. mlx5_ib_dbg(dev, "cache empty for order %d", order);
  680. mr = NULL;
  681. }
  682. }
  683. if (!mr)
  684. mr = reg_create(pd, virt_addr, length, umem, ncont, page_shift,
  685. access_flags);
  686. if (IS_ERR(mr)) {
  687. err = PTR_ERR(mr);
  688. goto error;
  689. }
  690. mlx5_ib_dbg(dev, "mkey 0x%x\n", mr->mmr.key);
  691. mr->umem = umem;
  692. mr->npages = npages;
  693. spin_lock(&dev->mr_lock);
  694. dev->mdev.priv.reg_pages += npages;
  695. spin_unlock(&dev->mr_lock);
  696. mr->ibmr.lkey = mr->mmr.key;
  697. mr->ibmr.rkey = mr->mmr.key;
  698. return &mr->ibmr;
  699. error:
  700. ib_umem_release(umem);
  701. return ERR_PTR(err);
  702. }
  703. static int unreg_umr(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr)
  704. {
  705. struct umr_common *umrc = &dev->umrc;
  706. struct ib_send_wr wr, *bad;
  707. int err;
  708. memset(&wr, 0, sizeof(wr));
  709. wr.wr_id = (u64)(unsigned long)mr;
  710. prep_umr_unreg_wqe(dev, &wr, mr->mmr.key);
  711. down(&umrc->sem);
  712. init_completion(&mr->done);
  713. err = ib_post_send(umrc->qp, &wr, &bad);
  714. if (err) {
  715. up(&umrc->sem);
  716. mlx5_ib_dbg(dev, "err %d\n", err);
  717. goto error;
  718. }
  719. wait_for_completion(&mr->done);
  720. up(&umrc->sem);
  721. if (mr->status != IB_WC_SUCCESS) {
  722. mlx5_ib_warn(dev, "unreg umr failed\n");
  723. err = -EFAULT;
  724. goto error;
  725. }
  726. return 0;
  727. error:
  728. return err;
  729. }
  730. int mlx5_ib_dereg_mr(struct ib_mr *ibmr)
  731. {
  732. struct mlx5_ib_dev *dev = to_mdev(ibmr->device);
  733. struct mlx5_ib_mr *mr = to_mmr(ibmr);
  734. struct ib_umem *umem = mr->umem;
  735. int npages = mr->npages;
  736. int umred = mr->umred;
  737. int err;
  738. if (!umred) {
  739. err = mlx5_core_destroy_mkey(&dev->mdev, &mr->mmr);
  740. if (err) {
  741. mlx5_ib_warn(dev, "failed to destroy mkey 0x%x (%d)\n",
  742. mr->mmr.key, err);
  743. return err;
  744. }
  745. } else {
  746. err = unreg_umr(dev, mr);
  747. if (err) {
  748. mlx5_ib_warn(dev, "failed unregister\n");
  749. return err;
  750. }
  751. free_cached_mr(dev, mr);
  752. }
  753. if (umem) {
  754. ib_umem_release(umem);
  755. spin_lock(&dev->mr_lock);
  756. dev->mdev.priv.reg_pages -= npages;
  757. spin_unlock(&dev->mr_lock);
  758. }
  759. if (!umred)
  760. kfree(mr);
  761. return 0;
  762. }
  763. struct ib_mr *mlx5_ib_alloc_fast_reg_mr(struct ib_pd *pd,
  764. int max_page_list_len)
  765. {
  766. struct mlx5_ib_dev *dev = to_mdev(pd->device);
  767. struct mlx5_create_mkey_mbox_in *in;
  768. struct mlx5_ib_mr *mr;
  769. int err;
  770. mr = kzalloc(sizeof(*mr), GFP_KERNEL);
  771. if (!mr)
  772. return ERR_PTR(-ENOMEM);
  773. in = kzalloc(sizeof(*in), GFP_KERNEL);
  774. if (!in) {
  775. err = -ENOMEM;
  776. goto err_free;
  777. }
  778. in->seg.status = 1 << 6; /* free */
  779. in->seg.xlt_oct_size = cpu_to_be32((max_page_list_len + 1) / 2);
  780. in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
  781. in->seg.flags = MLX5_PERM_UMR_EN | MLX5_ACCESS_MODE_MTT;
  782. in->seg.flags_pd = cpu_to_be32(to_mpd(pd)->pdn);
  783. /*
  784. * TBD not needed - issue 197292 */
  785. in->seg.log2_page_size = PAGE_SHIFT;
  786. err = mlx5_core_create_mkey(&dev->mdev, &mr->mmr, in, sizeof(*in));
  787. kfree(in);
  788. if (err)
  789. goto err_free;
  790. mr->ibmr.lkey = mr->mmr.key;
  791. mr->ibmr.rkey = mr->mmr.key;
  792. mr->umem = NULL;
  793. return &mr->ibmr;
  794. err_free:
  795. kfree(mr);
  796. return ERR_PTR(err);
  797. }
  798. struct ib_fast_reg_page_list *mlx5_ib_alloc_fast_reg_page_list(struct ib_device *ibdev,
  799. int page_list_len)
  800. {
  801. struct mlx5_ib_fast_reg_page_list *mfrpl;
  802. int size = page_list_len * sizeof(u64);
  803. mfrpl = kmalloc(sizeof(*mfrpl), GFP_KERNEL);
  804. if (!mfrpl)
  805. return ERR_PTR(-ENOMEM);
  806. mfrpl->ibfrpl.page_list = kmalloc(size, GFP_KERNEL);
  807. if (!mfrpl->ibfrpl.page_list)
  808. goto err_free;
  809. mfrpl->mapped_page_list = dma_alloc_coherent(ibdev->dma_device,
  810. size, &mfrpl->map,
  811. GFP_KERNEL);
  812. if (!mfrpl->mapped_page_list)
  813. goto err_free;
  814. WARN_ON(mfrpl->map & 0x3f);
  815. return &mfrpl->ibfrpl;
  816. err_free:
  817. kfree(mfrpl->ibfrpl.page_list);
  818. kfree(mfrpl);
  819. return ERR_PTR(-ENOMEM);
  820. }
  821. void mlx5_ib_free_fast_reg_page_list(struct ib_fast_reg_page_list *page_list)
  822. {
  823. struct mlx5_ib_fast_reg_page_list *mfrpl = to_mfrpl(page_list);
  824. struct mlx5_ib_dev *dev = to_mdev(page_list->device);
  825. int size = page_list->max_page_list_len * sizeof(u64);
  826. dma_free_coherent(&dev->mdev.pdev->dev, size, mfrpl->mapped_page_list,
  827. mfrpl->map);
  828. kfree(mfrpl->ibfrpl.page_list);
  829. kfree(mfrpl);
  830. }