cs4231.c 63 KB

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  1. /*
  2. * Driver for CS4231 sound chips found on Sparcs.
  3. * Copyright (C) 2002 David S. Miller <davem@redhat.com>
  4. *
  5. * Based entirely upon drivers/sbus/audio/cs4231.c which is:
  6. * Copyright (C) 1996, 1997, 1998, 1998 Derrick J Brashear (shadow@andrew.cmu.edu)
  7. * and also sound/isa/cs423x/cs4231_lib.c which is:
  8. * Copyright (c) by Jaroslav Kysela <perex@suse.cz>
  9. */
  10. #include <linux/config.h>
  11. #include <linux/module.h>
  12. #include <linux/kernel.h>
  13. #include <linux/slab.h>
  14. #include <linux/delay.h>
  15. #include <linux/init.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/moduleparam.h>
  18. #include <sound/driver.h>
  19. #include <sound/core.h>
  20. #include <sound/pcm.h>
  21. #include <sound/info.h>
  22. #include <sound/control.h>
  23. #include <sound/timer.h>
  24. #include <sound/initval.h>
  25. #include <sound/pcm_params.h>
  26. #include <asm/io.h>
  27. #include <asm/irq.h>
  28. #ifdef CONFIG_SBUS
  29. #define SBUS_SUPPORT
  30. #endif
  31. #ifdef SBUS_SUPPORT
  32. #include <asm/sbus.h>
  33. #endif
  34. #if defined(CONFIG_PCI) && defined(CONFIG_SPARC64)
  35. #define EBUS_SUPPORT
  36. #endif
  37. #ifdef EBUS_SUPPORT
  38. #include <linux/pci.h>
  39. #include <asm/ebus.h>
  40. #endif
  41. static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
  42. static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
  43. static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
  44. module_param_array(index, int, NULL, 0444);
  45. MODULE_PARM_DESC(index, "Index value for Sun CS4231 soundcard.");
  46. module_param_array(id, charp, NULL, 0444);
  47. MODULE_PARM_DESC(id, "ID string for Sun CS4231 soundcard.");
  48. module_param_array(enable, bool, NULL, 0444);
  49. MODULE_PARM_DESC(enable, "Enable Sun CS4231 soundcard.");
  50. MODULE_AUTHOR("Jaroslav Kysela, Derrick J. Brashear and David S. Miller");
  51. MODULE_DESCRIPTION("Sun CS4231");
  52. MODULE_LICENSE("GPL");
  53. MODULE_SUPPORTED_DEVICE("{{Sun,CS4231}}");
  54. typedef struct snd_cs4231 {
  55. spinlock_t lock;
  56. void __iomem *port;
  57. #ifdef EBUS_SUPPORT
  58. struct ebus_dma_info eb2c;
  59. struct ebus_dma_info eb2p;
  60. #endif
  61. u32 flags;
  62. #define CS4231_FLAG_EBUS 0x00000001
  63. #define CS4231_FLAG_PLAYBACK 0x00000002
  64. #define CS4231_FLAG_CAPTURE 0x00000004
  65. snd_card_t *card;
  66. snd_pcm_t *pcm;
  67. snd_pcm_substream_t *playback_substream;
  68. unsigned int p_periods_sent;
  69. snd_pcm_substream_t *capture_substream;
  70. unsigned int c_periods_sent;
  71. snd_timer_t *timer;
  72. unsigned short mode;
  73. #define CS4231_MODE_NONE 0x0000
  74. #define CS4231_MODE_PLAY 0x0001
  75. #define CS4231_MODE_RECORD 0x0002
  76. #define CS4231_MODE_TIMER 0x0004
  77. #define CS4231_MODE_OPEN (CS4231_MODE_PLAY|CS4231_MODE_RECORD|CS4231_MODE_TIMER)
  78. unsigned char image[32]; /* registers image */
  79. int mce_bit;
  80. int calibrate_mute;
  81. struct semaphore mce_mutex;
  82. struct semaphore open_mutex;
  83. union {
  84. #ifdef SBUS_SUPPORT
  85. struct sbus_dev *sdev;
  86. #endif
  87. #ifdef EBUS_SUPPORT
  88. struct pci_dev *pdev;
  89. #endif
  90. } dev_u;
  91. unsigned int irq[2];
  92. unsigned int regs_size;
  93. struct snd_cs4231 *next;
  94. } cs4231_t;
  95. static cs4231_t *cs4231_list;
  96. /* Eventually we can use sound/isa/cs423x/cs4231_lib.c directly, but for
  97. * now.... -DaveM
  98. */
  99. /* IO ports */
  100. #define CS4231P(chip, x) ((chip)->port + c_d_c_CS4231##x)
  101. /* XXX offsets are different than PC ISA chips... */
  102. #define c_d_c_CS4231REGSEL 0x0
  103. #define c_d_c_CS4231REG 0x4
  104. #define c_d_c_CS4231STATUS 0x8
  105. #define c_d_c_CS4231PIO 0xc
  106. /* codec registers */
  107. #define CS4231_LEFT_INPUT 0x00 /* left input control */
  108. #define CS4231_RIGHT_INPUT 0x01 /* right input control */
  109. #define CS4231_AUX1_LEFT_INPUT 0x02 /* left AUX1 input control */
  110. #define CS4231_AUX1_RIGHT_INPUT 0x03 /* right AUX1 input control */
  111. #define CS4231_AUX2_LEFT_INPUT 0x04 /* left AUX2 input control */
  112. #define CS4231_AUX2_RIGHT_INPUT 0x05 /* right AUX2 input control */
  113. #define CS4231_LEFT_OUTPUT 0x06 /* left output control register */
  114. #define CS4231_RIGHT_OUTPUT 0x07 /* right output control register */
  115. #define CS4231_PLAYBK_FORMAT 0x08 /* clock and data format - playback - bits 7-0 MCE */
  116. #define CS4231_IFACE_CTRL 0x09 /* interface control - bits 7-2 MCE */
  117. #define CS4231_PIN_CTRL 0x0a /* pin control */
  118. #define CS4231_TEST_INIT 0x0b /* test and initialization */
  119. #define CS4231_MISC_INFO 0x0c /* miscellaneaous information */
  120. #define CS4231_LOOPBACK 0x0d /* loopback control */
  121. #define CS4231_PLY_UPR_CNT 0x0e /* playback upper base count */
  122. #define CS4231_PLY_LWR_CNT 0x0f /* playback lower base count */
  123. #define CS4231_ALT_FEATURE_1 0x10 /* alternate #1 feature enable */
  124. #define CS4231_ALT_FEATURE_2 0x11 /* alternate #2 feature enable */
  125. #define CS4231_LEFT_LINE_IN 0x12 /* left line input control */
  126. #define CS4231_RIGHT_LINE_IN 0x13 /* right line input control */
  127. #define CS4231_TIMER_LOW 0x14 /* timer low byte */
  128. #define CS4231_TIMER_HIGH 0x15 /* timer high byte */
  129. #define CS4231_LEFT_MIC_INPUT 0x16 /* left MIC input control register (InterWave only) */
  130. #define CS4231_RIGHT_MIC_INPUT 0x17 /* right MIC input control register (InterWave only) */
  131. #define CS4236_EXT_REG 0x17 /* extended register access */
  132. #define CS4231_IRQ_STATUS 0x18 /* irq status register */
  133. #define CS4231_LINE_LEFT_OUTPUT 0x19 /* left line output control register (InterWave only) */
  134. #define CS4231_VERSION 0x19 /* CS4231(A) - version values */
  135. #define CS4231_MONO_CTRL 0x1a /* mono input/output control */
  136. #define CS4231_LINE_RIGHT_OUTPUT 0x1b /* right line output control register (InterWave only) */
  137. #define CS4235_LEFT_MASTER 0x1b /* left master output control */
  138. #define CS4231_REC_FORMAT 0x1c /* clock and data format - record - bits 7-0 MCE */
  139. #define CS4231_PLY_VAR_FREQ 0x1d /* playback variable frequency */
  140. #define CS4235_RIGHT_MASTER 0x1d /* right master output control */
  141. #define CS4231_REC_UPR_CNT 0x1e /* record upper count */
  142. #define CS4231_REC_LWR_CNT 0x1f /* record lower count */
  143. /* definitions for codec register select port - CODECP( REGSEL ) */
  144. #define CS4231_INIT 0x80 /* CODEC is initializing */
  145. #define CS4231_MCE 0x40 /* mode change enable */
  146. #define CS4231_TRD 0x20 /* transfer request disable */
  147. /* definitions for codec status register - CODECP( STATUS ) */
  148. #define CS4231_GLOBALIRQ 0x01 /* IRQ is active */
  149. /* definitions for codec irq status */
  150. #define CS4231_PLAYBACK_IRQ 0x10
  151. #define CS4231_RECORD_IRQ 0x20
  152. #define CS4231_TIMER_IRQ 0x40
  153. #define CS4231_ALL_IRQS 0x70
  154. #define CS4231_REC_UNDERRUN 0x08
  155. #define CS4231_REC_OVERRUN 0x04
  156. #define CS4231_PLY_OVERRUN 0x02
  157. #define CS4231_PLY_UNDERRUN 0x01
  158. /* definitions for CS4231_LEFT_INPUT and CS4231_RIGHT_INPUT registers */
  159. #define CS4231_ENABLE_MIC_GAIN 0x20
  160. #define CS4231_MIXS_LINE 0x00
  161. #define CS4231_MIXS_AUX1 0x40
  162. #define CS4231_MIXS_MIC 0x80
  163. #define CS4231_MIXS_ALL 0xc0
  164. /* definitions for clock and data format register - CS4231_PLAYBK_FORMAT */
  165. #define CS4231_LINEAR_8 0x00 /* 8-bit unsigned data */
  166. #define CS4231_ALAW_8 0x60 /* 8-bit A-law companded */
  167. #define CS4231_ULAW_8 0x20 /* 8-bit U-law companded */
  168. #define CS4231_LINEAR_16 0x40 /* 16-bit twos complement data - little endian */
  169. #define CS4231_LINEAR_16_BIG 0xc0 /* 16-bit twos complement data - big endian */
  170. #define CS4231_ADPCM_16 0xa0 /* 16-bit ADPCM */
  171. #define CS4231_STEREO 0x10 /* stereo mode */
  172. /* bits 3-1 define frequency divisor */
  173. #define CS4231_XTAL1 0x00 /* 24.576 crystal */
  174. #define CS4231_XTAL2 0x01 /* 16.9344 crystal */
  175. /* definitions for interface control register - CS4231_IFACE_CTRL */
  176. #define CS4231_RECORD_PIO 0x80 /* record PIO enable */
  177. #define CS4231_PLAYBACK_PIO 0x40 /* playback PIO enable */
  178. #define CS4231_CALIB_MODE 0x18 /* calibration mode bits */
  179. #define CS4231_AUTOCALIB 0x08 /* auto calibrate */
  180. #define CS4231_SINGLE_DMA 0x04 /* use single DMA channel */
  181. #define CS4231_RECORD_ENABLE 0x02 /* record enable */
  182. #define CS4231_PLAYBACK_ENABLE 0x01 /* playback enable */
  183. /* definitions for pin control register - CS4231_PIN_CTRL */
  184. #define CS4231_IRQ_ENABLE 0x02 /* enable IRQ */
  185. #define CS4231_XCTL1 0x40 /* external control #1 */
  186. #define CS4231_XCTL0 0x80 /* external control #0 */
  187. /* definitions for test and init register - CS4231_TEST_INIT */
  188. #define CS4231_CALIB_IN_PROGRESS 0x20 /* auto calibrate in progress */
  189. #define CS4231_DMA_REQUEST 0x10 /* DMA request in progress */
  190. /* definitions for misc control register - CS4231_MISC_INFO */
  191. #define CS4231_MODE2 0x40 /* MODE 2 */
  192. #define CS4231_IW_MODE3 0x6c /* MODE 3 - InterWave enhanced mode */
  193. #define CS4231_4236_MODE3 0xe0 /* MODE 3 - CS4236+ enhanced mode */
  194. /* definitions for alternate feature 1 register - CS4231_ALT_FEATURE_1 */
  195. #define CS4231_DACZ 0x01 /* zero DAC when underrun */
  196. #define CS4231_TIMER_ENABLE 0x40 /* codec timer enable */
  197. #define CS4231_OLB 0x80 /* output level bit */
  198. /* SBUS DMA register defines. */
  199. #define APCCSR 0x10UL /* APC DMA CSR */
  200. #define APCCVA 0x20UL /* APC Capture DMA Address */
  201. #define APCCC 0x24UL /* APC Capture Count */
  202. #define APCCNVA 0x28UL /* APC Capture DMA Next Address */
  203. #define APCCNC 0x2cUL /* APC Capture Next Count */
  204. #define APCPVA 0x30UL /* APC Play DMA Address */
  205. #define APCPC 0x34UL /* APC Play Count */
  206. #define APCPNVA 0x38UL /* APC Play DMA Next Address */
  207. #define APCPNC 0x3cUL /* APC Play Next Count */
  208. /* APCCSR bits */
  209. #define APC_INT_PENDING 0x800000 /* Interrupt Pending */
  210. #define APC_PLAY_INT 0x400000 /* Playback interrupt */
  211. #define APC_CAPT_INT 0x200000 /* Capture interrupt */
  212. #define APC_GENL_INT 0x100000 /* General interrupt */
  213. #define APC_XINT_ENA 0x80000 /* General ext int. enable */
  214. #define APC_XINT_PLAY 0x40000 /* Playback ext intr */
  215. #define APC_XINT_CAPT 0x20000 /* Capture ext intr */
  216. #define APC_XINT_GENL 0x10000 /* Error ext intr */
  217. #define APC_XINT_EMPT 0x8000 /* Pipe empty interrupt (0 write to pva) */
  218. #define APC_XINT_PEMP 0x4000 /* Play pipe empty (pva and pnva not set) */
  219. #define APC_XINT_PNVA 0x2000 /* Playback NVA dirty */
  220. #define APC_XINT_PENA 0x1000 /* play pipe empty Int enable */
  221. #define APC_XINT_COVF 0x800 /* Cap data dropped on floor */
  222. #define APC_XINT_CNVA 0x400 /* Capture NVA dirty */
  223. #define APC_XINT_CEMP 0x200 /* Capture pipe empty (cva and cnva not set) */
  224. #define APC_XINT_CENA 0x100 /* Cap. pipe empty int enable */
  225. #define APC_PPAUSE 0x80 /* Pause the play DMA */
  226. #define APC_CPAUSE 0x40 /* Pause the capture DMA */
  227. #define APC_CDC_RESET 0x20 /* CODEC RESET */
  228. #define APC_PDMA_READY 0x08 /* Play DMA Go */
  229. #define APC_CDMA_READY 0x04 /* Capture DMA Go */
  230. #define APC_CHIP_RESET 0x01 /* Reset the chip */
  231. /* EBUS DMA register offsets */
  232. #define EBDMA_CSR 0x00UL /* Control/Status */
  233. #define EBDMA_ADDR 0x04UL /* DMA Address */
  234. #define EBDMA_COUNT 0x08UL /* DMA Count */
  235. /*
  236. * Some variables
  237. */
  238. static unsigned char freq_bits[14] = {
  239. /* 5510 */ 0x00 | CS4231_XTAL2,
  240. /* 6620 */ 0x0E | CS4231_XTAL2,
  241. /* 8000 */ 0x00 | CS4231_XTAL1,
  242. /* 9600 */ 0x0E | CS4231_XTAL1,
  243. /* 11025 */ 0x02 | CS4231_XTAL2,
  244. /* 16000 */ 0x02 | CS4231_XTAL1,
  245. /* 18900 */ 0x04 | CS4231_XTAL2,
  246. /* 22050 */ 0x06 | CS4231_XTAL2,
  247. /* 27042 */ 0x04 | CS4231_XTAL1,
  248. /* 32000 */ 0x06 | CS4231_XTAL1,
  249. /* 33075 */ 0x0C | CS4231_XTAL2,
  250. /* 37800 */ 0x08 | CS4231_XTAL2,
  251. /* 44100 */ 0x0A | CS4231_XTAL2,
  252. /* 48000 */ 0x0C | CS4231_XTAL1
  253. };
  254. static unsigned int rates[14] = {
  255. 5510, 6620, 8000, 9600, 11025, 16000, 18900, 22050,
  256. 27042, 32000, 33075, 37800, 44100, 48000
  257. };
  258. static snd_pcm_hw_constraint_list_t hw_constraints_rates = {
  259. .count = 14,
  260. .list = rates,
  261. };
  262. static int snd_cs4231_xrate(snd_pcm_runtime_t *runtime)
  263. {
  264. return snd_pcm_hw_constraint_list(runtime, 0,
  265. SNDRV_PCM_HW_PARAM_RATE,
  266. &hw_constraints_rates);
  267. }
  268. static unsigned char snd_cs4231_original_image[32] =
  269. {
  270. 0x00, /* 00/00 - lic */
  271. 0x00, /* 01/01 - ric */
  272. 0x9f, /* 02/02 - la1ic */
  273. 0x9f, /* 03/03 - ra1ic */
  274. 0x9f, /* 04/04 - la2ic */
  275. 0x9f, /* 05/05 - ra2ic */
  276. 0xbf, /* 06/06 - loc */
  277. 0xbf, /* 07/07 - roc */
  278. 0x20, /* 08/08 - pdfr */
  279. CS4231_AUTOCALIB, /* 09/09 - ic */
  280. 0x00, /* 0a/10 - pc */
  281. 0x00, /* 0b/11 - ti */
  282. CS4231_MODE2, /* 0c/12 - mi */
  283. 0x00, /* 0d/13 - lbc */
  284. 0x00, /* 0e/14 - pbru */
  285. 0x00, /* 0f/15 - pbrl */
  286. 0x80, /* 10/16 - afei */
  287. 0x01, /* 11/17 - afeii */
  288. 0x9f, /* 12/18 - llic */
  289. 0x9f, /* 13/19 - rlic */
  290. 0x00, /* 14/20 - tlb */
  291. 0x00, /* 15/21 - thb */
  292. 0x00, /* 16/22 - la3mic/reserved */
  293. 0x00, /* 17/23 - ra3mic/reserved */
  294. 0x00, /* 18/24 - afs */
  295. 0x00, /* 19/25 - lamoc/version */
  296. 0x00, /* 1a/26 - mioc */
  297. 0x00, /* 1b/27 - ramoc/reserved */
  298. 0x20, /* 1c/28 - cdfr */
  299. 0x00, /* 1d/29 - res4 */
  300. 0x00, /* 1e/30 - cbru */
  301. 0x00, /* 1f/31 - cbrl */
  302. };
  303. static u8 __cs4231_readb(cs4231_t *cp, void __iomem *reg_addr)
  304. {
  305. #ifdef EBUS_SUPPORT
  306. if (cp->flags & CS4231_FLAG_EBUS) {
  307. return readb(reg_addr);
  308. } else {
  309. #endif
  310. #ifdef SBUS_SUPPORT
  311. return sbus_readb(reg_addr);
  312. #endif
  313. #ifdef EBUS_SUPPORT
  314. }
  315. #endif
  316. }
  317. static void __cs4231_writeb(cs4231_t *cp, u8 val, void __iomem *reg_addr)
  318. {
  319. #ifdef EBUS_SUPPORT
  320. if (cp->flags & CS4231_FLAG_EBUS) {
  321. return writeb(val, reg_addr);
  322. } else {
  323. #endif
  324. #ifdef SBUS_SUPPORT
  325. return sbus_writeb(val, reg_addr);
  326. #endif
  327. #ifdef EBUS_SUPPORT
  328. }
  329. #endif
  330. }
  331. /*
  332. * Basic I/O functions
  333. */
  334. static void snd_cs4231_outm(cs4231_t *chip, unsigned char reg,
  335. unsigned char mask, unsigned char value)
  336. {
  337. int timeout;
  338. unsigned char tmp;
  339. for (timeout = 250;
  340. timeout > 0 && (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT);
  341. timeout--)
  342. udelay(100);
  343. #ifdef CONFIG_SND_DEBUG
  344. if (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT)
  345. snd_printk("outm: auto calibration time out - reg = 0x%x, value = 0x%x\n", reg, value);
  346. #endif
  347. if (chip->calibrate_mute) {
  348. chip->image[reg] &= mask;
  349. chip->image[reg] |= value;
  350. } else {
  351. __cs4231_writeb(chip, chip->mce_bit | reg, CS4231P(chip, REGSEL));
  352. mb();
  353. tmp = (chip->image[reg] & mask) | value;
  354. __cs4231_writeb(chip, tmp, CS4231P(chip, REG));
  355. chip->image[reg] = tmp;
  356. mb();
  357. }
  358. }
  359. static void snd_cs4231_dout(cs4231_t *chip, unsigned char reg, unsigned char value)
  360. {
  361. int timeout;
  362. for (timeout = 250;
  363. timeout > 0 && (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT);
  364. timeout--)
  365. udelay(100);
  366. __cs4231_writeb(chip, chip->mce_bit | reg, CS4231P(chip, REGSEL));
  367. __cs4231_writeb(chip, value, CS4231P(chip, REG));
  368. mb();
  369. }
  370. static void snd_cs4231_out(cs4231_t *chip, unsigned char reg, unsigned char value)
  371. {
  372. int timeout;
  373. for (timeout = 250;
  374. timeout > 0 && (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT);
  375. timeout--)
  376. udelay(100);
  377. #ifdef CONFIG_SND_DEBUG
  378. if (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT)
  379. snd_printk("out: auto calibration time out - reg = 0x%x, value = 0x%x\n", reg, value);
  380. #endif
  381. __cs4231_writeb(chip, chip->mce_bit | reg, CS4231P(chip, REGSEL));
  382. __cs4231_writeb(chip, value, CS4231P(chip, REG));
  383. chip->image[reg] = value;
  384. mb();
  385. #if 0
  386. printk("codec out - reg 0x%x = 0x%x\n", chip->mce_bit | reg, value);
  387. #endif
  388. }
  389. static unsigned char snd_cs4231_in(cs4231_t *chip, unsigned char reg)
  390. {
  391. int timeout;
  392. unsigned char ret;
  393. for (timeout = 250;
  394. timeout > 0 && (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT);
  395. timeout--)
  396. udelay(100);
  397. #ifdef CONFIG_SND_DEBUG
  398. if (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT)
  399. snd_printk("in: auto calibration time out - reg = 0x%x\n", reg);
  400. #endif
  401. __cs4231_writeb(chip, chip->mce_bit | reg, CS4231P(chip, REGSEL));
  402. mb();
  403. ret = __cs4231_readb(chip, CS4231P(chip, REG));
  404. #if 0
  405. printk("codec in - reg 0x%x = 0x%x\n", chip->mce_bit | reg, ret);
  406. #endif
  407. return ret;
  408. }
  409. #if 0
  410. static void snd_cs4231_debug(cs4231_t *chip)
  411. {
  412. printk("CS4231 REGS: INDEX = 0x%02x ",
  413. __cs4231_readb(chip, CS4231P(chip, REGSEL)));
  414. printk(" STATUS = 0x%02x\n",
  415. __cs4231_readb(chip, CS4231P(chip, STATUS)));
  416. printk(" 0x00: left input = 0x%02x ", snd_cs4231_in(chip, 0x00));
  417. printk(" 0x10: alt 1 (CFIG 2) = 0x%02x\n", snd_cs4231_in(chip, 0x10));
  418. printk(" 0x01: right input = 0x%02x ", snd_cs4231_in(chip, 0x01));
  419. printk(" 0x11: alt 2 (CFIG 3) = 0x%02x\n", snd_cs4231_in(chip, 0x11));
  420. printk(" 0x02: GF1 left input = 0x%02x ", snd_cs4231_in(chip, 0x02));
  421. printk(" 0x12: left line in = 0x%02x\n", snd_cs4231_in(chip, 0x12));
  422. printk(" 0x03: GF1 right input = 0x%02x ", snd_cs4231_in(chip, 0x03));
  423. printk(" 0x13: right line in = 0x%02x\n", snd_cs4231_in(chip, 0x13));
  424. printk(" 0x04: CD left input = 0x%02x ", snd_cs4231_in(chip, 0x04));
  425. printk(" 0x14: timer low = 0x%02x\n", snd_cs4231_in(chip, 0x14));
  426. printk(" 0x05: CD right input = 0x%02x ", snd_cs4231_in(chip, 0x05));
  427. printk(" 0x15: timer high = 0x%02x\n", snd_cs4231_in(chip, 0x15));
  428. printk(" 0x06: left output = 0x%02x ", snd_cs4231_in(chip, 0x06));
  429. printk(" 0x16: left MIC (PnP) = 0x%02x\n", snd_cs4231_in(chip, 0x16));
  430. printk(" 0x07: right output = 0x%02x ", snd_cs4231_in(chip, 0x07));
  431. printk(" 0x17: right MIC (PnP) = 0x%02x\n", snd_cs4231_in(chip, 0x17));
  432. printk(" 0x08: playback format = 0x%02x ", snd_cs4231_in(chip, 0x08));
  433. printk(" 0x18: IRQ status = 0x%02x\n", snd_cs4231_in(chip, 0x18));
  434. printk(" 0x09: iface (CFIG 1) = 0x%02x ", snd_cs4231_in(chip, 0x09));
  435. printk(" 0x19: left line out = 0x%02x\n", snd_cs4231_in(chip, 0x19));
  436. printk(" 0x0a: pin control = 0x%02x ", snd_cs4231_in(chip, 0x0a));
  437. printk(" 0x1a: mono control = 0x%02x\n", snd_cs4231_in(chip, 0x1a));
  438. printk(" 0x0b: init & status = 0x%02x ", snd_cs4231_in(chip, 0x0b));
  439. printk(" 0x1b: right line out = 0x%02x\n", snd_cs4231_in(chip, 0x1b));
  440. printk(" 0x0c: revision & mode = 0x%02x ", snd_cs4231_in(chip, 0x0c));
  441. printk(" 0x1c: record format = 0x%02x\n", snd_cs4231_in(chip, 0x1c));
  442. printk(" 0x0d: loopback = 0x%02x ", snd_cs4231_in(chip, 0x0d));
  443. printk(" 0x1d: var freq (PnP) = 0x%02x\n", snd_cs4231_in(chip, 0x1d));
  444. printk(" 0x0e: ply upr count = 0x%02x ", snd_cs4231_in(chip, 0x0e));
  445. printk(" 0x1e: rec upr count = 0x%02x\n", snd_cs4231_in(chip, 0x1e));
  446. printk(" 0x0f: ply lwr count = 0x%02x ", snd_cs4231_in(chip, 0x0f));
  447. printk(" 0x1f: rec lwr count = 0x%02x\n", snd_cs4231_in(chip, 0x1f));
  448. }
  449. #endif
  450. /*
  451. * CS4231 detection / MCE routines
  452. */
  453. static void snd_cs4231_busy_wait(cs4231_t *chip)
  454. {
  455. int timeout;
  456. /* huh.. looks like this sequence is proper for CS4231A chip (GUS MAX) */
  457. for (timeout = 5; timeout > 0; timeout--)
  458. __cs4231_readb(chip, CS4231P(chip, REGSEL));
  459. /* end of cleanup sequence */
  460. for (timeout = 250;
  461. timeout > 0 && (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT);
  462. timeout--)
  463. udelay(100);
  464. }
  465. static void snd_cs4231_mce_up(cs4231_t *chip)
  466. {
  467. unsigned long flags;
  468. int timeout;
  469. spin_lock_irqsave(&chip->lock, flags);
  470. for (timeout = 250; timeout > 0 && (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT); timeout--)
  471. udelay(100);
  472. #ifdef CONFIG_SND_DEBUG
  473. if (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT)
  474. snd_printk("mce_up - auto calibration time out (0)\n");
  475. #endif
  476. chip->mce_bit |= CS4231_MCE;
  477. timeout = __cs4231_readb(chip, CS4231P(chip, REGSEL));
  478. if (timeout == 0x80)
  479. snd_printk("mce_up [%p]: serious init problem - codec still busy\n", chip->port);
  480. if (!(timeout & CS4231_MCE))
  481. __cs4231_writeb(chip, chip->mce_bit | (timeout & 0x1f), CS4231P(chip, REGSEL));
  482. spin_unlock_irqrestore(&chip->lock, flags);
  483. }
  484. static void snd_cs4231_mce_down(cs4231_t *chip)
  485. {
  486. unsigned long flags;
  487. int timeout;
  488. spin_lock_irqsave(&chip->lock, flags);
  489. snd_cs4231_busy_wait(chip);
  490. #if 0
  491. printk("(1) timeout = %i\n", timeout);
  492. #endif
  493. #ifdef CONFIG_SND_DEBUG
  494. if (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT)
  495. snd_printk("mce_down [%p] - auto calibration time out (0)\n", CS4231P(chip, REGSEL));
  496. #endif
  497. chip->mce_bit &= ~CS4231_MCE;
  498. timeout = __cs4231_readb(chip, CS4231P(chip, REGSEL));
  499. __cs4231_writeb(chip, chip->mce_bit | (timeout & 0x1f), CS4231P(chip, REGSEL));
  500. if (timeout == 0x80)
  501. snd_printk("mce_down [%p]: serious init problem - codec still busy\n", chip->port);
  502. if ((timeout & CS4231_MCE) == 0) {
  503. spin_unlock_irqrestore(&chip->lock, flags);
  504. return;
  505. }
  506. snd_cs4231_busy_wait(chip);
  507. /* calibration process */
  508. for (timeout = 500; timeout > 0 && (snd_cs4231_in(chip, CS4231_TEST_INIT) & CS4231_CALIB_IN_PROGRESS) == 0; timeout--)
  509. udelay(100);
  510. if ((snd_cs4231_in(chip, CS4231_TEST_INIT) & CS4231_CALIB_IN_PROGRESS) == 0) {
  511. snd_printd("cs4231_mce_down - auto calibration time out (1)\n");
  512. spin_unlock_irqrestore(&chip->lock, flags);
  513. return;
  514. }
  515. #if 0
  516. printk("(2) timeout = %i, jiffies = %li\n", timeout, jiffies);
  517. #endif
  518. /* in 10ms increments, check condition, up to 250ms */
  519. timeout = 25;
  520. while (snd_cs4231_in(chip, CS4231_TEST_INIT) & CS4231_CALIB_IN_PROGRESS) {
  521. spin_unlock_irqrestore(&chip->lock, flags);
  522. if (--timeout < 0) {
  523. snd_printk("mce_down - auto calibration time out (2)\n");
  524. return;
  525. }
  526. msleep(10);
  527. spin_lock_irqsave(&chip->lock, flags);
  528. }
  529. #if 0
  530. printk("(3) jiffies = %li\n", jiffies);
  531. #endif
  532. /* in 10ms increments, check condition, up to 100ms */
  533. timeout = 10;
  534. while (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT) {
  535. spin_unlock_irqrestore(&chip->lock, flags);
  536. if (--timeout < 0) {
  537. snd_printk("mce_down - auto calibration time out (3)\n");
  538. return;
  539. }
  540. msleep(10);
  541. spin_lock_irqsave(&chip->lock, flags);
  542. }
  543. spin_unlock_irqrestore(&chip->lock, flags);
  544. #if 0
  545. printk("(4) jiffies = %li\n", jiffies);
  546. snd_printk("mce_down - exit = 0x%x\n", __cs4231_readb(chip, CS4231P(chip, REGSEL)));
  547. #endif
  548. }
  549. #if 0 /* Unused for now... */
  550. static unsigned int snd_cs4231_get_count(unsigned char format, unsigned int size)
  551. {
  552. switch (format & 0xe0) {
  553. case CS4231_LINEAR_16:
  554. case CS4231_LINEAR_16_BIG:
  555. size >>= 1;
  556. break;
  557. case CS4231_ADPCM_16:
  558. return size >> 2;
  559. }
  560. if (format & CS4231_STEREO)
  561. size >>= 1;
  562. return size;
  563. }
  564. #endif
  565. #ifdef EBUS_SUPPORT
  566. static void snd_cs4231_ebus_advance_dma(struct ebus_dma_info *p, snd_pcm_substream_t *substream, unsigned int *periods_sent)
  567. {
  568. snd_pcm_runtime_t *runtime = substream->runtime;
  569. while (1) {
  570. unsigned int dma_size = snd_pcm_lib_period_bytes(substream);
  571. unsigned int offset = dma_size * (*periods_sent);
  572. if (dma_size >= (1 << 24))
  573. BUG();
  574. if (ebus_dma_request(p, runtime->dma_addr + offset, dma_size))
  575. return;
  576. #if 0
  577. printk("ebus_advance: Sent period %u (size[%x] offset[%x])\n",
  578. (*periods_sent), dma_size, offset);
  579. #endif
  580. (*periods_sent) = ((*periods_sent) + 1) % runtime->periods;
  581. }
  582. }
  583. #endif
  584. static void cs4231_dma_trigger(cs4231_t *chip, unsigned int what, int on)
  585. {
  586. #ifdef EBUS_SUPPORT
  587. if (chip->flags & CS4231_FLAG_EBUS) {
  588. if (what & CS4231_PLAYBACK_ENABLE) {
  589. if (on) {
  590. ebus_dma_prepare(&chip->eb2p, 0);
  591. ebus_dma_enable(&chip->eb2p, 1);
  592. snd_cs4231_ebus_advance_dma(&chip->eb2p,
  593. chip->playback_substream,
  594. &chip->p_periods_sent);
  595. } else {
  596. ebus_dma_enable(&chip->eb2p, 0);
  597. }
  598. }
  599. if (what & CS4231_RECORD_ENABLE) {
  600. if (on) {
  601. ebus_dma_prepare(&chip->eb2c, 1);
  602. ebus_dma_enable(&chip->eb2c, 1);
  603. snd_cs4231_ebus_advance_dma(&chip->eb2c,
  604. chip->capture_substream,
  605. &chip->c_periods_sent);
  606. } else {
  607. ebus_dma_enable(&chip->eb2c, 0);
  608. }
  609. }
  610. } else {
  611. #endif
  612. #ifdef SBUS_SUPPORT
  613. #endif
  614. #ifdef EBUS_SUPPORT
  615. }
  616. #endif
  617. }
  618. static int snd_cs4231_trigger(snd_pcm_substream_t *substream, int cmd)
  619. {
  620. cs4231_t *chip = snd_pcm_substream_chip(substream);
  621. int result = 0;
  622. switch (cmd) {
  623. case SNDRV_PCM_TRIGGER_START:
  624. case SNDRV_PCM_TRIGGER_STOP:
  625. {
  626. unsigned int what = 0;
  627. snd_pcm_substream_t *s;
  628. struct list_head *pos;
  629. unsigned long flags;
  630. snd_pcm_group_for_each(pos, substream) {
  631. s = snd_pcm_group_substream_entry(pos);
  632. if (s == chip->playback_substream) {
  633. what |= CS4231_PLAYBACK_ENABLE;
  634. snd_pcm_trigger_done(s, substream);
  635. } else if (s == chip->capture_substream) {
  636. what |= CS4231_RECORD_ENABLE;
  637. snd_pcm_trigger_done(s, substream);
  638. }
  639. }
  640. #if 0
  641. printk("TRIGGER: what[%x] on(%d)\n",
  642. what, (cmd == SNDRV_PCM_TRIGGER_START));
  643. #endif
  644. spin_lock_irqsave(&chip->lock, flags);
  645. if (cmd == SNDRV_PCM_TRIGGER_START) {
  646. cs4231_dma_trigger(chip, what, 1);
  647. chip->image[CS4231_IFACE_CTRL] |= what;
  648. if (what & CS4231_PLAYBACK_ENABLE) {
  649. snd_cs4231_out(chip, CS4231_PLY_LWR_CNT, 0xff);
  650. snd_cs4231_out(chip, CS4231_PLY_UPR_CNT, 0xff);
  651. }
  652. if (what & CS4231_RECORD_ENABLE) {
  653. snd_cs4231_out(chip, CS4231_REC_LWR_CNT, 0xff);
  654. snd_cs4231_out(chip, CS4231_REC_UPR_CNT, 0xff);
  655. }
  656. } else {
  657. cs4231_dma_trigger(chip, what, 0);
  658. chip->image[CS4231_IFACE_CTRL] &= ~what;
  659. }
  660. snd_cs4231_out(chip, CS4231_IFACE_CTRL,
  661. chip->image[CS4231_IFACE_CTRL]);
  662. spin_unlock_irqrestore(&chip->lock, flags);
  663. break;
  664. }
  665. default:
  666. result = -EINVAL;
  667. break;
  668. }
  669. #if 0
  670. snd_cs4231_debug(chip);
  671. #endif
  672. return result;
  673. }
  674. /*
  675. * CODEC I/O
  676. */
  677. static unsigned char snd_cs4231_get_rate(unsigned int rate)
  678. {
  679. int i;
  680. for (i = 0; i < 14; i++)
  681. if (rate == rates[i])
  682. return freq_bits[i];
  683. // snd_BUG();
  684. return freq_bits[13];
  685. }
  686. static unsigned char snd_cs4231_get_format(cs4231_t *chip, int format, int channels)
  687. {
  688. unsigned char rformat;
  689. rformat = CS4231_LINEAR_8;
  690. switch (format) {
  691. case SNDRV_PCM_FORMAT_MU_LAW: rformat = CS4231_ULAW_8; break;
  692. case SNDRV_PCM_FORMAT_A_LAW: rformat = CS4231_ALAW_8; break;
  693. case SNDRV_PCM_FORMAT_S16_LE: rformat = CS4231_LINEAR_16; break;
  694. case SNDRV_PCM_FORMAT_S16_BE: rformat = CS4231_LINEAR_16_BIG; break;
  695. case SNDRV_PCM_FORMAT_IMA_ADPCM: rformat = CS4231_ADPCM_16; break;
  696. }
  697. if (channels > 1)
  698. rformat |= CS4231_STEREO;
  699. #if 0
  700. snd_printk("get_format: 0x%x (mode=0x%x)\n", format, mode);
  701. #endif
  702. return rformat;
  703. }
  704. static void snd_cs4231_calibrate_mute(cs4231_t *chip, int mute)
  705. {
  706. unsigned long flags;
  707. mute = mute ? 1 : 0;
  708. spin_lock_irqsave(&chip->lock, flags);
  709. if (chip->calibrate_mute == mute) {
  710. spin_unlock_irqrestore(&chip->lock, flags);
  711. return;
  712. }
  713. if (!mute) {
  714. snd_cs4231_dout(chip, CS4231_LEFT_INPUT,
  715. chip->image[CS4231_LEFT_INPUT]);
  716. snd_cs4231_dout(chip, CS4231_RIGHT_INPUT,
  717. chip->image[CS4231_RIGHT_INPUT]);
  718. snd_cs4231_dout(chip, CS4231_LOOPBACK,
  719. chip->image[CS4231_LOOPBACK]);
  720. }
  721. snd_cs4231_dout(chip, CS4231_AUX1_LEFT_INPUT,
  722. mute ? 0x80 : chip->image[CS4231_AUX1_LEFT_INPUT]);
  723. snd_cs4231_dout(chip, CS4231_AUX1_RIGHT_INPUT,
  724. mute ? 0x80 : chip->image[CS4231_AUX1_RIGHT_INPUT]);
  725. snd_cs4231_dout(chip, CS4231_AUX2_LEFT_INPUT,
  726. mute ? 0x80 : chip->image[CS4231_AUX2_LEFT_INPUT]);
  727. snd_cs4231_dout(chip, CS4231_AUX2_RIGHT_INPUT,
  728. mute ? 0x80 : chip->image[CS4231_AUX2_RIGHT_INPUT]);
  729. snd_cs4231_dout(chip, CS4231_LEFT_OUTPUT,
  730. mute ? 0x80 : chip->image[CS4231_LEFT_OUTPUT]);
  731. snd_cs4231_dout(chip, CS4231_RIGHT_OUTPUT,
  732. mute ? 0x80 : chip->image[CS4231_RIGHT_OUTPUT]);
  733. snd_cs4231_dout(chip, CS4231_LEFT_LINE_IN,
  734. mute ? 0x80 : chip->image[CS4231_LEFT_LINE_IN]);
  735. snd_cs4231_dout(chip, CS4231_RIGHT_LINE_IN,
  736. mute ? 0x80 : chip->image[CS4231_RIGHT_LINE_IN]);
  737. snd_cs4231_dout(chip, CS4231_MONO_CTRL,
  738. mute ? 0xc0 : chip->image[CS4231_MONO_CTRL]);
  739. chip->calibrate_mute = mute;
  740. spin_unlock_irqrestore(&chip->lock, flags);
  741. }
  742. static void snd_cs4231_playback_format(cs4231_t *chip, snd_pcm_hw_params_t *params,
  743. unsigned char pdfr)
  744. {
  745. unsigned long flags;
  746. down(&chip->mce_mutex);
  747. snd_cs4231_calibrate_mute(chip, 1);
  748. snd_cs4231_mce_up(chip);
  749. spin_lock_irqsave(&chip->lock, flags);
  750. snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT,
  751. (chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE) ?
  752. (pdfr & 0xf0) | (chip->image[CS4231_REC_FORMAT] & 0x0f) :
  753. pdfr);
  754. spin_unlock_irqrestore(&chip->lock, flags);
  755. snd_cs4231_mce_down(chip);
  756. snd_cs4231_calibrate_mute(chip, 0);
  757. up(&chip->mce_mutex);
  758. }
  759. static void snd_cs4231_capture_format(cs4231_t *chip, snd_pcm_hw_params_t *params,
  760. unsigned char cdfr)
  761. {
  762. unsigned long flags;
  763. down(&chip->mce_mutex);
  764. snd_cs4231_calibrate_mute(chip, 1);
  765. snd_cs4231_mce_up(chip);
  766. spin_lock_irqsave(&chip->lock, flags);
  767. if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE)) {
  768. snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT,
  769. ((chip->image[CS4231_PLAYBK_FORMAT]) & 0xf0) |
  770. (cdfr & 0x0f));
  771. spin_unlock_irqrestore(&chip->lock, flags);
  772. snd_cs4231_mce_down(chip);
  773. snd_cs4231_mce_up(chip);
  774. spin_lock_irqsave(&chip->lock, flags);
  775. }
  776. snd_cs4231_out(chip, CS4231_REC_FORMAT, cdfr);
  777. spin_unlock_irqrestore(&chip->lock, flags);
  778. snd_cs4231_mce_down(chip);
  779. snd_cs4231_calibrate_mute(chip, 0);
  780. up(&chip->mce_mutex);
  781. }
  782. /*
  783. * Timer interface
  784. */
  785. static unsigned long snd_cs4231_timer_resolution(snd_timer_t *timer)
  786. {
  787. cs4231_t *chip = snd_timer_chip(timer);
  788. return chip->image[CS4231_PLAYBK_FORMAT] & 1 ? 9969 : 9920;
  789. }
  790. static int snd_cs4231_timer_start(snd_timer_t *timer)
  791. {
  792. unsigned long flags;
  793. unsigned int ticks;
  794. cs4231_t *chip = snd_timer_chip(timer);
  795. spin_lock_irqsave(&chip->lock, flags);
  796. ticks = timer->sticks;
  797. if ((chip->image[CS4231_ALT_FEATURE_1] & CS4231_TIMER_ENABLE) == 0 ||
  798. (unsigned char)(ticks >> 8) != chip->image[CS4231_TIMER_HIGH] ||
  799. (unsigned char)ticks != chip->image[CS4231_TIMER_LOW]) {
  800. snd_cs4231_out(chip, CS4231_TIMER_HIGH,
  801. chip->image[CS4231_TIMER_HIGH] =
  802. (unsigned char) (ticks >> 8));
  803. snd_cs4231_out(chip, CS4231_TIMER_LOW,
  804. chip->image[CS4231_TIMER_LOW] =
  805. (unsigned char) ticks);
  806. snd_cs4231_out(chip, CS4231_ALT_FEATURE_1,
  807. chip->image[CS4231_ALT_FEATURE_1] | CS4231_TIMER_ENABLE);
  808. }
  809. spin_unlock_irqrestore(&chip->lock, flags);
  810. return 0;
  811. }
  812. static int snd_cs4231_timer_stop(snd_timer_t *timer)
  813. {
  814. unsigned long flags;
  815. cs4231_t *chip = snd_timer_chip(timer);
  816. spin_lock_irqsave(&chip->lock, flags);
  817. snd_cs4231_out(chip, CS4231_ALT_FEATURE_1,
  818. chip->image[CS4231_ALT_FEATURE_1] &= ~CS4231_TIMER_ENABLE);
  819. spin_unlock_irqrestore(&chip->lock, flags);
  820. return 0;
  821. }
  822. static void snd_cs4231_init(cs4231_t *chip)
  823. {
  824. unsigned long flags;
  825. snd_cs4231_mce_down(chip);
  826. #ifdef SNDRV_DEBUG_MCE
  827. snd_printk("init: (1)\n");
  828. #endif
  829. snd_cs4231_mce_up(chip);
  830. spin_lock_irqsave(&chip->lock, flags);
  831. chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO |
  832. CS4231_RECORD_ENABLE | CS4231_RECORD_PIO |
  833. CS4231_CALIB_MODE);
  834. chip->image[CS4231_IFACE_CTRL] |= CS4231_AUTOCALIB;
  835. snd_cs4231_out(chip, CS4231_IFACE_CTRL, chip->image[CS4231_IFACE_CTRL]);
  836. spin_unlock_irqrestore(&chip->lock, flags);
  837. snd_cs4231_mce_down(chip);
  838. #ifdef SNDRV_DEBUG_MCE
  839. snd_printk("init: (2)\n");
  840. #endif
  841. snd_cs4231_mce_up(chip);
  842. spin_lock_irqsave(&chip->lock, flags);
  843. snd_cs4231_out(chip, CS4231_ALT_FEATURE_1, chip->image[CS4231_ALT_FEATURE_1]);
  844. spin_unlock_irqrestore(&chip->lock, flags);
  845. snd_cs4231_mce_down(chip);
  846. #ifdef SNDRV_DEBUG_MCE
  847. snd_printk("init: (3) - afei = 0x%x\n", chip->image[CS4231_ALT_FEATURE_1]);
  848. #endif
  849. spin_lock_irqsave(&chip->lock, flags);
  850. snd_cs4231_out(chip, CS4231_ALT_FEATURE_2, chip->image[CS4231_ALT_FEATURE_2]);
  851. spin_unlock_irqrestore(&chip->lock, flags);
  852. snd_cs4231_mce_up(chip);
  853. spin_lock_irqsave(&chip->lock, flags);
  854. snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT, chip->image[CS4231_PLAYBK_FORMAT]);
  855. spin_unlock_irqrestore(&chip->lock, flags);
  856. snd_cs4231_mce_down(chip);
  857. #ifdef SNDRV_DEBUG_MCE
  858. snd_printk("init: (4)\n");
  859. #endif
  860. snd_cs4231_mce_up(chip);
  861. spin_lock_irqsave(&chip->lock, flags);
  862. snd_cs4231_out(chip, CS4231_REC_FORMAT, chip->image[CS4231_REC_FORMAT]);
  863. spin_unlock_irqrestore(&chip->lock, flags);
  864. snd_cs4231_mce_down(chip);
  865. #ifdef SNDRV_DEBUG_MCE
  866. snd_printk("init: (5)\n");
  867. #endif
  868. }
  869. static int snd_cs4231_open(cs4231_t *chip, unsigned int mode)
  870. {
  871. unsigned long flags;
  872. down(&chip->open_mutex);
  873. if ((chip->mode & mode)) {
  874. up(&chip->open_mutex);
  875. return -EAGAIN;
  876. }
  877. if (chip->mode & CS4231_MODE_OPEN) {
  878. chip->mode |= mode;
  879. up(&chip->open_mutex);
  880. return 0;
  881. }
  882. /* ok. now enable and ack CODEC IRQ */
  883. spin_lock_irqsave(&chip->lock, flags);
  884. snd_cs4231_out(chip, CS4231_IRQ_STATUS, CS4231_PLAYBACK_IRQ |
  885. CS4231_RECORD_IRQ |
  886. CS4231_TIMER_IRQ);
  887. snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
  888. __cs4231_writeb(chip, 0, CS4231P(chip, STATUS)); /* clear IRQ */
  889. __cs4231_writeb(chip, 0, CS4231P(chip, STATUS)); /* clear IRQ */
  890. snd_cs4231_out(chip, CS4231_IRQ_STATUS, CS4231_PLAYBACK_IRQ |
  891. CS4231_RECORD_IRQ |
  892. CS4231_TIMER_IRQ);
  893. snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
  894. spin_unlock_irqrestore(&chip->lock, flags);
  895. chip->mode = mode;
  896. up(&chip->open_mutex);
  897. return 0;
  898. }
  899. static void snd_cs4231_close(cs4231_t *chip, unsigned int mode)
  900. {
  901. unsigned long flags;
  902. down(&chip->open_mutex);
  903. chip->mode &= ~mode;
  904. if (chip->mode & CS4231_MODE_OPEN) {
  905. up(&chip->open_mutex);
  906. return;
  907. }
  908. snd_cs4231_calibrate_mute(chip, 1);
  909. /* disable IRQ */
  910. spin_lock_irqsave(&chip->lock, flags);
  911. snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
  912. __cs4231_writeb(chip, 0, CS4231P(chip, STATUS)); /* clear IRQ */
  913. __cs4231_writeb(chip, 0, CS4231P(chip, STATUS)); /* clear IRQ */
  914. /* now disable record & playback */
  915. if (chip->image[CS4231_IFACE_CTRL] &
  916. (CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO |
  917. CS4231_RECORD_ENABLE | CS4231_RECORD_PIO)) {
  918. spin_unlock_irqrestore(&chip->lock, flags);
  919. snd_cs4231_mce_up(chip);
  920. spin_lock_irqsave(&chip->lock, flags);
  921. chip->image[CS4231_IFACE_CTRL] &=
  922. ~(CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO |
  923. CS4231_RECORD_ENABLE | CS4231_RECORD_PIO);
  924. snd_cs4231_out(chip, CS4231_IFACE_CTRL, chip->image[CS4231_IFACE_CTRL]);
  925. spin_unlock_irqrestore(&chip->lock, flags);
  926. snd_cs4231_mce_down(chip);
  927. spin_lock_irqsave(&chip->lock, flags);
  928. }
  929. /* clear IRQ again */
  930. snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
  931. __cs4231_writeb(chip, 0, CS4231P(chip, STATUS)); /* clear IRQ */
  932. __cs4231_writeb(chip, 0, CS4231P(chip, STATUS)); /* clear IRQ */
  933. spin_unlock_irqrestore(&chip->lock, flags);
  934. snd_cs4231_calibrate_mute(chip, 0);
  935. chip->mode = 0;
  936. up(&chip->open_mutex);
  937. }
  938. /*
  939. * timer open/close
  940. */
  941. static int snd_cs4231_timer_open(snd_timer_t *timer)
  942. {
  943. cs4231_t *chip = snd_timer_chip(timer);
  944. snd_cs4231_open(chip, CS4231_MODE_TIMER);
  945. return 0;
  946. }
  947. static int snd_cs4231_timer_close(snd_timer_t * timer)
  948. {
  949. cs4231_t *chip = snd_timer_chip(timer);
  950. snd_cs4231_close(chip, CS4231_MODE_TIMER);
  951. return 0;
  952. }
  953. static struct _snd_timer_hardware snd_cs4231_timer_table =
  954. {
  955. .flags = SNDRV_TIMER_HW_AUTO,
  956. .resolution = 9945,
  957. .ticks = 65535,
  958. .open = snd_cs4231_timer_open,
  959. .close = snd_cs4231_timer_close,
  960. .c_resolution = snd_cs4231_timer_resolution,
  961. .start = snd_cs4231_timer_start,
  962. .stop = snd_cs4231_timer_stop,
  963. };
  964. /*
  965. * ok.. exported functions..
  966. */
  967. static int snd_cs4231_playback_hw_params(snd_pcm_substream_t *substream,
  968. snd_pcm_hw_params_t *hw_params)
  969. {
  970. cs4231_t *chip = snd_pcm_substream_chip(substream);
  971. unsigned char new_pdfr;
  972. int err;
  973. if ((err = snd_pcm_lib_malloc_pages(substream,
  974. params_buffer_bytes(hw_params))) < 0)
  975. return err;
  976. new_pdfr = snd_cs4231_get_format(chip, params_format(hw_params),
  977. params_channels(hw_params)) |
  978. snd_cs4231_get_rate(params_rate(hw_params));
  979. snd_cs4231_playback_format(chip, hw_params, new_pdfr);
  980. return 0;
  981. }
  982. static int snd_cs4231_playback_hw_free(snd_pcm_substream_t *substream)
  983. {
  984. return snd_pcm_lib_free_pages(substream);
  985. }
  986. static int snd_cs4231_playback_prepare(snd_pcm_substream_t *substream)
  987. {
  988. cs4231_t *chip = snd_pcm_substream_chip(substream);
  989. unsigned long flags;
  990. spin_lock_irqsave(&chip->lock, flags);
  991. chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE |
  992. CS4231_PLAYBACK_PIO);
  993. spin_unlock_irqrestore(&chip->lock, flags);
  994. return 0;
  995. }
  996. static int snd_cs4231_capture_hw_params(snd_pcm_substream_t *substream,
  997. snd_pcm_hw_params_t *hw_params)
  998. {
  999. cs4231_t *chip = snd_pcm_substream_chip(substream);
  1000. unsigned char new_cdfr;
  1001. int err;
  1002. if ((err = snd_pcm_lib_malloc_pages(substream,
  1003. params_buffer_bytes(hw_params))) < 0)
  1004. return err;
  1005. new_cdfr = snd_cs4231_get_format(chip, params_format(hw_params),
  1006. params_channels(hw_params)) |
  1007. snd_cs4231_get_rate(params_rate(hw_params));
  1008. snd_cs4231_capture_format(chip, hw_params, new_cdfr);
  1009. return 0;
  1010. }
  1011. static int snd_cs4231_capture_hw_free(snd_pcm_substream_t *substream)
  1012. {
  1013. return snd_pcm_lib_free_pages(substream);
  1014. }
  1015. static int snd_cs4231_capture_prepare(snd_pcm_substream_t *substream)
  1016. {
  1017. cs4231_t *chip = snd_pcm_substream_chip(substream);
  1018. unsigned long flags;
  1019. spin_lock_irqsave(&chip->lock, flags);
  1020. chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_RECORD_ENABLE |
  1021. CS4231_RECORD_PIO);
  1022. spin_unlock_irqrestore(&chip->lock, flags);
  1023. return 0;
  1024. }
  1025. static void snd_cs4231_overrange(cs4231_t *chip)
  1026. {
  1027. unsigned long flags;
  1028. unsigned char res;
  1029. spin_lock_irqsave(&chip->lock, flags);
  1030. res = snd_cs4231_in(chip, CS4231_TEST_INIT);
  1031. spin_unlock_irqrestore(&chip->lock, flags);
  1032. if (res & (0x08 | 0x02)) /* detect overrange only above 0dB; may be user selectable? */
  1033. chip->capture_substream->runtime->overrange++;
  1034. }
  1035. static void snd_cs4231_generic_interrupt(cs4231_t *chip)
  1036. {
  1037. unsigned long flags;
  1038. unsigned char status;
  1039. status = snd_cs4231_in(chip, CS4231_IRQ_STATUS);
  1040. if (!status)
  1041. return;
  1042. if (status & CS4231_TIMER_IRQ) {
  1043. if (chip->timer)
  1044. snd_timer_interrupt(chip->timer, chip->timer->sticks);
  1045. }
  1046. if (status & CS4231_PLAYBACK_IRQ)
  1047. snd_pcm_period_elapsed(chip->playback_substream);
  1048. if (status & CS4231_RECORD_IRQ) {
  1049. snd_cs4231_overrange(chip);
  1050. snd_pcm_period_elapsed(chip->capture_substream);
  1051. }
  1052. /* ACK the CS4231 interrupt. */
  1053. spin_lock_irqsave(&chip->lock, flags);
  1054. snd_cs4231_outm(chip, CS4231_IRQ_STATUS, ~CS4231_ALL_IRQS | ~status, 0);
  1055. spin_unlock_irqrestore(&chip->lock, flags);
  1056. }
  1057. #ifdef SBUS_SUPPORT
  1058. static irqreturn_t snd_cs4231_sbus_interrupt(int irq, void *dev_id, struct pt_regs *regs)
  1059. {
  1060. cs4231_t *chip = dev_id;
  1061. u32 csr;
  1062. csr = sbus_readl(chip->port + APCCSR);
  1063. if (!(csr & (APC_INT_PENDING |
  1064. APC_PLAY_INT |
  1065. APC_CAPT_INT |
  1066. APC_GENL_INT |
  1067. APC_XINT_PEMP |
  1068. APC_XINT_CEMP)))
  1069. return IRQ_NONE;
  1070. /* ACK the APC interrupt. */
  1071. sbus_writel(csr, chip->port + APCCSR);
  1072. snd_cs4231_generic_interrupt(chip);
  1073. return IRQ_HANDLED;
  1074. }
  1075. #endif
  1076. #ifdef EBUS_SUPPORT
  1077. static void snd_cs4231_ebus_play_callback(struct ebus_dma_info *p, int event, void *cookie)
  1078. {
  1079. cs4231_t *chip = cookie;
  1080. if (chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE) {
  1081. snd_pcm_period_elapsed(chip->playback_substream);
  1082. snd_cs4231_ebus_advance_dma(p, chip->playback_substream,
  1083. &chip->p_periods_sent);
  1084. }
  1085. }
  1086. static void snd_cs4231_ebus_capture_callback(struct ebus_dma_info *p, int event, void *cookie)
  1087. {
  1088. cs4231_t *chip = cookie;
  1089. if (chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE) {
  1090. snd_pcm_period_elapsed(chip->capture_substream);
  1091. snd_cs4231_ebus_advance_dma(p, chip->capture_substream,
  1092. &chip->c_periods_sent);
  1093. }
  1094. }
  1095. #endif
  1096. static snd_pcm_uframes_t snd_cs4231_playback_pointer(snd_pcm_substream_t *substream)
  1097. {
  1098. cs4231_t *chip = snd_pcm_substream_chip(substream);
  1099. size_t ptr, residue, period_bytes;
  1100. if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE))
  1101. return 0;
  1102. period_bytes = snd_pcm_lib_period_bytes(substream);
  1103. ptr = period_bytes * chip->p_periods_sent;
  1104. #ifdef EBUS_SUPPORT
  1105. if (chip->flags & CS4231_FLAG_EBUS) {
  1106. residue = ebus_dma_residue(&chip->eb2p);
  1107. } else {
  1108. #endif
  1109. #ifdef SBUS_SUPPORT
  1110. residue = sbus_readl(chip->port + APCPC);
  1111. #endif
  1112. #ifdef EBUS_SUPPORT
  1113. }
  1114. #endif
  1115. ptr += (period_bytes - residue);
  1116. return bytes_to_frames(substream->runtime, ptr);
  1117. }
  1118. static snd_pcm_uframes_t snd_cs4231_capture_pointer(snd_pcm_substream_t * substream)
  1119. {
  1120. cs4231_t *chip = snd_pcm_substream_chip(substream);
  1121. size_t ptr, residue, period_bytes;
  1122. if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE))
  1123. return 0;
  1124. period_bytes = snd_pcm_lib_period_bytes(substream);
  1125. ptr = period_bytes * chip->c_periods_sent;
  1126. #ifdef EBUS_SUPPORT
  1127. if (chip->flags & CS4231_FLAG_EBUS) {
  1128. residue = ebus_dma_residue(&chip->eb2c);
  1129. } else {
  1130. #endif
  1131. #ifdef SBUS_SUPPORT
  1132. residue = sbus_readl(chip->port + APCCC);
  1133. #endif
  1134. #ifdef EBUS_SUPPORT
  1135. }
  1136. #endif
  1137. ptr += (period_bytes - residue);
  1138. return bytes_to_frames(substream->runtime, ptr);
  1139. }
  1140. /*
  1141. */
  1142. static int snd_cs4231_probe(cs4231_t *chip)
  1143. {
  1144. unsigned long flags;
  1145. int i, id, vers;
  1146. unsigned char *ptr;
  1147. #if 0
  1148. snd_cs4231_debug(chip);
  1149. #endif
  1150. id = vers = 0;
  1151. for (i = 0; i < 50; i++) {
  1152. mb();
  1153. if (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT)
  1154. udelay(2000);
  1155. else {
  1156. spin_lock_irqsave(&chip->lock, flags);
  1157. snd_cs4231_out(chip, CS4231_MISC_INFO, CS4231_MODE2);
  1158. id = snd_cs4231_in(chip, CS4231_MISC_INFO) & 0x0f;
  1159. vers = snd_cs4231_in(chip, CS4231_VERSION);
  1160. spin_unlock_irqrestore(&chip->lock, flags);
  1161. if (id == 0x0a)
  1162. break; /* this is valid value */
  1163. }
  1164. }
  1165. snd_printdd("cs4231: port = %p, id = 0x%x\n", chip->port, id);
  1166. if (id != 0x0a)
  1167. return -ENODEV; /* no valid device found */
  1168. spin_lock_irqsave(&chip->lock, flags);
  1169. /* Reset DMA engine. */
  1170. #ifdef EBUS_SUPPORT
  1171. if (chip->flags & CS4231_FLAG_EBUS) {
  1172. /* Done by ebus_dma_register */
  1173. } else {
  1174. #endif
  1175. #ifdef SBUS_SUPPORT
  1176. sbus_writel(APC_CHIP_RESET, chip->port + APCCSR);
  1177. sbus_writel(0x00, chip->port + APCCSR);
  1178. sbus_writel(sbus_readl(chip->port + APCCSR) | APC_CDC_RESET,
  1179. chip->port + APCCSR);
  1180. udelay(20);
  1181. sbus_writel(sbus_readl(chip->port + APCCSR) & ~APC_CDC_RESET,
  1182. chip->port + APCCSR);
  1183. sbus_writel(sbus_readl(chip->port + APCCSR) | (APC_XINT_ENA |
  1184. APC_XINT_PENA |
  1185. APC_XINT_CENA),
  1186. chip->port + APCCSR);
  1187. #endif
  1188. #ifdef EBUS_SUPPORT
  1189. }
  1190. #endif
  1191. __cs4231_readb(chip, CS4231P(chip, STATUS)); /* clear any pendings IRQ */
  1192. __cs4231_writeb(chip, 0, CS4231P(chip, STATUS));
  1193. mb();
  1194. spin_unlock_irqrestore(&chip->lock, flags);
  1195. chip->image[CS4231_MISC_INFO] = CS4231_MODE2;
  1196. chip->image[CS4231_IFACE_CTRL] =
  1197. chip->image[CS4231_IFACE_CTRL] & ~CS4231_SINGLE_DMA;
  1198. chip->image[CS4231_ALT_FEATURE_1] = 0x80;
  1199. chip->image[CS4231_ALT_FEATURE_2] = 0x01;
  1200. if (vers & 0x20)
  1201. chip->image[CS4231_ALT_FEATURE_2] |= 0x02;
  1202. ptr = (unsigned char *) &chip->image;
  1203. snd_cs4231_mce_down(chip);
  1204. spin_lock_irqsave(&chip->lock, flags);
  1205. for (i = 0; i < 32; i++) /* ok.. fill all CS4231 registers */
  1206. snd_cs4231_out(chip, i, *ptr++);
  1207. spin_unlock_irqrestore(&chip->lock, flags);
  1208. snd_cs4231_mce_up(chip);
  1209. snd_cs4231_mce_down(chip);
  1210. mdelay(2);
  1211. return 0; /* all things are ok.. */
  1212. }
  1213. static snd_pcm_hardware_t snd_cs4231_playback =
  1214. {
  1215. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  1216. SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_SYNC_START),
  1217. .formats = (SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW |
  1218. SNDRV_PCM_FMTBIT_IMA_ADPCM |
  1219. SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE |
  1220. SNDRV_PCM_FMTBIT_S16_BE),
  1221. .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_48000,
  1222. .rate_min = 5510,
  1223. .rate_max = 48000,
  1224. .channels_min = 1,
  1225. .channels_max = 2,
  1226. .buffer_bytes_max = (32*1024),
  1227. .period_bytes_min = 4096,
  1228. .period_bytes_max = (32*1024),
  1229. .periods_min = 1,
  1230. .periods_max = 1024,
  1231. };
  1232. static snd_pcm_hardware_t snd_cs4231_capture =
  1233. {
  1234. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  1235. SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_SYNC_START),
  1236. .formats = (SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW |
  1237. SNDRV_PCM_FMTBIT_IMA_ADPCM |
  1238. SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE |
  1239. SNDRV_PCM_FMTBIT_S16_BE),
  1240. .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_48000,
  1241. .rate_min = 5510,
  1242. .rate_max = 48000,
  1243. .channels_min = 1,
  1244. .channels_max = 2,
  1245. .buffer_bytes_max = (32*1024),
  1246. .period_bytes_min = 4096,
  1247. .period_bytes_max = (32*1024),
  1248. .periods_min = 1,
  1249. .periods_max = 1024,
  1250. };
  1251. static int snd_cs4231_playback_open(snd_pcm_substream_t *substream)
  1252. {
  1253. cs4231_t *chip = snd_pcm_substream_chip(substream);
  1254. snd_pcm_runtime_t *runtime = substream->runtime;
  1255. int err;
  1256. runtime->hw = snd_cs4231_playback;
  1257. if ((err = snd_cs4231_open(chip, CS4231_MODE_PLAY)) < 0) {
  1258. snd_free_pages(runtime->dma_area, runtime->dma_bytes);
  1259. return err;
  1260. }
  1261. chip->playback_substream = substream;
  1262. chip->p_periods_sent = 0;
  1263. snd_pcm_set_sync(substream);
  1264. snd_cs4231_xrate(runtime);
  1265. return 0;
  1266. }
  1267. static int snd_cs4231_capture_open(snd_pcm_substream_t *substream)
  1268. {
  1269. cs4231_t *chip = snd_pcm_substream_chip(substream);
  1270. snd_pcm_runtime_t *runtime = substream->runtime;
  1271. int err;
  1272. runtime->hw = snd_cs4231_capture;
  1273. if ((err = snd_cs4231_open(chip, CS4231_MODE_RECORD)) < 0) {
  1274. snd_free_pages(runtime->dma_area, runtime->dma_bytes);
  1275. return err;
  1276. }
  1277. chip->capture_substream = substream;
  1278. chip->c_periods_sent = 0;
  1279. snd_pcm_set_sync(substream);
  1280. snd_cs4231_xrate(runtime);
  1281. return 0;
  1282. }
  1283. static int snd_cs4231_playback_close(snd_pcm_substream_t *substream)
  1284. {
  1285. cs4231_t *chip = snd_pcm_substream_chip(substream);
  1286. chip->playback_substream = NULL;
  1287. snd_cs4231_close(chip, CS4231_MODE_PLAY);
  1288. return 0;
  1289. }
  1290. static int snd_cs4231_capture_close(snd_pcm_substream_t *substream)
  1291. {
  1292. cs4231_t *chip = snd_pcm_substream_chip(substream);
  1293. chip->capture_substream = NULL;
  1294. snd_cs4231_close(chip, CS4231_MODE_RECORD);
  1295. return 0;
  1296. }
  1297. /* XXX We can do some power-management, in particular on EBUS using
  1298. * XXX the audio AUXIO register...
  1299. */
  1300. static snd_pcm_ops_t snd_cs4231_playback_ops = {
  1301. .open = snd_cs4231_playback_open,
  1302. .close = snd_cs4231_playback_close,
  1303. .ioctl = snd_pcm_lib_ioctl,
  1304. .hw_params = snd_cs4231_playback_hw_params,
  1305. .hw_free = snd_cs4231_playback_hw_free,
  1306. .prepare = snd_cs4231_playback_prepare,
  1307. .trigger = snd_cs4231_trigger,
  1308. .pointer = snd_cs4231_playback_pointer,
  1309. };
  1310. static snd_pcm_ops_t snd_cs4231_capture_ops = {
  1311. .open = snd_cs4231_capture_open,
  1312. .close = snd_cs4231_capture_close,
  1313. .ioctl = snd_pcm_lib_ioctl,
  1314. .hw_params = snd_cs4231_capture_hw_params,
  1315. .hw_free = snd_cs4231_capture_hw_free,
  1316. .prepare = snd_cs4231_capture_prepare,
  1317. .trigger = snd_cs4231_trigger,
  1318. .pointer = snd_cs4231_capture_pointer,
  1319. };
  1320. static void snd_cs4231_pcm_free(snd_pcm_t *pcm)
  1321. {
  1322. cs4231_t *chip = pcm->private_data;
  1323. chip->pcm = NULL;
  1324. snd_pcm_lib_preallocate_free_for_all(pcm);
  1325. }
  1326. int snd_cs4231_pcm(cs4231_t *chip)
  1327. {
  1328. snd_pcm_t *pcm;
  1329. int err;
  1330. if ((err = snd_pcm_new(chip->card, "CS4231", 0, 1, 1, &pcm)) < 0)
  1331. return err;
  1332. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs4231_playback_ops);
  1333. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cs4231_capture_ops);
  1334. /* global setup */
  1335. pcm->private_data = chip;
  1336. pcm->private_free = snd_cs4231_pcm_free;
  1337. pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
  1338. strcpy(pcm->name, "CS4231");
  1339. #ifdef EBUS_SUPPORT
  1340. if (chip->flags & CS4231_FLAG_EBUS) {
  1341. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  1342. snd_dma_pci_data(chip->dev_u.pdev),
  1343. 64*1024, 128*1024);
  1344. } else {
  1345. #endif
  1346. #ifdef SBUS_SUPPORT
  1347. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_SBUS,
  1348. snd_dma_sbus_data(chip->dev_u.sdev),
  1349. 64*1024, 128*1024);
  1350. #endif
  1351. #ifdef EBUS_SUPPORT
  1352. }
  1353. #endif
  1354. chip->pcm = pcm;
  1355. return 0;
  1356. }
  1357. static void snd_cs4231_timer_free(snd_timer_t *timer)
  1358. {
  1359. cs4231_t *chip = timer->private_data;
  1360. chip->timer = NULL;
  1361. }
  1362. int snd_cs4231_timer(cs4231_t *chip)
  1363. {
  1364. snd_timer_t *timer;
  1365. snd_timer_id_t tid;
  1366. int err;
  1367. /* Timer initialization */
  1368. tid.dev_class = SNDRV_TIMER_CLASS_CARD;
  1369. tid.dev_sclass = SNDRV_TIMER_SCLASS_NONE;
  1370. tid.card = chip->card->number;
  1371. tid.device = 0;
  1372. tid.subdevice = 0;
  1373. if ((err = snd_timer_new(chip->card, "CS4231", &tid, &timer)) < 0)
  1374. return err;
  1375. strcpy(timer->name, "CS4231");
  1376. timer->private_data = chip;
  1377. timer->private_free = snd_cs4231_timer_free;
  1378. timer->hw = snd_cs4231_timer_table;
  1379. chip->timer = timer;
  1380. return 0;
  1381. }
  1382. /*
  1383. * MIXER part
  1384. */
  1385. static int snd_cs4231_info_mux(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
  1386. {
  1387. static char *texts[4] = {
  1388. "Line", "CD", "Mic", "Mix"
  1389. };
  1390. cs4231_t *chip = snd_kcontrol_chip(kcontrol);
  1391. snd_assert(chip->card != NULL, return -EINVAL);
  1392. uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
  1393. uinfo->count = 2;
  1394. uinfo->value.enumerated.items = 4;
  1395. if (uinfo->value.enumerated.item > 3)
  1396. uinfo->value.enumerated.item = 3;
  1397. strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
  1398. return 0;
  1399. }
  1400. static int snd_cs4231_get_mux(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
  1401. {
  1402. cs4231_t *chip = snd_kcontrol_chip(kcontrol);
  1403. unsigned long flags;
  1404. spin_lock_irqsave(&chip->lock, flags);
  1405. ucontrol->value.enumerated.item[0] =
  1406. (chip->image[CS4231_LEFT_INPUT] & CS4231_MIXS_ALL) >> 6;
  1407. ucontrol->value.enumerated.item[1] =
  1408. (chip->image[CS4231_RIGHT_INPUT] & CS4231_MIXS_ALL) >> 6;
  1409. spin_unlock_irqrestore(&chip->lock, flags);
  1410. return 0;
  1411. }
  1412. static int snd_cs4231_put_mux(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
  1413. {
  1414. cs4231_t *chip = snd_kcontrol_chip(kcontrol);
  1415. unsigned long flags;
  1416. unsigned short left, right;
  1417. int change;
  1418. if (ucontrol->value.enumerated.item[0] > 3 ||
  1419. ucontrol->value.enumerated.item[1] > 3)
  1420. return -EINVAL;
  1421. left = ucontrol->value.enumerated.item[0] << 6;
  1422. right = ucontrol->value.enumerated.item[1] << 6;
  1423. spin_lock_irqsave(&chip->lock, flags);
  1424. left = (chip->image[CS4231_LEFT_INPUT] & ~CS4231_MIXS_ALL) | left;
  1425. right = (chip->image[CS4231_RIGHT_INPUT] & ~CS4231_MIXS_ALL) | right;
  1426. change = left != chip->image[CS4231_LEFT_INPUT] ||
  1427. right != chip->image[CS4231_RIGHT_INPUT];
  1428. snd_cs4231_out(chip, CS4231_LEFT_INPUT, left);
  1429. snd_cs4231_out(chip, CS4231_RIGHT_INPUT, right);
  1430. spin_unlock_irqrestore(&chip->lock, flags);
  1431. return change;
  1432. }
  1433. int snd_cs4231_info_single(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
  1434. {
  1435. int mask = (kcontrol->private_value >> 16) & 0xff;
  1436. uinfo->type = (mask == 1) ?
  1437. SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
  1438. uinfo->count = 1;
  1439. uinfo->value.integer.min = 0;
  1440. uinfo->value.integer.max = mask;
  1441. return 0;
  1442. }
  1443. int snd_cs4231_get_single(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
  1444. {
  1445. cs4231_t *chip = snd_kcontrol_chip(kcontrol);
  1446. unsigned long flags;
  1447. int reg = kcontrol->private_value & 0xff;
  1448. int shift = (kcontrol->private_value >> 8) & 0xff;
  1449. int mask = (kcontrol->private_value >> 16) & 0xff;
  1450. int invert = (kcontrol->private_value >> 24) & 0xff;
  1451. spin_lock_irqsave(&chip->lock, flags);
  1452. ucontrol->value.integer.value[0] = (chip->image[reg] >> shift) & mask;
  1453. spin_unlock_irqrestore(&chip->lock, flags);
  1454. if (invert)
  1455. ucontrol->value.integer.value[0] =
  1456. (mask - ucontrol->value.integer.value[0]);
  1457. return 0;
  1458. }
  1459. int snd_cs4231_put_single(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
  1460. {
  1461. cs4231_t *chip = snd_kcontrol_chip(kcontrol);
  1462. unsigned long flags;
  1463. int reg = kcontrol->private_value & 0xff;
  1464. int shift = (kcontrol->private_value >> 8) & 0xff;
  1465. int mask = (kcontrol->private_value >> 16) & 0xff;
  1466. int invert = (kcontrol->private_value >> 24) & 0xff;
  1467. int change;
  1468. unsigned short val;
  1469. val = (ucontrol->value.integer.value[0] & mask);
  1470. if (invert)
  1471. val = mask - val;
  1472. val <<= shift;
  1473. spin_lock_irqsave(&chip->lock, flags);
  1474. val = (chip->image[reg] & ~(mask << shift)) | val;
  1475. change = val != chip->image[reg];
  1476. snd_cs4231_out(chip, reg, val);
  1477. spin_unlock_irqrestore(&chip->lock, flags);
  1478. return change;
  1479. }
  1480. int snd_cs4231_info_double(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
  1481. {
  1482. int mask = (kcontrol->private_value >> 24) & 0xff;
  1483. uinfo->type = mask == 1 ?
  1484. SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
  1485. uinfo->count = 2;
  1486. uinfo->value.integer.min = 0;
  1487. uinfo->value.integer.max = mask;
  1488. return 0;
  1489. }
  1490. int snd_cs4231_get_double(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
  1491. {
  1492. cs4231_t *chip = snd_kcontrol_chip(kcontrol);
  1493. unsigned long flags;
  1494. int left_reg = kcontrol->private_value & 0xff;
  1495. int right_reg = (kcontrol->private_value >> 8) & 0xff;
  1496. int shift_left = (kcontrol->private_value >> 16) & 0x07;
  1497. int shift_right = (kcontrol->private_value >> 19) & 0x07;
  1498. int mask = (kcontrol->private_value >> 24) & 0xff;
  1499. int invert = (kcontrol->private_value >> 22) & 1;
  1500. spin_lock_irqsave(&chip->lock, flags);
  1501. ucontrol->value.integer.value[0] = (chip->image[left_reg] >> shift_left) & mask;
  1502. ucontrol->value.integer.value[1] = (chip->image[right_reg] >> shift_right) & mask;
  1503. spin_unlock_irqrestore(&chip->lock, flags);
  1504. if (invert) {
  1505. ucontrol->value.integer.value[0] =
  1506. (mask - ucontrol->value.integer.value[0]);
  1507. ucontrol->value.integer.value[1] =
  1508. (mask - ucontrol->value.integer.value[1]);
  1509. }
  1510. return 0;
  1511. }
  1512. int snd_cs4231_put_double(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
  1513. {
  1514. cs4231_t *chip = snd_kcontrol_chip(kcontrol);
  1515. unsigned long flags;
  1516. int left_reg = kcontrol->private_value & 0xff;
  1517. int right_reg = (kcontrol->private_value >> 8) & 0xff;
  1518. int shift_left = (kcontrol->private_value >> 16) & 0x07;
  1519. int shift_right = (kcontrol->private_value >> 19) & 0x07;
  1520. int mask = (kcontrol->private_value >> 24) & 0xff;
  1521. int invert = (kcontrol->private_value >> 22) & 1;
  1522. int change;
  1523. unsigned short val1, val2;
  1524. val1 = ucontrol->value.integer.value[0] & mask;
  1525. val2 = ucontrol->value.integer.value[1] & mask;
  1526. if (invert) {
  1527. val1 = mask - val1;
  1528. val2 = mask - val2;
  1529. }
  1530. val1 <<= shift_left;
  1531. val2 <<= shift_right;
  1532. spin_lock_irqsave(&chip->lock, flags);
  1533. val1 = (chip->image[left_reg] & ~(mask << shift_left)) | val1;
  1534. val2 = (chip->image[right_reg] & ~(mask << shift_right)) | val2;
  1535. change = val1 != chip->image[left_reg] || val2 != chip->image[right_reg];
  1536. snd_cs4231_out(chip, left_reg, val1);
  1537. snd_cs4231_out(chip, right_reg, val2);
  1538. spin_unlock_irqrestore(&chip->lock, flags);
  1539. return change;
  1540. }
  1541. #define CS4231_SINGLE(xname, xindex, reg, shift, mask, invert) \
  1542. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
  1543. .info = snd_cs4231_info_single, \
  1544. .get = snd_cs4231_get_single, .put = snd_cs4231_put_single, \
  1545. .private_value = reg | (shift << 8) | (mask << 16) | (invert << 24) }
  1546. #define CS4231_DOUBLE(xname, xindex, left_reg, right_reg, shift_left, shift_right, mask, invert) \
  1547. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
  1548. .info = snd_cs4231_info_double, \
  1549. .get = snd_cs4231_get_double, .put = snd_cs4231_put_double, \
  1550. .private_value = left_reg | (right_reg << 8) | (shift_left << 16) | (shift_right << 19) | (mask << 24) | (invert << 22) }
  1551. static snd_kcontrol_new_t snd_cs4231_controls[] = {
  1552. CS4231_DOUBLE("PCM Playback Switch", 0, CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT, 7, 7, 1, 1),
  1553. CS4231_DOUBLE("PCM Playback Volume", 0, CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT, 0, 0, 63, 1),
  1554. CS4231_DOUBLE("Line Playback Switch", 0, CS4231_LEFT_LINE_IN, CS4231_RIGHT_LINE_IN, 7, 7, 1, 1),
  1555. CS4231_DOUBLE("Line Playback Volume", 0, CS4231_LEFT_LINE_IN, CS4231_RIGHT_LINE_IN, 0, 0, 31, 1),
  1556. CS4231_DOUBLE("Aux Playback Switch", 0, CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 7, 7, 1, 1),
  1557. CS4231_DOUBLE("Aux Playback Volume", 0, CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 0, 0, 31, 1),
  1558. CS4231_DOUBLE("Aux Playback Switch", 1, CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 7, 7, 1, 1),
  1559. CS4231_DOUBLE("Aux Playback Volume", 1, CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 0, 0, 31, 1),
  1560. CS4231_SINGLE("Mono Playback Switch", 0, CS4231_MONO_CTRL, 7, 1, 1),
  1561. CS4231_SINGLE("Mono Playback Volume", 0, CS4231_MONO_CTRL, 0, 15, 1),
  1562. CS4231_SINGLE("Mono Output Playback Switch", 0, CS4231_MONO_CTRL, 6, 1, 1),
  1563. CS4231_SINGLE("Mono Output Playback Bypass", 0, CS4231_MONO_CTRL, 5, 1, 0),
  1564. CS4231_DOUBLE("Capture Volume", 0, CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 0, 0, 15, 0),
  1565. {
  1566. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1567. .name = "Capture Source",
  1568. .info = snd_cs4231_info_mux,
  1569. .get = snd_cs4231_get_mux,
  1570. .put = snd_cs4231_put_mux,
  1571. },
  1572. CS4231_DOUBLE("Mic Boost", 0, CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 5, 5, 1, 0),
  1573. CS4231_SINGLE("Loopback Capture Switch", 0, CS4231_LOOPBACK, 0, 1, 0),
  1574. CS4231_SINGLE("Loopback Capture Volume", 0, CS4231_LOOPBACK, 2, 63, 1),
  1575. /* SPARC specific uses of XCTL{0,1} general purpose outputs. */
  1576. CS4231_SINGLE("Line Out Switch", 0, CS4231_PIN_CTRL, 6, 1, 1),
  1577. CS4231_SINGLE("Headphone Out Switch", 0, CS4231_PIN_CTRL, 7, 1, 1)
  1578. };
  1579. int snd_cs4231_mixer(cs4231_t *chip)
  1580. {
  1581. snd_card_t *card;
  1582. int err, idx;
  1583. snd_assert(chip != NULL && chip->pcm != NULL, return -EINVAL);
  1584. card = chip->card;
  1585. strcpy(card->mixername, chip->pcm->name);
  1586. for (idx = 0; idx < ARRAY_SIZE(snd_cs4231_controls); idx++) {
  1587. if ((err = snd_ctl_add(card,
  1588. snd_ctl_new1(&snd_cs4231_controls[idx],
  1589. chip))) < 0)
  1590. return err;
  1591. }
  1592. return 0;
  1593. }
  1594. static int dev;
  1595. static int cs4231_attach_begin(snd_card_t **rcard)
  1596. {
  1597. snd_card_t *card;
  1598. *rcard = NULL;
  1599. if (dev >= SNDRV_CARDS)
  1600. return -ENODEV;
  1601. if (!enable[dev]) {
  1602. dev++;
  1603. return -ENOENT;
  1604. }
  1605. card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
  1606. if (card == NULL)
  1607. return -ENOMEM;
  1608. strcpy(card->driver, "CS4231");
  1609. strcpy(card->shortname, "Sun CS4231");
  1610. *rcard = card;
  1611. return 0;
  1612. }
  1613. static int cs4231_attach_finish(snd_card_t *card, cs4231_t *chip)
  1614. {
  1615. int err;
  1616. if ((err = snd_cs4231_pcm(chip)) < 0)
  1617. goto out_err;
  1618. if ((err = snd_cs4231_mixer(chip)) < 0)
  1619. goto out_err;
  1620. if ((err = snd_cs4231_timer(chip)) < 0)
  1621. goto out_err;
  1622. if ((err = snd_card_register(card)) < 0)
  1623. goto out_err;
  1624. chip->next = cs4231_list;
  1625. cs4231_list = chip;
  1626. dev++;
  1627. return 0;
  1628. out_err:
  1629. snd_card_free(card);
  1630. return err;
  1631. }
  1632. #ifdef SBUS_SUPPORT
  1633. static int snd_cs4231_sbus_free(cs4231_t *chip)
  1634. {
  1635. if (chip->irq[0])
  1636. free_irq(chip->irq[0], chip);
  1637. if (chip->port)
  1638. sbus_iounmap(chip->port, chip->regs_size);
  1639. if (chip->timer)
  1640. snd_device_free(chip->card, chip->timer);
  1641. kfree(chip);
  1642. return 0;
  1643. }
  1644. static int snd_cs4231_sbus_dev_free(snd_device_t *device)
  1645. {
  1646. cs4231_t *cp = device->device_data;
  1647. return snd_cs4231_sbus_free(cp);
  1648. }
  1649. static snd_device_ops_t snd_cs4231_sbus_dev_ops = {
  1650. .dev_free = snd_cs4231_sbus_dev_free,
  1651. };
  1652. static int __init snd_cs4231_sbus_create(snd_card_t *card,
  1653. struct sbus_dev *sdev,
  1654. int dev,
  1655. cs4231_t **rchip)
  1656. {
  1657. cs4231_t *chip;
  1658. int err;
  1659. *rchip = NULL;
  1660. chip = kcalloc(1, sizeof(*chip), GFP_KERNEL);
  1661. if (chip == NULL)
  1662. return -ENOMEM;
  1663. spin_lock_init(&chip->lock);
  1664. init_MUTEX(&chip->mce_mutex);
  1665. init_MUTEX(&chip->open_mutex);
  1666. chip->card = card;
  1667. chip->dev_u.sdev = sdev;
  1668. chip->regs_size = sdev->reg_addrs[0].reg_size;
  1669. memcpy(&chip->image, &snd_cs4231_original_image,
  1670. sizeof(snd_cs4231_original_image));
  1671. chip->port = sbus_ioremap(&sdev->resource[0], 0,
  1672. chip->regs_size, "cs4231");
  1673. if (!chip->port) {
  1674. snd_printk("cs4231-%d: Unable to map chip registers.\n", dev);
  1675. return -EIO;
  1676. }
  1677. if (request_irq(sdev->irqs[0], snd_cs4231_sbus_interrupt,
  1678. SA_SHIRQ, "cs4231", chip)) {
  1679. snd_printk("cs4231-%d: Unable to grab SBUS IRQ %s\n",
  1680. dev,
  1681. __irq_itoa(sdev->irqs[0]));
  1682. snd_cs4231_sbus_free(chip);
  1683. return -EBUSY;
  1684. }
  1685. chip->irq[0] = sdev->irqs[0];
  1686. if (snd_cs4231_probe(chip) < 0) {
  1687. snd_cs4231_sbus_free(chip);
  1688. return -ENODEV;
  1689. }
  1690. snd_cs4231_init(chip);
  1691. if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL,
  1692. chip, &snd_cs4231_sbus_dev_ops)) < 0) {
  1693. snd_cs4231_sbus_free(chip);
  1694. return err;
  1695. }
  1696. *rchip = chip;
  1697. return 0;
  1698. }
  1699. static int cs4231_sbus_attach(struct sbus_dev *sdev)
  1700. {
  1701. struct resource *rp = &sdev->resource[0];
  1702. cs4231_t *cp;
  1703. snd_card_t *card;
  1704. int err;
  1705. err = cs4231_attach_begin(&card);
  1706. if (err)
  1707. return err;
  1708. sprintf(card->longname, "%s at 0x%02lx:0x%08lx, irq %s",
  1709. card->shortname,
  1710. rp->flags & 0xffL,
  1711. rp->start,
  1712. __irq_itoa(sdev->irqs[0]));
  1713. if ((err = snd_cs4231_sbus_create(card, sdev, dev, &cp)) < 0) {
  1714. snd_card_free(card);
  1715. return err;
  1716. }
  1717. return cs4231_attach_finish(card, cp);
  1718. }
  1719. #endif
  1720. #ifdef EBUS_SUPPORT
  1721. static int snd_cs4231_ebus_free(cs4231_t *chip)
  1722. {
  1723. if (chip->eb2c.regs) {
  1724. ebus_dma_unregister(&chip->eb2c);
  1725. iounmap(chip->eb2c.regs);
  1726. }
  1727. if (chip->eb2p.regs) {
  1728. ebus_dma_unregister(&chip->eb2p);
  1729. iounmap(chip->eb2p.regs);
  1730. }
  1731. if (chip->port)
  1732. iounmap(chip->port);
  1733. if (chip->timer)
  1734. snd_device_free(chip->card, chip->timer);
  1735. kfree(chip);
  1736. return 0;
  1737. }
  1738. static int snd_cs4231_ebus_dev_free(snd_device_t *device)
  1739. {
  1740. cs4231_t *cp = device->device_data;
  1741. return snd_cs4231_ebus_free(cp);
  1742. }
  1743. static snd_device_ops_t snd_cs4231_ebus_dev_ops = {
  1744. .dev_free = snd_cs4231_ebus_dev_free,
  1745. };
  1746. static int __init snd_cs4231_ebus_create(snd_card_t *card,
  1747. struct linux_ebus_device *edev,
  1748. int dev,
  1749. cs4231_t **rchip)
  1750. {
  1751. cs4231_t *chip;
  1752. int err;
  1753. *rchip = NULL;
  1754. chip = kcalloc(1, sizeof(*chip), GFP_KERNEL);
  1755. if (chip == NULL)
  1756. return -ENOMEM;
  1757. spin_lock_init(&chip->lock);
  1758. spin_lock_init(&chip->eb2c.lock);
  1759. spin_lock_init(&chip->eb2p.lock);
  1760. init_MUTEX(&chip->mce_mutex);
  1761. init_MUTEX(&chip->open_mutex);
  1762. chip->flags |= CS4231_FLAG_EBUS;
  1763. chip->card = card;
  1764. chip->dev_u.pdev = edev->bus->self;
  1765. memcpy(&chip->image, &snd_cs4231_original_image,
  1766. sizeof(snd_cs4231_original_image));
  1767. strcpy(chip->eb2c.name, "cs4231(capture)");
  1768. chip->eb2c.flags = EBUS_DMA_FLAG_USE_EBDMA_HANDLER;
  1769. chip->eb2c.callback = snd_cs4231_ebus_capture_callback;
  1770. chip->eb2c.client_cookie = chip;
  1771. chip->eb2c.irq = edev->irqs[0];
  1772. strcpy(chip->eb2p.name, "cs4231(play)");
  1773. chip->eb2p.flags = EBUS_DMA_FLAG_USE_EBDMA_HANDLER;
  1774. chip->eb2p.callback = snd_cs4231_ebus_play_callback;
  1775. chip->eb2p.client_cookie = chip;
  1776. chip->eb2p.irq = edev->irqs[1];
  1777. chip->port = ioremap(edev->resource[0].start, 0x10);
  1778. chip->eb2p.regs = ioremap(edev->resource[1].start, 0x10);
  1779. chip->eb2c.regs = ioremap(edev->resource[2].start, 0x10);
  1780. if (!chip->port || !chip->eb2p.regs || !chip->eb2c.regs) {
  1781. snd_cs4231_ebus_free(chip);
  1782. snd_printk("cs4231-%d: Unable to map chip registers.\n", dev);
  1783. return -EIO;
  1784. }
  1785. if (ebus_dma_register(&chip->eb2c)) {
  1786. snd_cs4231_ebus_free(chip);
  1787. snd_printk("cs4231-%d: Unable to register EBUS capture DMA\n", dev);
  1788. return -EBUSY;
  1789. }
  1790. if (ebus_dma_irq_enable(&chip->eb2c, 1)) {
  1791. snd_cs4231_ebus_free(chip);
  1792. snd_printk("cs4231-%d: Unable to enable EBUS capture IRQ\n", dev);
  1793. return -EBUSY;
  1794. }
  1795. if (ebus_dma_register(&chip->eb2p)) {
  1796. snd_cs4231_ebus_free(chip);
  1797. snd_printk("cs4231-%d: Unable to register EBUS play DMA\n", dev);
  1798. return -EBUSY;
  1799. }
  1800. if (ebus_dma_irq_enable(&chip->eb2p, 1)) {
  1801. snd_cs4231_ebus_free(chip);
  1802. snd_printk("cs4231-%d: Unable to enable EBUS play IRQ\n", dev);
  1803. return -EBUSY;
  1804. }
  1805. if (snd_cs4231_probe(chip) < 0) {
  1806. snd_cs4231_ebus_free(chip);
  1807. return -ENODEV;
  1808. }
  1809. snd_cs4231_init(chip);
  1810. if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL,
  1811. chip, &snd_cs4231_ebus_dev_ops)) < 0) {
  1812. snd_cs4231_ebus_free(chip);
  1813. return err;
  1814. }
  1815. *rchip = chip;
  1816. return 0;
  1817. }
  1818. static int cs4231_ebus_attach(struct linux_ebus_device *edev)
  1819. {
  1820. snd_card_t *card;
  1821. cs4231_t *chip;
  1822. int err;
  1823. err = cs4231_attach_begin(&card);
  1824. if (err)
  1825. return err;
  1826. sprintf(card->longname, "%s at 0x%lx, irq %s",
  1827. card->shortname,
  1828. edev->resource[0].start,
  1829. __irq_itoa(edev->irqs[0]));
  1830. if ((err = snd_cs4231_ebus_create(card, edev, dev, &chip)) < 0) {
  1831. snd_card_free(card);
  1832. return err;
  1833. }
  1834. return cs4231_attach_finish(card, chip);
  1835. }
  1836. #endif
  1837. static int __init cs4231_init(void)
  1838. {
  1839. #ifdef SBUS_SUPPORT
  1840. struct sbus_bus *sbus;
  1841. struct sbus_dev *sdev;
  1842. #endif
  1843. #ifdef EBUS_SUPPORT
  1844. struct linux_ebus *ebus;
  1845. struct linux_ebus_device *edev;
  1846. #endif
  1847. int found;
  1848. found = 0;
  1849. #ifdef SBUS_SUPPORT
  1850. for_all_sbusdev(sdev, sbus) {
  1851. if (!strcmp(sdev->prom_name, "SUNW,CS4231")) {
  1852. if (cs4231_sbus_attach(sdev) == 0)
  1853. found++;
  1854. }
  1855. }
  1856. #endif
  1857. #ifdef EBUS_SUPPORT
  1858. for_each_ebus(ebus) {
  1859. for_each_ebusdev(edev, ebus) {
  1860. int match = 0;
  1861. if (!strcmp(edev->prom_name, "SUNW,CS4231")) {
  1862. match = 1;
  1863. } else if (!strcmp(edev->prom_name, "audio")) {
  1864. char compat[16];
  1865. prom_getstring(edev->prom_node, "compatible",
  1866. compat, sizeof(compat));
  1867. compat[15] = '\0';
  1868. if (!strcmp(compat, "SUNW,CS4231"))
  1869. match = 1;
  1870. }
  1871. if (match &&
  1872. cs4231_ebus_attach(edev) == 0)
  1873. found++;
  1874. }
  1875. }
  1876. #endif
  1877. return (found > 0) ? 0 : -EIO;
  1878. }
  1879. static void __exit cs4231_exit(void)
  1880. {
  1881. cs4231_t *p = cs4231_list;
  1882. while (p != NULL) {
  1883. cs4231_t *next = p->next;
  1884. snd_card_free(p->card);
  1885. p = next;
  1886. }
  1887. cs4231_list = NULL;
  1888. }
  1889. module_init(cs4231_init);
  1890. module_exit(cs4231_exit);