ymfpci_main.c 63 KB

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  1. /*
  2. * Copyright (c) by Jaroslav Kysela <perex@suse.cz>
  3. * Routines for control of YMF724/740/744/754 chips
  4. *
  5. * BUGS:
  6. * --
  7. *
  8. * TODO:
  9. * --
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License as published by
  13. * the Free Software Foundation; either version 2 of the License, or
  14. * (at your option) any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  24. *
  25. */
  26. #include <sound/driver.h>
  27. #include <linux/delay.h>
  28. #include <linux/init.h>
  29. #include <linux/interrupt.h>
  30. #include <linux/pci.h>
  31. #include <linux/sched.h>
  32. #include <linux/slab.h>
  33. #include <linux/vmalloc.h>
  34. #include <sound/core.h>
  35. #include <sound/control.h>
  36. #include <sound/info.h>
  37. #include <sound/ymfpci.h>
  38. #include <sound/asoundef.h>
  39. #include <sound/mpu401.h>
  40. #include <asm/io.h>
  41. /*
  42. * constants
  43. */
  44. /*
  45. * common I/O routines
  46. */
  47. static void snd_ymfpci_irq_wait(ymfpci_t *chip);
  48. static inline u8 snd_ymfpci_readb(ymfpci_t *chip, u32 offset)
  49. {
  50. return readb(chip->reg_area_virt + offset);
  51. }
  52. static inline void snd_ymfpci_writeb(ymfpci_t *chip, u32 offset, u8 val)
  53. {
  54. writeb(val, chip->reg_area_virt + offset);
  55. }
  56. static inline u16 snd_ymfpci_readw(ymfpci_t *chip, u32 offset)
  57. {
  58. return readw(chip->reg_area_virt + offset);
  59. }
  60. static inline void snd_ymfpci_writew(ymfpci_t *chip, u32 offset, u16 val)
  61. {
  62. writew(val, chip->reg_area_virt + offset);
  63. }
  64. static inline u32 snd_ymfpci_readl(ymfpci_t *chip, u32 offset)
  65. {
  66. return readl(chip->reg_area_virt + offset);
  67. }
  68. static inline void snd_ymfpci_writel(ymfpci_t *chip, u32 offset, u32 val)
  69. {
  70. writel(val, chip->reg_area_virt + offset);
  71. }
  72. static int snd_ymfpci_codec_ready(ymfpci_t *chip, int secondary)
  73. {
  74. signed long end_time;
  75. u32 reg = secondary ? YDSXGR_SECSTATUSADR : YDSXGR_PRISTATUSADR;
  76. end_time = (jiffies + ((3 * HZ) / 4)) + 1;
  77. do {
  78. if ((snd_ymfpci_readw(chip, reg) & 0x8000) == 0)
  79. return 0;
  80. set_current_state(TASK_UNINTERRUPTIBLE);
  81. schedule_timeout(1);
  82. } while (end_time - (signed long)jiffies >= 0);
  83. snd_printk("codec_ready: codec %i is not ready [0x%x]\n", secondary, snd_ymfpci_readw(chip, reg));
  84. return -EBUSY;
  85. }
  86. static void snd_ymfpci_codec_write(ac97_t *ac97, u16 reg, u16 val)
  87. {
  88. ymfpci_t *chip = ac97->private_data;
  89. u32 cmd;
  90. snd_ymfpci_codec_ready(chip, 0);
  91. cmd = ((YDSXG_AC97WRITECMD | reg) << 16) | val;
  92. snd_ymfpci_writel(chip, YDSXGR_AC97CMDDATA, cmd);
  93. }
  94. static u16 snd_ymfpci_codec_read(ac97_t *ac97, u16 reg)
  95. {
  96. ymfpci_t *chip = ac97->private_data;
  97. if (snd_ymfpci_codec_ready(chip, 0))
  98. return ~0;
  99. snd_ymfpci_writew(chip, YDSXGR_AC97CMDADR, YDSXG_AC97READCMD | reg);
  100. if (snd_ymfpci_codec_ready(chip, 0))
  101. return ~0;
  102. if (chip->device_id == PCI_DEVICE_ID_YAMAHA_744 && chip->rev < 2) {
  103. int i;
  104. for (i = 0; i < 600; i++)
  105. snd_ymfpci_readw(chip, YDSXGR_PRISTATUSDATA);
  106. }
  107. return snd_ymfpci_readw(chip, YDSXGR_PRISTATUSDATA);
  108. }
  109. /*
  110. * Misc routines
  111. */
  112. static u32 snd_ymfpci_calc_delta(u32 rate)
  113. {
  114. switch (rate) {
  115. case 8000: return 0x02aaab00;
  116. case 11025: return 0x03accd00;
  117. case 16000: return 0x05555500;
  118. case 22050: return 0x07599a00;
  119. case 32000: return 0x0aaaab00;
  120. case 44100: return 0x0eb33300;
  121. default: return ((rate << 16) / 375) << 5;
  122. }
  123. }
  124. static u32 def_rate[8] = {
  125. 100, 2000, 8000, 11025, 16000, 22050, 32000, 48000
  126. };
  127. static u32 snd_ymfpci_calc_lpfK(u32 rate)
  128. {
  129. u32 i;
  130. static u32 val[8] = {
  131. 0x00570000, 0x06AA0000, 0x18B20000, 0x20930000,
  132. 0x2B9A0000, 0x35A10000, 0x3EAA0000, 0x40000000
  133. };
  134. if (rate == 44100)
  135. return 0x40000000; /* FIXME: What's the right value? */
  136. for (i = 0; i < 8; i++)
  137. if (rate <= def_rate[i])
  138. return val[i];
  139. return val[0];
  140. }
  141. static u32 snd_ymfpci_calc_lpfQ(u32 rate)
  142. {
  143. u32 i;
  144. static u32 val[8] = {
  145. 0x35280000, 0x34A70000, 0x32020000, 0x31770000,
  146. 0x31390000, 0x31C90000, 0x33D00000, 0x40000000
  147. };
  148. if (rate == 44100)
  149. return 0x370A0000;
  150. for (i = 0; i < 8; i++)
  151. if (rate <= def_rate[i])
  152. return val[i];
  153. return val[0];
  154. }
  155. /*
  156. * Hardware start management
  157. */
  158. static void snd_ymfpci_hw_start(ymfpci_t *chip)
  159. {
  160. unsigned long flags;
  161. spin_lock_irqsave(&chip->reg_lock, flags);
  162. if (chip->start_count++ > 0)
  163. goto __end;
  164. snd_ymfpci_writel(chip, YDSXGR_MODE,
  165. snd_ymfpci_readl(chip, YDSXGR_MODE) | 3);
  166. chip->active_bank = snd_ymfpci_readl(chip, YDSXGR_CTRLSELECT) & 1;
  167. __end:
  168. spin_unlock_irqrestore(&chip->reg_lock, flags);
  169. }
  170. static void snd_ymfpci_hw_stop(ymfpci_t *chip)
  171. {
  172. unsigned long flags;
  173. long timeout = 1000;
  174. spin_lock_irqsave(&chip->reg_lock, flags);
  175. if (--chip->start_count > 0)
  176. goto __end;
  177. snd_ymfpci_writel(chip, YDSXGR_MODE,
  178. snd_ymfpci_readl(chip, YDSXGR_MODE) & ~3);
  179. while (timeout-- > 0) {
  180. if ((snd_ymfpci_readl(chip, YDSXGR_STATUS) & 2) == 0)
  181. break;
  182. }
  183. if (atomic_read(&chip->interrupt_sleep_count)) {
  184. atomic_set(&chip->interrupt_sleep_count, 0);
  185. wake_up(&chip->interrupt_sleep);
  186. }
  187. __end:
  188. spin_unlock_irqrestore(&chip->reg_lock, flags);
  189. }
  190. /*
  191. * Playback voice management
  192. */
  193. static int voice_alloc(ymfpci_t *chip, ymfpci_voice_type_t type, int pair, ymfpci_voice_t **rvoice)
  194. {
  195. ymfpci_voice_t *voice, *voice2;
  196. int idx;
  197. *rvoice = NULL;
  198. for (idx = 0; idx < YDSXG_PLAYBACK_VOICES; idx += pair ? 2 : 1) {
  199. voice = &chip->voices[idx];
  200. voice2 = pair ? &chip->voices[idx+1] : NULL;
  201. if (voice->use || (voice2 && voice2->use))
  202. continue;
  203. voice->use = 1;
  204. if (voice2)
  205. voice2->use = 1;
  206. switch (type) {
  207. case YMFPCI_PCM:
  208. voice->pcm = 1;
  209. if (voice2)
  210. voice2->pcm = 1;
  211. break;
  212. case YMFPCI_SYNTH:
  213. voice->synth = 1;
  214. break;
  215. case YMFPCI_MIDI:
  216. voice->midi = 1;
  217. break;
  218. }
  219. snd_ymfpci_hw_start(chip);
  220. if (voice2)
  221. snd_ymfpci_hw_start(chip);
  222. *rvoice = voice;
  223. return 0;
  224. }
  225. return -ENOMEM;
  226. }
  227. static int snd_ymfpci_voice_alloc(ymfpci_t *chip, ymfpci_voice_type_t type, int pair, ymfpci_voice_t **rvoice)
  228. {
  229. unsigned long flags;
  230. int result;
  231. snd_assert(rvoice != NULL, return -EINVAL);
  232. snd_assert(!pair || type == YMFPCI_PCM, return -EINVAL);
  233. spin_lock_irqsave(&chip->voice_lock, flags);
  234. for (;;) {
  235. result = voice_alloc(chip, type, pair, rvoice);
  236. if (result == 0 || type != YMFPCI_PCM)
  237. break;
  238. /* TODO: synth/midi voice deallocation */
  239. break;
  240. }
  241. spin_unlock_irqrestore(&chip->voice_lock, flags);
  242. return result;
  243. }
  244. static int snd_ymfpci_voice_free(ymfpci_t *chip, ymfpci_voice_t *pvoice)
  245. {
  246. unsigned long flags;
  247. snd_assert(pvoice != NULL, return -EINVAL);
  248. snd_ymfpci_hw_stop(chip);
  249. spin_lock_irqsave(&chip->voice_lock, flags);
  250. pvoice->use = pvoice->pcm = pvoice->synth = pvoice->midi = 0;
  251. pvoice->ypcm = NULL;
  252. pvoice->interrupt = NULL;
  253. spin_unlock_irqrestore(&chip->voice_lock, flags);
  254. return 0;
  255. }
  256. /*
  257. * PCM part
  258. */
  259. static void snd_ymfpci_pcm_interrupt(ymfpci_t *chip, ymfpci_voice_t *voice)
  260. {
  261. ymfpci_pcm_t *ypcm;
  262. u32 pos, delta;
  263. if ((ypcm = voice->ypcm) == NULL)
  264. return;
  265. if (ypcm->substream == NULL)
  266. return;
  267. spin_lock(&chip->reg_lock);
  268. if (ypcm->running) {
  269. pos = le32_to_cpu(voice->bank[chip->active_bank].start);
  270. if (pos < ypcm->last_pos)
  271. delta = pos + (ypcm->buffer_size - ypcm->last_pos);
  272. else
  273. delta = pos - ypcm->last_pos;
  274. ypcm->period_pos += delta;
  275. ypcm->last_pos = pos;
  276. if (ypcm->period_pos >= ypcm->period_size) {
  277. // printk("done - active_bank = 0x%x, start = 0x%x\n", chip->active_bank, voice->bank[chip->active_bank].start);
  278. ypcm->period_pos %= ypcm->period_size;
  279. spin_unlock(&chip->reg_lock);
  280. snd_pcm_period_elapsed(ypcm->substream);
  281. spin_lock(&chip->reg_lock);
  282. }
  283. }
  284. spin_unlock(&chip->reg_lock);
  285. }
  286. static void snd_ymfpci_pcm_capture_interrupt(snd_pcm_substream_t *substream)
  287. {
  288. snd_pcm_runtime_t *runtime = substream->runtime;
  289. ymfpci_pcm_t *ypcm = runtime->private_data;
  290. ymfpci_t *chip = ypcm->chip;
  291. u32 pos, delta;
  292. spin_lock(&chip->reg_lock);
  293. if (ypcm->running) {
  294. pos = le32_to_cpu(chip->bank_capture[ypcm->capture_bank_number][chip->active_bank]->start) >> ypcm->shift;
  295. if (pos < ypcm->last_pos)
  296. delta = pos + (ypcm->buffer_size - ypcm->last_pos);
  297. else
  298. delta = pos - ypcm->last_pos;
  299. ypcm->period_pos += delta;
  300. ypcm->last_pos = pos;
  301. if (ypcm->period_pos >= ypcm->period_size) {
  302. ypcm->period_pos %= ypcm->period_size;
  303. // printk("done - active_bank = 0x%x, start = 0x%x\n", chip->active_bank, voice->bank[chip->active_bank].start);
  304. spin_unlock(&chip->reg_lock);
  305. snd_pcm_period_elapsed(substream);
  306. spin_lock(&chip->reg_lock);
  307. }
  308. }
  309. spin_unlock(&chip->reg_lock);
  310. }
  311. static int snd_ymfpci_playback_trigger(snd_pcm_substream_t * substream,
  312. int cmd)
  313. {
  314. ymfpci_t *chip = snd_pcm_substream_chip(substream);
  315. ymfpci_pcm_t *ypcm = substream->runtime->private_data;
  316. int result = 0;
  317. spin_lock(&chip->reg_lock);
  318. if (ypcm->voices[0] == NULL) {
  319. result = -EINVAL;
  320. goto __unlock;
  321. }
  322. switch (cmd) {
  323. case SNDRV_PCM_TRIGGER_START:
  324. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  325. case SNDRV_PCM_TRIGGER_RESUME:
  326. chip->ctrl_playback[ypcm->voices[0]->number + 1] = cpu_to_le32(ypcm->voices[0]->bank_addr);
  327. if (ypcm->voices[1] != NULL)
  328. chip->ctrl_playback[ypcm->voices[1]->number + 1] = cpu_to_le32(ypcm->voices[1]->bank_addr);
  329. ypcm->running = 1;
  330. break;
  331. case SNDRV_PCM_TRIGGER_STOP:
  332. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  333. case SNDRV_PCM_TRIGGER_SUSPEND:
  334. chip->ctrl_playback[ypcm->voices[0]->number + 1] = 0;
  335. if (ypcm->voices[1] != NULL)
  336. chip->ctrl_playback[ypcm->voices[1]->number + 1] = 0;
  337. ypcm->running = 0;
  338. break;
  339. default:
  340. result = -EINVAL;
  341. break;
  342. }
  343. __unlock:
  344. spin_unlock(&chip->reg_lock);
  345. return result;
  346. }
  347. static int snd_ymfpci_capture_trigger(snd_pcm_substream_t * substream,
  348. int cmd)
  349. {
  350. ymfpci_t *chip = snd_pcm_substream_chip(substream);
  351. ymfpci_pcm_t *ypcm = substream->runtime->private_data;
  352. int result = 0;
  353. u32 tmp;
  354. spin_lock(&chip->reg_lock);
  355. switch (cmd) {
  356. case SNDRV_PCM_TRIGGER_START:
  357. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  358. case SNDRV_PCM_TRIGGER_RESUME:
  359. tmp = snd_ymfpci_readl(chip, YDSXGR_MAPOFREC) | (1 << ypcm->capture_bank_number);
  360. snd_ymfpci_writel(chip, YDSXGR_MAPOFREC, tmp);
  361. ypcm->running = 1;
  362. break;
  363. case SNDRV_PCM_TRIGGER_STOP:
  364. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  365. case SNDRV_PCM_TRIGGER_SUSPEND:
  366. tmp = snd_ymfpci_readl(chip, YDSXGR_MAPOFREC) & ~(1 << ypcm->capture_bank_number);
  367. snd_ymfpci_writel(chip, YDSXGR_MAPOFREC, tmp);
  368. ypcm->running = 0;
  369. break;
  370. default:
  371. result = -EINVAL;
  372. break;
  373. }
  374. spin_unlock(&chip->reg_lock);
  375. return result;
  376. }
  377. static int snd_ymfpci_pcm_voice_alloc(ymfpci_pcm_t *ypcm, int voices)
  378. {
  379. int err;
  380. if (ypcm->voices[1] != NULL && voices < 2) {
  381. snd_ymfpci_voice_free(ypcm->chip, ypcm->voices[1]);
  382. ypcm->voices[1] = NULL;
  383. }
  384. if (voices == 1 && ypcm->voices[0] != NULL)
  385. return 0; /* already allocated */
  386. if (voices == 2 && ypcm->voices[0] != NULL && ypcm->voices[1] != NULL)
  387. return 0; /* already allocated */
  388. if (voices > 1) {
  389. if (ypcm->voices[0] != NULL && ypcm->voices[1] == NULL) {
  390. snd_ymfpci_voice_free(ypcm->chip, ypcm->voices[0]);
  391. ypcm->voices[0] = NULL;
  392. }
  393. }
  394. err = snd_ymfpci_voice_alloc(ypcm->chip, YMFPCI_PCM, voices > 1, &ypcm->voices[0]);
  395. if (err < 0)
  396. return err;
  397. ypcm->voices[0]->ypcm = ypcm;
  398. ypcm->voices[0]->interrupt = snd_ymfpci_pcm_interrupt;
  399. if (voices > 1) {
  400. ypcm->voices[1] = &ypcm->chip->voices[ypcm->voices[0]->number + 1];
  401. ypcm->voices[1]->ypcm = ypcm;
  402. }
  403. return 0;
  404. }
  405. static void snd_ymfpci_pcm_init_voice(ymfpci_voice_t *voice, int stereo,
  406. int rate, int w_16, unsigned long addr,
  407. unsigned int end,
  408. int output_front, int output_rear)
  409. {
  410. u32 format;
  411. u32 delta = snd_ymfpci_calc_delta(rate);
  412. u32 lpfQ = snd_ymfpci_calc_lpfQ(rate);
  413. u32 lpfK = snd_ymfpci_calc_lpfK(rate);
  414. snd_ymfpci_playback_bank_t *bank;
  415. unsigned int nbank;
  416. snd_assert(voice != NULL, return);
  417. format = (stereo ? 0x00010000 : 0) | (w_16 ? 0 : 0x80000000);
  418. for (nbank = 0; nbank < 2; nbank++) {
  419. bank = &voice->bank[nbank];
  420. bank->format = cpu_to_le32(format);
  421. bank->loop_default = 0;
  422. bank->base = cpu_to_le32(addr);
  423. bank->loop_start = 0;
  424. bank->loop_end = cpu_to_le32(end);
  425. bank->loop_frac = 0;
  426. bank->eg_gain_end = cpu_to_le32(0x40000000);
  427. bank->lpfQ = cpu_to_le32(lpfQ);
  428. bank->status = 0;
  429. bank->num_of_frames = 0;
  430. bank->loop_count = 0;
  431. bank->start = 0;
  432. bank->start_frac = 0;
  433. bank->delta =
  434. bank->delta_end = cpu_to_le32(delta);
  435. bank->lpfK =
  436. bank->lpfK_end = cpu_to_le32(lpfK);
  437. bank->eg_gain = cpu_to_le32(0x40000000);
  438. bank->lpfD1 =
  439. bank->lpfD2 = 0;
  440. bank->left_gain =
  441. bank->right_gain =
  442. bank->left_gain_end =
  443. bank->right_gain_end =
  444. bank->eff1_gain =
  445. bank->eff2_gain =
  446. bank->eff3_gain =
  447. bank->eff1_gain_end =
  448. bank->eff2_gain_end =
  449. bank->eff3_gain_end = 0;
  450. if (!stereo) {
  451. if (output_front) {
  452. bank->left_gain =
  453. bank->right_gain =
  454. bank->left_gain_end =
  455. bank->right_gain_end = cpu_to_le32(0x40000000);
  456. }
  457. if (output_rear) {
  458. bank->eff2_gain =
  459. bank->eff2_gain_end =
  460. bank->eff3_gain =
  461. bank->eff3_gain_end = cpu_to_le32(0x40000000);
  462. }
  463. } else {
  464. if (output_front) {
  465. if ((voice->number & 1) == 0) {
  466. bank->left_gain =
  467. bank->left_gain_end = cpu_to_le32(0x40000000);
  468. } else {
  469. bank->format |= cpu_to_le32(1);
  470. bank->right_gain =
  471. bank->right_gain_end = cpu_to_le32(0x40000000);
  472. }
  473. }
  474. if (output_rear) {
  475. if ((voice->number & 1) == 0) {
  476. bank->eff3_gain =
  477. bank->eff3_gain_end = cpu_to_le32(0x40000000);
  478. } else {
  479. bank->format |= cpu_to_le32(1);
  480. bank->eff2_gain =
  481. bank->eff2_gain_end = cpu_to_le32(0x40000000);
  482. }
  483. }
  484. }
  485. }
  486. }
  487. static int __devinit snd_ymfpci_ac3_init(ymfpci_t *chip)
  488. {
  489. if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
  490. 4096, &chip->ac3_tmp_base) < 0)
  491. return -ENOMEM;
  492. chip->bank_effect[3][0]->base =
  493. chip->bank_effect[3][1]->base = cpu_to_le32(chip->ac3_tmp_base.addr);
  494. chip->bank_effect[3][0]->loop_end =
  495. chip->bank_effect[3][1]->loop_end = cpu_to_le32(1024);
  496. chip->bank_effect[4][0]->base =
  497. chip->bank_effect[4][1]->base = cpu_to_le32(chip->ac3_tmp_base.addr + 2048);
  498. chip->bank_effect[4][0]->loop_end =
  499. chip->bank_effect[4][1]->loop_end = cpu_to_le32(1024);
  500. spin_lock_irq(&chip->reg_lock);
  501. snd_ymfpci_writel(chip, YDSXGR_MAPOFEFFECT,
  502. snd_ymfpci_readl(chip, YDSXGR_MAPOFEFFECT) | 3 << 3);
  503. spin_unlock_irq(&chip->reg_lock);
  504. return 0;
  505. }
  506. static int snd_ymfpci_ac3_done(ymfpci_t *chip)
  507. {
  508. spin_lock_irq(&chip->reg_lock);
  509. snd_ymfpci_writel(chip, YDSXGR_MAPOFEFFECT,
  510. snd_ymfpci_readl(chip, YDSXGR_MAPOFEFFECT) & ~(3 << 3));
  511. spin_unlock_irq(&chip->reg_lock);
  512. // snd_ymfpci_irq_wait(chip);
  513. if (chip->ac3_tmp_base.area) {
  514. snd_dma_free_pages(&chip->ac3_tmp_base);
  515. chip->ac3_tmp_base.area = NULL;
  516. }
  517. return 0;
  518. }
  519. static int snd_ymfpci_playback_hw_params(snd_pcm_substream_t * substream,
  520. snd_pcm_hw_params_t * hw_params)
  521. {
  522. snd_pcm_runtime_t *runtime = substream->runtime;
  523. ymfpci_pcm_t *ypcm = runtime->private_data;
  524. int err;
  525. if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
  526. return err;
  527. if ((err = snd_ymfpci_pcm_voice_alloc(ypcm, params_channels(hw_params))) < 0)
  528. return err;
  529. return 0;
  530. }
  531. static int snd_ymfpci_playback_hw_free(snd_pcm_substream_t * substream)
  532. {
  533. ymfpci_t *chip = snd_pcm_substream_chip(substream);
  534. snd_pcm_runtime_t *runtime = substream->runtime;
  535. ymfpci_pcm_t *ypcm;
  536. if (runtime->private_data == NULL)
  537. return 0;
  538. ypcm = runtime->private_data;
  539. /* wait, until the PCI operations are not finished */
  540. snd_ymfpci_irq_wait(chip);
  541. snd_pcm_lib_free_pages(substream);
  542. if (ypcm->voices[1]) {
  543. snd_ymfpci_voice_free(chip, ypcm->voices[1]);
  544. ypcm->voices[1] = NULL;
  545. }
  546. if (ypcm->voices[0]) {
  547. snd_ymfpci_voice_free(chip, ypcm->voices[0]);
  548. ypcm->voices[0] = NULL;
  549. }
  550. return 0;
  551. }
  552. static int snd_ymfpci_playback_prepare(snd_pcm_substream_t * substream)
  553. {
  554. // ymfpci_t *chip = snd_pcm_substream_chip(substream);
  555. snd_pcm_runtime_t *runtime = substream->runtime;
  556. ymfpci_pcm_t *ypcm = runtime->private_data;
  557. unsigned int nvoice;
  558. ypcm->period_size = runtime->period_size;
  559. ypcm->buffer_size = runtime->buffer_size;
  560. ypcm->period_pos = 0;
  561. ypcm->last_pos = 0;
  562. for (nvoice = 0; nvoice < runtime->channels; nvoice++)
  563. snd_ymfpci_pcm_init_voice(ypcm->voices[nvoice],
  564. runtime->channels == 2,
  565. runtime->rate,
  566. snd_pcm_format_width(runtime->format) == 16,
  567. runtime->dma_addr,
  568. ypcm->buffer_size,
  569. ypcm->output_front,
  570. ypcm->output_rear);
  571. return 0;
  572. }
  573. static int snd_ymfpci_capture_hw_params(snd_pcm_substream_t * substream,
  574. snd_pcm_hw_params_t * hw_params)
  575. {
  576. return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
  577. }
  578. static int snd_ymfpci_capture_hw_free(snd_pcm_substream_t * substream)
  579. {
  580. ymfpci_t *chip = snd_pcm_substream_chip(substream);
  581. /* wait, until the PCI operations are not finished */
  582. snd_ymfpci_irq_wait(chip);
  583. return snd_pcm_lib_free_pages(substream);
  584. }
  585. static int snd_ymfpci_capture_prepare(snd_pcm_substream_t * substream)
  586. {
  587. ymfpci_t *chip = snd_pcm_substream_chip(substream);
  588. snd_pcm_runtime_t *runtime = substream->runtime;
  589. ymfpci_pcm_t *ypcm = runtime->private_data;
  590. snd_ymfpci_capture_bank_t * bank;
  591. int nbank;
  592. u32 rate, format;
  593. ypcm->period_size = runtime->period_size;
  594. ypcm->buffer_size = runtime->buffer_size;
  595. ypcm->period_pos = 0;
  596. ypcm->last_pos = 0;
  597. ypcm->shift = 0;
  598. rate = ((48000 * 4096) / runtime->rate) - 1;
  599. format = 0;
  600. if (runtime->channels == 2) {
  601. format |= 2;
  602. ypcm->shift++;
  603. }
  604. if (snd_pcm_format_width(runtime->format) == 8)
  605. format |= 1;
  606. else
  607. ypcm->shift++;
  608. switch (ypcm->capture_bank_number) {
  609. case 0:
  610. snd_ymfpci_writel(chip, YDSXGR_RECFORMAT, format);
  611. snd_ymfpci_writel(chip, YDSXGR_RECSLOTSR, rate);
  612. break;
  613. case 1:
  614. snd_ymfpci_writel(chip, YDSXGR_ADCFORMAT, format);
  615. snd_ymfpci_writel(chip, YDSXGR_ADCSLOTSR, rate);
  616. break;
  617. }
  618. for (nbank = 0; nbank < 2; nbank++) {
  619. bank = chip->bank_capture[ypcm->capture_bank_number][nbank];
  620. bank->base = cpu_to_le32(runtime->dma_addr);
  621. bank->loop_end = cpu_to_le32(ypcm->buffer_size << ypcm->shift);
  622. bank->start = 0;
  623. bank->num_of_loops = 0;
  624. }
  625. return 0;
  626. }
  627. static snd_pcm_uframes_t snd_ymfpci_playback_pointer(snd_pcm_substream_t * substream)
  628. {
  629. ymfpci_t *chip = snd_pcm_substream_chip(substream);
  630. snd_pcm_runtime_t *runtime = substream->runtime;
  631. ymfpci_pcm_t *ypcm = runtime->private_data;
  632. ymfpci_voice_t *voice = ypcm->voices[0];
  633. if (!(ypcm->running && voice))
  634. return 0;
  635. return le32_to_cpu(voice->bank[chip->active_bank].start);
  636. }
  637. static snd_pcm_uframes_t snd_ymfpci_capture_pointer(snd_pcm_substream_t * substream)
  638. {
  639. ymfpci_t *chip = snd_pcm_substream_chip(substream);
  640. snd_pcm_runtime_t *runtime = substream->runtime;
  641. ymfpci_pcm_t *ypcm = runtime->private_data;
  642. if (!ypcm->running)
  643. return 0;
  644. return le32_to_cpu(chip->bank_capture[ypcm->capture_bank_number][chip->active_bank]->start) >> ypcm->shift;
  645. }
  646. static void snd_ymfpci_irq_wait(ymfpci_t *chip)
  647. {
  648. wait_queue_t wait;
  649. int loops = 4;
  650. while (loops-- > 0) {
  651. if ((snd_ymfpci_readl(chip, YDSXGR_MODE) & 3) == 0)
  652. continue;
  653. init_waitqueue_entry(&wait, current);
  654. add_wait_queue(&chip->interrupt_sleep, &wait);
  655. atomic_inc(&chip->interrupt_sleep_count);
  656. set_current_state(TASK_UNINTERRUPTIBLE);
  657. schedule_timeout(HZ/20);
  658. remove_wait_queue(&chip->interrupt_sleep, &wait);
  659. }
  660. }
  661. static irqreturn_t snd_ymfpci_interrupt(int irq, void *dev_id, struct pt_regs *regs)
  662. {
  663. ymfpci_t *chip = dev_id;
  664. u32 status, nvoice, mode;
  665. ymfpci_voice_t *voice;
  666. status = snd_ymfpci_readl(chip, YDSXGR_STATUS);
  667. if (status & 0x80000000) {
  668. chip->active_bank = snd_ymfpci_readl(chip, YDSXGR_CTRLSELECT) & 1;
  669. spin_lock(&chip->voice_lock);
  670. for (nvoice = 0; nvoice < YDSXG_PLAYBACK_VOICES; nvoice++) {
  671. voice = &chip->voices[nvoice];
  672. if (voice->interrupt)
  673. voice->interrupt(chip, voice);
  674. }
  675. for (nvoice = 0; nvoice < YDSXG_CAPTURE_VOICES; nvoice++) {
  676. if (chip->capture_substream[nvoice])
  677. snd_ymfpci_pcm_capture_interrupt(chip->capture_substream[nvoice]);
  678. }
  679. #if 0
  680. for (nvoice = 0; nvoice < YDSXG_EFFECT_VOICES; nvoice++) {
  681. if (chip->effect_substream[nvoice])
  682. snd_ymfpci_pcm_effect_interrupt(chip->effect_substream[nvoice]);
  683. }
  684. #endif
  685. spin_unlock(&chip->voice_lock);
  686. spin_lock(&chip->reg_lock);
  687. snd_ymfpci_writel(chip, YDSXGR_STATUS, 0x80000000);
  688. mode = snd_ymfpci_readl(chip, YDSXGR_MODE) | 2;
  689. snd_ymfpci_writel(chip, YDSXGR_MODE, mode);
  690. spin_unlock(&chip->reg_lock);
  691. if (atomic_read(&chip->interrupt_sleep_count)) {
  692. atomic_set(&chip->interrupt_sleep_count, 0);
  693. wake_up(&chip->interrupt_sleep);
  694. }
  695. }
  696. status = snd_ymfpci_readw(chip, YDSXGR_INTFLAG);
  697. if (status & 1) {
  698. if (chip->timer)
  699. snd_timer_interrupt(chip->timer, chip->timer->sticks);
  700. }
  701. snd_ymfpci_writew(chip, YDSXGR_INTFLAG, status);
  702. if (chip->rawmidi)
  703. snd_mpu401_uart_interrupt(irq, chip->rawmidi->private_data, regs);
  704. return IRQ_HANDLED;
  705. }
  706. static snd_pcm_hardware_t snd_ymfpci_playback =
  707. {
  708. .info = (SNDRV_PCM_INFO_MMAP |
  709. SNDRV_PCM_INFO_MMAP_VALID |
  710. SNDRV_PCM_INFO_INTERLEAVED |
  711. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  712. SNDRV_PCM_INFO_PAUSE |
  713. SNDRV_PCM_INFO_RESUME),
  714. .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
  715. .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
  716. .rate_min = 8000,
  717. .rate_max = 48000,
  718. .channels_min = 1,
  719. .channels_max = 2,
  720. .buffer_bytes_max = 256 * 1024, /* FIXME: enough? */
  721. .period_bytes_min = 64,
  722. .period_bytes_max = 256 * 1024, /* FIXME: enough? */
  723. .periods_min = 3,
  724. .periods_max = 1024,
  725. .fifo_size = 0,
  726. };
  727. static snd_pcm_hardware_t snd_ymfpci_capture =
  728. {
  729. .info = (SNDRV_PCM_INFO_MMAP |
  730. SNDRV_PCM_INFO_MMAP_VALID |
  731. SNDRV_PCM_INFO_INTERLEAVED |
  732. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  733. SNDRV_PCM_INFO_PAUSE |
  734. SNDRV_PCM_INFO_RESUME),
  735. .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
  736. .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
  737. .rate_min = 8000,
  738. .rate_max = 48000,
  739. .channels_min = 1,
  740. .channels_max = 2,
  741. .buffer_bytes_max = 256 * 1024, /* FIXME: enough? */
  742. .period_bytes_min = 64,
  743. .period_bytes_max = 256 * 1024, /* FIXME: enough? */
  744. .periods_min = 3,
  745. .periods_max = 1024,
  746. .fifo_size = 0,
  747. };
  748. static void snd_ymfpci_pcm_free_substream(snd_pcm_runtime_t *runtime)
  749. {
  750. kfree(runtime->private_data);
  751. }
  752. static int snd_ymfpci_playback_open_1(snd_pcm_substream_t * substream)
  753. {
  754. ymfpci_t *chip = snd_pcm_substream_chip(substream);
  755. snd_pcm_runtime_t *runtime = substream->runtime;
  756. ymfpci_pcm_t *ypcm;
  757. ypcm = kcalloc(1, sizeof(*ypcm), GFP_KERNEL);
  758. if (ypcm == NULL)
  759. return -ENOMEM;
  760. ypcm->chip = chip;
  761. ypcm->type = PLAYBACK_VOICE;
  762. ypcm->substream = substream;
  763. runtime->hw = snd_ymfpci_playback;
  764. runtime->private_data = ypcm;
  765. runtime->private_free = snd_ymfpci_pcm_free_substream;
  766. /* FIXME? True value is 256/48 = 5.33333 ms */
  767. snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_PERIOD_TIME, 5333, UINT_MAX);
  768. return 0;
  769. }
  770. /* call with spinlock held */
  771. static void ymfpci_open_extension(ymfpci_t *chip)
  772. {
  773. if (! chip->rear_opened) {
  774. if (! chip->spdif_opened) /* set AC3 */
  775. snd_ymfpci_writel(chip, YDSXGR_MODE,
  776. snd_ymfpci_readl(chip, YDSXGR_MODE) | (1 << 30));
  777. /* enable second codec (4CHEN) */
  778. snd_ymfpci_writew(chip, YDSXGR_SECCONFIG,
  779. (snd_ymfpci_readw(chip, YDSXGR_SECCONFIG) & ~0x0330) | 0x0010);
  780. }
  781. }
  782. /* call with spinlock held */
  783. static void ymfpci_close_extension(ymfpci_t *chip)
  784. {
  785. if (! chip->rear_opened) {
  786. if (! chip->spdif_opened)
  787. snd_ymfpci_writel(chip, YDSXGR_MODE,
  788. snd_ymfpci_readl(chip, YDSXGR_MODE) & ~(1 << 30));
  789. snd_ymfpci_writew(chip, YDSXGR_SECCONFIG,
  790. (snd_ymfpci_readw(chip, YDSXGR_SECCONFIG) & ~0x0330) & ~0x0010);
  791. }
  792. }
  793. static int snd_ymfpci_playback_open(snd_pcm_substream_t * substream)
  794. {
  795. ymfpci_t *chip = snd_pcm_substream_chip(substream);
  796. snd_pcm_runtime_t *runtime = substream->runtime;
  797. ymfpci_pcm_t *ypcm;
  798. int err;
  799. if ((err = snd_ymfpci_playback_open_1(substream)) < 0)
  800. return err;
  801. ypcm = runtime->private_data;
  802. ypcm->output_front = 1;
  803. ypcm->output_rear = chip->mode_dup4ch ? 1 : 0;
  804. spin_lock_irq(&chip->reg_lock);
  805. if (ypcm->output_rear) {
  806. ymfpci_open_extension(chip);
  807. chip->rear_opened++;
  808. }
  809. spin_unlock_irq(&chip->reg_lock);
  810. return 0;
  811. }
  812. static int snd_ymfpci_playback_spdif_open(snd_pcm_substream_t * substream)
  813. {
  814. ymfpci_t *chip = snd_pcm_substream_chip(substream);
  815. snd_pcm_runtime_t *runtime = substream->runtime;
  816. ymfpci_pcm_t *ypcm;
  817. int err;
  818. if ((err = snd_ymfpci_playback_open_1(substream)) < 0)
  819. return err;
  820. ypcm = runtime->private_data;
  821. ypcm->output_front = 0;
  822. ypcm->output_rear = 1;
  823. spin_lock_irq(&chip->reg_lock);
  824. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTCTRL,
  825. snd_ymfpci_readw(chip, YDSXGR_SPDIFOUTCTRL) | 2);
  826. ymfpci_open_extension(chip);
  827. chip->spdif_pcm_bits = chip->spdif_bits;
  828. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTSTATUS, chip->spdif_pcm_bits);
  829. chip->spdif_opened++;
  830. spin_unlock_irq(&chip->reg_lock);
  831. chip->spdif_pcm_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
  832. snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE |
  833. SNDRV_CTL_EVENT_MASK_INFO, &chip->spdif_pcm_ctl->id);
  834. return 0;
  835. }
  836. static int snd_ymfpci_playback_4ch_open(snd_pcm_substream_t * substream)
  837. {
  838. ymfpci_t *chip = snd_pcm_substream_chip(substream);
  839. snd_pcm_runtime_t *runtime = substream->runtime;
  840. ymfpci_pcm_t *ypcm;
  841. int err;
  842. if ((err = snd_ymfpci_playback_open_1(substream)) < 0)
  843. return err;
  844. ypcm = runtime->private_data;
  845. ypcm->output_front = 0;
  846. ypcm->output_rear = 1;
  847. spin_lock_irq(&chip->reg_lock);
  848. ymfpci_open_extension(chip);
  849. chip->rear_opened++;
  850. spin_unlock_irq(&chip->reg_lock);
  851. return 0;
  852. }
  853. static int snd_ymfpci_capture_open(snd_pcm_substream_t * substream,
  854. u32 capture_bank_number)
  855. {
  856. ymfpci_t *chip = snd_pcm_substream_chip(substream);
  857. snd_pcm_runtime_t *runtime = substream->runtime;
  858. ymfpci_pcm_t *ypcm;
  859. ypcm = kcalloc(1, sizeof(*ypcm), GFP_KERNEL);
  860. if (ypcm == NULL)
  861. return -ENOMEM;
  862. ypcm->chip = chip;
  863. ypcm->type = capture_bank_number + CAPTURE_REC;
  864. ypcm->substream = substream;
  865. ypcm->capture_bank_number = capture_bank_number;
  866. chip->capture_substream[capture_bank_number] = substream;
  867. runtime->hw = snd_ymfpci_capture;
  868. /* FIXME? True value is 256/48 = 5.33333 ms */
  869. snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_PERIOD_TIME, 5333, UINT_MAX);
  870. runtime->private_data = ypcm;
  871. runtime->private_free = snd_ymfpci_pcm_free_substream;
  872. snd_ymfpci_hw_start(chip);
  873. return 0;
  874. }
  875. static int snd_ymfpci_capture_rec_open(snd_pcm_substream_t * substream)
  876. {
  877. return snd_ymfpci_capture_open(substream, 0);
  878. }
  879. static int snd_ymfpci_capture_ac97_open(snd_pcm_substream_t * substream)
  880. {
  881. return snd_ymfpci_capture_open(substream, 1);
  882. }
  883. static int snd_ymfpci_playback_close_1(snd_pcm_substream_t * substream)
  884. {
  885. return 0;
  886. }
  887. static int snd_ymfpci_playback_close(snd_pcm_substream_t * substream)
  888. {
  889. ymfpci_t *chip = snd_pcm_substream_chip(substream);
  890. ymfpci_pcm_t *ypcm = substream->runtime->private_data;
  891. spin_lock_irq(&chip->reg_lock);
  892. if (ypcm->output_rear && chip->rear_opened > 0) {
  893. chip->rear_opened--;
  894. ymfpci_close_extension(chip);
  895. }
  896. spin_unlock_irq(&chip->reg_lock);
  897. return snd_ymfpci_playback_close_1(substream);
  898. }
  899. static int snd_ymfpci_playback_spdif_close(snd_pcm_substream_t * substream)
  900. {
  901. ymfpci_t *chip = snd_pcm_substream_chip(substream);
  902. spin_lock_irq(&chip->reg_lock);
  903. chip->spdif_opened = 0;
  904. ymfpci_close_extension(chip);
  905. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTCTRL,
  906. snd_ymfpci_readw(chip, YDSXGR_SPDIFOUTCTRL) & ~2);
  907. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTSTATUS, chip->spdif_bits);
  908. spin_unlock_irq(&chip->reg_lock);
  909. chip->spdif_pcm_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
  910. snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE |
  911. SNDRV_CTL_EVENT_MASK_INFO, &chip->spdif_pcm_ctl->id);
  912. return snd_ymfpci_playback_close_1(substream);
  913. }
  914. static int snd_ymfpci_playback_4ch_close(snd_pcm_substream_t * substream)
  915. {
  916. ymfpci_t *chip = snd_pcm_substream_chip(substream);
  917. spin_lock_irq(&chip->reg_lock);
  918. if (chip->rear_opened > 0) {
  919. chip->rear_opened--;
  920. ymfpci_close_extension(chip);
  921. }
  922. spin_unlock_irq(&chip->reg_lock);
  923. return snd_ymfpci_playback_close_1(substream);
  924. }
  925. static int snd_ymfpci_capture_close(snd_pcm_substream_t * substream)
  926. {
  927. ymfpci_t *chip = snd_pcm_substream_chip(substream);
  928. snd_pcm_runtime_t *runtime = substream->runtime;
  929. ymfpci_pcm_t *ypcm = runtime->private_data;
  930. if (ypcm != NULL) {
  931. chip->capture_substream[ypcm->capture_bank_number] = NULL;
  932. snd_ymfpci_hw_stop(chip);
  933. }
  934. return 0;
  935. }
  936. static snd_pcm_ops_t snd_ymfpci_playback_ops = {
  937. .open = snd_ymfpci_playback_open,
  938. .close = snd_ymfpci_playback_close,
  939. .ioctl = snd_pcm_lib_ioctl,
  940. .hw_params = snd_ymfpci_playback_hw_params,
  941. .hw_free = snd_ymfpci_playback_hw_free,
  942. .prepare = snd_ymfpci_playback_prepare,
  943. .trigger = snd_ymfpci_playback_trigger,
  944. .pointer = snd_ymfpci_playback_pointer,
  945. };
  946. static snd_pcm_ops_t snd_ymfpci_capture_rec_ops = {
  947. .open = snd_ymfpci_capture_rec_open,
  948. .close = snd_ymfpci_capture_close,
  949. .ioctl = snd_pcm_lib_ioctl,
  950. .hw_params = snd_ymfpci_capture_hw_params,
  951. .hw_free = snd_ymfpci_capture_hw_free,
  952. .prepare = snd_ymfpci_capture_prepare,
  953. .trigger = snd_ymfpci_capture_trigger,
  954. .pointer = snd_ymfpci_capture_pointer,
  955. };
  956. static void snd_ymfpci_pcm_free(snd_pcm_t *pcm)
  957. {
  958. ymfpci_t *chip = pcm->private_data;
  959. chip->pcm = NULL;
  960. snd_pcm_lib_preallocate_free_for_all(pcm);
  961. }
  962. int __devinit snd_ymfpci_pcm(ymfpci_t *chip, int device, snd_pcm_t ** rpcm)
  963. {
  964. snd_pcm_t *pcm;
  965. int err;
  966. if (rpcm)
  967. *rpcm = NULL;
  968. if ((err = snd_pcm_new(chip->card, "YMFPCI", device, 32, 1, &pcm)) < 0)
  969. return err;
  970. pcm->private_data = chip;
  971. pcm->private_free = snd_ymfpci_pcm_free;
  972. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ymfpci_playback_ops);
  973. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ymfpci_capture_rec_ops);
  974. /* global setup */
  975. pcm->info_flags = 0;
  976. strcpy(pcm->name, "YMFPCI");
  977. chip->pcm = pcm;
  978. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  979. snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
  980. if (rpcm)
  981. *rpcm = pcm;
  982. return 0;
  983. }
  984. static snd_pcm_ops_t snd_ymfpci_capture_ac97_ops = {
  985. .open = snd_ymfpci_capture_ac97_open,
  986. .close = snd_ymfpci_capture_close,
  987. .ioctl = snd_pcm_lib_ioctl,
  988. .hw_params = snd_ymfpci_capture_hw_params,
  989. .hw_free = snd_ymfpci_capture_hw_free,
  990. .prepare = snd_ymfpci_capture_prepare,
  991. .trigger = snd_ymfpci_capture_trigger,
  992. .pointer = snd_ymfpci_capture_pointer,
  993. };
  994. static void snd_ymfpci_pcm2_free(snd_pcm_t *pcm)
  995. {
  996. ymfpci_t *chip = pcm->private_data;
  997. chip->pcm2 = NULL;
  998. snd_pcm_lib_preallocate_free_for_all(pcm);
  999. }
  1000. int __devinit snd_ymfpci_pcm2(ymfpci_t *chip, int device, snd_pcm_t ** rpcm)
  1001. {
  1002. snd_pcm_t *pcm;
  1003. int err;
  1004. if (rpcm)
  1005. *rpcm = NULL;
  1006. if ((err = snd_pcm_new(chip->card, "YMFPCI - PCM2", device, 0, 1, &pcm)) < 0)
  1007. return err;
  1008. pcm->private_data = chip;
  1009. pcm->private_free = snd_ymfpci_pcm2_free;
  1010. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ymfpci_capture_ac97_ops);
  1011. /* global setup */
  1012. pcm->info_flags = 0;
  1013. sprintf(pcm->name, "YMFPCI - %s",
  1014. chip->device_id == PCI_DEVICE_ID_YAMAHA_754 ? "Direct Recording" : "AC'97");
  1015. chip->pcm2 = pcm;
  1016. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  1017. snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
  1018. if (rpcm)
  1019. *rpcm = pcm;
  1020. return 0;
  1021. }
  1022. static snd_pcm_ops_t snd_ymfpci_playback_spdif_ops = {
  1023. .open = snd_ymfpci_playback_spdif_open,
  1024. .close = snd_ymfpci_playback_spdif_close,
  1025. .ioctl = snd_pcm_lib_ioctl,
  1026. .hw_params = snd_ymfpci_playback_hw_params,
  1027. .hw_free = snd_ymfpci_playback_hw_free,
  1028. .prepare = snd_ymfpci_playback_prepare,
  1029. .trigger = snd_ymfpci_playback_trigger,
  1030. .pointer = snd_ymfpci_playback_pointer,
  1031. };
  1032. static void snd_ymfpci_pcm_spdif_free(snd_pcm_t *pcm)
  1033. {
  1034. ymfpci_t *chip = pcm->private_data;
  1035. chip->pcm_spdif = NULL;
  1036. snd_pcm_lib_preallocate_free_for_all(pcm);
  1037. }
  1038. int __devinit snd_ymfpci_pcm_spdif(ymfpci_t *chip, int device, snd_pcm_t ** rpcm)
  1039. {
  1040. snd_pcm_t *pcm;
  1041. int err;
  1042. if (rpcm)
  1043. *rpcm = NULL;
  1044. if ((err = snd_pcm_new(chip->card, "YMFPCI - IEC958", device, 1, 0, &pcm)) < 0)
  1045. return err;
  1046. pcm->private_data = chip;
  1047. pcm->private_free = snd_ymfpci_pcm_spdif_free;
  1048. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ymfpci_playback_spdif_ops);
  1049. /* global setup */
  1050. pcm->info_flags = 0;
  1051. strcpy(pcm->name, "YMFPCI - IEC958");
  1052. chip->pcm_spdif = pcm;
  1053. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  1054. snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
  1055. if (rpcm)
  1056. *rpcm = pcm;
  1057. return 0;
  1058. }
  1059. static snd_pcm_ops_t snd_ymfpci_playback_4ch_ops = {
  1060. .open = snd_ymfpci_playback_4ch_open,
  1061. .close = snd_ymfpci_playback_4ch_close,
  1062. .ioctl = snd_pcm_lib_ioctl,
  1063. .hw_params = snd_ymfpci_playback_hw_params,
  1064. .hw_free = snd_ymfpci_playback_hw_free,
  1065. .prepare = snd_ymfpci_playback_prepare,
  1066. .trigger = snd_ymfpci_playback_trigger,
  1067. .pointer = snd_ymfpci_playback_pointer,
  1068. };
  1069. static void snd_ymfpci_pcm_4ch_free(snd_pcm_t *pcm)
  1070. {
  1071. ymfpci_t *chip = pcm->private_data;
  1072. chip->pcm_4ch = NULL;
  1073. snd_pcm_lib_preallocate_free_for_all(pcm);
  1074. }
  1075. int __devinit snd_ymfpci_pcm_4ch(ymfpci_t *chip, int device, snd_pcm_t ** rpcm)
  1076. {
  1077. snd_pcm_t *pcm;
  1078. int err;
  1079. if (rpcm)
  1080. *rpcm = NULL;
  1081. if ((err = snd_pcm_new(chip->card, "YMFPCI - Rear", device, 1, 0, &pcm)) < 0)
  1082. return err;
  1083. pcm->private_data = chip;
  1084. pcm->private_free = snd_ymfpci_pcm_4ch_free;
  1085. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ymfpci_playback_4ch_ops);
  1086. /* global setup */
  1087. pcm->info_flags = 0;
  1088. strcpy(pcm->name, "YMFPCI - Rear PCM");
  1089. chip->pcm_4ch = pcm;
  1090. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  1091. snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
  1092. if (rpcm)
  1093. *rpcm = pcm;
  1094. return 0;
  1095. }
  1096. static int snd_ymfpci_spdif_default_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
  1097. {
  1098. uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
  1099. uinfo->count = 1;
  1100. return 0;
  1101. }
  1102. static int snd_ymfpci_spdif_default_get(snd_kcontrol_t * kcontrol,
  1103. snd_ctl_elem_value_t * ucontrol)
  1104. {
  1105. ymfpci_t *chip = snd_kcontrol_chip(kcontrol);
  1106. spin_lock_irq(&chip->reg_lock);
  1107. ucontrol->value.iec958.status[0] = (chip->spdif_bits >> 0) & 0xff;
  1108. ucontrol->value.iec958.status[1] = (chip->spdif_bits >> 8) & 0xff;
  1109. spin_unlock_irq(&chip->reg_lock);
  1110. return 0;
  1111. }
  1112. static int snd_ymfpci_spdif_default_put(snd_kcontrol_t * kcontrol,
  1113. snd_ctl_elem_value_t * ucontrol)
  1114. {
  1115. ymfpci_t *chip = snd_kcontrol_chip(kcontrol);
  1116. unsigned int val;
  1117. int change;
  1118. val = ((ucontrol->value.iec958.status[0] & 0x3e) << 0) |
  1119. (ucontrol->value.iec958.status[1] << 8);
  1120. spin_lock_irq(&chip->reg_lock);
  1121. change = chip->spdif_bits != val;
  1122. chip->spdif_bits = val;
  1123. if ((snd_ymfpci_readw(chip, YDSXGR_SPDIFOUTCTRL) & 1) && chip->pcm_spdif == NULL)
  1124. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTSTATUS, chip->spdif_bits);
  1125. spin_unlock_irq(&chip->reg_lock);
  1126. return change;
  1127. }
  1128. static snd_kcontrol_new_t snd_ymfpci_spdif_default __devinitdata =
  1129. {
  1130. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1131. .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
  1132. .info = snd_ymfpci_spdif_default_info,
  1133. .get = snd_ymfpci_spdif_default_get,
  1134. .put = snd_ymfpci_spdif_default_put
  1135. };
  1136. static int snd_ymfpci_spdif_mask_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
  1137. {
  1138. uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
  1139. uinfo->count = 1;
  1140. return 0;
  1141. }
  1142. static int snd_ymfpci_spdif_mask_get(snd_kcontrol_t * kcontrol,
  1143. snd_ctl_elem_value_t * ucontrol)
  1144. {
  1145. ymfpci_t *chip = snd_kcontrol_chip(kcontrol);
  1146. spin_lock_irq(&chip->reg_lock);
  1147. ucontrol->value.iec958.status[0] = 0x3e;
  1148. ucontrol->value.iec958.status[1] = 0xff;
  1149. spin_unlock_irq(&chip->reg_lock);
  1150. return 0;
  1151. }
  1152. static snd_kcontrol_new_t snd_ymfpci_spdif_mask __devinitdata =
  1153. {
  1154. .access = SNDRV_CTL_ELEM_ACCESS_READ,
  1155. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1156. .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
  1157. .info = snd_ymfpci_spdif_mask_info,
  1158. .get = snd_ymfpci_spdif_mask_get,
  1159. };
  1160. static int snd_ymfpci_spdif_stream_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
  1161. {
  1162. uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
  1163. uinfo->count = 1;
  1164. return 0;
  1165. }
  1166. static int snd_ymfpci_spdif_stream_get(snd_kcontrol_t * kcontrol,
  1167. snd_ctl_elem_value_t * ucontrol)
  1168. {
  1169. ymfpci_t *chip = snd_kcontrol_chip(kcontrol);
  1170. spin_lock_irq(&chip->reg_lock);
  1171. ucontrol->value.iec958.status[0] = (chip->spdif_pcm_bits >> 0) & 0xff;
  1172. ucontrol->value.iec958.status[1] = (chip->spdif_pcm_bits >> 8) & 0xff;
  1173. spin_unlock_irq(&chip->reg_lock);
  1174. return 0;
  1175. }
  1176. static int snd_ymfpci_spdif_stream_put(snd_kcontrol_t * kcontrol,
  1177. snd_ctl_elem_value_t * ucontrol)
  1178. {
  1179. ymfpci_t *chip = snd_kcontrol_chip(kcontrol);
  1180. unsigned int val;
  1181. int change;
  1182. val = ((ucontrol->value.iec958.status[0] & 0x3e) << 0) |
  1183. (ucontrol->value.iec958.status[1] << 8);
  1184. spin_lock_irq(&chip->reg_lock);
  1185. change = chip->spdif_pcm_bits != val;
  1186. chip->spdif_pcm_bits = val;
  1187. if ((snd_ymfpci_readw(chip, YDSXGR_SPDIFOUTCTRL) & 2))
  1188. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTSTATUS, chip->spdif_pcm_bits);
  1189. spin_unlock_irq(&chip->reg_lock);
  1190. return change;
  1191. }
  1192. static snd_kcontrol_new_t snd_ymfpci_spdif_stream __devinitdata =
  1193. {
  1194. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
  1195. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1196. .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
  1197. .info = snd_ymfpci_spdif_stream_info,
  1198. .get = snd_ymfpci_spdif_stream_get,
  1199. .put = snd_ymfpci_spdif_stream_put
  1200. };
  1201. static int snd_ymfpci_drec_source_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *info)
  1202. {
  1203. static char *texts[3] = {"AC'97", "IEC958", "ZV Port"};
  1204. info->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
  1205. info->count = 1;
  1206. info->value.enumerated.items = 3;
  1207. if (info->value.enumerated.item > 2)
  1208. info->value.enumerated.item = 2;
  1209. strcpy(info->value.enumerated.name, texts[info->value.enumerated.item]);
  1210. return 0;
  1211. }
  1212. static int snd_ymfpci_drec_source_get(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *value)
  1213. {
  1214. ymfpci_t *chip = snd_kcontrol_chip(kcontrol);
  1215. u16 reg;
  1216. spin_lock_irq(&chip->reg_lock);
  1217. reg = snd_ymfpci_readw(chip, YDSXGR_GLOBALCTRL);
  1218. spin_unlock_irq(&chip->reg_lock);
  1219. if (!(reg & 0x100))
  1220. value->value.enumerated.item[0] = 0;
  1221. else
  1222. value->value.enumerated.item[0] = 1 + ((reg & 0x200) != 0);
  1223. return 0;
  1224. }
  1225. static int snd_ymfpci_drec_source_put(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *value)
  1226. {
  1227. ymfpci_t *chip = snd_kcontrol_chip(kcontrol);
  1228. u16 reg, old_reg;
  1229. spin_lock_irq(&chip->reg_lock);
  1230. old_reg = snd_ymfpci_readw(chip, YDSXGR_GLOBALCTRL);
  1231. if (value->value.enumerated.item[0] == 0)
  1232. reg = old_reg & ~0x100;
  1233. else
  1234. reg = (old_reg & ~0x300) | 0x100 | ((value->value.enumerated.item[0] == 2) << 9);
  1235. snd_ymfpci_writew(chip, YDSXGR_GLOBALCTRL, reg);
  1236. spin_unlock_irq(&chip->reg_lock);
  1237. return reg != old_reg;
  1238. }
  1239. static snd_kcontrol_new_t snd_ymfpci_drec_source __devinitdata = {
  1240. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
  1241. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1242. .name = "Direct Recording Source",
  1243. .info = snd_ymfpci_drec_source_info,
  1244. .get = snd_ymfpci_drec_source_get,
  1245. .put = snd_ymfpci_drec_source_put
  1246. };
  1247. /*
  1248. * Mixer controls
  1249. */
  1250. #define YMFPCI_SINGLE(xname, xindex, reg) \
  1251. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
  1252. .info = snd_ymfpci_info_single, \
  1253. .get = snd_ymfpci_get_single, .put = snd_ymfpci_put_single, \
  1254. .private_value = reg }
  1255. static int snd_ymfpci_info_single(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
  1256. {
  1257. switch (kcontrol->private_value) {
  1258. case YDSXGR_SPDIFOUTCTRL: break;
  1259. case YDSXGR_SPDIFINCTRL: break;
  1260. default: return -EINVAL;
  1261. }
  1262. uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
  1263. uinfo->count = 1;
  1264. uinfo->value.integer.min = 0;
  1265. uinfo->value.integer.max = 1;
  1266. return 0;
  1267. }
  1268. static int snd_ymfpci_get_single(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
  1269. {
  1270. ymfpci_t *chip = snd_kcontrol_chip(kcontrol);
  1271. int reg = kcontrol->private_value;
  1272. unsigned int shift = 0, mask = 1;
  1273. switch (kcontrol->private_value) {
  1274. case YDSXGR_SPDIFOUTCTRL: break;
  1275. case YDSXGR_SPDIFINCTRL: break;
  1276. default: return -EINVAL;
  1277. }
  1278. ucontrol->value.integer.value[0] = (snd_ymfpci_readl(chip, reg) >> shift) & mask;
  1279. return 0;
  1280. }
  1281. static int snd_ymfpci_put_single(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
  1282. {
  1283. ymfpci_t *chip = snd_kcontrol_chip(kcontrol);
  1284. int reg = kcontrol->private_value;
  1285. unsigned int shift = 0, mask = 1;
  1286. int change;
  1287. unsigned int val, oval;
  1288. switch (kcontrol->private_value) {
  1289. case YDSXGR_SPDIFOUTCTRL: break;
  1290. case YDSXGR_SPDIFINCTRL: break;
  1291. default: return -EINVAL;
  1292. }
  1293. val = (ucontrol->value.integer.value[0] & mask);
  1294. val <<= shift;
  1295. spin_lock_irq(&chip->reg_lock);
  1296. oval = snd_ymfpci_readl(chip, reg);
  1297. val = (oval & ~(mask << shift)) | val;
  1298. change = val != oval;
  1299. snd_ymfpci_writel(chip, reg, val);
  1300. spin_unlock_irq(&chip->reg_lock);
  1301. return change;
  1302. }
  1303. #define YMFPCI_DOUBLE(xname, xindex, reg) \
  1304. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
  1305. .info = snd_ymfpci_info_double, \
  1306. .get = snd_ymfpci_get_double, .put = snd_ymfpci_put_double, \
  1307. .private_value = reg }
  1308. static int snd_ymfpci_info_double(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
  1309. {
  1310. unsigned int reg = kcontrol->private_value;
  1311. if (reg < 0x80 || reg >= 0xc0)
  1312. return -EINVAL;
  1313. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  1314. uinfo->count = 2;
  1315. uinfo->value.integer.min = 0;
  1316. uinfo->value.integer.max = 16383;
  1317. return 0;
  1318. }
  1319. static int snd_ymfpci_get_double(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
  1320. {
  1321. ymfpci_t *chip = snd_kcontrol_chip(kcontrol);
  1322. unsigned int reg = kcontrol->private_value;
  1323. unsigned int shift_left = 0, shift_right = 16, mask = 16383;
  1324. unsigned int val;
  1325. if (reg < 0x80 || reg >= 0xc0)
  1326. return -EINVAL;
  1327. spin_lock_irq(&chip->reg_lock);
  1328. val = snd_ymfpci_readl(chip, reg);
  1329. spin_unlock_irq(&chip->reg_lock);
  1330. ucontrol->value.integer.value[0] = (val >> shift_left) & mask;
  1331. ucontrol->value.integer.value[1] = (val >> shift_right) & mask;
  1332. return 0;
  1333. }
  1334. static int snd_ymfpci_put_double(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
  1335. {
  1336. ymfpci_t *chip = snd_kcontrol_chip(kcontrol);
  1337. unsigned int reg = kcontrol->private_value;
  1338. unsigned int shift_left = 0, shift_right = 16, mask = 16383;
  1339. int change;
  1340. unsigned int val1, val2, oval;
  1341. if (reg < 0x80 || reg >= 0xc0)
  1342. return -EINVAL;
  1343. val1 = ucontrol->value.integer.value[0] & mask;
  1344. val2 = ucontrol->value.integer.value[1] & mask;
  1345. val1 <<= shift_left;
  1346. val2 <<= shift_right;
  1347. spin_lock_irq(&chip->reg_lock);
  1348. oval = snd_ymfpci_readl(chip, reg);
  1349. val1 = (oval & ~((mask << shift_left) | (mask << shift_right))) | val1 | val2;
  1350. change = val1 != oval;
  1351. snd_ymfpci_writel(chip, reg, val1);
  1352. spin_unlock_irq(&chip->reg_lock);
  1353. return change;
  1354. }
  1355. /*
  1356. * 4ch duplication
  1357. */
  1358. static int snd_ymfpci_info_dup4ch(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
  1359. {
  1360. uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
  1361. uinfo->count = 1;
  1362. uinfo->value.integer.min = 0;
  1363. uinfo->value.integer.max = 1;
  1364. return 0;
  1365. }
  1366. static int snd_ymfpci_get_dup4ch(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
  1367. {
  1368. ymfpci_t *chip = snd_kcontrol_chip(kcontrol);
  1369. ucontrol->value.integer.value[0] = chip->mode_dup4ch;
  1370. return 0;
  1371. }
  1372. static int snd_ymfpci_put_dup4ch(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
  1373. {
  1374. ymfpci_t *chip = snd_kcontrol_chip(kcontrol);
  1375. int change;
  1376. change = (ucontrol->value.integer.value[0] != chip->mode_dup4ch);
  1377. if (change)
  1378. chip->mode_dup4ch = !!ucontrol->value.integer.value[0];
  1379. return change;
  1380. }
  1381. static snd_kcontrol_new_t snd_ymfpci_controls[] __devinitdata = {
  1382. YMFPCI_DOUBLE("Wave Playback Volume", 0, YDSXGR_NATIVEDACOUTVOL),
  1383. YMFPCI_DOUBLE("Wave Capture Volume", 0, YDSXGR_NATIVEDACLOOPVOL),
  1384. YMFPCI_DOUBLE("Digital Capture Volume", 0, YDSXGR_NATIVEDACINVOL),
  1385. YMFPCI_DOUBLE("Digital Capture Volume", 1, YDSXGR_NATIVEADCINVOL),
  1386. YMFPCI_DOUBLE("ADC Playback Volume", 0, YDSXGR_PRIADCOUTVOL),
  1387. YMFPCI_DOUBLE("ADC Capture Volume", 0, YDSXGR_PRIADCLOOPVOL),
  1388. YMFPCI_DOUBLE("ADC Playback Volume", 1, YDSXGR_SECADCOUTVOL),
  1389. YMFPCI_DOUBLE("ADC Capture Volume", 1, YDSXGR_SECADCLOOPVOL),
  1390. YMFPCI_DOUBLE("FM Legacy Volume", 0, YDSXGR_LEGACYOUTVOL),
  1391. YMFPCI_DOUBLE(SNDRV_CTL_NAME_IEC958("AC97 ", PLAYBACK,VOLUME), 0, YDSXGR_ZVOUTVOL),
  1392. YMFPCI_DOUBLE(SNDRV_CTL_NAME_IEC958("", CAPTURE,VOLUME), 0, YDSXGR_ZVLOOPVOL),
  1393. YMFPCI_DOUBLE(SNDRV_CTL_NAME_IEC958("AC97 ",PLAYBACK,VOLUME), 1, YDSXGR_SPDIFOUTVOL),
  1394. YMFPCI_DOUBLE(SNDRV_CTL_NAME_IEC958("",CAPTURE,VOLUME), 1, YDSXGR_SPDIFLOOPVOL),
  1395. YMFPCI_SINGLE(SNDRV_CTL_NAME_IEC958("",PLAYBACK,SWITCH), 0, YDSXGR_SPDIFOUTCTRL),
  1396. YMFPCI_SINGLE(SNDRV_CTL_NAME_IEC958("",CAPTURE,SWITCH), 0, YDSXGR_SPDIFINCTRL),
  1397. {
  1398. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1399. .name = "4ch Duplication",
  1400. .info = snd_ymfpci_info_dup4ch,
  1401. .get = snd_ymfpci_get_dup4ch,
  1402. .put = snd_ymfpci_put_dup4ch,
  1403. },
  1404. };
  1405. /*
  1406. * GPIO
  1407. */
  1408. static int snd_ymfpci_get_gpio_out(ymfpci_t *chip, int pin)
  1409. {
  1410. u16 reg, mode;
  1411. unsigned long flags;
  1412. spin_lock_irqsave(&chip->reg_lock, flags);
  1413. reg = snd_ymfpci_readw(chip, YDSXGR_GPIOFUNCENABLE);
  1414. reg &= ~(1 << (pin + 8));
  1415. reg |= (1 << pin);
  1416. snd_ymfpci_writew(chip, YDSXGR_GPIOFUNCENABLE, reg);
  1417. /* set the level mode for input line */
  1418. mode = snd_ymfpci_readw(chip, YDSXGR_GPIOTYPECONFIG);
  1419. mode &= ~(3 << (pin * 2));
  1420. snd_ymfpci_writew(chip, YDSXGR_GPIOTYPECONFIG, mode);
  1421. snd_ymfpci_writew(chip, YDSXGR_GPIOFUNCENABLE, reg | (1 << (pin + 8)));
  1422. mode = snd_ymfpci_readw(chip, YDSXGR_GPIOINSTATUS);
  1423. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1424. return (mode >> pin) & 1;
  1425. }
  1426. static int snd_ymfpci_set_gpio_out(ymfpci_t *chip, int pin, int enable)
  1427. {
  1428. u16 reg;
  1429. unsigned long flags;
  1430. spin_lock_irqsave(&chip->reg_lock, flags);
  1431. reg = snd_ymfpci_readw(chip, YDSXGR_GPIOFUNCENABLE);
  1432. reg &= ~(1 << pin);
  1433. reg &= ~(1 << (pin + 8));
  1434. snd_ymfpci_writew(chip, YDSXGR_GPIOFUNCENABLE, reg);
  1435. snd_ymfpci_writew(chip, YDSXGR_GPIOOUTCTRL, enable << pin);
  1436. snd_ymfpci_writew(chip, YDSXGR_GPIOFUNCENABLE, reg | (1 << (pin + 8)));
  1437. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1438. return 0;
  1439. }
  1440. static int snd_ymfpci_gpio_sw_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
  1441. {
  1442. uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
  1443. uinfo->count = 1;
  1444. uinfo->value.integer.min = 0;
  1445. uinfo->value.integer.max = 1;
  1446. return 0;
  1447. }
  1448. static int snd_ymfpci_gpio_sw_get(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
  1449. {
  1450. ymfpci_t *chip = snd_kcontrol_chip(kcontrol);
  1451. int pin = (int)kcontrol->private_value;
  1452. ucontrol->value.integer.value[0] = snd_ymfpci_get_gpio_out(chip, pin);
  1453. return 0;
  1454. }
  1455. static int snd_ymfpci_gpio_sw_put(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
  1456. {
  1457. ymfpci_t *chip = snd_kcontrol_chip(kcontrol);
  1458. int pin = (int)kcontrol->private_value;
  1459. if (snd_ymfpci_get_gpio_out(chip, pin) != ucontrol->value.integer.value[0]) {
  1460. snd_ymfpci_set_gpio_out(chip, pin, !!ucontrol->value.integer.value[0]);
  1461. ucontrol->value.integer.value[0] = snd_ymfpci_get_gpio_out(chip, pin);
  1462. return 1;
  1463. }
  1464. return 0;
  1465. }
  1466. static snd_kcontrol_new_t snd_ymfpci_rear_shared __devinitdata = {
  1467. .name = "Shared Rear/Line-In Switch",
  1468. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1469. .info = snd_ymfpci_gpio_sw_info,
  1470. .get = snd_ymfpci_gpio_sw_get,
  1471. .put = snd_ymfpci_gpio_sw_put,
  1472. .private_value = 2,
  1473. };
  1474. /*
  1475. * Mixer routines
  1476. */
  1477. static void snd_ymfpci_mixer_free_ac97_bus(ac97_bus_t *bus)
  1478. {
  1479. ymfpci_t *chip = bus->private_data;
  1480. chip->ac97_bus = NULL;
  1481. }
  1482. static void snd_ymfpci_mixer_free_ac97(ac97_t *ac97)
  1483. {
  1484. ymfpci_t *chip = ac97->private_data;
  1485. chip->ac97 = NULL;
  1486. }
  1487. int __devinit snd_ymfpci_mixer(ymfpci_t *chip, int rear_switch)
  1488. {
  1489. ac97_template_t ac97;
  1490. snd_kcontrol_t *kctl;
  1491. unsigned int idx;
  1492. int err;
  1493. static ac97_bus_ops_t ops = {
  1494. .write = snd_ymfpci_codec_write,
  1495. .read = snd_ymfpci_codec_read,
  1496. };
  1497. if ((err = snd_ac97_bus(chip->card, 0, &ops, chip, &chip->ac97_bus)) < 0)
  1498. return err;
  1499. chip->ac97_bus->private_free = snd_ymfpci_mixer_free_ac97_bus;
  1500. chip->ac97_bus->no_vra = 1; /* YMFPCI doesn't need VRA */
  1501. memset(&ac97, 0, sizeof(ac97));
  1502. ac97.private_data = chip;
  1503. ac97.private_free = snd_ymfpci_mixer_free_ac97;
  1504. if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97)) < 0)
  1505. return err;
  1506. /* to be sure */
  1507. snd_ac97_update_bits(chip->ac97, AC97_EXTENDED_STATUS,
  1508. AC97_EA_VRA|AC97_EA_VRM, 0);
  1509. for (idx = 0; idx < ARRAY_SIZE(snd_ymfpci_controls); idx++) {
  1510. if ((err = snd_ctl_add(chip->card, snd_ctl_new1(&snd_ymfpci_controls[idx], chip))) < 0)
  1511. return err;
  1512. }
  1513. /* add S/PDIF control */
  1514. snd_assert(chip->pcm_spdif != NULL, return -EIO);
  1515. if ((err = snd_ctl_add(chip->card, kctl = snd_ctl_new1(&snd_ymfpci_spdif_default, chip))) < 0)
  1516. return err;
  1517. kctl->id.device = chip->pcm_spdif->device;
  1518. if ((err = snd_ctl_add(chip->card, kctl = snd_ctl_new1(&snd_ymfpci_spdif_mask, chip))) < 0)
  1519. return err;
  1520. kctl->id.device = chip->pcm_spdif->device;
  1521. if ((err = snd_ctl_add(chip->card, kctl = snd_ctl_new1(&snd_ymfpci_spdif_stream, chip))) < 0)
  1522. return err;
  1523. kctl->id.device = chip->pcm_spdif->device;
  1524. chip->spdif_pcm_ctl = kctl;
  1525. /* direct recording source */
  1526. if (chip->device_id == PCI_DEVICE_ID_YAMAHA_754 &&
  1527. (err = snd_ctl_add(chip->card, kctl = snd_ctl_new1(&snd_ymfpci_drec_source, chip))) < 0)
  1528. return err;
  1529. /*
  1530. * shared rear/line-in
  1531. */
  1532. if (rear_switch) {
  1533. if ((err = snd_ctl_add(chip->card, snd_ctl_new1(&snd_ymfpci_rear_shared, chip))) < 0)
  1534. return err;
  1535. }
  1536. return 0;
  1537. }
  1538. /*
  1539. * timer
  1540. */
  1541. static int snd_ymfpci_timer_start(snd_timer_t *timer)
  1542. {
  1543. ymfpci_t *chip;
  1544. unsigned long flags;
  1545. unsigned int count;
  1546. chip = snd_timer_chip(timer);
  1547. count = timer->sticks - 1;
  1548. if (count == 0) /* minimum time is 20.8 us */
  1549. count = 1;
  1550. spin_lock_irqsave(&chip->reg_lock, flags);
  1551. snd_ymfpci_writew(chip, YDSXGR_TIMERCOUNT, count);
  1552. snd_ymfpci_writeb(chip, YDSXGR_TIMERCTRL, 0x03);
  1553. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1554. return 0;
  1555. }
  1556. static int snd_ymfpci_timer_stop(snd_timer_t *timer)
  1557. {
  1558. ymfpci_t *chip;
  1559. unsigned long flags;
  1560. chip = snd_timer_chip(timer);
  1561. spin_lock_irqsave(&chip->reg_lock, flags);
  1562. snd_ymfpci_writeb(chip, YDSXGR_TIMERCTRL, 0x00);
  1563. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1564. return 0;
  1565. }
  1566. static int snd_ymfpci_timer_precise_resolution(snd_timer_t *timer,
  1567. unsigned long *num, unsigned long *den)
  1568. {
  1569. *num = 1;
  1570. *den = 96000;
  1571. return 0;
  1572. }
  1573. static struct _snd_timer_hardware snd_ymfpci_timer_hw = {
  1574. .flags = SNDRV_TIMER_HW_AUTO,
  1575. .resolution = 10417, /* 1/2fs = 10.41666...us */
  1576. .ticks = 65536,
  1577. .start = snd_ymfpci_timer_start,
  1578. .stop = snd_ymfpci_timer_stop,
  1579. .precise_resolution = snd_ymfpci_timer_precise_resolution,
  1580. };
  1581. int __devinit snd_ymfpci_timer(ymfpci_t *chip, int device)
  1582. {
  1583. snd_timer_t *timer = NULL;
  1584. snd_timer_id_t tid;
  1585. int err;
  1586. tid.dev_class = SNDRV_TIMER_CLASS_CARD;
  1587. tid.dev_sclass = SNDRV_TIMER_SCLASS_NONE;
  1588. tid.card = chip->card->number;
  1589. tid.device = device;
  1590. tid.subdevice = 0;
  1591. if ((err = snd_timer_new(chip->card, "YMFPCI", &tid, &timer)) >= 0) {
  1592. strcpy(timer->name, "YMFPCI timer");
  1593. timer->private_data = chip;
  1594. timer->hw = snd_ymfpci_timer_hw;
  1595. }
  1596. chip->timer = timer;
  1597. return err;
  1598. }
  1599. /*
  1600. * proc interface
  1601. */
  1602. static void snd_ymfpci_proc_read(snd_info_entry_t *entry,
  1603. snd_info_buffer_t * buffer)
  1604. {
  1605. ymfpci_t *chip = entry->private_data;
  1606. int i;
  1607. snd_iprintf(buffer, "YMFPCI\n\n");
  1608. for (i = 0; i <= YDSXGR_WORKBASE; i += 4)
  1609. snd_iprintf(buffer, "%04x: %04x\n", i, snd_ymfpci_readl(chip, i));
  1610. }
  1611. static int __devinit snd_ymfpci_proc_init(snd_card_t * card, ymfpci_t *chip)
  1612. {
  1613. snd_info_entry_t *entry;
  1614. if (! snd_card_proc_new(card, "ymfpci", &entry))
  1615. snd_info_set_text_ops(entry, chip, 1024, snd_ymfpci_proc_read);
  1616. return 0;
  1617. }
  1618. /*
  1619. * initialization routines
  1620. */
  1621. static void snd_ymfpci_aclink_reset(struct pci_dev * pci)
  1622. {
  1623. u8 cmd;
  1624. pci_read_config_byte(pci, PCIR_DSXG_CTRL, &cmd);
  1625. #if 0 // force to reset
  1626. if (cmd & 0x03) {
  1627. #endif
  1628. pci_write_config_byte(pci, PCIR_DSXG_CTRL, cmd & 0xfc);
  1629. pci_write_config_byte(pci, PCIR_DSXG_CTRL, cmd | 0x03);
  1630. pci_write_config_byte(pci, PCIR_DSXG_CTRL, cmd & 0xfc);
  1631. pci_write_config_word(pci, PCIR_DSXG_PWRCTRL1, 0);
  1632. pci_write_config_word(pci, PCIR_DSXG_PWRCTRL2, 0);
  1633. #if 0
  1634. }
  1635. #endif
  1636. }
  1637. static void snd_ymfpci_enable_dsp(ymfpci_t *chip)
  1638. {
  1639. snd_ymfpci_writel(chip, YDSXGR_CONFIG, 0x00000001);
  1640. }
  1641. static void snd_ymfpci_disable_dsp(ymfpci_t *chip)
  1642. {
  1643. u32 val;
  1644. int timeout = 1000;
  1645. val = snd_ymfpci_readl(chip, YDSXGR_CONFIG);
  1646. if (val)
  1647. snd_ymfpci_writel(chip, YDSXGR_CONFIG, 0x00000000);
  1648. while (timeout-- > 0) {
  1649. val = snd_ymfpci_readl(chip, YDSXGR_STATUS);
  1650. if ((val & 0x00000002) == 0)
  1651. break;
  1652. }
  1653. }
  1654. #include "ymfpci_image.h"
  1655. static void snd_ymfpci_download_image(ymfpci_t *chip)
  1656. {
  1657. int i;
  1658. u16 ctrl;
  1659. unsigned long *inst;
  1660. snd_ymfpci_writel(chip, YDSXGR_NATIVEDACOUTVOL, 0x00000000);
  1661. snd_ymfpci_disable_dsp(chip);
  1662. snd_ymfpci_writel(chip, YDSXGR_MODE, 0x00010000);
  1663. snd_ymfpci_writel(chip, YDSXGR_MODE, 0x00000000);
  1664. snd_ymfpci_writel(chip, YDSXGR_MAPOFREC, 0x00000000);
  1665. snd_ymfpci_writel(chip, YDSXGR_MAPOFEFFECT, 0x00000000);
  1666. snd_ymfpci_writel(chip, YDSXGR_PLAYCTRLBASE, 0x00000000);
  1667. snd_ymfpci_writel(chip, YDSXGR_RECCTRLBASE, 0x00000000);
  1668. snd_ymfpci_writel(chip, YDSXGR_EFFCTRLBASE, 0x00000000);
  1669. ctrl = snd_ymfpci_readw(chip, YDSXGR_GLOBALCTRL);
  1670. snd_ymfpci_writew(chip, YDSXGR_GLOBALCTRL, ctrl & ~0x0007);
  1671. /* setup DSP instruction code */
  1672. for (i = 0; i < YDSXG_DSPLENGTH / 4; i++)
  1673. snd_ymfpci_writel(chip, YDSXGR_DSPINSTRAM + (i << 2), DspInst[i]);
  1674. /* setup control instruction code */
  1675. switch (chip->device_id) {
  1676. case PCI_DEVICE_ID_YAMAHA_724F:
  1677. case PCI_DEVICE_ID_YAMAHA_740C:
  1678. case PCI_DEVICE_ID_YAMAHA_744:
  1679. case PCI_DEVICE_ID_YAMAHA_754:
  1680. inst = CntrlInst1E;
  1681. break;
  1682. default:
  1683. inst = CntrlInst;
  1684. break;
  1685. }
  1686. for (i = 0; i < YDSXG_CTRLLENGTH / 4; i++)
  1687. snd_ymfpci_writel(chip, YDSXGR_CTRLINSTRAM + (i << 2), inst[i]);
  1688. snd_ymfpci_enable_dsp(chip);
  1689. }
  1690. static int __devinit snd_ymfpci_memalloc(ymfpci_t *chip)
  1691. {
  1692. long size, playback_ctrl_size;
  1693. int voice, bank, reg;
  1694. u8 *ptr;
  1695. dma_addr_t ptr_addr;
  1696. playback_ctrl_size = 4 + 4 * YDSXG_PLAYBACK_VOICES;
  1697. chip->bank_size_playback = snd_ymfpci_readl(chip, YDSXGR_PLAYCTRLSIZE) << 2;
  1698. chip->bank_size_capture = snd_ymfpci_readl(chip, YDSXGR_RECCTRLSIZE) << 2;
  1699. chip->bank_size_effect = snd_ymfpci_readl(chip, YDSXGR_EFFCTRLSIZE) << 2;
  1700. chip->work_size = YDSXG_DEFAULT_WORK_SIZE;
  1701. size = ((playback_ctrl_size + 0x00ff) & ~0x00ff) +
  1702. ((chip->bank_size_playback * 2 * YDSXG_PLAYBACK_VOICES + 0x00ff) & ~0x00ff) +
  1703. ((chip->bank_size_capture * 2 * YDSXG_CAPTURE_VOICES + 0x00ff) & ~0x00ff) +
  1704. ((chip->bank_size_effect * 2 * YDSXG_EFFECT_VOICES + 0x00ff) & ~0x00ff) +
  1705. chip->work_size;
  1706. /* work_ptr must be aligned to 256 bytes, but it's already
  1707. covered with the kernel page allocation mechanism */
  1708. if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
  1709. size, &chip->work_ptr) < 0)
  1710. return -ENOMEM;
  1711. ptr = chip->work_ptr.area;
  1712. ptr_addr = chip->work_ptr.addr;
  1713. memset(ptr, 0, size); /* for sure */
  1714. chip->bank_base_playback = ptr;
  1715. chip->bank_base_playback_addr = ptr_addr;
  1716. chip->ctrl_playback = (u32 *)ptr;
  1717. chip->ctrl_playback[0] = cpu_to_le32(YDSXG_PLAYBACK_VOICES);
  1718. ptr += (playback_ctrl_size + 0x00ff) & ~0x00ff;
  1719. ptr_addr += (playback_ctrl_size + 0x00ff) & ~0x00ff;
  1720. for (voice = 0; voice < YDSXG_PLAYBACK_VOICES; voice++) {
  1721. chip->voices[voice].number = voice;
  1722. chip->voices[voice].bank = (snd_ymfpci_playback_bank_t *)ptr;
  1723. chip->voices[voice].bank_addr = ptr_addr;
  1724. for (bank = 0; bank < 2; bank++) {
  1725. chip->bank_playback[voice][bank] = (snd_ymfpci_playback_bank_t *)ptr;
  1726. ptr += chip->bank_size_playback;
  1727. ptr_addr += chip->bank_size_playback;
  1728. }
  1729. }
  1730. ptr = (char *)(((unsigned long)ptr + 0x00ff) & ~0x00ff);
  1731. ptr_addr = (ptr_addr + 0x00ff) & ~0x00ff;
  1732. chip->bank_base_capture = ptr;
  1733. chip->bank_base_capture_addr = ptr_addr;
  1734. for (voice = 0; voice < YDSXG_CAPTURE_VOICES; voice++)
  1735. for (bank = 0; bank < 2; bank++) {
  1736. chip->bank_capture[voice][bank] = (snd_ymfpci_capture_bank_t *)ptr;
  1737. ptr += chip->bank_size_capture;
  1738. ptr_addr += chip->bank_size_capture;
  1739. }
  1740. ptr = (char *)(((unsigned long)ptr + 0x00ff) & ~0x00ff);
  1741. ptr_addr = (ptr_addr + 0x00ff) & ~0x00ff;
  1742. chip->bank_base_effect = ptr;
  1743. chip->bank_base_effect_addr = ptr_addr;
  1744. for (voice = 0; voice < YDSXG_EFFECT_VOICES; voice++)
  1745. for (bank = 0; bank < 2; bank++) {
  1746. chip->bank_effect[voice][bank] = (snd_ymfpci_effect_bank_t *)ptr;
  1747. ptr += chip->bank_size_effect;
  1748. ptr_addr += chip->bank_size_effect;
  1749. }
  1750. ptr = (char *)(((unsigned long)ptr + 0x00ff) & ~0x00ff);
  1751. ptr_addr = (ptr_addr + 0x00ff) & ~0x00ff;
  1752. chip->work_base = ptr;
  1753. chip->work_base_addr = ptr_addr;
  1754. snd_assert(ptr + chip->work_size == chip->work_ptr.area + chip->work_ptr.bytes, );
  1755. snd_ymfpci_writel(chip, YDSXGR_PLAYCTRLBASE, chip->bank_base_playback_addr);
  1756. snd_ymfpci_writel(chip, YDSXGR_RECCTRLBASE, chip->bank_base_capture_addr);
  1757. snd_ymfpci_writel(chip, YDSXGR_EFFCTRLBASE, chip->bank_base_effect_addr);
  1758. snd_ymfpci_writel(chip, YDSXGR_WORKBASE, chip->work_base_addr);
  1759. snd_ymfpci_writel(chip, YDSXGR_WORKSIZE, chip->work_size >> 2);
  1760. /* S/PDIF output initialization */
  1761. chip->spdif_bits = chip->spdif_pcm_bits = SNDRV_PCM_DEFAULT_CON_SPDIF & 0xffff;
  1762. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTCTRL, 0);
  1763. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTSTATUS, chip->spdif_bits);
  1764. /* S/PDIF input initialization */
  1765. snd_ymfpci_writew(chip, YDSXGR_SPDIFINCTRL, 0);
  1766. /* digital mixer setup */
  1767. for (reg = 0x80; reg < 0xc0; reg += 4)
  1768. snd_ymfpci_writel(chip, reg, 0);
  1769. snd_ymfpci_writel(chip, YDSXGR_NATIVEDACOUTVOL, 0x3fff3fff);
  1770. snd_ymfpci_writel(chip, YDSXGR_ZVOUTVOL, 0x3fff3fff);
  1771. snd_ymfpci_writel(chip, YDSXGR_SPDIFOUTVOL, 0x3fff3fff);
  1772. snd_ymfpci_writel(chip, YDSXGR_NATIVEADCINVOL, 0x3fff3fff);
  1773. snd_ymfpci_writel(chip, YDSXGR_NATIVEDACINVOL, 0x3fff3fff);
  1774. snd_ymfpci_writel(chip, YDSXGR_PRIADCLOOPVOL, 0x3fff3fff);
  1775. snd_ymfpci_writel(chip, YDSXGR_LEGACYOUTVOL, 0x3fff3fff);
  1776. return 0;
  1777. }
  1778. static int snd_ymfpci_free(ymfpci_t *chip)
  1779. {
  1780. u16 ctrl;
  1781. snd_assert(chip != NULL, return -EINVAL);
  1782. if (chip->res_reg_area) { /* don't touch busy hardware */
  1783. snd_ymfpci_writel(chip, YDSXGR_NATIVEDACOUTVOL, 0);
  1784. snd_ymfpci_writel(chip, YDSXGR_BUF441OUTVOL, 0);
  1785. snd_ymfpci_writel(chip, YDSXGR_LEGACYOUTVOL, 0);
  1786. snd_ymfpci_writel(chip, YDSXGR_STATUS, ~0);
  1787. snd_ymfpci_disable_dsp(chip);
  1788. snd_ymfpci_writel(chip, YDSXGR_PLAYCTRLBASE, 0);
  1789. snd_ymfpci_writel(chip, YDSXGR_RECCTRLBASE, 0);
  1790. snd_ymfpci_writel(chip, YDSXGR_EFFCTRLBASE, 0);
  1791. snd_ymfpci_writel(chip, YDSXGR_WORKBASE, 0);
  1792. snd_ymfpci_writel(chip, YDSXGR_WORKSIZE, 0);
  1793. ctrl = snd_ymfpci_readw(chip, YDSXGR_GLOBALCTRL);
  1794. snd_ymfpci_writew(chip, YDSXGR_GLOBALCTRL, ctrl & ~0x0007);
  1795. }
  1796. snd_ymfpci_ac3_done(chip);
  1797. /* Set PCI device to D3 state */
  1798. #if 0
  1799. /* FIXME: temporarily disabled, otherwise we cannot fire up
  1800. * the chip again unless reboot. ACPI bug?
  1801. */
  1802. pci_set_power_state(chip->pci, 3);
  1803. #endif
  1804. #ifdef CONFIG_PM
  1805. vfree(chip->saved_regs);
  1806. #endif
  1807. if (chip->mpu_res) {
  1808. release_resource(chip->mpu_res);
  1809. kfree_nocheck(chip->mpu_res);
  1810. }
  1811. if (chip->fm_res) {
  1812. release_resource(chip->fm_res);
  1813. kfree_nocheck(chip->fm_res);
  1814. }
  1815. snd_ymfpci_free_gameport(chip);
  1816. if (chip->reg_area_virt)
  1817. iounmap(chip->reg_area_virt);
  1818. if (chip->work_ptr.area)
  1819. snd_dma_free_pages(&chip->work_ptr);
  1820. if (chip->irq >= 0)
  1821. free_irq(chip->irq, (void *)chip);
  1822. if (chip->res_reg_area) {
  1823. release_resource(chip->res_reg_area);
  1824. kfree_nocheck(chip->res_reg_area);
  1825. }
  1826. pci_write_config_word(chip->pci, 0x40, chip->old_legacy_ctrl);
  1827. pci_disable_device(chip->pci);
  1828. kfree(chip);
  1829. return 0;
  1830. }
  1831. static int snd_ymfpci_dev_free(snd_device_t *device)
  1832. {
  1833. ymfpci_t *chip = device->device_data;
  1834. return snd_ymfpci_free(chip);
  1835. }
  1836. #ifdef CONFIG_PM
  1837. static int saved_regs_index[] = {
  1838. /* spdif */
  1839. YDSXGR_SPDIFOUTCTRL,
  1840. YDSXGR_SPDIFOUTSTATUS,
  1841. YDSXGR_SPDIFINCTRL,
  1842. /* volumes */
  1843. YDSXGR_PRIADCLOOPVOL,
  1844. YDSXGR_NATIVEDACINVOL,
  1845. YDSXGR_NATIVEDACOUTVOL,
  1846. // YDSXGR_BUF441OUTVOL,
  1847. YDSXGR_NATIVEADCINVOL,
  1848. YDSXGR_SPDIFLOOPVOL,
  1849. YDSXGR_SPDIFOUTVOL,
  1850. YDSXGR_ZVOUTVOL,
  1851. YDSXGR_LEGACYOUTVOL,
  1852. /* address bases */
  1853. YDSXGR_PLAYCTRLBASE,
  1854. YDSXGR_RECCTRLBASE,
  1855. YDSXGR_EFFCTRLBASE,
  1856. YDSXGR_WORKBASE,
  1857. /* capture set up */
  1858. YDSXGR_MAPOFREC,
  1859. YDSXGR_RECFORMAT,
  1860. YDSXGR_RECSLOTSR,
  1861. YDSXGR_ADCFORMAT,
  1862. YDSXGR_ADCSLOTSR,
  1863. };
  1864. #define YDSXGR_NUM_SAVED_REGS ARRAY_SIZE(saved_regs_index)
  1865. static int snd_ymfpci_suspend(snd_card_t *card, pm_message_t state)
  1866. {
  1867. ymfpci_t *chip = card->pm_private_data;
  1868. unsigned int i;
  1869. snd_pcm_suspend_all(chip->pcm);
  1870. snd_pcm_suspend_all(chip->pcm2);
  1871. snd_pcm_suspend_all(chip->pcm_spdif);
  1872. snd_pcm_suspend_all(chip->pcm_4ch);
  1873. snd_ac97_suspend(chip->ac97);
  1874. for (i = 0; i < YDSXGR_NUM_SAVED_REGS; i++)
  1875. chip->saved_regs[i] = snd_ymfpci_readl(chip, saved_regs_index[i]);
  1876. chip->saved_ydsxgr_mode = snd_ymfpci_readl(chip, YDSXGR_MODE);
  1877. snd_ymfpci_writel(chip, YDSXGR_NATIVEDACOUTVOL, 0);
  1878. snd_ymfpci_disable_dsp(chip);
  1879. pci_disable_device(chip->pci);
  1880. return 0;
  1881. }
  1882. static int snd_ymfpci_resume(snd_card_t *card)
  1883. {
  1884. ymfpci_t *chip = card->pm_private_data;
  1885. unsigned int i;
  1886. pci_enable_device(chip->pci);
  1887. pci_set_master(chip->pci);
  1888. snd_ymfpci_aclink_reset(chip->pci);
  1889. snd_ymfpci_codec_ready(chip, 0);
  1890. snd_ymfpci_download_image(chip);
  1891. udelay(100);
  1892. for (i = 0; i < YDSXGR_NUM_SAVED_REGS; i++)
  1893. snd_ymfpci_writel(chip, saved_regs_index[i], chip->saved_regs[i]);
  1894. snd_ac97_resume(chip->ac97);
  1895. /* start hw again */
  1896. if (chip->start_count > 0) {
  1897. spin_lock_irq(&chip->reg_lock);
  1898. snd_ymfpci_writel(chip, YDSXGR_MODE, chip->saved_ydsxgr_mode);
  1899. chip->active_bank = snd_ymfpci_readl(chip, YDSXGR_CTRLSELECT);
  1900. spin_unlock_irq(&chip->reg_lock);
  1901. }
  1902. return 0;
  1903. }
  1904. #endif /* CONFIG_PM */
  1905. int __devinit snd_ymfpci_create(snd_card_t * card,
  1906. struct pci_dev * pci,
  1907. unsigned short old_legacy_ctrl,
  1908. ymfpci_t ** rchip)
  1909. {
  1910. ymfpci_t *chip;
  1911. int err;
  1912. static snd_device_ops_t ops = {
  1913. .dev_free = snd_ymfpci_dev_free,
  1914. };
  1915. *rchip = NULL;
  1916. /* enable PCI device */
  1917. if ((err = pci_enable_device(pci)) < 0)
  1918. return err;
  1919. chip = kcalloc(1, sizeof(*chip), GFP_KERNEL);
  1920. if (chip == NULL) {
  1921. pci_disable_device(pci);
  1922. return -ENOMEM;
  1923. }
  1924. chip->old_legacy_ctrl = old_legacy_ctrl;
  1925. spin_lock_init(&chip->reg_lock);
  1926. spin_lock_init(&chip->voice_lock);
  1927. init_waitqueue_head(&chip->interrupt_sleep);
  1928. atomic_set(&chip->interrupt_sleep_count, 0);
  1929. chip->card = card;
  1930. chip->pci = pci;
  1931. chip->irq = -1;
  1932. chip->device_id = pci->device;
  1933. pci_read_config_byte(pci, PCI_REVISION_ID, (u8 *)&chip->rev);
  1934. chip->reg_area_phys = pci_resource_start(pci, 0);
  1935. chip->reg_area_virt = ioremap_nocache(chip->reg_area_phys, 0x8000);
  1936. pci_set_master(pci);
  1937. if ((chip->res_reg_area = request_mem_region(chip->reg_area_phys, 0x8000, "YMFPCI")) == NULL) {
  1938. snd_printk("unable to grab memory region 0x%lx-0x%lx\n", chip->reg_area_phys, chip->reg_area_phys + 0x8000 - 1);
  1939. snd_ymfpci_free(chip);
  1940. return -EBUSY;
  1941. }
  1942. if (request_irq(pci->irq, snd_ymfpci_interrupt, SA_INTERRUPT|SA_SHIRQ, "YMFPCI", (void *) chip)) {
  1943. snd_printk("unable to grab IRQ %d\n", pci->irq);
  1944. snd_ymfpci_free(chip);
  1945. return -EBUSY;
  1946. }
  1947. chip->irq = pci->irq;
  1948. snd_ymfpci_aclink_reset(pci);
  1949. if (snd_ymfpci_codec_ready(chip, 0) < 0) {
  1950. snd_ymfpci_free(chip);
  1951. return -EIO;
  1952. }
  1953. snd_ymfpci_download_image(chip);
  1954. udelay(100); /* seems we need a delay after downloading image.. */
  1955. if (snd_ymfpci_memalloc(chip) < 0) {
  1956. snd_ymfpci_free(chip);
  1957. return -EIO;
  1958. }
  1959. if ((err = snd_ymfpci_ac3_init(chip)) < 0) {
  1960. snd_ymfpci_free(chip);
  1961. return err;
  1962. }
  1963. #ifdef CONFIG_PM
  1964. chip->saved_regs = vmalloc(YDSXGR_NUM_SAVED_REGS * sizeof(u32));
  1965. if (chip->saved_regs == NULL) {
  1966. snd_ymfpci_free(chip);
  1967. return -ENOMEM;
  1968. }
  1969. snd_card_set_pm_callback(card, snd_ymfpci_suspend, snd_ymfpci_resume, chip);
  1970. #endif
  1971. if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
  1972. snd_ymfpci_free(chip);
  1973. return err;
  1974. }
  1975. snd_ymfpci_proc_init(card, chip);
  1976. snd_card_set_dev(card, &pci->dev);
  1977. *rchip = chip;
  1978. return 0;
  1979. }