s3c2410.c 16 KB

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  1. /* linux/drivers/mtd/nand/s3c2410.c
  2. *
  3. * Copyright (c) 2004 Simtec Electronics
  4. * Ben Dooks <ben@simtec.co.uk>
  5. *
  6. * Samsung S3C2410 NAND driver
  7. *
  8. * Changelog:
  9. * 21-Sep-2004 BJD Initial version
  10. * 23-Sep-2004 BJD Mulitple device support
  11. * 28-Sep-2004 BJD Fixed ECC placement for Hardware mode
  12. * 12-Oct-2004 BJD Fixed errors in use of platform data
  13. *
  14. * $Id: s3c2410.c,v 1.7 2005/01/05 18:05:14 dwmw2 Exp $
  15. *
  16. * This program is free software; you can redistribute it and/or modify
  17. * it under the terms of the GNU General Public License as published by
  18. * the Free Software Foundation; either version 2 of the License, or
  19. * (at your option) any later version.
  20. *
  21. * This program is distributed in the hope that it will be useful,
  22. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  23. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  24. * GNU General Public License for more details.
  25. *
  26. * You should have received a copy of the GNU General Public License
  27. * along with this program; if not, write to the Free Software
  28. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  29. */
  30. #include <config/mtd/nand/s3c2410/hwecc.h>
  31. #include <config/mtd/nand/s3c2410/debug.h>
  32. #ifdef CONFIG_MTD_NAND_S3C2410_DEBUG
  33. #define DEBUG
  34. #endif
  35. #include <linux/module.h>
  36. #include <linux/types.h>
  37. #include <linux/init.h>
  38. #include <linux/kernel.h>
  39. #include <linux/string.h>
  40. #include <linux/ioport.h>
  41. #include <linux/device.h>
  42. #include <linux/delay.h>
  43. #include <linux/err.h>
  44. #include <linux/mtd/mtd.h>
  45. #include <linux/mtd/nand.h>
  46. #include <linux/mtd/nand_ecc.h>
  47. #include <linux/mtd/partitions.h>
  48. #include <asm/io.h>
  49. #include <asm/mach-types.h>
  50. #include <asm/hardware/clock.h>
  51. #include <asm/arch/regs-nand.h>
  52. #include <asm/arch/nand.h>
  53. #define PFX "s3c2410-nand: "
  54. #ifdef CONFIG_MTD_NAND_S3C2410_HWECC
  55. static int hardware_ecc = 1;
  56. #else
  57. static int hardware_ecc = 0;
  58. #endif
  59. /* new oob placement block for use with hardware ecc generation
  60. */
  61. static struct nand_oobinfo nand_hw_eccoob = {
  62. .useecc = MTD_NANDECC_AUTOPLACE,
  63. .eccbytes = 3,
  64. .eccpos = {0, 1, 2 },
  65. .oobfree = { {8, 8} }
  66. };
  67. /* controller and mtd information */
  68. struct s3c2410_nand_info;
  69. struct s3c2410_nand_mtd {
  70. struct mtd_info mtd;
  71. struct nand_chip chip;
  72. struct s3c2410_nand_set *set;
  73. struct s3c2410_nand_info *info;
  74. int scan_res;
  75. };
  76. /* overview of the s3c2410 nand state */
  77. struct s3c2410_nand_info {
  78. /* mtd info */
  79. struct nand_hw_control controller;
  80. struct s3c2410_nand_mtd *mtds;
  81. struct s3c2410_platform_nand *platform;
  82. /* device info */
  83. struct device *device;
  84. struct resource *area;
  85. struct clk *clk;
  86. void *regs;
  87. int mtd_count;
  88. };
  89. /* conversion functions */
  90. static struct s3c2410_nand_mtd *s3c2410_nand_mtd_toours(struct mtd_info *mtd)
  91. {
  92. return container_of(mtd, struct s3c2410_nand_mtd, mtd);
  93. }
  94. static struct s3c2410_nand_info *s3c2410_nand_mtd_toinfo(struct mtd_info *mtd)
  95. {
  96. return s3c2410_nand_mtd_toours(mtd)->info;
  97. }
  98. static struct s3c2410_nand_info *to_nand_info(struct device *dev)
  99. {
  100. return dev_get_drvdata(dev);
  101. }
  102. static struct s3c2410_platform_nand *to_nand_plat(struct device *dev)
  103. {
  104. return dev->platform_data;
  105. }
  106. /* timing calculations */
  107. #define NS_IN_KHZ 10000000
  108. static int s3c2410_nand_calc_rate(int wanted, unsigned long clk, int max)
  109. {
  110. int result;
  111. result = (wanted * NS_IN_KHZ) / clk;
  112. result++;
  113. pr_debug("result %d from %ld, %d\n", result, clk, wanted);
  114. if (result > max) {
  115. printk("%d ns is too big for current clock rate %ld\n",
  116. wanted, clk);
  117. return -1;
  118. }
  119. if (result < 1)
  120. result = 1;
  121. return result;
  122. }
  123. #define to_ns(ticks,clk) (((clk) * (ticks)) / NS_IN_KHZ)
  124. /* controller setup */
  125. static int s3c2410_nand_inithw(struct s3c2410_nand_info *info,
  126. struct device *dev)
  127. {
  128. struct s3c2410_platform_nand *plat = to_nand_plat(dev);
  129. unsigned int tacls, twrph0, twrph1;
  130. unsigned long clkrate = clk_get_rate(info->clk);
  131. unsigned long cfg;
  132. /* calculate the timing information for the controller */
  133. if (plat != NULL) {
  134. tacls = s3c2410_nand_calc_rate(plat->tacls, clkrate, 8);
  135. twrph0 = s3c2410_nand_calc_rate(plat->twrph0, clkrate, 8);
  136. twrph1 = s3c2410_nand_calc_rate(plat->twrph1, clkrate, 8);
  137. } else {
  138. /* default timings */
  139. tacls = 8;
  140. twrph0 = 8;
  141. twrph1 = 8;
  142. }
  143. if (tacls < 0 || twrph0 < 0 || twrph1 < 0) {
  144. printk(KERN_ERR PFX "cannot get timings suitable for board\n");
  145. return -EINVAL;
  146. }
  147. printk(KERN_INFO PFX "timing: Tacls %ldns, Twrph0 %ldns, Twrph1 %ldns\n",
  148. to_ns(tacls, clkrate),
  149. to_ns(twrph0, clkrate),
  150. to_ns(twrph1, clkrate));
  151. cfg = S3C2410_NFCONF_EN;
  152. cfg |= S3C2410_NFCONF_TACLS(tacls-1);
  153. cfg |= S3C2410_NFCONF_TWRPH0(twrph0-1);
  154. cfg |= S3C2410_NFCONF_TWRPH1(twrph1-1);
  155. pr_debug(PFX "NF_CONF is 0x%lx\n", cfg);
  156. writel(cfg, info->regs + S3C2410_NFCONF);
  157. return 0;
  158. }
  159. /* select chip */
  160. static void s3c2410_nand_select_chip(struct mtd_info *mtd, int chip)
  161. {
  162. struct s3c2410_nand_info *info;
  163. struct s3c2410_nand_mtd *nmtd;
  164. struct nand_chip *this = mtd->priv;
  165. unsigned long cur;
  166. nmtd = this->priv;
  167. info = nmtd->info;
  168. cur = readl(info->regs + S3C2410_NFCONF);
  169. if (chip == -1) {
  170. cur |= S3C2410_NFCONF_nFCE;
  171. } else {
  172. if (chip > nmtd->set->nr_chips) {
  173. printk(KERN_ERR PFX "chip %d out of range\n", chip);
  174. return;
  175. }
  176. if (info->platform != NULL) {
  177. if (info->platform->select_chip != NULL)
  178. (info->platform->select_chip)(nmtd->set, chip);
  179. }
  180. cur &= ~S3C2410_NFCONF_nFCE;
  181. }
  182. writel(cur, info->regs + S3C2410_NFCONF);
  183. }
  184. /* command and control functions */
  185. static void s3c2410_nand_hwcontrol(struct mtd_info *mtd, int cmd)
  186. {
  187. struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
  188. unsigned long cur;
  189. switch (cmd) {
  190. case NAND_CTL_SETNCE:
  191. cur = readl(info->regs + S3C2410_NFCONF);
  192. cur &= ~S3C2410_NFCONF_nFCE;
  193. writel(cur, info->regs + S3C2410_NFCONF);
  194. break;
  195. case NAND_CTL_CLRNCE:
  196. cur = readl(info->regs + S3C2410_NFCONF);
  197. cur |= S3C2410_NFCONF_nFCE;
  198. writel(cur, info->regs + S3C2410_NFCONF);
  199. break;
  200. /* we don't need to implement these */
  201. case NAND_CTL_SETCLE:
  202. case NAND_CTL_CLRCLE:
  203. case NAND_CTL_SETALE:
  204. case NAND_CTL_CLRALE:
  205. pr_debug(PFX "s3c2410_nand_hwcontrol(%d) unusedn", cmd);
  206. break;
  207. }
  208. }
  209. /* s3c2410_nand_command
  210. *
  211. * This function implements sending commands and the relevant address
  212. * information to the chip, via the hardware controller. Since the
  213. * S3C2410 generates the correct ALE/CLE signaling automatically, we
  214. * do not need to use hwcontrol.
  215. */
  216. static void s3c2410_nand_command (struct mtd_info *mtd, unsigned command,
  217. int column, int page_addr)
  218. {
  219. register struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
  220. register struct nand_chip *this = mtd->priv;
  221. /*
  222. * Write out the command to the device.
  223. */
  224. if (command == NAND_CMD_SEQIN) {
  225. int readcmd;
  226. if (column >= mtd->oobblock) {
  227. /* OOB area */
  228. column -= mtd->oobblock;
  229. readcmd = NAND_CMD_READOOB;
  230. } else if (column < 256) {
  231. /* First 256 bytes --> READ0 */
  232. readcmd = NAND_CMD_READ0;
  233. } else {
  234. column -= 256;
  235. readcmd = NAND_CMD_READ1;
  236. }
  237. writeb(readcmd, info->regs + S3C2410_NFCMD);
  238. }
  239. writeb(command, info->regs + S3C2410_NFCMD);
  240. /* Set ALE and clear CLE to start address cycle */
  241. if (column != -1 || page_addr != -1) {
  242. /* Serially input address */
  243. if (column != -1) {
  244. /* Adjust columns for 16 bit buswidth */
  245. if (this->options & NAND_BUSWIDTH_16)
  246. column >>= 1;
  247. writeb(column, info->regs + S3C2410_NFADDR);
  248. }
  249. if (page_addr != -1) {
  250. writeb((unsigned char) (page_addr), info->regs + S3C2410_NFADDR);
  251. writeb((unsigned char) (page_addr >> 8), info->regs + S3C2410_NFADDR);
  252. /* One more address cycle for higher density devices */
  253. if (this->chipsize & 0x0c000000)
  254. writeb((unsigned char) ((page_addr >> 16) & 0x0f),
  255. info->regs + S3C2410_NFADDR);
  256. }
  257. /* Latch in address */
  258. }
  259. /*
  260. * program and erase have their own busy handlers
  261. * status and sequential in needs no delay
  262. */
  263. switch (command) {
  264. case NAND_CMD_PAGEPROG:
  265. case NAND_CMD_ERASE1:
  266. case NAND_CMD_ERASE2:
  267. case NAND_CMD_SEQIN:
  268. case NAND_CMD_STATUS:
  269. return;
  270. case NAND_CMD_RESET:
  271. if (this->dev_ready)
  272. break;
  273. udelay(this->chip_delay);
  274. writeb(NAND_CMD_STATUS, info->regs + S3C2410_NFCMD);
  275. while ( !(this->read_byte(mtd) & 0x40));
  276. return;
  277. /* This applies to read commands */
  278. default:
  279. /*
  280. * If we don't have access to the busy pin, we apply the given
  281. * command delay
  282. */
  283. if (!this->dev_ready) {
  284. udelay (this->chip_delay);
  285. return;
  286. }
  287. }
  288. /* Apply this short delay always to ensure that we do wait tWB in
  289. * any case on any machine. */
  290. ndelay (100);
  291. /* wait until command is processed */
  292. while (!this->dev_ready(mtd));
  293. }
  294. /* s3c2410_nand_devready()
  295. *
  296. * returns 0 if the nand is busy, 1 if it is ready
  297. */
  298. static int s3c2410_nand_devready(struct mtd_info *mtd)
  299. {
  300. struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
  301. return readb(info->regs + S3C2410_NFSTAT) & S3C2410_NFSTAT_BUSY;
  302. }
  303. /* ECC handling functions */
  304. static int s3c2410_nand_correct_data(struct mtd_info *mtd, u_char *dat,
  305. u_char *read_ecc, u_char *calc_ecc)
  306. {
  307. pr_debug("s3c2410_nand_correct_data(%p,%p,%p,%p)\n",
  308. mtd, dat, read_ecc, calc_ecc);
  309. pr_debug("eccs: read %02x,%02x,%02x vs calc %02x,%02x,%02x\n",
  310. read_ecc[0], read_ecc[1], read_ecc[2],
  311. calc_ecc[0], calc_ecc[1], calc_ecc[2]);
  312. if (read_ecc[0] == calc_ecc[0] &&
  313. read_ecc[1] == calc_ecc[1] &&
  314. read_ecc[2] == calc_ecc[2])
  315. return 0;
  316. /* we curently have no method for correcting the error */
  317. return -1;
  318. }
  319. static void s3c2410_nand_enable_hwecc(struct mtd_info *mtd, int mode)
  320. {
  321. struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
  322. unsigned long ctrl;
  323. ctrl = readl(info->regs + S3C2410_NFCONF);
  324. ctrl |= S3C2410_NFCONF_INITECC;
  325. writel(ctrl, info->regs + S3C2410_NFCONF);
  326. }
  327. static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd,
  328. const u_char *dat, u_char *ecc_code)
  329. {
  330. struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
  331. ecc_code[0] = readb(info->regs + S3C2410_NFECC + 0);
  332. ecc_code[1] = readb(info->regs + S3C2410_NFECC + 1);
  333. ecc_code[2] = readb(info->regs + S3C2410_NFECC + 2);
  334. pr_debug("calculate_ecc: returning ecc %02x,%02x,%02x\n",
  335. ecc_code[0], ecc_code[1], ecc_code[2]);
  336. return 0;
  337. }
  338. /* over-ride the standard functions for a little more speed? */
  339. static void s3c2410_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
  340. {
  341. struct nand_chip *this = mtd->priv;
  342. readsb(this->IO_ADDR_R, buf, len);
  343. }
  344. static void s3c2410_nand_write_buf(struct mtd_info *mtd,
  345. const u_char *buf, int len)
  346. {
  347. struct nand_chip *this = mtd->priv;
  348. writesb(this->IO_ADDR_W, buf, len);
  349. }
  350. /* device management functions */
  351. static int s3c2410_nand_remove(struct device *dev)
  352. {
  353. struct s3c2410_nand_info *info = to_nand_info(dev);
  354. dev_set_drvdata(dev, NULL);
  355. if (info == NULL)
  356. return 0;
  357. /* first thing we need to do is release all our mtds
  358. * and their partitions, then go through freeing the
  359. * resources used
  360. */
  361. if (info->mtds != NULL) {
  362. struct s3c2410_nand_mtd *ptr = info->mtds;
  363. int mtdno;
  364. for (mtdno = 0; mtdno < info->mtd_count; mtdno++, ptr++) {
  365. pr_debug("releasing mtd %d (%p)\n", mtdno, ptr);
  366. nand_release(&ptr->mtd);
  367. }
  368. kfree(info->mtds);
  369. }
  370. /* free the common resources */
  371. if (info->clk != NULL && !IS_ERR(info->clk)) {
  372. clk_disable(info->clk);
  373. clk_unuse(info->clk);
  374. clk_put(info->clk);
  375. }
  376. if (info->regs != NULL) {
  377. iounmap(info->regs);
  378. info->regs = NULL;
  379. }
  380. if (info->area != NULL) {
  381. release_resource(info->area);
  382. kfree(info->area);
  383. info->area = NULL;
  384. }
  385. kfree(info);
  386. return 0;
  387. }
  388. #ifdef CONFIG_MTD_PARTITIONS
  389. static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info,
  390. struct s3c2410_nand_mtd *mtd,
  391. struct s3c2410_nand_set *set)
  392. {
  393. if (set == NULL)
  394. return add_mtd_device(&mtd->mtd);
  395. if (set->nr_partitions > 0 && set->partitions != NULL) {
  396. return add_mtd_partitions(&mtd->mtd,
  397. set->partitions,
  398. set->nr_partitions);
  399. }
  400. return add_mtd_device(&mtd->mtd);
  401. }
  402. #else
  403. static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info,
  404. struct s3c2410_nand_mtd *mtd,
  405. struct s3c2410_nand_set *set)
  406. {
  407. return add_mtd_device(&mtd->mtd);
  408. }
  409. #endif
  410. /* s3c2410_nand_init_chip
  411. *
  412. * init a single instance of an chip
  413. */
  414. static void s3c2410_nand_init_chip(struct s3c2410_nand_info *info,
  415. struct s3c2410_nand_mtd *nmtd,
  416. struct s3c2410_nand_set *set)
  417. {
  418. struct nand_chip *chip = &nmtd->chip;
  419. chip->IO_ADDR_R = (char *)info->regs + S3C2410_NFDATA;
  420. chip->IO_ADDR_W = (char *)info->regs + S3C2410_NFDATA;
  421. chip->hwcontrol = s3c2410_nand_hwcontrol;
  422. chip->dev_ready = s3c2410_nand_devready;
  423. chip->cmdfunc = s3c2410_nand_command;
  424. chip->write_buf = s3c2410_nand_write_buf;
  425. chip->read_buf = s3c2410_nand_read_buf;
  426. chip->select_chip = s3c2410_nand_select_chip;
  427. chip->chip_delay = 50;
  428. chip->priv = nmtd;
  429. chip->options = 0;
  430. chip->controller = &info->controller;
  431. nmtd->info = info;
  432. nmtd->mtd.priv = chip;
  433. nmtd->set = set;
  434. if (hardware_ecc) {
  435. chip->correct_data = s3c2410_nand_correct_data;
  436. chip->enable_hwecc = s3c2410_nand_enable_hwecc;
  437. chip->calculate_ecc = s3c2410_nand_calculate_ecc;
  438. chip->eccmode = NAND_ECC_HW3_512;
  439. chip->autooob = &nand_hw_eccoob;
  440. } else {
  441. chip->eccmode = NAND_ECC_SOFT;
  442. }
  443. }
  444. /* s3c2410_nand_probe
  445. *
  446. * called by device layer when it finds a device matching
  447. * one our driver can handled. This code checks to see if
  448. * it can allocate all necessary resources then calls the
  449. * nand layer to look for devices
  450. */
  451. static int s3c2410_nand_probe(struct device *dev)
  452. {
  453. struct platform_device *pdev = to_platform_device(dev);
  454. struct s3c2410_platform_nand *plat = to_nand_plat(dev);
  455. struct s3c2410_nand_info *info;
  456. struct s3c2410_nand_mtd *nmtd;
  457. struct s3c2410_nand_set *sets;
  458. struct resource *res;
  459. int err = 0;
  460. int size;
  461. int nr_sets;
  462. int setno;
  463. pr_debug("s3c2410_nand_probe(%p)\n", dev);
  464. info = kmalloc(sizeof(*info), GFP_KERNEL);
  465. if (info == NULL) {
  466. printk(KERN_ERR PFX "no memory for flash info\n");
  467. err = -ENOMEM;
  468. goto exit_error;
  469. }
  470. memzero(info, sizeof(*info));
  471. dev_set_drvdata(dev, info);
  472. spin_lock_init(&info->controller.lock);
  473. /* get the clock source and enable it */
  474. info->clk = clk_get(dev, "nand");
  475. if (IS_ERR(info->clk)) {
  476. printk(KERN_ERR PFX "failed to get clock");
  477. err = -ENOENT;
  478. goto exit_error;
  479. }
  480. clk_use(info->clk);
  481. clk_enable(info->clk);
  482. /* allocate and map the resource */
  483. res = pdev->resource; /* assume that the flash has one resource */
  484. size = res->end - res->start + 1;
  485. info->area = request_mem_region(res->start, size, pdev->name);
  486. if (info->area == NULL) {
  487. printk(KERN_ERR PFX "cannot reserve register region\n");
  488. err = -ENOENT;
  489. goto exit_error;
  490. }
  491. info->device = dev;
  492. info->platform = plat;
  493. info->regs = ioremap(res->start, size);
  494. if (info->regs == NULL) {
  495. printk(KERN_ERR PFX "cannot reserve register region\n");
  496. err = -EIO;
  497. goto exit_error;
  498. }
  499. printk(KERN_INFO PFX "mapped registers at %p\n", info->regs);
  500. /* initialise the hardware */
  501. err = s3c2410_nand_inithw(info, dev);
  502. if (err != 0)
  503. goto exit_error;
  504. sets = (plat != NULL) ? plat->sets : NULL;
  505. nr_sets = (plat != NULL) ? plat->nr_sets : 1;
  506. info->mtd_count = nr_sets;
  507. /* allocate our information */
  508. size = nr_sets * sizeof(*info->mtds);
  509. info->mtds = kmalloc(size, GFP_KERNEL);
  510. if (info->mtds == NULL) {
  511. printk(KERN_ERR PFX "failed to allocate mtd storage\n");
  512. err = -ENOMEM;
  513. goto exit_error;
  514. }
  515. memzero(info->mtds, size);
  516. /* initialise all possible chips */
  517. nmtd = info->mtds;
  518. for (setno = 0; setno < nr_sets; setno++, nmtd++) {
  519. pr_debug("initialising set %d (%p, info %p)\n",
  520. setno, nmtd, info);
  521. s3c2410_nand_init_chip(info, nmtd, sets);
  522. nmtd->scan_res = nand_scan(&nmtd->mtd,
  523. (sets) ? sets->nr_chips : 1);
  524. if (nmtd->scan_res == 0) {
  525. s3c2410_nand_add_partition(info, nmtd, sets);
  526. }
  527. if (sets != NULL)
  528. sets++;
  529. }
  530. pr_debug("initialised ok\n");
  531. return 0;
  532. exit_error:
  533. s3c2410_nand_remove(dev);
  534. if (err == 0)
  535. err = -EINVAL;
  536. return err;
  537. }
  538. static struct device_driver s3c2410_nand_driver = {
  539. .name = "s3c2410-nand",
  540. .bus = &platform_bus_type,
  541. .probe = s3c2410_nand_probe,
  542. .remove = s3c2410_nand_remove,
  543. };
  544. static int __init s3c2410_nand_init(void)
  545. {
  546. printk("S3C2410 NAND Driver, (c) 2004 Simtec Electronics\n");
  547. return driver_register(&s3c2410_nand_driver);
  548. }
  549. static void __exit s3c2410_nand_exit(void)
  550. {
  551. driver_unregister(&s3c2410_nand_driver);
  552. }
  553. module_init(s3c2410_nand_init);
  554. module_exit(s3c2410_nand_exit);
  555. MODULE_LICENSE("GPL");
  556. MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
  557. MODULE_DESCRIPTION("S3C2410 MTD NAND driver");