sis5513.c 28 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984
  1. /*
  2. * linux/drivers/ide/pci/sis5513.c Version 0.16ac+vp Jun 18, 2003
  3. *
  4. * Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org>
  5. * Copyright (C) 2002 Lionel Bouton <Lionel.Bouton@inet6.fr>, Maintainer
  6. * Copyright (C) 2003 Vojtech Pavlik <vojtech@suse.cz>
  7. * May be copied or modified under the terms of the GNU General Public License
  8. *
  9. *
  10. * Thanks :
  11. *
  12. * SiS Taiwan : for direct support and hardware.
  13. * Daniela Engert : for initial ATA100 advices and numerous others.
  14. * John Fremlin, Manfred Spraul, Dave Morgan, Peter Kjellerstedt :
  15. * for checking code correctness, providing patches.
  16. *
  17. *
  18. * Original tests and design on the SiS620 chipset.
  19. * ATA100 tests and design on the SiS735 chipset.
  20. * ATA16/33 support from specs
  21. * ATA133 support for SiS961/962 by L.C. Chang <lcchang@sis.com.tw>
  22. * ATA133 961/962/963 fixes by Vojtech Pavlik <vojtech@suse.cz>
  23. *
  24. * Documentation:
  25. * SiS chipset documentation available under NDA to companies only
  26. * (not to individuals).
  27. */
  28. /*
  29. * The original SiS5513 comes from a SiS5511/55112/5513 chipset. The original
  30. * SiS5513 was also used in the SiS5596/5513 chipset. Thus if we see a SiS5511
  31. * or SiS5596, we can assume we see the first MWDMA-16 capable SiS5513 chip.
  32. *
  33. * Later SiS chipsets integrated the 5513 functionality into the NorthBridge,
  34. * starting with SiS5571 and up to SiS745. The PCI ID didn't change, though. We
  35. * can figure out that we have a more modern and more capable 5513 by looking
  36. * for the respective NorthBridge IDs.
  37. *
  38. * Even later (96x family) SiS chipsets use the MuTIOL link and place the 5513
  39. * into the SouthBrige. Here we cannot rely on looking up the NorthBridge PCI
  40. * ID, while the now ATA-133 capable 5513 still has the same PCI ID.
  41. * Fortunately the 5513 can be 'unmasked' by fiddling with some config space
  42. * bits, changing its device id to the true one - 5517 for 961 and 5518 for
  43. * 962/963.
  44. */
  45. #include <linux/config.h>
  46. #include <linux/types.h>
  47. #include <linux/module.h>
  48. #include <linux/kernel.h>
  49. #include <linux/delay.h>
  50. #include <linux/timer.h>
  51. #include <linux/mm.h>
  52. #include <linux/ioport.h>
  53. #include <linux/blkdev.h>
  54. #include <linux/hdreg.h>
  55. #include <linux/interrupt.h>
  56. #include <linux/pci.h>
  57. #include <linux/init.h>
  58. #include <linux/ide.h>
  59. #include <asm/irq.h>
  60. #include "ide-timing.h"
  61. #define DISPLAY_SIS_TIMINGS
  62. /* registers layout and init values are chipset family dependant */
  63. #define ATA_16 0x01
  64. #define ATA_33 0x02
  65. #define ATA_66 0x03
  66. #define ATA_100a 0x04 // SiS730/SiS550 is ATA100 with ATA66 layout
  67. #define ATA_100 0x05
  68. #define ATA_133a 0x06 // SiS961b with 133 support
  69. #define ATA_133 0x07 // SiS962/963
  70. static u8 chipset_family;
  71. /*
  72. * Devices supported
  73. */
  74. static const struct {
  75. const char *name;
  76. u16 host_id;
  77. u8 chipset_family;
  78. u8 flags;
  79. } SiSHostChipInfo[] = {
  80. { "SiS745", PCI_DEVICE_ID_SI_745, ATA_100 },
  81. { "SiS735", PCI_DEVICE_ID_SI_735, ATA_100 },
  82. { "SiS733", PCI_DEVICE_ID_SI_733, ATA_100 },
  83. { "SiS635", PCI_DEVICE_ID_SI_635, ATA_100 },
  84. { "SiS633", PCI_DEVICE_ID_SI_633, ATA_100 },
  85. { "SiS730", PCI_DEVICE_ID_SI_730, ATA_100a },
  86. { "SiS550", PCI_DEVICE_ID_SI_550, ATA_100a },
  87. { "SiS640", PCI_DEVICE_ID_SI_640, ATA_66 },
  88. { "SiS630", PCI_DEVICE_ID_SI_630, ATA_66 },
  89. { "SiS620", PCI_DEVICE_ID_SI_620, ATA_66 },
  90. { "SiS540", PCI_DEVICE_ID_SI_540, ATA_66 },
  91. { "SiS530", PCI_DEVICE_ID_SI_530, ATA_66 },
  92. { "SiS5600", PCI_DEVICE_ID_SI_5600, ATA_33 },
  93. { "SiS5598", PCI_DEVICE_ID_SI_5598, ATA_33 },
  94. { "SiS5597", PCI_DEVICE_ID_SI_5597, ATA_33 },
  95. { "SiS5591/2", PCI_DEVICE_ID_SI_5591, ATA_33 },
  96. { "SiS5582", PCI_DEVICE_ID_SI_5582, ATA_33 },
  97. { "SiS5581", PCI_DEVICE_ID_SI_5581, ATA_33 },
  98. { "SiS5596", PCI_DEVICE_ID_SI_5596, ATA_16 },
  99. { "SiS5571", PCI_DEVICE_ID_SI_5571, ATA_16 },
  100. { "SiS551x", PCI_DEVICE_ID_SI_5511, ATA_16 },
  101. };
  102. /* Cycle time bits and values vary across chip dma capabilities
  103. These three arrays hold the register layout and the values to set.
  104. Indexed by chipset_family and (dma_mode - XFER_UDMA_0) */
  105. /* {0, ATA_16, ATA_33, ATA_66, ATA_100a, ATA_100, ATA_133} */
  106. static u8 cycle_time_offset[] = {0,0,5,4,4,0,0};
  107. static u8 cycle_time_range[] = {0,0,2,3,3,4,4};
  108. static u8 cycle_time_value[][XFER_UDMA_6 - XFER_UDMA_0 + 1] = {
  109. {0,0,0,0,0,0,0}, /* no udma */
  110. {0,0,0,0,0,0,0}, /* no udma */
  111. {3,2,1,0,0,0,0}, /* ATA_33 */
  112. {7,5,3,2,1,0,0}, /* ATA_66 */
  113. {7,5,3,2,1,0,0}, /* ATA_100a (730 specific), differences are on cycle_time range and offset */
  114. {11,7,5,4,2,1,0}, /* ATA_100 */
  115. {15,10,7,5,3,2,1}, /* ATA_133a (earliest 691 southbridges) */
  116. {15,10,7,5,3,2,1}, /* ATA_133 */
  117. };
  118. /* CRC Valid Setup Time vary across IDE clock setting 33/66/100/133
  119. See SiS962 data sheet for more detail */
  120. static u8 cvs_time_value[][XFER_UDMA_6 - XFER_UDMA_0 + 1] = {
  121. {0,0,0,0,0,0,0}, /* no udma */
  122. {0,0,0,0,0,0,0}, /* no udma */
  123. {2,1,1,0,0,0,0},
  124. {4,3,2,1,0,0,0},
  125. {4,3,2,1,0,0,0},
  126. {6,4,3,1,1,1,0},
  127. {9,6,4,2,2,2,2},
  128. {9,6,4,2,2,2,2},
  129. };
  130. /* Initialize time, Active time, Recovery time vary across
  131. IDE clock settings. These 3 arrays hold the register value
  132. for PIO0/1/2/3/4 and DMA0/1/2 mode in order */
  133. static u8 ini_time_value[][8] = {
  134. {0,0,0,0,0,0,0,0},
  135. {0,0,0,0,0,0,0,0},
  136. {2,1,0,0,0,1,0,0},
  137. {4,3,1,1,1,3,1,1},
  138. {4,3,1,1,1,3,1,1},
  139. {6,4,2,2,2,4,2,2},
  140. {9,6,3,3,3,6,3,3},
  141. {9,6,3,3,3,6,3,3},
  142. };
  143. static u8 act_time_value[][8] = {
  144. {0,0,0,0,0,0,0,0},
  145. {0,0,0,0,0,0,0,0},
  146. {9,9,9,2,2,7,2,2},
  147. {19,19,19,5,4,14,5,4},
  148. {19,19,19,5,4,14,5,4},
  149. {28,28,28,7,6,21,7,6},
  150. {38,38,38,10,9,28,10,9},
  151. {38,38,38,10,9,28,10,9},
  152. };
  153. static u8 rco_time_value[][8] = {
  154. {0,0,0,0,0,0,0,0},
  155. {0,0,0,0,0,0,0,0},
  156. {9,2,0,2,0,7,1,1},
  157. {19,5,1,5,2,16,3,2},
  158. {19,5,1,5,2,16,3,2},
  159. {30,9,3,9,4,25,6,4},
  160. {40,12,4,12,5,34,12,5},
  161. {40,12,4,12,5,34,12,5},
  162. };
  163. /*
  164. * Printing configuration
  165. */
  166. /* Used for chipset type printing at boot time */
  167. static char* chipset_capability[] = {
  168. "ATA", "ATA 16",
  169. "ATA 33", "ATA 66",
  170. "ATA 100 (1st gen)", "ATA 100 (2nd gen)",
  171. "ATA 133 (1st gen)", "ATA 133 (2nd gen)"
  172. };
  173. #if defined(DISPLAY_SIS_TIMINGS) && defined(CONFIG_PROC_FS)
  174. #include <linux/stat.h>
  175. #include <linux/proc_fs.h>
  176. static u8 sis_proc = 0;
  177. static struct pci_dev *bmide_dev;
  178. static char* cable_type[] = {
  179. "80 pins",
  180. "40 pins"
  181. };
  182. static char* recovery_time[] ={
  183. "12 PCICLK", "1 PCICLK",
  184. "2 PCICLK", "3 PCICLK",
  185. "4 PCICLK", "5 PCICLCK",
  186. "6 PCICLK", "7 PCICLCK",
  187. "8 PCICLK", "9 PCICLCK",
  188. "10 PCICLK", "11 PCICLK",
  189. "13 PCICLK", "14 PCICLK",
  190. "15 PCICLK", "15 PCICLK"
  191. };
  192. static char* active_time[] = {
  193. "8 PCICLK", "1 PCICLCK",
  194. "2 PCICLK", "3 PCICLK",
  195. "4 PCICLK", "5 PCICLK",
  196. "6 PCICLK", "12 PCICLK"
  197. };
  198. static char* cycle_time[] = {
  199. "Reserved", "2 CLK",
  200. "3 CLK", "4 CLK",
  201. "5 CLK", "6 CLK",
  202. "7 CLK", "8 CLK",
  203. "9 CLK", "10 CLK",
  204. "11 CLK", "12 CLK",
  205. "13 CLK", "14 CLK",
  206. "15 CLK", "16 CLK"
  207. };
  208. /* Generic add master or slave info function */
  209. static char* get_drives_info (char *buffer, u8 pos)
  210. {
  211. u8 reg00, reg01, reg10, reg11; /* timing registers */
  212. u32 regdw0, regdw1;
  213. char* p = buffer;
  214. /* Postwrite/Prefetch */
  215. if (chipset_family < ATA_133) {
  216. pci_read_config_byte(bmide_dev, 0x4b, &reg00);
  217. p += sprintf(p, "Drive %d: Postwrite %s \t \t Postwrite %s\n",
  218. pos, (reg00 & (0x10 << pos)) ? "Enabled" : "Disabled",
  219. (reg00 & (0x40 << pos)) ? "Enabled" : "Disabled");
  220. p += sprintf(p, " Prefetch %s \t \t Prefetch %s\n",
  221. (reg00 & (0x01 << pos)) ? "Enabled" : "Disabled",
  222. (reg00 & (0x04 << pos)) ? "Enabled" : "Disabled");
  223. pci_read_config_byte(bmide_dev, 0x40+2*pos, &reg00);
  224. pci_read_config_byte(bmide_dev, 0x41+2*pos, &reg01);
  225. pci_read_config_byte(bmide_dev, 0x44+2*pos, &reg10);
  226. pci_read_config_byte(bmide_dev, 0x45+2*pos, &reg11);
  227. } else {
  228. u32 reg54h;
  229. u8 drive_pci = 0x40;
  230. pci_read_config_dword(bmide_dev, 0x54, &reg54h);
  231. if (reg54h & 0x40000000) {
  232. // Configuration space remapped to 0x70
  233. drive_pci = 0x70;
  234. }
  235. pci_read_config_dword(bmide_dev, (unsigned long)drive_pci+4*pos, &regdw0);
  236. pci_read_config_dword(bmide_dev, (unsigned long)drive_pci+4*pos+8, &regdw1);
  237. p += sprintf(p, "Drive %d:\n", pos);
  238. }
  239. /* UDMA */
  240. if (chipset_family >= ATA_133) {
  241. p += sprintf(p, " UDMA %s \t \t \t UDMA %s\n",
  242. (regdw0 & 0x04) ? "Enabled" : "Disabled",
  243. (regdw1 & 0x04) ? "Enabled" : "Disabled");
  244. p += sprintf(p, " UDMA Cycle Time %s \t UDMA Cycle Time %s\n",
  245. cycle_time[(regdw0 & 0xF0) >> 4],
  246. cycle_time[(regdw1 & 0xF0) >> 4]);
  247. } else if (chipset_family >= ATA_33) {
  248. p += sprintf(p, " UDMA %s \t \t \t UDMA %s\n",
  249. (reg01 & 0x80) ? "Enabled" : "Disabled",
  250. (reg11 & 0x80) ? "Enabled" : "Disabled");
  251. p += sprintf(p, " UDMA Cycle Time ");
  252. switch(chipset_family) {
  253. case ATA_33: p += sprintf(p, cycle_time[(reg01 & 0x60) >> 5]); break;
  254. case ATA_66:
  255. case ATA_100a: p += sprintf(p, cycle_time[(reg01 & 0x70) >> 4]); break;
  256. case ATA_100:
  257. case ATA_133a: p += sprintf(p, cycle_time[reg01 & 0x0F]); break;
  258. default: p += sprintf(p, "?"); break;
  259. }
  260. p += sprintf(p, " \t UDMA Cycle Time ");
  261. switch(chipset_family) {
  262. case ATA_33: p += sprintf(p, cycle_time[(reg11 & 0x60) >> 5]); break;
  263. case ATA_66:
  264. case ATA_100a: p += sprintf(p, cycle_time[(reg11 & 0x70) >> 4]); break;
  265. case ATA_100:
  266. case ATA_133a: p += sprintf(p, cycle_time[reg11 & 0x0F]); break;
  267. default: p += sprintf(p, "?"); break;
  268. }
  269. p += sprintf(p, "\n");
  270. }
  271. if (chipset_family < ATA_133) { /* else case TODO */
  272. /* Data Active */
  273. p += sprintf(p, " Data Active Time ");
  274. switch(chipset_family) {
  275. case ATA_16: /* confirmed */
  276. case ATA_33:
  277. case ATA_66:
  278. case ATA_100a: p += sprintf(p, active_time[reg01 & 0x07]); break;
  279. case ATA_100:
  280. case ATA_133a: p += sprintf(p, active_time[(reg00 & 0x70) >> 4]); break;
  281. default: p += sprintf(p, "?"); break;
  282. }
  283. p += sprintf(p, " \t Data Active Time ");
  284. switch(chipset_family) {
  285. case ATA_16:
  286. case ATA_33:
  287. case ATA_66:
  288. case ATA_100a: p += sprintf(p, active_time[reg11 & 0x07]); break;
  289. case ATA_100:
  290. case ATA_133a: p += sprintf(p, active_time[(reg10 & 0x70) >> 4]); break;
  291. default: p += sprintf(p, "?"); break;
  292. }
  293. p += sprintf(p, "\n");
  294. /* Data Recovery */
  295. /* warning: may need (reg&0x07) for pre ATA66 chips */
  296. p += sprintf(p, " Data Recovery Time %s \t Data Recovery Time %s\n",
  297. recovery_time[reg00 & 0x0f], recovery_time[reg10 & 0x0f]);
  298. }
  299. return p;
  300. }
  301. static char* get_masters_info(char* buffer)
  302. {
  303. return get_drives_info(buffer, 0);
  304. }
  305. static char* get_slaves_info(char* buffer)
  306. {
  307. return get_drives_info(buffer, 1);
  308. }
  309. /* Main get_info, called on /proc/ide/sis reads */
  310. static int sis_get_info (char *buffer, char **addr, off_t offset, int count)
  311. {
  312. char *p = buffer;
  313. int len;
  314. u8 reg;
  315. u16 reg2, reg3;
  316. p += sprintf(p, "\nSiS 5513 ");
  317. switch(chipset_family) {
  318. case ATA_16: p += sprintf(p, "DMA 16"); break;
  319. case ATA_33: p += sprintf(p, "Ultra 33"); break;
  320. case ATA_66: p += sprintf(p, "Ultra 66"); break;
  321. case ATA_100a:
  322. case ATA_100: p += sprintf(p, "Ultra 100"); break;
  323. case ATA_133a:
  324. case ATA_133: p += sprintf(p, "Ultra 133"); break;
  325. default: p+= sprintf(p, "Unknown???"); break;
  326. }
  327. p += sprintf(p, " chipset\n");
  328. p += sprintf(p, "--------------- Primary Channel "
  329. "---------------- Secondary Channel "
  330. "-------------\n");
  331. /* Status */
  332. pci_read_config_byte(bmide_dev, 0x4a, &reg);
  333. if (chipset_family == ATA_133) {
  334. pci_read_config_word(bmide_dev, 0x50, &reg2);
  335. pci_read_config_word(bmide_dev, 0x52, &reg3);
  336. }
  337. p += sprintf(p, "Channel Status: ");
  338. if (chipset_family < ATA_66) {
  339. p += sprintf(p, "%s \t \t \t \t %s\n",
  340. (reg & 0x04) ? "On" : "Off",
  341. (reg & 0x02) ? "On" : "Off");
  342. } else if (chipset_family < ATA_133) {
  343. p += sprintf(p, "%s \t \t \t \t %s \n",
  344. (reg & 0x02) ? "On" : "Off",
  345. (reg & 0x04) ? "On" : "Off");
  346. } else { /* ATA_133 */
  347. p += sprintf(p, "%s \t \t \t \t %s \n",
  348. (reg2 & 0x02) ? "On" : "Off",
  349. (reg3 & 0x02) ? "On" : "Off");
  350. }
  351. /* Operation Mode */
  352. pci_read_config_byte(bmide_dev, 0x09, &reg);
  353. p += sprintf(p, "Operation Mode: %s \t \t \t %s \n",
  354. (reg & 0x01) ? "Native" : "Compatible",
  355. (reg & 0x04) ? "Native" : "Compatible");
  356. /* 80-pin cable ? */
  357. if (chipset_family >= ATA_133) {
  358. p += sprintf(p, "Cable Type: %s \t \t \t %s\n",
  359. (reg2 & 0x01) ? cable_type[1] : cable_type[0],
  360. (reg3 & 0x01) ? cable_type[1] : cable_type[0]);
  361. } else if (chipset_family > ATA_33) {
  362. pci_read_config_byte(bmide_dev, 0x48, &reg);
  363. p += sprintf(p, "Cable Type: %s \t \t \t %s\n",
  364. (reg & 0x10) ? cable_type[1] : cable_type[0],
  365. (reg & 0x20) ? cable_type[1] : cable_type[0]);
  366. }
  367. /* Prefetch Count */
  368. if (chipset_family < ATA_133) {
  369. pci_read_config_word(bmide_dev, 0x4c, &reg2);
  370. pci_read_config_word(bmide_dev, 0x4e, &reg3);
  371. p += sprintf(p, "Prefetch Count: %d \t \t \t \t %d\n",
  372. reg2, reg3);
  373. }
  374. p = get_masters_info(p);
  375. p = get_slaves_info(p);
  376. len = (p - buffer) - offset;
  377. *addr = buffer + offset;
  378. return len > count ? count : len;
  379. }
  380. #endif /* defined(DISPLAY_SIS_TIMINGS) && defined(CONFIG_PROC_FS) */
  381. static u8 sis5513_ratemask (ide_drive_t *drive)
  382. {
  383. u8 rates[] = { 0, 0, 1, 2, 3, 3, 4, 4 };
  384. u8 mode = rates[chipset_family];
  385. if (!eighty_ninty_three(drive))
  386. mode = min(mode, (u8)1);
  387. return mode;
  388. }
  389. /*
  390. * Configuration functions
  391. */
  392. /* Enables per-drive prefetch and postwrite */
  393. static void config_drive_art_rwp (ide_drive_t *drive)
  394. {
  395. ide_hwif_t *hwif = HWIF(drive);
  396. struct pci_dev *dev = hwif->pci_dev;
  397. u8 reg4bh = 0;
  398. u8 rw_prefetch = (0x11 << drive->dn);
  399. if (drive->media != ide_disk)
  400. return;
  401. pci_read_config_byte(dev, 0x4b, &reg4bh);
  402. if ((reg4bh & rw_prefetch) != rw_prefetch)
  403. pci_write_config_byte(dev, 0x4b, reg4bh|rw_prefetch);
  404. }
  405. /* Set per-drive active and recovery time */
  406. static void config_art_rwp_pio (ide_drive_t *drive, u8 pio)
  407. {
  408. ide_hwif_t *hwif = HWIF(drive);
  409. struct pci_dev *dev = hwif->pci_dev;
  410. u8 timing, drive_pci, test1, test2;
  411. u16 eide_pio_timing[6] = {600, 390, 240, 180, 120, 90};
  412. u16 xfer_pio = drive->id->eide_pio_modes;
  413. config_drive_art_rwp(drive);
  414. pio = ide_get_best_pio_mode(drive, 255, pio, NULL);
  415. if (xfer_pio> 4)
  416. xfer_pio = 0;
  417. if (drive->id->eide_pio_iordy > 0) {
  418. for (xfer_pio = 5;
  419. (xfer_pio > 0) &&
  420. (drive->id->eide_pio_iordy > eide_pio_timing[xfer_pio]);
  421. xfer_pio--);
  422. } else {
  423. xfer_pio = (drive->id->eide_pio_modes & 4) ? 0x05 :
  424. (drive->id->eide_pio_modes & 2) ? 0x04 :
  425. (drive->id->eide_pio_modes & 1) ? 0x03 : xfer_pio;
  426. }
  427. timing = (xfer_pio >= pio) ? xfer_pio : pio;
  428. /* In pre ATA_133 case, drives sit at 0x40 + 4*drive->dn */
  429. drive_pci = 0x40;
  430. /* In SiS962 case drives sit at (0x40 or 0x70) + 8*drive->dn) */
  431. if (chipset_family >= ATA_133) {
  432. u32 reg54h;
  433. pci_read_config_dword(dev, 0x54, &reg54h);
  434. if (reg54h & 0x40000000) drive_pci = 0x70;
  435. drive_pci += ((drive->dn)*0x4);
  436. } else {
  437. drive_pci += ((drive->dn)*0x2);
  438. }
  439. /* register layout changed with newer ATA100 chips */
  440. if (chipset_family < ATA_100) {
  441. pci_read_config_byte(dev, drive_pci, &test1);
  442. pci_read_config_byte(dev, drive_pci+1, &test2);
  443. /* Clear active and recovery timings */
  444. test1 &= ~0x0F;
  445. test2 &= ~0x07;
  446. switch(timing) {
  447. case 4: test1 |= 0x01; test2 |= 0x03; break;
  448. case 3: test1 |= 0x03; test2 |= 0x03; break;
  449. case 2: test1 |= 0x04; test2 |= 0x04; break;
  450. case 1: test1 |= 0x07; test2 |= 0x06; break;
  451. default: break;
  452. }
  453. pci_write_config_byte(dev, drive_pci, test1);
  454. pci_write_config_byte(dev, drive_pci+1, test2);
  455. } else if (chipset_family < ATA_133) {
  456. switch(timing) { /* active recovery
  457. v v */
  458. case 4: test1 = 0x30|0x01; break;
  459. case 3: test1 = 0x30|0x03; break;
  460. case 2: test1 = 0x40|0x04; break;
  461. case 1: test1 = 0x60|0x07; break;
  462. default: break;
  463. }
  464. pci_write_config_byte(dev, drive_pci, test1);
  465. } else { /* ATA_133 */
  466. u32 test3;
  467. pci_read_config_dword(dev, drive_pci, &test3);
  468. test3 &= 0xc0c00fff;
  469. if (test3 & 0x08) {
  470. test3 |= (unsigned long)ini_time_value[ATA_133][timing] << 12;
  471. test3 |= (unsigned long)act_time_value[ATA_133][timing] << 16;
  472. test3 |= (unsigned long)rco_time_value[ATA_133][timing] << 24;
  473. } else {
  474. test3 |= (unsigned long)ini_time_value[ATA_100][timing] << 12;
  475. test3 |= (unsigned long)act_time_value[ATA_100][timing] << 16;
  476. test3 |= (unsigned long)rco_time_value[ATA_100][timing] << 24;
  477. }
  478. pci_write_config_dword(dev, drive_pci, test3);
  479. }
  480. }
  481. static int config_chipset_for_pio (ide_drive_t *drive, u8 pio)
  482. {
  483. if (pio == 255)
  484. pio = ide_find_best_mode(drive, XFER_PIO | XFER_EPIO) - XFER_PIO_0;
  485. config_art_rwp_pio(drive, pio);
  486. return ide_config_drive_speed(drive, XFER_PIO_0 + min_t(u8, pio, 4));
  487. }
  488. static int sis5513_tune_chipset (ide_drive_t *drive, u8 xferspeed)
  489. {
  490. ide_hwif_t *hwif = HWIF(drive);
  491. struct pci_dev *dev = hwif->pci_dev;
  492. u8 drive_pci, reg, speed;
  493. u32 regdw;
  494. speed = ide_rate_filter(sis5513_ratemask(drive), xferspeed);
  495. /* See config_art_rwp_pio for drive pci config registers */
  496. drive_pci = 0x40;
  497. if (chipset_family >= ATA_133) {
  498. u32 reg54h;
  499. pci_read_config_dword(dev, 0x54, &reg54h);
  500. if (reg54h & 0x40000000) drive_pci = 0x70;
  501. drive_pci += ((drive->dn)*0x4);
  502. pci_read_config_dword(dev, (unsigned long)drive_pci, &regdw);
  503. /* Disable UDMA bit for non UDMA modes on UDMA chips */
  504. if (speed < XFER_UDMA_0) {
  505. regdw &= 0xfffffffb;
  506. pci_write_config_dword(dev, (unsigned long)drive_pci, regdw);
  507. }
  508. } else {
  509. drive_pci += ((drive->dn)*0x2);
  510. pci_read_config_byte(dev, drive_pci+1, &reg);
  511. /* Disable UDMA bit for non UDMA modes on UDMA chips */
  512. if ((speed < XFER_UDMA_0) && (chipset_family > ATA_16)) {
  513. reg &= 0x7F;
  514. pci_write_config_byte(dev, drive_pci+1, reg);
  515. }
  516. }
  517. /* Config chip for mode */
  518. switch(speed) {
  519. case XFER_UDMA_6:
  520. case XFER_UDMA_5:
  521. case XFER_UDMA_4:
  522. case XFER_UDMA_3:
  523. case XFER_UDMA_2:
  524. case XFER_UDMA_1:
  525. case XFER_UDMA_0:
  526. if (chipset_family >= ATA_133) {
  527. regdw |= 0x04;
  528. regdw &= 0xfffff00f;
  529. /* check if ATA133 enable */
  530. if (regdw & 0x08) {
  531. regdw |= (unsigned long)cycle_time_value[ATA_133][speed-XFER_UDMA_0] << 4;
  532. regdw |= (unsigned long)cvs_time_value[ATA_133][speed-XFER_UDMA_0] << 8;
  533. } else {
  534. /* if ATA133 disable, we should not set speed above UDMA5 */
  535. if (speed > XFER_UDMA_5)
  536. speed = XFER_UDMA_5;
  537. regdw |= (unsigned long)cycle_time_value[ATA_100][speed-XFER_UDMA_0] << 4;
  538. regdw |= (unsigned long)cvs_time_value[ATA_100][speed-XFER_UDMA_0] << 8;
  539. }
  540. pci_write_config_dword(dev, (unsigned long)drive_pci, regdw);
  541. } else {
  542. /* Force the UDMA bit on if we want to use UDMA */
  543. reg |= 0x80;
  544. /* clean reg cycle time bits */
  545. reg &= ~((0xFF >> (8 - cycle_time_range[chipset_family]))
  546. << cycle_time_offset[chipset_family]);
  547. /* set reg cycle time bits */
  548. reg |= cycle_time_value[chipset_family][speed-XFER_UDMA_0]
  549. << cycle_time_offset[chipset_family];
  550. pci_write_config_byte(dev, drive_pci+1, reg);
  551. }
  552. break;
  553. case XFER_MW_DMA_2:
  554. case XFER_MW_DMA_1:
  555. case XFER_MW_DMA_0:
  556. case XFER_SW_DMA_2:
  557. case XFER_SW_DMA_1:
  558. case XFER_SW_DMA_0:
  559. break;
  560. case XFER_PIO_4: return((int) config_chipset_for_pio(drive, 4));
  561. case XFER_PIO_3: return((int) config_chipset_for_pio(drive, 3));
  562. case XFER_PIO_2: return((int) config_chipset_for_pio(drive, 2));
  563. case XFER_PIO_1: return((int) config_chipset_for_pio(drive, 1));
  564. case XFER_PIO_0:
  565. default: return((int) config_chipset_for_pio(drive, 0));
  566. }
  567. return ((int) ide_config_drive_speed(drive, speed));
  568. }
  569. static void sis5513_tune_drive (ide_drive_t *drive, u8 pio)
  570. {
  571. (void) config_chipset_for_pio(drive, pio);
  572. }
  573. /*
  574. * ((id->hw_config & 0x4000|0x2000) && (HWIF(drive)->udma_four))
  575. */
  576. static int config_chipset_for_dma (ide_drive_t *drive)
  577. {
  578. u8 speed = ide_dma_speed(drive, sis5513_ratemask(drive));
  579. #ifdef DEBUG
  580. printk("SIS5513: config_chipset_for_dma, drive %d, ultra %x\n",
  581. drive->dn, drive->id->dma_ultra);
  582. #endif
  583. if (!(speed))
  584. return 0;
  585. sis5513_tune_chipset(drive, speed);
  586. return ide_dma_enable(drive);
  587. }
  588. static int sis5513_config_drive_xfer_rate (ide_drive_t *drive)
  589. {
  590. ide_hwif_t *hwif = HWIF(drive);
  591. struct hd_driveid *id = drive->id;
  592. drive->init_speed = 0;
  593. if (id && (id->capability & 1) && drive->autodma) {
  594. if (ide_use_dma(drive)) {
  595. if (config_chipset_for_dma(drive))
  596. return hwif->ide_dma_on(drive);
  597. }
  598. goto fast_ata_pio;
  599. } else if ((id->capability & 8) || (id->field_valid & 2)) {
  600. fast_ata_pio:
  601. sis5513_tune_drive(drive, 5);
  602. return hwif->ide_dma_off_quietly(drive);
  603. }
  604. /* IORDY not supported */
  605. return 0;
  606. }
  607. /* initiates/aborts (U)DMA read/write operations on a drive. */
  608. static int sis5513_config_xfer_rate (ide_drive_t *drive)
  609. {
  610. config_drive_art_rwp(drive);
  611. config_art_rwp_pio(drive, 5);
  612. return sis5513_config_drive_xfer_rate(drive);
  613. }
  614. /*
  615. Future simpler config_xfer_rate :
  616. When ide_find_best_mode is made bad-drive aware
  617. - remove config_drive_xfer_rate and config_chipset_for_dma,
  618. - replace config_xfer_rate with the following
  619. static int sis5513_config_xfer_rate (ide_drive_t *drive)
  620. {
  621. u16 w80 = HWIF(drive)->udma_four;
  622. u16 speed;
  623. config_drive_art_rwp(drive);
  624. config_art_rwp_pio(drive, 5);
  625. speed = ide_find_best_mode(drive,
  626. XFER_PIO | XFER_EPIO | XFER_SWDMA | XFER_MWDMA |
  627. (chipset_family >= ATA_33 ? XFER_UDMA : 0) |
  628. (w80 && chipset_family >= ATA_66 ? XFER_UDMA_66 : 0) |
  629. (w80 && chipset_family >= ATA_100a ? XFER_UDMA_100 : 0) |
  630. (w80 && chipset_family >= ATA_133a ? XFER_UDMA_133 : 0));
  631. sis5513_tune_chipset(drive, speed);
  632. if (drive->autodma && (speed & XFER_MODE) != XFER_PIO)
  633. return HWIF(drive)->ide_dma_on(drive);
  634. return HWIF(drive)->ide_dma_off_quietly(drive);
  635. }
  636. */
  637. /* Chip detection and general config */
  638. static unsigned int __devinit init_chipset_sis5513 (struct pci_dev *dev, const char *name)
  639. {
  640. struct pci_dev *host;
  641. int i = 0;
  642. chipset_family = 0;
  643. for (i = 0; i < ARRAY_SIZE(SiSHostChipInfo) && !chipset_family; i++) {
  644. host = pci_find_device(PCI_VENDOR_ID_SI, SiSHostChipInfo[i].host_id, NULL);
  645. if (!host)
  646. continue;
  647. chipset_family = SiSHostChipInfo[i].chipset_family;
  648. /* Special case for SiS630 : 630S/ET is ATA_100a */
  649. if (SiSHostChipInfo[i].host_id == PCI_DEVICE_ID_SI_630) {
  650. u8 hostrev;
  651. pci_read_config_byte(host, PCI_REVISION_ID, &hostrev);
  652. if (hostrev >= 0x30)
  653. chipset_family = ATA_100a;
  654. }
  655. printk(KERN_INFO "SIS5513: %s %s controller\n",
  656. SiSHostChipInfo[i].name, chipset_capability[chipset_family]);
  657. }
  658. if (!chipset_family) { /* Belongs to pci-quirks */
  659. u32 idemisc;
  660. u16 trueid;
  661. /* Disable ID masking and register remapping */
  662. pci_read_config_dword(dev, 0x54, &idemisc);
  663. pci_write_config_dword(dev, 0x54, (idemisc & 0x7fffffff));
  664. pci_read_config_word(dev, PCI_DEVICE_ID, &trueid);
  665. pci_write_config_dword(dev, 0x54, idemisc);
  666. if (trueid == 0x5518) {
  667. printk(KERN_INFO "SIS5513: SiS 962/963 MuTIOL IDE UDMA133 controller\n");
  668. chipset_family = ATA_133;
  669. /* Check for 5513 compability mapping
  670. * We must use this, else the port enabled code will fail,
  671. * as it expects the enablebits at 0x4a.
  672. */
  673. if ((idemisc & 0x40000000) == 0) {
  674. pci_write_config_dword(dev, 0x54, idemisc | 0x40000000);
  675. printk(KERN_INFO "SIS5513: Switching to 5513 register mapping\n");
  676. }
  677. }
  678. }
  679. if (!chipset_family) { /* Belongs to pci-quirks */
  680. struct pci_dev *lpc_bridge;
  681. u16 trueid;
  682. u8 prefctl;
  683. u8 idecfg;
  684. u8 sbrev;
  685. pci_read_config_byte(dev, 0x4a, &idecfg);
  686. pci_write_config_byte(dev, 0x4a, idecfg | 0x10);
  687. pci_read_config_word(dev, PCI_DEVICE_ID, &trueid);
  688. pci_write_config_byte(dev, 0x4a, idecfg);
  689. if (trueid == 0x5517) { /* SiS 961/961B */
  690. lpc_bridge = pci_find_slot(0x00, 0x10); /* Bus 0, Dev 2, Fn 0 */
  691. pci_read_config_byte(lpc_bridge, PCI_REVISION_ID, &sbrev);
  692. pci_read_config_byte(dev, 0x49, &prefctl);
  693. if (sbrev == 0x10 && (prefctl & 0x80)) {
  694. printk(KERN_INFO "SIS5513: SiS 961B MuTIOL IDE UDMA133 controller\n");
  695. chipset_family = ATA_133a;
  696. } else {
  697. printk(KERN_INFO "SIS5513: SiS 961 MuTIOL IDE UDMA100 controller\n");
  698. chipset_family = ATA_100;
  699. }
  700. }
  701. }
  702. if (!chipset_family)
  703. return -1;
  704. /* Make general config ops here
  705. 1/ tell IDE channels to operate in Compatibility mode only
  706. 2/ tell old chips to allow per drive IDE timings */
  707. {
  708. u8 reg;
  709. u16 regw;
  710. switch(chipset_family) {
  711. case ATA_133:
  712. /* SiS962 operation mode */
  713. pci_read_config_word(dev, 0x50, &regw);
  714. if (regw & 0x08)
  715. pci_write_config_word(dev, 0x50, regw&0xfff7);
  716. pci_read_config_word(dev, 0x52, &regw);
  717. if (regw & 0x08)
  718. pci_write_config_word(dev, 0x52, regw&0xfff7);
  719. break;
  720. case ATA_133a:
  721. case ATA_100:
  722. /* Fixup latency */
  723. pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x80);
  724. /* Set compatibility bit */
  725. pci_read_config_byte(dev, 0x49, &reg);
  726. if (!(reg & 0x01)) {
  727. pci_write_config_byte(dev, 0x49, reg|0x01);
  728. }
  729. break;
  730. case ATA_100a:
  731. case ATA_66:
  732. /* Fixup latency */
  733. pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x10);
  734. /* On ATA_66 chips the bit was elsewhere */
  735. pci_read_config_byte(dev, 0x52, &reg);
  736. if (!(reg & 0x04)) {
  737. pci_write_config_byte(dev, 0x52, reg|0x04);
  738. }
  739. break;
  740. case ATA_33:
  741. /* On ATA_33 we didn't have a single bit to set */
  742. pci_read_config_byte(dev, 0x09, &reg);
  743. if ((reg & 0x0f) != 0x00) {
  744. pci_write_config_byte(dev, 0x09, reg&0xf0);
  745. }
  746. case ATA_16:
  747. /* force per drive recovery and active timings
  748. needed on ATA_33 and below chips */
  749. pci_read_config_byte(dev, 0x52, &reg);
  750. if (!(reg & 0x08)) {
  751. pci_write_config_byte(dev, 0x52, reg|0x08);
  752. }
  753. break;
  754. }
  755. #if defined(DISPLAY_SIS_TIMINGS) && defined(CONFIG_PROC_FS)
  756. if (!sis_proc) {
  757. sis_proc = 1;
  758. bmide_dev = dev;
  759. ide_pci_create_host_proc("sis", sis_get_info);
  760. }
  761. #endif
  762. }
  763. return 0;
  764. }
  765. static unsigned int __devinit ata66_sis5513 (ide_hwif_t *hwif)
  766. {
  767. u8 ata66 = 0;
  768. if (chipset_family >= ATA_133) {
  769. u16 regw = 0;
  770. u16 reg_addr = hwif->channel ? 0x52: 0x50;
  771. pci_read_config_word(hwif->pci_dev, reg_addr, &regw);
  772. ata66 = (regw & 0x8000) ? 0 : 1;
  773. } else if (chipset_family >= ATA_66) {
  774. u8 reg48h = 0;
  775. u8 mask = hwif->channel ? 0x20 : 0x10;
  776. pci_read_config_byte(hwif->pci_dev, 0x48, &reg48h);
  777. ata66 = (reg48h & mask) ? 0 : 1;
  778. }
  779. return ata66;
  780. }
  781. static void __devinit init_hwif_sis5513 (ide_hwif_t *hwif)
  782. {
  783. hwif->autodma = 0;
  784. if (!hwif->irq)
  785. hwif->irq = hwif->channel ? 15 : 14;
  786. hwif->tuneproc = &sis5513_tune_drive;
  787. hwif->speedproc = &sis5513_tune_chipset;
  788. if (!(hwif->dma_base)) {
  789. hwif->drives[0].autotune = 1;
  790. hwif->drives[1].autotune = 1;
  791. return;
  792. }
  793. hwif->atapi_dma = 1;
  794. hwif->ultra_mask = 0x7f;
  795. hwif->mwdma_mask = 0x07;
  796. hwif->swdma_mask = 0x07;
  797. if (!chipset_family)
  798. return;
  799. if (!(hwif->udma_four))
  800. hwif->udma_four = ata66_sis5513(hwif);
  801. if (chipset_family > ATA_16) {
  802. hwif->ide_dma_check = &sis5513_config_xfer_rate;
  803. if (!noautodma)
  804. hwif->autodma = 1;
  805. }
  806. hwif->drives[0].autodma = hwif->autodma;
  807. hwif->drives[1].autodma = hwif->autodma;
  808. return;
  809. }
  810. static ide_pci_device_t sis5513_chipset __devinitdata = {
  811. .name = "SIS5513",
  812. .init_chipset = init_chipset_sis5513,
  813. .init_hwif = init_hwif_sis5513,
  814. .channels = 2,
  815. .autodma = NOAUTODMA,
  816. .enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
  817. .bootable = ON_BOARD,
  818. };
  819. static int __devinit sis5513_init_one(struct pci_dev *dev, const struct pci_device_id *id)
  820. {
  821. return ide_setup_pci_device(dev, &sis5513_chipset);
  822. }
  823. static struct pci_device_id sis5513_pci_tbl[] = {
  824. { PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5513, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
  825. { PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5518, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
  826. { 0, },
  827. };
  828. MODULE_DEVICE_TABLE(pci, sis5513_pci_tbl);
  829. static struct pci_driver driver = {
  830. .name = "SIS_IDE",
  831. .id_table = sis5513_pci_tbl,
  832. .probe = sis5513_init_one,
  833. };
  834. static int sis5513_ide_init(void)
  835. {
  836. return ide_pci_register_driver(&driver);
  837. }
  838. module_init(sis5513_ide_init);
  839. MODULE_AUTHOR("Lionel Bouton, L C Chang, Andre Hedrick, Vojtech Pavlik");
  840. MODULE_DESCRIPTION("PCI driver module for SIS IDE");
  841. MODULE_LICENSE("GPL");
  842. /*
  843. * TODO:
  844. * - CLEANUP
  845. * - Use drivers/ide/ide-timing.h !
  846. * - More checks in the config registers (force values instead of
  847. * relying on the BIOS setting them correctly).
  848. * - Further optimisations ?
  849. * . for example ATA66+ regs 0x48 & 0x4A
  850. */