i2c-sis96x.c 9.1 KB

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  1. /*
  2. sis96x.c - Part of lm_sensors, Linux kernel modules for hardware
  3. monitoring
  4. Copyright (c) 2003 Mark M. Hoffman <mhoffman@lightlink.com>
  5. This program is free software; you can redistribute it and/or modify
  6. it under the terms of the GNU General Public License as published by
  7. the Free Software Foundation; either version 2 of the License, or
  8. (at your option) any later version.
  9. This program is distributed in the hope that it will be useful,
  10. but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. GNU General Public License for more details.
  13. You should have received a copy of the GNU General Public License
  14. along with this program; if not, write to the Free Software
  15. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  16. */
  17. /*
  18. This module must be considered BETA unless and until
  19. the chipset manufacturer releases a datasheet.
  20. The register definitions are based on the SiS630.
  21. This module relies on quirk_sis_96x_smbus (drivers/pci/quirks.c)
  22. for just about every machine for which users have reported.
  23. If this module isn't detecting your 96x south bridge, have a
  24. look there.
  25. We assume there can only be one SiS96x with one SMBus interface.
  26. */
  27. #include <linux/module.h>
  28. #include <linux/pci.h>
  29. #include <linux/kernel.h>
  30. #include <linux/delay.h>
  31. #include <linux/stddef.h>
  32. #include <linux/sched.h>
  33. #include <linux/ioport.h>
  34. #include <linux/i2c.h>
  35. #include <linux/init.h>
  36. #include <asm/io.h>
  37. /*
  38. HISTORY:
  39. 2003-05-11 1.0.0 Updated from lm_sensors project for kernel 2.5
  40. (was i2c-sis645.c from lm_sensors 2.7.0)
  41. */
  42. #define SIS96x_VERSION "1.0.0"
  43. /* base address register in PCI config space */
  44. #define SIS96x_BAR 0x04
  45. /* SiS96x SMBus registers */
  46. #define SMB_STS 0x00
  47. #define SMB_EN 0x01
  48. #define SMB_CNT 0x02
  49. #define SMB_HOST_CNT 0x03
  50. #define SMB_ADDR 0x04
  51. #define SMB_CMD 0x05
  52. #define SMB_PCOUNT 0x06
  53. #define SMB_COUNT 0x07
  54. #define SMB_BYTE 0x08
  55. #define SMB_DEV_ADDR 0x10
  56. #define SMB_DB0 0x11
  57. #define SMB_DB1 0x12
  58. #define SMB_SAA 0x13
  59. /* register count for request_region */
  60. #define SMB_IOSIZE 0x20
  61. /* Other settings */
  62. #define MAX_TIMEOUT 500
  63. /* SiS96x SMBus constants */
  64. #define SIS96x_QUICK 0x00
  65. #define SIS96x_BYTE 0x01
  66. #define SIS96x_BYTE_DATA 0x02
  67. #define SIS96x_WORD_DATA 0x03
  68. #define SIS96x_PROC_CALL 0x04
  69. #define SIS96x_BLOCK_DATA 0x05
  70. static struct i2c_adapter sis96x_adapter;
  71. static u16 sis96x_smbus_base = 0;
  72. static inline u8 sis96x_read(u8 reg)
  73. {
  74. return inb(sis96x_smbus_base + reg) ;
  75. }
  76. static inline void sis96x_write(u8 reg, u8 data)
  77. {
  78. outb(data, sis96x_smbus_base + reg) ;
  79. }
  80. /* Execute a SMBus transaction.
  81. int size is from SIS96x_QUICK to SIS96x_BLOCK_DATA
  82. */
  83. static int sis96x_transaction(int size)
  84. {
  85. int temp;
  86. int result = 0;
  87. int timeout = 0;
  88. dev_dbg(&sis96x_adapter.dev, "SMBus transaction %d\n", size);
  89. /* Make sure the SMBus host is ready to start transmitting */
  90. if (((temp = sis96x_read(SMB_CNT)) & 0x03) != 0x00) {
  91. dev_dbg(&sis96x_adapter.dev, "SMBus busy (0x%02x). "
  92. "Resetting...\n", temp);
  93. /* kill the transaction */
  94. sis96x_write(SMB_HOST_CNT, 0x20);
  95. /* check it again */
  96. if (((temp = sis96x_read(SMB_CNT)) & 0x03) != 0x00) {
  97. dev_dbg(&sis96x_adapter.dev, "Failed (0x%02x)\n", temp);
  98. return -1;
  99. } else {
  100. dev_dbg(&sis96x_adapter.dev, "Successful\n");
  101. }
  102. }
  103. /* Turn off timeout interrupts, set fast host clock */
  104. sis96x_write(SMB_CNT, 0x20);
  105. /* clear all (sticky) status flags */
  106. temp = sis96x_read(SMB_STS);
  107. sis96x_write(SMB_STS, temp & 0x1e);
  108. /* start the transaction by setting bit 4 and size bits */
  109. sis96x_write(SMB_HOST_CNT, 0x10 | (size & 0x07));
  110. /* We will always wait for a fraction of a second! */
  111. do {
  112. msleep(1);
  113. temp = sis96x_read(SMB_STS);
  114. } while (!(temp & 0x0e) && (timeout++ < MAX_TIMEOUT));
  115. /* If the SMBus is still busy, we give up */
  116. if (timeout >= MAX_TIMEOUT) {
  117. dev_dbg(&sis96x_adapter.dev, "SMBus Timeout! (0x%02x)\n", temp);
  118. result = -1;
  119. }
  120. /* device error - probably missing ACK */
  121. if (temp & 0x02) {
  122. dev_dbg(&sis96x_adapter.dev, "Failed bus transaction!\n");
  123. result = -1;
  124. }
  125. /* bus collision */
  126. if (temp & 0x04) {
  127. dev_dbg(&sis96x_adapter.dev, "Bus collision!\n");
  128. result = -1;
  129. }
  130. /* Finish up by resetting the bus */
  131. sis96x_write(SMB_STS, temp);
  132. if ((temp = sis96x_read(SMB_STS))) {
  133. dev_dbg(&sis96x_adapter.dev, "Failed reset at "
  134. "end of transaction! (0x%02x)\n", temp);
  135. }
  136. return result;
  137. }
  138. /* Return -1 on error. */
  139. static s32 sis96x_access(struct i2c_adapter * adap, u16 addr,
  140. unsigned short flags, char read_write,
  141. u8 command, int size, union i2c_smbus_data * data)
  142. {
  143. switch (size) {
  144. case I2C_SMBUS_QUICK:
  145. sis96x_write(SMB_ADDR, ((addr & 0x7f) << 1) | (read_write & 0x01));
  146. size = SIS96x_QUICK;
  147. break;
  148. case I2C_SMBUS_BYTE:
  149. sis96x_write(SMB_ADDR, ((addr & 0x7f) << 1) | (read_write & 0x01));
  150. if (read_write == I2C_SMBUS_WRITE)
  151. sis96x_write(SMB_CMD, command);
  152. size = SIS96x_BYTE;
  153. break;
  154. case I2C_SMBUS_BYTE_DATA:
  155. sis96x_write(SMB_ADDR, ((addr & 0x7f) << 1) | (read_write & 0x01));
  156. sis96x_write(SMB_CMD, command);
  157. if (read_write == I2C_SMBUS_WRITE)
  158. sis96x_write(SMB_BYTE, data->byte);
  159. size = SIS96x_BYTE_DATA;
  160. break;
  161. case I2C_SMBUS_PROC_CALL:
  162. case I2C_SMBUS_WORD_DATA:
  163. sis96x_write(SMB_ADDR, ((addr & 0x7f) << 1) | (read_write & 0x01));
  164. sis96x_write(SMB_CMD, command);
  165. if (read_write == I2C_SMBUS_WRITE) {
  166. sis96x_write(SMB_BYTE, data->word & 0xff);
  167. sis96x_write(SMB_BYTE + 1, (data->word & 0xff00) >> 8);
  168. }
  169. size = (size == I2C_SMBUS_PROC_CALL ?
  170. SIS96x_PROC_CALL : SIS96x_WORD_DATA);
  171. break;
  172. case I2C_SMBUS_BLOCK_DATA:
  173. /* TO DO: */
  174. dev_info(&adap->dev, "SMBus block not implemented!\n");
  175. return -1;
  176. break;
  177. default:
  178. dev_info(&adap->dev, "Unsupported I2C size\n");
  179. return -1;
  180. break;
  181. }
  182. if (sis96x_transaction(size))
  183. return -1;
  184. if ((size != SIS96x_PROC_CALL) &&
  185. ((read_write == I2C_SMBUS_WRITE) || (size == SIS96x_QUICK)))
  186. return 0;
  187. switch (size) {
  188. case SIS96x_BYTE:
  189. case SIS96x_BYTE_DATA:
  190. data->byte = sis96x_read(SMB_BYTE);
  191. break;
  192. case SIS96x_WORD_DATA:
  193. case SIS96x_PROC_CALL:
  194. data->word = sis96x_read(SMB_BYTE) +
  195. (sis96x_read(SMB_BYTE + 1) << 8);
  196. break;
  197. }
  198. return 0;
  199. }
  200. static u32 sis96x_func(struct i2c_adapter *adapter)
  201. {
  202. return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
  203. I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
  204. I2C_FUNC_SMBUS_PROC_CALL;
  205. }
  206. static struct i2c_algorithm smbus_algorithm = {
  207. .name = "Non-I2C SMBus adapter",
  208. .id = I2C_ALGO_SMBUS,
  209. .smbus_xfer = sis96x_access,
  210. .functionality = sis96x_func,
  211. };
  212. static struct i2c_adapter sis96x_adapter = {
  213. .owner = THIS_MODULE,
  214. .class = I2C_CLASS_HWMON,
  215. .algo = &smbus_algorithm,
  216. .name = "unset",
  217. };
  218. static struct pci_device_id sis96x_ids[] = {
  219. { PCI_DEVICE(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_SMBUS) },
  220. { 0, }
  221. };
  222. MODULE_DEVICE_TABLE (pci, sis96x_ids);
  223. static int __devinit sis96x_probe(struct pci_dev *dev,
  224. const struct pci_device_id *id)
  225. {
  226. u16 ww = 0;
  227. int retval;
  228. if (sis96x_smbus_base) {
  229. dev_err(&dev->dev, "Only one device supported.\n");
  230. return -EBUSY;
  231. }
  232. pci_read_config_word(dev, PCI_CLASS_DEVICE, &ww);
  233. if (PCI_CLASS_SERIAL_SMBUS != ww) {
  234. dev_err(&dev->dev, "Unsupported device class 0x%04x!\n", ww);
  235. return -ENODEV;
  236. }
  237. sis96x_smbus_base = pci_resource_start(dev, SIS96x_BAR);
  238. if (!sis96x_smbus_base) {
  239. dev_err(&dev->dev, "SiS96x SMBus base address "
  240. "not initialized!\n");
  241. return -EINVAL;
  242. }
  243. dev_info(&dev->dev, "SiS96x SMBus base address: 0x%04x\n",
  244. sis96x_smbus_base);
  245. /* Everything is happy, let's grab the memory and set things up. */
  246. if (!request_region(sis96x_smbus_base, SMB_IOSIZE, "sis96x-smbus")) {
  247. dev_err(&dev->dev, "SMBus registers 0x%04x-0x%04x "
  248. "already in use!\n", sis96x_smbus_base,
  249. sis96x_smbus_base + SMB_IOSIZE - 1);
  250. sis96x_smbus_base = 0;
  251. return -EINVAL;
  252. }
  253. /* set up the driverfs linkage to our parent device */
  254. sis96x_adapter.dev.parent = &dev->dev;
  255. snprintf(sis96x_adapter.name, I2C_NAME_SIZE,
  256. "SiS96x SMBus adapter at 0x%04x", sis96x_smbus_base);
  257. if ((retval = i2c_add_adapter(&sis96x_adapter))) {
  258. dev_err(&dev->dev, "Couldn't register adapter!\n");
  259. release_region(sis96x_smbus_base, SMB_IOSIZE);
  260. sis96x_smbus_base = 0;
  261. }
  262. return retval;
  263. }
  264. static void __devexit sis96x_remove(struct pci_dev *dev)
  265. {
  266. if (sis96x_smbus_base) {
  267. i2c_del_adapter(&sis96x_adapter);
  268. release_region(sis96x_smbus_base, SMB_IOSIZE);
  269. sis96x_smbus_base = 0;
  270. }
  271. }
  272. static struct pci_driver sis96x_driver = {
  273. .name = "sis96x_smbus",
  274. .id_table = sis96x_ids,
  275. .probe = sis96x_probe,
  276. .remove = __devexit_p(sis96x_remove),
  277. };
  278. static int __init i2c_sis96x_init(void)
  279. {
  280. printk(KERN_INFO "i2c-sis96x version %s\n", SIS96x_VERSION);
  281. return pci_register_driver(&sis96x_driver);
  282. }
  283. static void __exit i2c_sis96x_exit(void)
  284. {
  285. pci_unregister_driver(&sis96x_driver);
  286. }
  287. MODULE_AUTHOR("Mark M. Hoffman <mhoffman@lightlink.com>");
  288. MODULE_DESCRIPTION("SiS96x SMBus driver");
  289. MODULE_LICENSE("GPL");
  290. /* Register initialization functions using helper macros */
  291. module_init(i2c_sis96x_init);
  292. module_exit(i2c_sis96x_exit);