mga_dma.c 19 KB

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  1. /* mga_dma.c -- DMA support for mga g200/g400 -*- linux-c -*-
  2. * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com
  3. *
  4. * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
  5. * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
  6. * All Rights Reserved.
  7. *
  8. * Permission is hereby granted, free of charge, to any person obtaining a
  9. * copy of this software and associated documentation files (the "Software"),
  10. * to deal in the Software without restriction, including without limitation
  11. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12. * and/or sell copies of the Software, and to permit persons to whom the
  13. * Software is furnished to do so, subject to the following conditions:
  14. *
  15. * The above copyright notice and this permission notice (including the next
  16. * paragraph) shall be included in all copies or substantial portions of the
  17. * Software.
  18. *
  19. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  22. * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  23. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  24. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  25. * DEALINGS IN THE SOFTWARE.
  26. *
  27. * Authors:
  28. * Rickard E. (Rik) Faith <faith@valinux.com>
  29. * Jeff Hartmann <jhartmann@valinux.com>
  30. * Keith Whitwell <keith@tungstengraphics.com>
  31. *
  32. * Rewritten by:
  33. * Gareth Hughes <gareth@valinux.com>
  34. */
  35. #include "drmP.h"
  36. #include "drm.h"
  37. #include "mga_drm.h"
  38. #include "mga_drv.h"
  39. #define MGA_DEFAULT_USEC_TIMEOUT 10000
  40. #define MGA_FREELIST_DEBUG 0
  41. static int mga_do_cleanup_dma( drm_device_t *dev );
  42. /* ================================================================
  43. * Engine control
  44. */
  45. int mga_do_wait_for_idle( drm_mga_private_t *dev_priv )
  46. {
  47. u32 status = 0;
  48. int i;
  49. DRM_DEBUG( "\n" );
  50. for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
  51. status = MGA_READ( MGA_STATUS ) & MGA_ENGINE_IDLE_MASK;
  52. if ( status == MGA_ENDPRDMASTS ) {
  53. MGA_WRITE8( MGA_CRTC_INDEX, 0 );
  54. return 0;
  55. }
  56. DRM_UDELAY( 1 );
  57. }
  58. #if MGA_DMA_DEBUG
  59. DRM_ERROR( "failed!\n" );
  60. DRM_INFO( " status=0x%08x\n", status );
  61. #endif
  62. return DRM_ERR(EBUSY);
  63. }
  64. static int mga_do_dma_reset( drm_mga_private_t *dev_priv )
  65. {
  66. drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
  67. drm_mga_primary_buffer_t *primary = &dev_priv->prim;
  68. DRM_DEBUG( "\n" );
  69. /* The primary DMA stream should look like new right about now.
  70. */
  71. primary->tail = 0;
  72. primary->space = primary->size;
  73. primary->last_flush = 0;
  74. sarea_priv->last_wrap = 0;
  75. /* FIXME: Reset counters, buffer ages etc...
  76. */
  77. /* FIXME: What else do we need to reinitialize? WARP stuff?
  78. */
  79. return 0;
  80. }
  81. /* ================================================================
  82. * Primary DMA stream
  83. */
  84. void mga_do_dma_flush( drm_mga_private_t *dev_priv )
  85. {
  86. drm_mga_primary_buffer_t *primary = &dev_priv->prim;
  87. u32 head, tail;
  88. u32 status = 0;
  89. int i;
  90. DMA_LOCALS;
  91. DRM_DEBUG( "\n" );
  92. /* We need to wait so that we can do an safe flush */
  93. for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
  94. status = MGA_READ( MGA_STATUS ) & MGA_ENGINE_IDLE_MASK;
  95. if ( status == MGA_ENDPRDMASTS ) break;
  96. DRM_UDELAY( 1 );
  97. }
  98. if ( primary->tail == primary->last_flush ) {
  99. DRM_DEBUG( " bailing out...\n" );
  100. return;
  101. }
  102. tail = primary->tail + dev_priv->primary->offset;
  103. /* We need to pad the stream between flushes, as the card
  104. * actually (partially?) reads the first of these commands.
  105. * See page 4-16 in the G400 manual, middle of the page or so.
  106. */
  107. BEGIN_DMA( 1 );
  108. DMA_BLOCK( MGA_DMAPAD, 0x00000000,
  109. MGA_DMAPAD, 0x00000000,
  110. MGA_DMAPAD, 0x00000000,
  111. MGA_DMAPAD, 0x00000000 );
  112. ADVANCE_DMA();
  113. primary->last_flush = primary->tail;
  114. head = MGA_READ( MGA_PRIMADDRESS );
  115. if ( head <= tail ) {
  116. primary->space = primary->size - primary->tail;
  117. } else {
  118. primary->space = head - tail;
  119. }
  120. DRM_DEBUG( " head = 0x%06lx\n", head - dev_priv->primary->offset );
  121. DRM_DEBUG( " tail = 0x%06lx\n", tail - dev_priv->primary->offset );
  122. DRM_DEBUG( " space = 0x%06x\n", primary->space );
  123. mga_flush_write_combine();
  124. MGA_WRITE( MGA_PRIMEND, tail | MGA_PAGPXFER );
  125. DRM_DEBUG( "done.\n" );
  126. }
  127. void mga_do_dma_wrap_start( drm_mga_private_t *dev_priv )
  128. {
  129. drm_mga_primary_buffer_t *primary = &dev_priv->prim;
  130. u32 head, tail;
  131. DMA_LOCALS;
  132. DRM_DEBUG( "\n" );
  133. BEGIN_DMA_WRAP();
  134. DMA_BLOCK( MGA_DMAPAD, 0x00000000,
  135. MGA_DMAPAD, 0x00000000,
  136. MGA_DMAPAD, 0x00000000,
  137. MGA_DMAPAD, 0x00000000 );
  138. ADVANCE_DMA();
  139. tail = primary->tail + dev_priv->primary->offset;
  140. primary->tail = 0;
  141. primary->last_flush = 0;
  142. primary->last_wrap++;
  143. head = MGA_READ( MGA_PRIMADDRESS );
  144. if ( head == dev_priv->primary->offset ) {
  145. primary->space = primary->size;
  146. } else {
  147. primary->space = head - dev_priv->primary->offset;
  148. }
  149. DRM_DEBUG( " head = 0x%06lx\n",
  150. head - dev_priv->primary->offset );
  151. DRM_DEBUG( " tail = 0x%06x\n", primary->tail );
  152. DRM_DEBUG( " wrap = %d\n", primary->last_wrap );
  153. DRM_DEBUG( " space = 0x%06x\n", primary->space );
  154. mga_flush_write_combine();
  155. MGA_WRITE( MGA_PRIMEND, tail | MGA_PAGPXFER );
  156. set_bit( 0, &primary->wrapped );
  157. DRM_DEBUG( "done.\n" );
  158. }
  159. void mga_do_dma_wrap_end( drm_mga_private_t *dev_priv )
  160. {
  161. drm_mga_primary_buffer_t *primary = &dev_priv->prim;
  162. drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
  163. u32 head = dev_priv->primary->offset;
  164. DRM_DEBUG( "\n" );
  165. sarea_priv->last_wrap++;
  166. DRM_DEBUG( " wrap = %d\n", sarea_priv->last_wrap );
  167. mga_flush_write_combine();
  168. MGA_WRITE( MGA_PRIMADDRESS, head | MGA_DMA_GENERAL );
  169. clear_bit( 0, &primary->wrapped );
  170. DRM_DEBUG( "done.\n" );
  171. }
  172. /* ================================================================
  173. * Freelist management
  174. */
  175. #define MGA_BUFFER_USED ~0
  176. #define MGA_BUFFER_FREE 0
  177. #if MGA_FREELIST_DEBUG
  178. static void mga_freelist_print( drm_device_t *dev )
  179. {
  180. drm_mga_private_t *dev_priv = dev->dev_private;
  181. drm_mga_freelist_t *entry;
  182. DRM_INFO( "\n" );
  183. DRM_INFO( "current dispatch: last=0x%x done=0x%x\n",
  184. dev_priv->sarea_priv->last_dispatch,
  185. (unsigned int)(MGA_READ( MGA_PRIMADDRESS ) -
  186. dev_priv->primary->offset) );
  187. DRM_INFO( "current freelist:\n" );
  188. for ( entry = dev_priv->head->next ; entry ; entry = entry->next ) {
  189. DRM_INFO( " %p idx=%2d age=0x%x 0x%06lx\n",
  190. entry, entry->buf->idx, entry->age.head,
  191. entry->age.head - dev_priv->primary->offset );
  192. }
  193. DRM_INFO( "\n" );
  194. }
  195. #endif
  196. static int mga_freelist_init( drm_device_t *dev, drm_mga_private_t *dev_priv )
  197. {
  198. drm_device_dma_t *dma = dev->dma;
  199. drm_buf_t *buf;
  200. drm_mga_buf_priv_t *buf_priv;
  201. drm_mga_freelist_t *entry;
  202. int i;
  203. DRM_DEBUG( "count=%d\n", dma->buf_count );
  204. dev_priv->head = drm_alloc( sizeof(drm_mga_freelist_t),
  205. DRM_MEM_DRIVER );
  206. if ( dev_priv->head == NULL )
  207. return DRM_ERR(ENOMEM);
  208. memset( dev_priv->head, 0, sizeof(drm_mga_freelist_t) );
  209. SET_AGE( &dev_priv->head->age, MGA_BUFFER_USED, 0 );
  210. for ( i = 0 ; i < dma->buf_count ; i++ ) {
  211. buf = dma->buflist[i];
  212. buf_priv = buf->dev_private;
  213. entry = drm_alloc( sizeof(drm_mga_freelist_t),
  214. DRM_MEM_DRIVER );
  215. if ( entry == NULL )
  216. return DRM_ERR(ENOMEM);
  217. memset( entry, 0, sizeof(drm_mga_freelist_t) );
  218. entry->next = dev_priv->head->next;
  219. entry->prev = dev_priv->head;
  220. SET_AGE( &entry->age, MGA_BUFFER_FREE, 0 );
  221. entry->buf = buf;
  222. if ( dev_priv->head->next != NULL )
  223. dev_priv->head->next->prev = entry;
  224. if ( entry->next == NULL )
  225. dev_priv->tail = entry;
  226. buf_priv->list_entry = entry;
  227. buf_priv->discard = 0;
  228. buf_priv->dispatched = 0;
  229. dev_priv->head->next = entry;
  230. }
  231. return 0;
  232. }
  233. static void mga_freelist_cleanup( drm_device_t *dev )
  234. {
  235. drm_mga_private_t *dev_priv = dev->dev_private;
  236. drm_mga_freelist_t *entry;
  237. drm_mga_freelist_t *next;
  238. DRM_DEBUG( "\n" );
  239. entry = dev_priv->head;
  240. while ( entry ) {
  241. next = entry->next;
  242. drm_free( entry, sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER );
  243. entry = next;
  244. }
  245. dev_priv->head = dev_priv->tail = NULL;
  246. }
  247. #if 0
  248. /* FIXME: Still needed?
  249. */
  250. static void mga_freelist_reset( drm_device_t *dev )
  251. {
  252. drm_device_dma_t *dma = dev->dma;
  253. drm_buf_t *buf;
  254. drm_mga_buf_priv_t *buf_priv;
  255. int i;
  256. for ( i = 0 ; i < dma->buf_count ; i++ ) {
  257. buf = dma->buflist[i];
  258. buf_priv = buf->dev_private;
  259. SET_AGE( &buf_priv->list_entry->age,
  260. MGA_BUFFER_FREE, 0 );
  261. }
  262. }
  263. #endif
  264. static drm_buf_t *mga_freelist_get( drm_device_t *dev )
  265. {
  266. drm_mga_private_t *dev_priv = dev->dev_private;
  267. drm_mga_freelist_t *next;
  268. drm_mga_freelist_t *prev;
  269. drm_mga_freelist_t *tail = dev_priv->tail;
  270. u32 head, wrap;
  271. DRM_DEBUG( "\n" );
  272. head = MGA_READ( MGA_PRIMADDRESS );
  273. wrap = dev_priv->sarea_priv->last_wrap;
  274. DRM_DEBUG( " tail=0x%06lx %d\n",
  275. tail->age.head ?
  276. tail->age.head - dev_priv->primary->offset : 0,
  277. tail->age.wrap );
  278. DRM_DEBUG( " head=0x%06lx %d\n",
  279. head - dev_priv->primary->offset, wrap );
  280. if ( TEST_AGE( &tail->age, head, wrap ) ) {
  281. prev = dev_priv->tail->prev;
  282. next = dev_priv->tail;
  283. prev->next = NULL;
  284. next->prev = next->next = NULL;
  285. dev_priv->tail = prev;
  286. SET_AGE( &next->age, MGA_BUFFER_USED, 0 );
  287. return next->buf;
  288. }
  289. DRM_DEBUG( "returning NULL!\n" );
  290. return NULL;
  291. }
  292. int mga_freelist_put( drm_device_t *dev, drm_buf_t *buf )
  293. {
  294. drm_mga_private_t *dev_priv = dev->dev_private;
  295. drm_mga_buf_priv_t *buf_priv = buf->dev_private;
  296. drm_mga_freelist_t *head, *entry, *prev;
  297. DRM_DEBUG( "age=0x%06lx wrap=%d\n",
  298. buf_priv->list_entry->age.head -
  299. dev_priv->primary->offset,
  300. buf_priv->list_entry->age.wrap );
  301. entry = buf_priv->list_entry;
  302. head = dev_priv->head;
  303. if ( buf_priv->list_entry->age.head == MGA_BUFFER_USED ) {
  304. SET_AGE( &entry->age, MGA_BUFFER_FREE, 0 );
  305. prev = dev_priv->tail;
  306. prev->next = entry;
  307. entry->prev = prev;
  308. entry->next = NULL;
  309. } else {
  310. prev = head->next;
  311. head->next = entry;
  312. prev->prev = entry;
  313. entry->prev = head;
  314. entry->next = prev;
  315. }
  316. return 0;
  317. }
  318. /* ================================================================
  319. * DMA initialization, cleanup
  320. */
  321. static int mga_do_init_dma( drm_device_t *dev, drm_mga_init_t *init )
  322. {
  323. drm_mga_private_t *dev_priv;
  324. int ret;
  325. DRM_DEBUG( "\n" );
  326. dev_priv = drm_alloc( sizeof(drm_mga_private_t), DRM_MEM_DRIVER );
  327. if ( !dev_priv )
  328. return DRM_ERR(ENOMEM);
  329. memset( dev_priv, 0, sizeof(drm_mga_private_t) );
  330. dev_priv->chipset = init->chipset;
  331. dev_priv->usec_timeout = MGA_DEFAULT_USEC_TIMEOUT;
  332. if ( init->sgram ) {
  333. dev_priv->clear_cmd = MGA_DWGCTL_CLEAR | MGA_ATYPE_BLK;
  334. } else {
  335. dev_priv->clear_cmd = MGA_DWGCTL_CLEAR | MGA_ATYPE_RSTR;
  336. }
  337. dev_priv->maccess = init->maccess;
  338. dev_priv->fb_cpp = init->fb_cpp;
  339. dev_priv->front_offset = init->front_offset;
  340. dev_priv->front_pitch = init->front_pitch;
  341. dev_priv->back_offset = init->back_offset;
  342. dev_priv->back_pitch = init->back_pitch;
  343. dev_priv->depth_cpp = init->depth_cpp;
  344. dev_priv->depth_offset = init->depth_offset;
  345. dev_priv->depth_pitch = init->depth_pitch;
  346. /* FIXME: Need to support AGP textures...
  347. */
  348. dev_priv->texture_offset = init->texture_offset[0];
  349. dev_priv->texture_size = init->texture_size[0];
  350. DRM_GETSAREA();
  351. if(!dev_priv->sarea) {
  352. DRM_ERROR( "failed to find sarea!\n" );
  353. /* Assign dev_private so we can do cleanup. */
  354. dev->dev_private = (void *)dev_priv;
  355. mga_do_cleanup_dma( dev );
  356. return DRM_ERR(EINVAL);
  357. }
  358. dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset);
  359. if(!dev_priv->mmio) {
  360. DRM_ERROR( "failed to find mmio region!\n" );
  361. /* Assign dev_private so we can do cleanup. */
  362. dev->dev_private = (void *)dev_priv;
  363. mga_do_cleanup_dma( dev );
  364. return DRM_ERR(EINVAL);
  365. }
  366. dev_priv->status = drm_core_findmap(dev, init->status_offset);
  367. if(!dev_priv->status) {
  368. DRM_ERROR( "failed to find status page!\n" );
  369. /* Assign dev_private so we can do cleanup. */
  370. dev->dev_private = (void *)dev_priv;
  371. mga_do_cleanup_dma( dev );
  372. return DRM_ERR(EINVAL);
  373. }
  374. dev_priv->warp = drm_core_findmap(dev, init->warp_offset);
  375. if(!dev_priv->warp) {
  376. DRM_ERROR( "failed to find warp microcode region!\n" );
  377. /* Assign dev_private so we can do cleanup. */
  378. dev->dev_private = (void *)dev_priv;
  379. mga_do_cleanup_dma( dev );
  380. return DRM_ERR(EINVAL);
  381. }
  382. dev_priv->primary = drm_core_findmap(dev, init->primary_offset);
  383. if(!dev_priv->primary) {
  384. DRM_ERROR( "failed to find primary dma region!\n" );
  385. /* Assign dev_private so we can do cleanup. */
  386. dev->dev_private = (void *)dev_priv;
  387. mga_do_cleanup_dma( dev );
  388. return DRM_ERR(EINVAL);
  389. }
  390. dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
  391. if(!dev->agp_buffer_map) {
  392. DRM_ERROR( "failed to find dma buffer region!\n" );
  393. /* Assign dev_private so we can do cleanup. */
  394. dev->dev_private = (void *)dev_priv;
  395. mga_do_cleanup_dma( dev );
  396. return DRM_ERR(EINVAL);
  397. }
  398. dev_priv->sarea_priv =
  399. (drm_mga_sarea_t *)((u8 *)dev_priv->sarea->handle +
  400. init->sarea_priv_offset);
  401. drm_core_ioremap( dev_priv->warp, dev );
  402. drm_core_ioremap( dev_priv->primary, dev );
  403. drm_core_ioremap( dev->agp_buffer_map, dev );
  404. if(!dev_priv->warp->handle ||
  405. !dev_priv->primary->handle ||
  406. !dev->agp_buffer_map->handle ) {
  407. DRM_ERROR( "failed to ioremap agp regions!\n" );
  408. /* Assign dev_private so we can do cleanup. */
  409. dev->dev_private = (void *)dev_priv;
  410. mga_do_cleanup_dma( dev );
  411. return DRM_ERR(ENOMEM);
  412. }
  413. ret = mga_warp_install_microcode( dev_priv );
  414. if ( ret < 0 ) {
  415. DRM_ERROR( "failed to install WARP ucode!\n" );
  416. /* Assign dev_private so we can do cleanup. */
  417. dev->dev_private = (void *)dev_priv;
  418. mga_do_cleanup_dma( dev );
  419. return ret;
  420. }
  421. ret = mga_warp_init( dev_priv );
  422. if ( ret < 0 ) {
  423. DRM_ERROR( "failed to init WARP engine!\n" );
  424. /* Assign dev_private so we can do cleanup. */
  425. dev->dev_private = (void *)dev_priv;
  426. mga_do_cleanup_dma( dev );
  427. return ret;
  428. }
  429. dev_priv->prim.status = (u32 *)dev_priv->status->handle;
  430. mga_do_wait_for_idle( dev_priv );
  431. /* Init the primary DMA registers.
  432. */
  433. MGA_WRITE( MGA_PRIMADDRESS,
  434. dev_priv->primary->offset | MGA_DMA_GENERAL );
  435. #if 0
  436. MGA_WRITE( MGA_PRIMPTR,
  437. virt_to_bus((void *)dev_priv->prim.status) |
  438. MGA_PRIMPTREN0 | /* Soft trap, SECEND, SETUPEND */
  439. MGA_PRIMPTREN1 ); /* DWGSYNC */
  440. #endif
  441. dev_priv->prim.start = (u8 *)dev_priv->primary->handle;
  442. dev_priv->prim.end = ((u8 *)dev_priv->primary->handle
  443. + dev_priv->primary->size);
  444. dev_priv->prim.size = dev_priv->primary->size;
  445. dev_priv->prim.tail = 0;
  446. dev_priv->prim.space = dev_priv->prim.size;
  447. dev_priv->prim.wrapped = 0;
  448. dev_priv->prim.last_flush = 0;
  449. dev_priv->prim.last_wrap = 0;
  450. dev_priv->prim.high_mark = 256 * DMA_BLOCK_SIZE;
  451. dev_priv->prim.status[0] = dev_priv->primary->offset;
  452. dev_priv->prim.status[1] = 0;
  453. dev_priv->sarea_priv->last_wrap = 0;
  454. dev_priv->sarea_priv->last_frame.head = 0;
  455. dev_priv->sarea_priv->last_frame.wrap = 0;
  456. if ( mga_freelist_init( dev, dev_priv ) < 0 ) {
  457. DRM_ERROR( "could not initialize freelist\n" );
  458. /* Assign dev_private so we can do cleanup. */
  459. dev->dev_private = (void *)dev_priv;
  460. mga_do_cleanup_dma( dev );
  461. return DRM_ERR(ENOMEM);
  462. }
  463. /* Make dev_private visable to others. */
  464. dev->dev_private = (void *)dev_priv;
  465. return 0;
  466. }
  467. static int mga_do_cleanup_dma( drm_device_t *dev )
  468. {
  469. DRM_DEBUG( "\n" );
  470. /* Make sure interrupts are disabled here because the uninstall ioctl
  471. * may not have been called from userspace and after dev_private
  472. * is freed, it's too late.
  473. */
  474. if ( dev->irq_enabled ) drm_irq_uninstall(dev);
  475. if ( dev->dev_private ) {
  476. drm_mga_private_t *dev_priv = dev->dev_private;
  477. if ( dev_priv->warp != NULL )
  478. drm_core_ioremapfree( dev_priv->warp, dev );
  479. if ( dev_priv->primary != NULL )
  480. drm_core_ioremapfree( dev_priv->primary, dev );
  481. if ( dev->agp_buffer_map != NULL )
  482. drm_core_ioremapfree( dev->agp_buffer_map, dev );
  483. if ( dev_priv->head != NULL ) {
  484. mga_freelist_cleanup( dev );
  485. }
  486. drm_free( dev->dev_private, sizeof(drm_mga_private_t),
  487. DRM_MEM_DRIVER );
  488. dev->dev_private = NULL;
  489. }
  490. return 0;
  491. }
  492. int mga_dma_init( DRM_IOCTL_ARGS )
  493. {
  494. DRM_DEVICE;
  495. drm_mga_init_t init;
  496. LOCK_TEST_WITH_RETURN( dev, filp );
  497. DRM_COPY_FROM_USER_IOCTL( init, (drm_mga_init_t __user *)data, sizeof(init) );
  498. switch ( init.func ) {
  499. case MGA_INIT_DMA:
  500. return mga_do_init_dma( dev, &init );
  501. case MGA_CLEANUP_DMA:
  502. return mga_do_cleanup_dma( dev );
  503. }
  504. return DRM_ERR(EINVAL);
  505. }
  506. /* ================================================================
  507. * Primary DMA stream management
  508. */
  509. int mga_dma_flush( DRM_IOCTL_ARGS )
  510. {
  511. DRM_DEVICE;
  512. drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private;
  513. drm_lock_t lock;
  514. LOCK_TEST_WITH_RETURN( dev, filp );
  515. DRM_COPY_FROM_USER_IOCTL( lock, (drm_lock_t __user *)data, sizeof(lock) );
  516. DRM_DEBUG( "%s%s%s\n",
  517. (lock.flags & _DRM_LOCK_FLUSH) ? "flush, " : "",
  518. (lock.flags & _DRM_LOCK_FLUSH_ALL) ? "flush all, " : "",
  519. (lock.flags & _DRM_LOCK_QUIESCENT) ? "idle, " : "" );
  520. WRAP_WAIT_WITH_RETURN( dev_priv );
  521. if ( lock.flags & (_DRM_LOCK_FLUSH | _DRM_LOCK_FLUSH_ALL) ) {
  522. mga_do_dma_flush( dev_priv );
  523. }
  524. if ( lock.flags & _DRM_LOCK_QUIESCENT ) {
  525. #if MGA_DMA_DEBUG
  526. int ret = mga_do_wait_for_idle( dev_priv );
  527. if ( ret < 0 )
  528. DRM_INFO( "%s: -EBUSY\n", __FUNCTION__ );
  529. return ret;
  530. #else
  531. return mga_do_wait_for_idle( dev_priv );
  532. #endif
  533. } else {
  534. return 0;
  535. }
  536. }
  537. int mga_dma_reset( DRM_IOCTL_ARGS )
  538. {
  539. DRM_DEVICE;
  540. drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private;
  541. LOCK_TEST_WITH_RETURN( dev, filp );
  542. return mga_do_dma_reset( dev_priv );
  543. }
  544. /* ================================================================
  545. * DMA buffer management
  546. */
  547. static int mga_dma_get_buffers( DRMFILE filp,
  548. drm_device_t *dev, drm_dma_t *d )
  549. {
  550. drm_buf_t *buf;
  551. int i;
  552. for ( i = d->granted_count ; i < d->request_count ; i++ ) {
  553. buf = mga_freelist_get( dev );
  554. if ( !buf ) return DRM_ERR(EAGAIN);
  555. buf->filp = filp;
  556. if ( DRM_COPY_TO_USER( &d->request_indices[i],
  557. &buf->idx, sizeof(buf->idx) ) )
  558. return DRM_ERR(EFAULT);
  559. if ( DRM_COPY_TO_USER( &d->request_sizes[i],
  560. &buf->total, sizeof(buf->total) ) )
  561. return DRM_ERR(EFAULT);
  562. d->granted_count++;
  563. }
  564. return 0;
  565. }
  566. int mga_dma_buffers( DRM_IOCTL_ARGS )
  567. {
  568. DRM_DEVICE;
  569. drm_device_dma_t *dma = dev->dma;
  570. drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private;
  571. drm_dma_t __user *argp = (void __user *)data;
  572. drm_dma_t d;
  573. int ret = 0;
  574. LOCK_TEST_WITH_RETURN( dev, filp );
  575. DRM_COPY_FROM_USER_IOCTL( d, argp, sizeof(d) );
  576. /* Please don't send us buffers.
  577. */
  578. if ( d.send_count != 0 ) {
  579. DRM_ERROR( "Process %d trying to send %d buffers via drmDMA\n",
  580. DRM_CURRENTPID, d.send_count );
  581. return DRM_ERR(EINVAL);
  582. }
  583. /* We'll send you buffers.
  584. */
  585. if ( d.request_count < 0 || d.request_count > dma->buf_count ) {
  586. DRM_ERROR( "Process %d trying to get %d buffers (of %d max)\n",
  587. DRM_CURRENTPID, d.request_count, dma->buf_count );
  588. return DRM_ERR(EINVAL);
  589. }
  590. WRAP_TEST_WITH_RETURN( dev_priv );
  591. d.granted_count = 0;
  592. if ( d.request_count ) {
  593. ret = mga_dma_get_buffers( filp, dev, &d );
  594. }
  595. DRM_COPY_TO_USER_IOCTL( argp, d, sizeof(d) );
  596. return ret;
  597. }
  598. void mga_driver_pretakedown(drm_device_t *dev)
  599. {
  600. mga_do_cleanup_dma( dev );
  601. }
  602. int mga_driver_dma_quiescent(drm_device_t *dev)
  603. {
  604. drm_mga_private_t *dev_priv = dev->dev_private;
  605. return mga_do_wait_for_idle( dev_priv );
  606. }