i810_dma.c 36 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385
  1. /* i810_dma.c -- DMA support for the i810 -*- linux-c -*-
  2. * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com
  3. *
  4. * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
  5. * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
  6. * All Rights Reserved.
  7. *
  8. * Permission is hereby granted, free of charge, to any person obtaining a
  9. * copy of this software and associated documentation files (the "Software"),
  10. * to deal in the Software without restriction, including without limitation
  11. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12. * and/or sell copies of the Software, and to permit persons to whom the
  13. * Software is furnished to do so, subject to the following conditions:
  14. *
  15. * The above copyright notice and this permission notice (including the next
  16. * paragraph) shall be included in all copies or substantial portions of the
  17. * Software.
  18. *
  19. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  22. * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  23. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  24. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  25. * DEALINGS IN THE SOFTWARE.
  26. *
  27. * Authors: Rickard E. (Rik) Faith <faith@valinux.com>
  28. * Jeff Hartmann <jhartmann@valinux.com>
  29. * Keith Whitwell <keith@tungstengraphics.com>
  30. *
  31. */
  32. #include "drmP.h"
  33. #include "drm.h"
  34. #include "i810_drm.h"
  35. #include "i810_drv.h"
  36. #include <linux/interrupt.h> /* For task queue support */
  37. #include <linux/delay.h>
  38. #include <linux/pagemap.h>
  39. #define I810_BUF_FREE 2
  40. #define I810_BUF_CLIENT 1
  41. #define I810_BUF_HARDWARE 0
  42. #define I810_BUF_UNMAPPED 0
  43. #define I810_BUF_MAPPED 1
  44. #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,4,2)
  45. #define down_write down
  46. #define up_write up
  47. #endif
  48. static drm_buf_t *i810_freelist_get(drm_device_t *dev)
  49. {
  50. drm_device_dma_t *dma = dev->dma;
  51. int i;
  52. int used;
  53. /* Linear search might not be the best solution */
  54. for (i = 0; i < dma->buf_count; i++) {
  55. drm_buf_t *buf = dma->buflist[ i ];
  56. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  57. /* In use is already a pointer */
  58. used = cmpxchg(buf_priv->in_use, I810_BUF_FREE,
  59. I810_BUF_CLIENT);
  60. if (used == I810_BUF_FREE) {
  61. return buf;
  62. }
  63. }
  64. return NULL;
  65. }
  66. /* This should only be called if the buffer is not sent to the hardware
  67. * yet, the hardware updates in use for us once its on the ring buffer.
  68. */
  69. static int i810_freelist_put(drm_device_t *dev, drm_buf_t *buf)
  70. {
  71. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  72. int used;
  73. /* In use is already a pointer */
  74. used = cmpxchg(buf_priv->in_use, I810_BUF_CLIENT, I810_BUF_FREE);
  75. if (used != I810_BUF_CLIENT) {
  76. DRM_ERROR("Freeing buffer thats not in use : %d\n", buf->idx);
  77. return -EINVAL;
  78. }
  79. return 0;
  80. }
  81. static struct file_operations i810_buffer_fops = {
  82. .open = drm_open,
  83. .flush = drm_flush,
  84. .release = drm_release,
  85. .ioctl = drm_ioctl,
  86. .mmap = i810_mmap_buffers,
  87. .fasync = drm_fasync,
  88. };
  89. int i810_mmap_buffers(struct file *filp, struct vm_area_struct *vma)
  90. {
  91. drm_file_t *priv = filp->private_data;
  92. drm_device_t *dev;
  93. drm_i810_private_t *dev_priv;
  94. drm_buf_t *buf;
  95. drm_i810_buf_priv_t *buf_priv;
  96. lock_kernel();
  97. dev = priv->head->dev;
  98. dev_priv = dev->dev_private;
  99. buf = dev_priv->mmap_buffer;
  100. buf_priv = buf->dev_private;
  101. vma->vm_flags |= (VM_IO | VM_DONTCOPY);
  102. vma->vm_file = filp;
  103. buf_priv->currently_mapped = I810_BUF_MAPPED;
  104. unlock_kernel();
  105. if (io_remap_pfn_range(vma, vma->vm_start,
  106. VM_OFFSET(vma) >> PAGE_SHIFT,
  107. vma->vm_end - vma->vm_start,
  108. vma->vm_page_prot)) return -EAGAIN;
  109. return 0;
  110. }
  111. static int i810_map_buffer(drm_buf_t *buf, struct file *filp)
  112. {
  113. drm_file_t *priv = filp->private_data;
  114. drm_device_t *dev = priv->head->dev;
  115. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  116. drm_i810_private_t *dev_priv = dev->dev_private;
  117. struct file_operations *old_fops;
  118. int retcode = 0;
  119. if (buf_priv->currently_mapped == I810_BUF_MAPPED)
  120. return -EINVAL;
  121. down_write( &current->mm->mmap_sem );
  122. old_fops = filp->f_op;
  123. filp->f_op = &i810_buffer_fops;
  124. dev_priv->mmap_buffer = buf;
  125. buf_priv->virtual = (void *)do_mmap(filp, 0, buf->total,
  126. PROT_READ|PROT_WRITE,
  127. MAP_SHARED,
  128. buf->bus_address);
  129. dev_priv->mmap_buffer = NULL;
  130. filp->f_op = old_fops;
  131. if ((unsigned long)buf_priv->virtual > -1024UL) {
  132. /* Real error */
  133. DRM_ERROR("mmap error\n");
  134. retcode = (signed int)buf_priv->virtual;
  135. buf_priv->virtual = NULL;
  136. }
  137. up_write( &current->mm->mmap_sem );
  138. return retcode;
  139. }
  140. static int i810_unmap_buffer(drm_buf_t *buf)
  141. {
  142. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  143. int retcode = 0;
  144. if (buf_priv->currently_mapped != I810_BUF_MAPPED)
  145. return -EINVAL;
  146. down_write(&current->mm->mmap_sem);
  147. retcode = do_munmap(current->mm,
  148. (unsigned long)buf_priv->virtual,
  149. (size_t) buf->total);
  150. up_write(&current->mm->mmap_sem);
  151. buf_priv->currently_mapped = I810_BUF_UNMAPPED;
  152. buf_priv->virtual = NULL;
  153. return retcode;
  154. }
  155. static int i810_dma_get_buffer(drm_device_t *dev, drm_i810_dma_t *d,
  156. struct file *filp)
  157. {
  158. drm_buf_t *buf;
  159. drm_i810_buf_priv_t *buf_priv;
  160. int retcode = 0;
  161. buf = i810_freelist_get(dev);
  162. if (!buf) {
  163. retcode = -ENOMEM;
  164. DRM_DEBUG("retcode=%d\n", retcode);
  165. return retcode;
  166. }
  167. retcode = i810_map_buffer(buf, filp);
  168. if (retcode) {
  169. i810_freelist_put(dev, buf);
  170. DRM_ERROR("mapbuf failed, retcode %d\n", retcode);
  171. return retcode;
  172. }
  173. buf->filp = filp;
  174. buf_priv = buf->dev_private;
  175. d->granted = 1;
  176. d->request_idx = buf->idx;
  177. d->request_size = buf->total;
  178. d->virtual = buf_priv->virtual;
  179. return retcode;
  180. }
  181. static int i810_dma_cleanup(drm_device_t *dev)
  182. {
  183. drm_device_dma_t *dma = dev->dma;
  184. /* Make sure interrupts are disabled here because the uninstall ioctl
  185. * may not have been called from userspace and after dev_private
  186. * is freed, it's too late.
  187. */
  188. if (drm_core_check_feature(dev, DRIVER_HAVE_IRQ) && dev->irq_enabled)
  189. drm_irq_uninstall(dev);
  190. if (dev->dev_private) {
  191. int i;
  192. drm_i810_private_t *dev_priv =
  193. (drm_i810_private_t *) dev->dev_private;
  194. if (dev_priv->ring.virtual_start) {
  195. drm_ioremapfree((void *) dev_priv->ring.virtual_start,
  196. dev_priv->ring.Size, dev);
  197. }
  198. if (dev_priv->hw_status_page) {
  199. pci_free_consistent(dev->pdev, PAGE_SIZE,
  200. dev_priv->hw_status_page,
  201. dev_priv->dma_status_page);
  202. /* Need to rewrite hardware status page */
  203. I810_WRITE(0x02080, 0x1ffff000);
  204. }
  205. drm_free(dev->dev_private, sizeof(drm_i810_private_t),
  206. DRM_MEM_DRIVER);
  207. dev->dev_private = NULL;
  208. for (i = 0; i < dma->buf_count; i++) {
  209. drm_buf_t *buf = dma->buflist[ i ];
  210. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  211. if ( buf_priv->kernel_virtual && buf->total )
  212. drm_ioremapfree(buf_priv->kernel_virtual, buf->total, dev);
  213. }
  214. }
  215. return 0;
  216. }
  217. static int i810_wait_ring(drm_device_t *dev, int n)
  218. {
  219. drm_i810_private_t *dev_priv = dev->dev_private;
  220. drm_i810_ring_buffer_t *ring = &(dev_priv->ring);
  221. int iters = 0;
  222. unsigned long end;
  223. unsigned int last_head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  224. end = jiffies + (HZ*3);
  225. while (ring->space < n) {
  226. ring->head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  227. ring->space = ring->head - (ring->tail+8);
  228. if (ring->space < 0) ring->space += ring->Size;
  229. if (ring->head != last_head) {
  230. end = jiffies + (HZ*3);
  231. last_head = ring->head;
  232. }
  233. iters++;
  234. if (time_before(end, jiffies)) {
  235. DRM_ERROR("space: %d wanted %d\n", ring->space, n);
  236. DRM_ERROR("lockup\n");
  237. goto out_wait_ring;
  238. }
  239. udelay(1);
  240. }
  241. out_wait_ring:
  242. return iters;
  243. }
  244. static void i810_kernel_lost_context(drm_device_t *dev)
  245. {
  246. drm_i810_private_t *dev_priv = dev->dev_private;
  247. drm_i810_ring_buffer_t *ring = &(dev_priv->ring);
  248. ring->head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  249. ring->tail = I810_READ(LP_RING + RING_TAIL);
  250. ring->space = ring->head - (ring->tail+8);
  251. if (ring->space < 0) ring->space += ring->Size;
  252. }
  253. static int i810_freelist_init(drm_device_t *dev, drm_i810_private_t *dev_priv)
  254. {
  255. drm_device_dma_t *dma = dev->dma;
  256. int my_idx = 24;
  257. u32 *hw_status = (u32 *)(dev_priv->hw_status_page + my_idx);
  258. int i;
  259. if (dma->buf_count > 1019) {
  260. /* Not enough space in the status page for the freelist */
  261. return -EINVAL;
  262. }
  263. for (i = 0; i < dma->buf_count; i++) {
  264. drm_buf_t *buf = dma->buflist[ i ];
  265. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  266. buf_priv->in_use = hw_status++;
  267. buf_priv->my_use_idx = my_idx;
  268. my_idx += 4;
  269. *buf_priv->in_use = I810_BUF_FREE;
  270. buf_priv->kernel_virtual = drm_ioremap(buf->bus_address,
  271. buf->total, dev);
  272. }
  273. return 0;
  274. }
  275. static int i810_dma_initialize(drm_device_t *dev,
  276. drm_i810_private_t *dev_priv,
  277. drm_i810_init_t *init)
  278. {
  279. struct list_head *list;
  280. memset(dev_priv, 0, sizeof(drm_i810_private_t));
  281. list_for_each(list, &dev->maplist->head) {
  282. drm_map_list_t *r_list = list_entry(list, drm_map_list_t, head);
  283. if (r_list->map &&
  284. r_list->map->type == _DRM_SHM &&
  285. r_list->map->flags & _DRM_CONTAINS_LOCK ) {
  286. dev_priv->sarea_map = r_list->map;
  287. break;
  288. }
  289. }
  290. if (!dev_priv->sarea_map) {
  291. dev->dev_private = (void *)dev_priv;
  292. i810_dma_cleanup(dev);
  293. DRM_ERROR("can not find sarea!\n");
  294. return -EINVAL;
  295. }
  296. dev_priv->mmio_map = drm_core_findmap(dev, init->mmio_offset);
  297. if (!dev_priv->mmio_map) {
  298. dev->dev_private = (void *)dev_priv;
  299. i810_dma_cleanup(dev);
  300. DRM_ERROR("can not find mmio map!\n");
  301. return -EINVAL;
  302. }
  303. dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
  304. if (!dev->agp_buffer_map) {
  305. dev->dev_private = (void *)dev_priv;
  306. i810_dma_cleanup(dev);
  307. DRM_ERROR("can not find dma buffer map!\n");
  308. return -EINVAL;
  309. }
  310. dev_priv->sarea_priv = (drm_i810_sarea_t *)
  311. ((u8 *)dev_priv->sarea_map->handle +
  312. init->sarea_priv_offset);
  313. dev_priv->ring.Start = init->ring_start;
  314. dev_priv->ring.End = init->ring_end;
  315. dev_priv->ring.Size = init->ring_size;
  316. dev_priv->ring.virtual_start = drm_ioremap(dev->agp->base +
  317. init->ring_start,
  318. init->ring_size, dev);
  319. if (dev_priv->ring.virtual_start == NULL) {
  320. dev->dev_private = (void *) dev_priv;
  321. i810_dma_cleanup(dev);
  322. DRM_ERROR("can not ioremap virtual address for"
  323. " ring buffer\n");
  324. return -ENOMEM;
  325. }
  326. dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
  327. dev_priv->w = init->w;
  328. dev_priv->h = init->h;
  329. dev_priv->pitch = init->pitch;
  330. dev_priv->back_offset = init->back_offset;
  331. dev_priv->depth_offset = init->depth_offset;
  332. dev_priv->front_offset = init->front_offset;
  333. dev_priv->overlay_offset = init->overlay_offset;
  334. dev_priv->overlay_physical = init->overlay_physical;
  335. dev_priv->front_di1 = init->front_offset | init->pitch_bits;
  336. dev_priv->back_di1 = init->back_offset | init->pitch_bits;
  337. dev_priv->zi1 = init->depth_offset | init->pitch_bits;
  338. /* Program Hardware Status Page */
  339. dev_priv->hw_status_page =
  340. pci_alloc_consistent(dev->pdev, PAGE_SIZE,
  341. &dev_priv->dma_status_page);
  342. if (!dev_priv->hw_status_page) {
  343. dev->dev_private = (void *)dev_priv;
  344. i810_dma_cleanup(dev);
  345. DRM_ERROR("Can not allocate hardware status page\n");
  346. return -ENOMEM;
  347. }
  348. memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
  349. DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
  350. I810_WRITE(0x02080, dev_priv->dma_status_page);
  351. DRM_DEBUG("Enabled hardware status page\n");
  352. /* Now we need to init our freelist */
  353. if (i810_freelist_init(dev, dev_priv) != 0) {
  354. dev->dev_private = (void *)dev_priv;
  355. i810_dma_cleanup(dev);
  356. DRM_ERROR("Not enough space in the status page for"
  357. " the freelist\n");
  358. return -ENOMEM;
  359. }
  360. dev->dev_private = (void *)dev_priv;
  361. return 0;
  362. }
  363. /* i810 DRM version 1.1 used a smaller init structure with different
  364. * ordering of values than is currently used (drm >= 1.2). There is
  365. * no defined way to detect the XFree version to correct this problem,
  366. * however by checking using this procedure we can detect the correct
  367. * thing to do.
  368. *
  369. * #1 Read the Smaller init structure from user-space
  370. * #2 Verify the overlay_physical is a valid physical address, or NULL
  371. * If it isn't then we have a v1.1 client. Fix up params.
  372. * If it is, then we have a 1.2 client... get the rest of the data.
  373. */
  374. static int i810_dma_init_compat(drm_i810_init_t *init, unsigned long arg)
  375. {
  376. /* Get v1.1 init data */
  377. if (copy_from_user(init, (drm_i810_pre12_init_t __user *)arg,
  378. sizeof(drm_i810_pre12_init_t))) {
  379. return -EFAULT;
  380. }
  381. if ((!init->overlay_physical) || (init->overlay_physical > 4096)) {
  382. /* This is a v1.2 client, just get the v1.2 init data */
  383. DRM_INFO("Using POST v1.2 init.\n");
  384. if (copy_from_user(init, (drm_i810_init_t __user *)arg,
  385. sizeof(drm_i810_init_t))) {
  386. return -EFAULT;
  387. }
  388. } else {
  389. /* This is a v1.1 client, fix the params */
  390. DRM_INFO("Using PRE v1.2 init.\n");
  391. init->pitch_bits = init->h;
  392. init->pitch = init->w;
  393. init->h = init->overlay_physical;
  394. init->w = init->overlay_offset;
  395. init->overlay_physical = 0;
  396. init->overlay_offset = 0;
  397. }
  398. return 0;
  399. }
  400. static int i810_dma_init(struct inode *inode, struct file *filp,
  401. unsigned int cmd, unsigned long arg)
  402. {
  403. drm_file_t *priv = filp->private_data;
  404. drm_device_t *dev = priv->head->dev;
  405. drm_i810_private_t *dev_priv;
  406. drm_i810_init_t init;
  407. int retcode = 0;
  408. /* Get only the init func */
  409. if (copy_from_user(&init, (void __user *)arg, sizeof(drm_i810_init_func_t)))
  410. return -EFAULT;
  411. switch(init.func) {
  412. case I810_INIT_DMA:
  413. /* This case is for backward compatibility. It
  414. * handles XFree 4.1.0 and 4.2.0, and has to
  415. * do some parameter checking as described below.
  416. * It will someday go away.
  417. */
  418. retcode = i810_dma_init_compat(&init, arg);
  419. if (retcode)
  420. return retcode;
  421. dev_priv = drm_alloc(sizeof(drm_i810_private_t),
  422. DRM_MEM_DRIVER);
  423. if (dev_priv == NULL)
  424. return -ENOMEM;
  425. retcode = i810_dma_initialize(dev, dev_priv, &init);
  426. break;
  427. default:
  428. case I810_INIT_DMA_1_4:
  429. DRM_INFO("Using v1.4 init.\n");
  430. if (copy_from_user(&init, (drm_i810_init_t __user *)arg,
  431. sizeof(drm_i810_init_t))) {
  432. return -EFAULT;
  433. }
  434. dev_priv = drm_alloc(sizeof(drm_i810_private_t),
  435. DRM_MEM_DRIVER);
  436. if (dev_priv == NULL)
  437. return -ENOMEM;
  438. retcode = i810_dma_initialize(dev, dev_priv, &init);
  439. break;
  440. case I810_CLEANUP_DMA:
  441. DRM_INFO("DMA Cleanup\n");
  442. retcode = i810_dma_cleanup(dev);
  443. break;
  444. }
  445. return retcode;
  446. }
  447. /* Most efficient way to verify state for the i810 is as it is
  448. * emitted. Non-conformant state is silently dropped.
  449. *
  450. * Use 'volatile' & local var tmp to force the emitted values to be
  451. * identical to the verified ones.
  452. */
  453. static void i810EmitContextVerified( drm_device_t *dev,
  454. volatile unsigned int *code )
  455. {
  456. drm_i810_private_t *dev_priv = dev->dev_private;
  457. int i, j = 0;
  458. unsigned int tmp;
  459. RING_LOCALS;
  460. BEGIN_LP_RING( I810_CTX_SETUP_SIZE );
  461. OUT_RING( GFX_OP_COLOR_FACTOR );
  462. OUT_RING( code[I810_CTXREG_CF1] );
  463. OUT_RING( GFX_OP_STIPPLE );
  464. OUT_RING( code[I810_CTXREG_ST1] );
  465. for ( i = 4 ; i < I810_CTX_SETUP_SIZE ; i++ ) {
  466. tmp = code[i];
  467. if ((tmp & (7<<29)) == (3<<29) &&
  468. (tmp & (0x1f<<24)) < (0x1d<<24))
  469. {
  470. OUT_RING( tmp );
  471. j++;
  472. }
  473. else printk("constext state dropped!!!\n");
  474. }
  475. if (j & 1)
  476. OUT_RING( 0 );
  477. ADVANCE_LP_RING();
  478. }
  479. static void i810EmitTexVerified( drm_device_t *dev,
  480. volatile unsigned int *code )
  481. {
  482. drm_i810_private_t *dev_priv = dev->dev_private;
  483. int i, j = 0;
  484. unsigned int tmp;
  485. RING_LOCALS;
  486. BEGIN_LP_RING( I810_TEX_SETUP_SIZE );
  487. OUT_RING( GFX_OP_MAP_INFO );
  488. OUT_RING( code[I810_TEXREG_MI1] );
  489. OUT_RING( code[I810_TEXREG_MI2] );
  490. OUT_RING( code[I810_TEXREG_MI3] );
  491. for ( i = 4 ; i < I810_TEX_SETUP_SIZE ; i++ ) {
  492. tmp = code[i];
  493. if ((tmp & (7<<29)) == (3<<29) &&
  494. (tmp & (0x1f<<24)) < (0x1d<<24))
  495. {
  496. OUT_RING( tmp );
  497. j++;
  498. }
  499. else printk("texture state dropped!!!\n");
  500. }
  501. if (j & 1)
  502. OUT_RING( 0 );
  503. ADVANCE_LP_RING();
  504. }
  505. /* Need to do some additional checking when setting the dest buffer.
  506. */
  507. static void i810EmitDestVerified( drm_device_t *dev,
  508. volatile unsigned int *code )
  509. {
  510. drm_i810_private_t *dev_priv = dev->dev_private;
  511. unsigned int tmp;
  512. RING_LOCALS;
  513. BEGIN_LP_RING( I810_DEST_SETUP_SIZE + 2 );
  514. tmp = code[I810_DESTREG_DI1];
  515. if (tmp == dev_priv->front_di1 || tmp == dev_priv->back_di1) {
  516. OUT_RING( CMD_OP_DESTBUFFER_INFO );
  517. OUT_RING( tmp );
  518. } else
  519. DRM_DEBUG("bad di1 %x (allow %x or %x)\n",
  520. tmp, dev_priv->front_di1, dev_priv->back_di1);
  521. /* invarient:
  522. */
  523. OUT_RING( CMD_OP_Z_BUFFER_INFO );
  524. OUT_RING( dev_priv->zi1 );
  525. OUT_RING( GFX_OP_DESTBUFFER_VARS );
  526. OUT_RING( code[I810_DESTREG_DV1] );
  527. OUT_RING( GFX_OP_DRAWRECT_INFO );
  528. OUT_RING( code[I810_DESTREG_DR1] );
  529. OUT_RING( code[I810_DESTREG_DR2] );
  530. OUT_RING( code[I810_DESTREG_DR3] );
  531. OUT_RING( code[I810_DESTREG_DR4] );
  532. OUT_RING( 0 );
  533. ADVANCE_LP_RING();
  534. }
  535. static void i810EmitState( drm_device_t *dev )
  536. {
  537. drm_i810_private_t *dev_priv = dev->dev_private;
  538. drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
  539. unsigned int dirty = sarea_priv->dirty;
  540. DRM_DEBUG("%s %x\n", __FUNCTION__, dirty);
  541. if (dirty & I810_UPLOAD_BUFFERS) {
  542. i810EmitDestVerified( dev, sarea_priv->BufferState );
  543. sarea_priv->dirty &= ~I810_UPLOAD_BUFFERS;
  544. }
  545. if (dirty & I810_UPLOAD_CTX) {
  546. i810EmitContextVerified( dev, sarea_priv->ContextState );
  547. sarea_priv->dirty &= ~I810_UPLOAD_CTX;
  548. }
  549. if (dirty & I810_UPLOAD_TEX0) {
  550. i810EmitTexVerified( dev, sarea_priv->TexState[0] );
  551. sarea_priv->dirty &= ~I810_UPLOAD_TEX0;
  552. }
  553. if (dirty & I810_UPLOAD_TEX1) {
  554. i810EmitTexVerified( dev, sarea_priv->TexState[1] );
  555. sarea_priv->dirty &= ~I810_UPLOAD_TEX1;
  556. }
  557. }
  558. /* need to verify
  559. */
  560. static void i810_dma_dispatch_clear( drm_device_t *dev, int flags,
  561. unsigned int clear_color,
  562. unsigned int clear_zval )
  563. {
  564. drm_i810_private_t *dev_priv = dev->dev_private;
  565. drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
  566. int nbox = sarea_priv->nbox;
  567. drm_clip_rect_t *pbox = sarea_priv->boxes;
  568. int pitch = dev_priv->pitch;
  569. int cpp = 2;
  570. int i;
  571. RING_LOCALS;
  572. if ( dev_priv->current_page == 1 ) {
  573. unsigned int tmp = flags;
  574. flags &= ~(I810_FRONT | I810_BACK);
  575. if (tmp & I810_FRONT) flags |= I810_BACK;
  576. if (tmp & I810_BACK) flags |= I810_FRONT;
  577. }
  578. i810_kernel_lost_context(dev);
  579. if (nbox > I810_NR_SAREA_CLIPRECTS)
  580. nbox = I810_NR_SAREA_CLIPRECTS;
  581. for (i = 0 ; i < nbox ; i++, pbox++) {
  582. unsigned int x = pbox->x1;
  583. unsigned int y = pbox->y1;
  584. unsigned int width = (pbox->x2 - x) * cpp;
  585. unsigned int height = pbox->y2 - y;
  586. unsigned int start = y * pitch + x * cpp;
  587. if (pbox->x1 > pbox->x2 ||
  588. pbox->y1 > pbox->y2 ||
  589. pbox->x2 > dev_priv->w ||
  590. pbox->y2 > dev_priv->h)
  591. continue;
  592. if ( flags & I810_FRONT ) {
  593. BEGIN_LP_RING( 6 );
  594. OUT_RING( BR00_BITBLT_CLIENT |
  595. BR00_OP_COLOR_BLT | 0x3 );
  596. OUT_RING( BR13_SOLID_PATTERN | (0xF0 << 16) | pitch );
  597. OUT_RING( (height << 16) | width );
  598. OUT_RING( start );
  599. OUT_RING( clear_color );
  600. OUT_RING( 0 );
  601. ADVANCE_LP_RING();
  602. }
  603. if ( flags & I810_BACK ) {
  604. BEGIN_LP_RING( 6 );
  605. OUT_RING( BR00_BITBLT_CLIENT |
  606. BR00_OP_COLOR_BLT | 0x3 );
  607. OUT_RING( BR13_SOLID_PATTERN | (0xF0 << 16) | pitch );
  608. OUT_RING( (height << 16) | width );
  609. OUT_RING( dev_priv->back_offset + start );
  610. OUT_RING( clear_color );
  611. OUT_RING( 0 );
  612. ADVANCE_LP_RING();
  613. }
  614. if ( flags & I810_DEPTH ) {
  615. BEGIN_LP_RING( 6 );
  616. OUT_RING( BR00_BITBLT_CLIENT |
  617. BR00_OP_COLOR_BLT | 0x3 );
  618. OUT_RING( BR13_SOLID_PATTERN | (0xF0 << 16) | pitch );
  619. OUT_RING( (height << 16) | width );
  620. OUT_RING( dev_priv->depth_offset + start );
  621. OUT_RING( clear_zval );
  622. OUT_RING( 0 );
  623. ADVANCE_LP_RING();
  624. }
  625. }
  626. }
  627. static void i810_dma_dispatch_swap( drm_device_t *dev )
  628. {
  629. drm_i810_private_t *dev_priv = dev->dev_private;
  630. drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
  631. int nbox = sarea_priv->nbox;
  632. drm_clip_rect_t *pbox = sarea_priv->boxes;
  633. int pitch = dev_priv->pitch;
  634. int cpp = 2;
  635. int i;
  636. RING_LOCALS;
  637. DRM_DEBUG("swapbuffers\n");
  638. i810_kernel_lost_context(dev);
  639. if (nbox > I810_NR_SAREA_CLIPRECTS)
  640. nbox = I810_NR_SAREA_CLIPRECTS;
  641. for (i = 0 ; i < nbox; i++, pbox++)
  642. {
  643. unsigned int w = pbox->x2 - pbox->x1;
  644. unsigned int h = pbox->y2 - pbox->y1;
  645. unsigned int dst = pbox->x1*cpp + pbox->y1*pitch;
  646. unsigned int start = dst;
  647. if (pbox->x1 > pbox->x2 ||
  648. pbox->y1 > pbox->y2 ||
  649. pbox->x2 > dev_priv->w ||
  650. pbox->y2 > dev_priv->h)
  651. continue;
  652. BEGIN_LP_RING( 6 );
  653. OUT_RING( BR00_BITBLT_CLIENT | BR00_OP_SRC_COPY_BLT | 0x4 );
  654. OUT_RING( pitch | (0xCC << 16));
  655. OUT_RING( (h << 16) | (w * cpp));
  656. if (dev_priv->current_page == 0)
  657. OUT_RING(dev_priv->front_offset + start);
  658. else
  659. OUT_RING(dev_priv->back_offset + start);
  660. OUT_RING( pitch );
  661. if (dev_priv->current_page == 0)
  662. OUT_RING(dev_priv->back_offset + start);
  663. else
  664. OUT_RING(dev_priv->front_offset + start);
  665. ADVANCE_LP_RING();
  666. }
  667. }
  668. static void i810_dma_dispatch_vertex(drm_device_t *dev,
  669. drm_buf_t *buf,
  670. int discard,
  671. int used)
  672. {
  673. drm_i810_private_t *dev_priv = dev->dev_private;
  674. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  675. drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
  676. drm_clip_rect_t *box = sarea_priv->boxes;
  677. int nbox = sarea_priv->nbox;
  678. unsigned long address = (unsigned long)buf->bus_address;
  679. unsigned long start = address - dev->agp->base;
  680. int i = 0;
  681. RING_LOCALS;
  682. i810_kernel_lost_context(dev);
  683. if (nbox > I810_NR_SAREA_CLIPRECTS)
  684. nbox = I810_NR_SAREA_CLIPRECTS;
  685. if (used > 4*1024)
  686. used = 0;
  687. if (sarea_priv->dirty)
  688. i810EmitState( dev );
  689. if (buf_priv->currently_mapped == I810_BUF_MAPPED) {
  690. unsigned int prim = (sarea_priv->vertex_prim & PR_MASK);
  691. *(u32 *)buf_priv->kernel_virtual = ((GFX_OP_PRIMITIVE | prim | ((used/4)-2)));
  692. if (used & 4) {
  693. *(u32 *)((u32)buf_priv->kernel_virtual + used) = 0;
  694. used += 4;
  695. }
  696. i810_unmap_buffer(buf);
  697. }
  698. if (used) {
  699. do {
  700. if (i < nbox) {
  701. BEGIN_LP_RING(4);
  702. OUT_RING( GFX_OP_SCISSOR | SC_UPDATE_SCISSOR |
  703. SC_ENABLE );
  704. OUT_RING( GFX_OP_SCISSOR_INFO );
  705. OUT_RING( box[i].x1 | (box[i].y1<<16) );
  706. OUT_RING( (box[i].x2-1) | ((box[i].y2-1)<<16) );
  707. ADVANCE_LP_RING();
  708. }
  709. BEGIN_LP_RING(4);
  710. OUT_RING( CMD_OP_BATCH_BUFFER );
  711. OUT_RING( start | BB1_PROTECTED );
  712. OUT_RING( start + used - 4 );
  713. OUT_RING( 0 );
  714. ADVANCE_LP_RING();
  715. } while (++i < nbox);
  716. }
  717. if (discard) {
  718. dev_priv->counter++;
  719. (void) cmpxchg(buf_priv->in_use, I810_BUF_CLIENT,
  720. I810_BUF_HARDWARE);
  721. BEGIN_LP_RING(8);
  722. OUT_RING( CMD_STORE_DWORD_IDX );
  723. OUT_RING( 20 );
  724. OUT_RING( dev_priv->counter );
  725. OUT_RING( CMD_STORE_DWORD_IDX );
  726. OUT_RING( buf_priv->my_use_idx );
  727. OUT_RING( I810_BUF_FREE );
  728. OUT_RING( CMD_REPORT_HEAD );
  729. OUT_RING( 0 );
  730. ADVANCE_LP_RING();
  731. }
  732. }
  733. static void i810_dma_dispatch_flip( drm_device_t *dev )
  734. {
  735. drm_i810_private_t *dev_priv = dev->dev_private;
  736. int pitch = dev_priv->pitch;
  737. RING_LOCALS;
  738. DRM_DEBUG( "%s: page=%d pfCurrentPage=%d\n",
  739. __FUNCTION__,
  740. dev_priv->current_page,
  741. dev_priv->sarea_priv->pf_current_page);
  742. i810_kernel_lost_context(dev);
  743. BEGIN_LP_RING( 2 );
  744. OUT_RING( INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE );
  745. OUT_RING( 0 );
  746. ADVANCE_LP_RING();
  747. BEGIN_LP_RING( I810_DEST_SETUP_SIZE + 2 );
  748. /* On i815 at least ASYNC is buggy */
  749. /* pitch<<5 is from 11.2.8 p158,
  750. its the pitch / 8 then left shifted 8,
  751. so (pitch >> 3) << 8 */
  752. OUT_RING( CMD_OP_FRONTBUFFER_INFO | (pitch<<5) /*| ASYNC_FLIP */ );
  753. if ( dev_priv->current_page == 0 ) {
  754. OUT_RING( dev_priv->back_offset );
  755. dev_priv->current_page = 1;
  756. } else {
  757. OUT_RING( dev_priv->front_offset );
  758. dev_priv->current_page = 0;
  759. }
  760. OUT_RING(0);
  761. ADVANCE_LP_RING();
  762. BEGIN_LP_RING(2);
  763. OUT_RING( CMD_OP_WAIT_FOR_EVENT | WAIT_FOR_PLANE_A_FLIP );
  764. OUT_RING( 0 );
  765. ADVANCE_LP_RING();
  766. /* Increment the frame counter. The client-side 3D driver must
  767. * throttle the framerate by waiting for this value before
  768. * performing the swapbuffer ioctl.
  769. */
  770. dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
  771. }
  772. static void i810_dma_quiescent(drm_device_t *dev)
  773. {
  774. drm_i810_private_t *dev_priv = dev->dev_private;
  775. RING_LOCALS;
  776. /* printk("%s\n", __FUNCTION__); */
  777. i810_kernel_lost_context(dev);
  778. BEGIN_LP_RING(4);
  779. OUT_RING( INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE );
  780. OUT_RING( CMD_REPORT_HEAD );
  781. OUT_RING( 0 );
  782. OUT_RING( 0 );
  783. ADVANCE_LP_RING();
  784. i810_wait_ring( dev, dev_priv->ring.Size - 8 );
  785. }
  786. static int i810_flush_queue(drm_device_t *dev)
  787. {
  788. drm_i810_private_t *dev_priv = dev->dev_private;
  789. drm_device_dma_t *dma = dev->dma;
  790. int i, ret = 0;
  791. RING_LOCALS;
  792. /* printk("%s\n", __FUNCTION__); */
  793. i810_kernel_lost_context(dev);
  794. BEGIN_LP_RING(2);
  795. OUT_RING( CMD_REPORT_HEAD );
  796. OUT_RING( 0 );
  797. ADVANCE_LP_RING();
  798. i810_wait_ring( dev, dev_priv->ring.Size - 8 );
  799. for (i = 0; i < dma->buf_count; i++) {
  800. drm_buf_t *buf = dma->buflist[ i ];
  801. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  802. int used = cmpxchg(buf_priv->in_use, I810_BUF_HARDWARE,
  803. I810_BUF_FREE);
  804. if (used == I810_BUF_HARDWARE)
  805. DRM_DEBUG("reclaimed from HARDWARE\n");
  806. if (used == I810_BUF_CLIENT)
  807. DRM_DEBUG("still on client\n");
  808. }
  809. return ret;
  810. }
  811. /* Must be called with the lock held */
  812. void i810_reclaim_buffers(drm_device_t *dev, struct file *filp)
  813. {
  814. drm_device_dma_t *dma = dev->dma;
  815. int i;
  816. if (!dma) return;
  817. if (!dev->dev_private) return;
  818. if (!dma->buflist) return;
  819. i810_flush_queue(dev);
  820. for (i = 0; i < dma->buf_count; i++) {
  821. drm_buf_t *buf = dma->buflist[ i ];
  822. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  823. if (buf->filp == filp && buf_priv) {
  824. int used = cmpxchg(buf_priv->in_use, I810_BUF_CLIENT,
  825. I810_BUF_FREE);
  826. if (used == I810_BUF_CLIENT)
  827. DRM_DEBUG("reclaimed from client\n");
  828. if (buf_priv->currently_mapped == I810_BUF_MAPPED)
  829. buf_priv->currently_mapped = I810_BUF_UNMAPPED;
  830. }
  831. }
  832. }
  833. int i810_flush_ioctl(struct inode *inode, struct file *filp,
  834. unsigned int cmd, unsigned long arg)
  835. {
  836. drm_file_t *priv = filp->private_data;
  837. drm_device_t *dev = priv->head->dev;
  838. LOCK_TEST_WITH_RETURN(dev, filp);
  839. i810_flush_queue(dev);
  840. return 0;
  841. }
  842. static int i810_dma_vertex(struct inode *inode, struct file *filp,
  843. unsigned int cmd, unsigned long arg)
  844. {
  845. drm_file_t *priv = filp->private_data;
  846. drm_device_t *dev = priv->head->dev;
  847. drm_device_dma_t *dma = dev->dma;
  848. drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private;
  849. u32 *hw_status = dev_priv->hw_status_page;
  850. drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
  851. dev_priv->sarea_priv;
  852. drm_i810_vertex_t vertex;
  853. if (copy_from_user(&vertex, (drm_i810_vertex_t __user *)arg, sizeof(vertex)))
  854. return -EFAULT;
  855. LOCK_TEST_WITH_RETURN(dev, filp);
  856. DRM_DEBUG("i810 dma vertex, idx %d used %d discard %d\n",
  857. vertex.idx, vertex.used, vertex.discard);
  858. if (vertex.idx < 0 || vertex.idx > dma->buf_count)
  859. return -EINVAL;
  860. i810_dma_dispatch_vertex( dev,
  861. dma->buflist[ vertex.idx ],
  862. vertex.discard, vertex.used );
  863. atomic_add(vertex.used, &dev->counts[_DRM_STAT_SECONDARY]);
  864. atomic_inc(&dev->counts[_DRM_STAT_DMA]);
  865. sarea_priv->last_enqueue = dev_priv->counter-1;
  866. sarea_priv->last_dispatch = (int) hw_status[5];
  867. return 0;
  868. }
  869. static int i810_clear_bufs(struct inode *inode, struct file *filp,
  870. unsigned int cmd, unsigned long arg)
  871. {
  872. drm_file_t *priv = filp->private_data;
  873. drm_device_t *dev = priv->head->dev;
  874. drm_i810_clear_t clear;
  875. if (copy_from_user(&clear, (drm_i810_clear_t __user *)arg, sizeof(clear)))
  876. return -EFAULT;
  877. LOCK_TEST_WITH_RETURN(dev, filp);
  878. /* GH: Someone's doing nasty things... */
  879. if (!dev->dev_private) {
  880. return -EINVAL;
  881. }
  882. i810_dma_dispatch_clear( dev, clear.flags,
  883. clear.clear_color,
  884. clear.clear_depth );
  885. return 0;
  886. }
  887. static int i810_swap_bufs(struct inode *inode, struct file *filp,
  888. unsigned int cmd, unsigned long arg)
  889. {
  890. drm_file_t *priv = filp->private_data;
  891. drm_device_t *dev = priv->head->dev;
  892. DRM_DEBUG("i810_swap_bufs\n");
  893. LOCK_TEST_WITH_RETURN(dev, filp);
  894. i810_dma_dispatch_swap( dev );
  895. return 0;
  896. }
  897. static int i810_getage(struct inode *inode, struct file *filp, unsigned int cmd,
  898. unsigned long arg)
  899. {
  900. drm_file_t *priv = filp->private_data;
  901. drm_device_t *dev = priv->head->dev;
  902. drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private;
  903. u32 *hw_status = dev_priv->hw_status_page;
  904. drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
  905. dev_priv->sarea_priv;
  906. sarea_priv->last_dispatch = (int) hw_status[5];
  907. return 0;
  908. }
  909. static int i810_getbuf(struct inode *inode, struct file *filp, unsigned int cmd,
  910. unsigned long arg)
  911. {
  912. drm_file_t *priv = filp->private_data;
  913. drm_device_t *dev = priv->head->dev;
  914. int retcode = 0;
  915. drm_i810_dma_t d;
  916. drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private;
  917. u32 *hw_status = dev_priv->hw_status_page;
  918. drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
  919. dev_priv->sarea_priv;
  920. if (copy_from_user(&d, (drm_i810_dma_t __user *)arg, sizeof(d)))
  921. return -EFAULT;
  922. LOCK_TEST_WITH_RETURN(dev, filp);
  923. d.granted = 0;
  924. retcode = i810_dma_get_buffer(dev, &d, filp);
  925. DRM_DEBUG("i810_dma: %d returning %d, granted = %d\n",
  926. current->pid, retcode, d.granted);
  927. if (copy_to_user((drm_dma_t __user *)arg, &d, sizeof(d)))
  928. return -EFAULT;
  929. sarea_priv->last_dispatch = (int) hw_status[5];
  930. return retcode;
  931. }
  932. static int i810_copybuf(struct inode *inode,
  933. struct file *filp, unsigned int cmd, unsigned long arg)
  934. {
  935. /* Never copy - 2.4.x doesn't need it */
  936. return 0;
  937. }
  938. static int i810_docopy(struct inode *inode, struct file *filp, unsigned int cmd,
  939. unsigned long arg)
  940. {
  941. /* Never copy - 2.4.x doesn't need it */
  942. return 0;
  943. }
  944. static void i810_dma_dispatch_mc(drm_device_t *dev, drm_buf_t *buf, int used,
  945. unsigned int last_render)
  946. {
  947. drm_i810_private_t *dev_priv = dev->dev_private;
  948. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  949. drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
  950. unsigned long address = (unsigned long)buf->bus_address;
  951. unsigned long start = address - dev->agp->base;
  952. int u;
  953. RING_LOCALS;
  954. i810_kernel_lost_context(dev);
  955. u = cmpxchg(buf_priv->in_use, I810_BUF_CLIENT,
  956. I810_BUF_HARDWARE);
  957. if (u != I810_BUF_CLIENT) {
  958. DRM_DEBUG("MC found buffer that isn't mine!\n");
  959. }
  960. if (used > 4*1024)
  961. used = 0;
  962. sarea_priv->dirty = 0x7f;
  963. DRM_DEBUG("dispatch mc addr 0x%lx, used 0x%x\n",
  964. address, used);
  965. dev_priv->counter++;
  966. DRM_DEBUG("dispatch counter : %ld\n", dev_priv->counter);
  967. DRM_DEBUG("i810_dma_dispatch_mc\n");
  968. DRM_DEBUG("start : %lx\n", start);
  969. DRM_DEBUG("used : %d\n", used);
  970. DRM_DEBUG("start + used - 4 : %ld\n", start + used - 4);
  971. if (buf_priv->currently_mapped == I810_BUF_MAPPED) {
  972. if (used & 4) {
  973. *(u32 *)((u32)buf_priv->virtual + used) = 0;
  974. used += 4;
  975. }
  976. i810_unmap_buffer(buf);
  977. }
  978. BEGIN_LP_RING(4);
  979. OUT_RING( CMD_OP_BATCH_BUFFER );
  980. OUT_RING( start | BB1_PROTECTED );
  981. OUT_RING( start + used - 4 );
  982. OUT_RING( 0 );
  983. ADVANCE_LP_RING();
  984. BEGIN_LP_RING(8);
  985. OUT_RING( CMD_STORE_DWORD_IDX );
  986. OUT_RING( buf_priv->my_use_idx );
  987. OUT_RING( I810_BUF_FREE );
  988. OUT_RING( 0 );
  989. OUT_RING( CMD_STORE_DWORD_IDX );
  990. OUT_RING( 16 );
  991. OUT_RING( last_render );
  992. OUT_RING( 0 );
  993. ADVANCE_LP_RING();
  994. }
  995. static int i810_dma_mc(struct inode *inode, struct file *filp,
  996. unsigned int cmd, unsigned long arg)
  997. {
  998. drm_file_t *priv = filp->private_data;
  999. drm_device_t *dev = priv->head->dev;
  1000. drm_device_dma_t *dma = dev->dma;
  1001. drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private;
  1002. u32 *hw_status = dev_priv->hw_status_page;
  1003. drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
  1004. dev_priv->sarea_priv;
  1005. drm_i810_mc_t mc;
  1006. if (copy_from_user(&mc, (drm_i810_mc_t __user *)arg, sizeof(mc)))
  1007. return -EFAULT;
  1008. LOCK_TEST_WITH_RETURN(dev, filp);
  1009. if (mc.idx >= dma->buf_count || mc.idx < 0)
  1010. return -EINVAL;
  1011. i810_dma_dispatch_mc(dev, dma->buflist[mc.idx], mc.used,
  1012. mc.last_render );
  1013. atomic_add(mc.used, &dev->counts[_DRM_STAT_SECONDARY]);
  1014. atomic_inc(&dev->counts[_DRM_STAT_DMA]);
  1015. sarea_priv->last_enqueue = dev_priv->counter-1;
  1016. sarea_priv->last_dispatch = (int) hw_status[5];
  1017. return 0;
  1018. }
  1019. static int i810_rstatus(struct inode *inode, struct file *filp,
  1020. unsigned int cmd, unsigned long arg)
  1021. {
  1022. drm_file_t *priv = filp->private_data;
  1023. drm_device_t *dev = priv->head->dev;
  1024. drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private;
  1025. return (int)(((u32 *)(dev_priv->hw_status_page))[4]);
  1026. }
  1027. static int i810_ov0_info(struct inode *inode, struct file *filp,
  1028. unsigned int cmd, unsigned long arg)
  1029. {
  1030. drm_file_t *priv = filp->private_data;
  1031. drm_device_t *dev = priv->head->dev;
  1032. drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private;
  1033. drm_i810_overlay_t data;
  1034. data.offset = dev_priv->overlay_offset;
  1035. data.physical = dev_priv->overlay_physical;
  1036. if (copy_to_user((drm_i810_overlay_t __user *)arg,&data,sizeof(data)))
  1037. return -EFAULT;
  1038. return 0;
  1039. }
  1040. static int i810_fstatus(struct inode *inode, struct file *filp,
  1041. unsigned int cmd, unsigned long arg)
  1042. {
  1043. drm_file_t *priv = filp->private_data;
  1044. drm_device_t *dev = priv->head->dev;
  1045. drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private;
  1046. LOCK_TEST_WITH_RETURN(dev, filp);
  1047. return I810_READ(0x30008);
  1048. }
  1049. static int i810_ov0_flip(struct inode *inode, struct file *filp,
  1050. unsigned int cmd, unsigned long arg)
  1051. {
  1052. drm_file_t *priv = filp->private_data;
  1053. drm_device_t *dev = priv->head->dev;
  1054. drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private;
  1055. LOCK_TEST_WITH_RETURN(dev, filp);
  1056. //Tell the overlay to update
  1057. I810_WRITE(0x30000,dev_priv->overlay_physical | 0x80000000);
  1058. return 0;
  1059. }
  1060. /* Not sure why this isn't set all the time:
  1061. */
  1062. static void i810_do_init_pageflip( drm_device_t *dev )
  1063. {
  1064. drm_i810_private_t *dev_priv = dev->dev_private;
  1065. DRM_DEBUG("%s\n", __FUNCTION__);
  1066. dev_priv->page_flipping = 1;
  1067. dev_priv->current_page = 0;
  1068. dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
  1069. }
  1070. static int i810_do_cleanup_pageflip( drm_device_t *dev )
  1071. {
  1072. drm_i810_private_t *dev_priv = dev->dev_private;
  1073. DRM_DEBUG("%s\n", __FUNCTION__);
  1074. if (dev_priv->current_page != 0)
  1075. i810_dma_dispatch_flip( dev );
  1076. dev_priv->page_flipping = 0;
  1077. return 0;
  1078. }
  1079. static int i810_flip_bufs(struct inode *inode, struct file *filp,
  1080. unsigned int cmd, unsigned long arg)
  1081. {
  1082. drm_file_t *priv = filp->private_data;
  1083. drm_device_t *dev = priv->head->dev;
  1084. drm_i810_private_t *dev_priv = dev->dev_private;
  1085. DRM_DEBUG("%s\n", __FUNCTION__);
  1086. LOCK_TEST_WITH_RETURN(dev, filp);
  1087. if (!dev_priv->page_flipping)
  1088. i810_do_init_pageflip( dev );
  1089. i810_dma_dispatch_flip( dev );
  1090. return 0;
  1091. }
  1092. void i810_driver_pretakedown(drm_device_t *dev)
  1093. {
  1094. i810_dma_cleanup( dev );
  1095. }
  1096. void i810_driver_prerelease(drm_device_t *dev, DRMFILE filp)
  1097. {
  1098. if (dev->dev_private) {
  1099. drm_i810_private_t *dev_priv = dev->dev_private;
  1100. if (dev_priv->page_flipping) {
  1101. i810_do_cleanup_pageflip(dev);
  1102. }
  1103. }
  1104. }
  1105. void i810_driver_release(drm_device_t *dev, struct file *filp)
  1106. {
  1107. i810_reclaim_buffers(dev, filp);
  1108. }
  1109. int i810_driver_dma_quiescent(drm_device_t *dev)
  1110. {
  1111. i810_dma_quiescent( dev );
  1112. return 0;
  1113. }
  1114. drm_ioctl_desc_t i810_ioctls[] = {
  1115. [DRM_IOCTL_NR(DRM_I810_INIT)] = { i810_dma_init, 1, 1 },
  1116. [DRM_IOCTL_NR(DRM_I810_VERTEX)] = { i810_dma_vertex, 1, 0 },
  1117. [DRM_IOCTL_NR(DRM_I810_CLEAR)] = { i810_clear_bufs, 1, 0 },
  1118. [DRM_IOCTL_NR(DRM_I810_FLUSH)] = { i810_flush_ioctl, 1, 0 },
  1119. [DRM_IOCTL_NR(DRM_I810_GETAGE)] = { i810_getage, 1, 0 },
  1120. [DRM_IOCTL_NR(DRM_I810_GETBUF)] = { i810_getbuf, 1, 0 },
  1121. [DRM_IOCTL_NR(DRM_I810_SWAP)] = { i810_swap_bufs, 1, 0 },
  1122. [DRM_IOCTL_NR(DRM_I810_COPY)] = { i810_copybuf, 1, 0 },
  1123. [DRM_IOCTL_NR(DRM_I810_DOCOPY)] = { i810_docopy, 1, 0 },
  1124. [DRM_IOCTL_NR(DRM_I810_OV0INFO)] = { i810_ov0_info, 1, 0 },
  1125. [DRM_IOCTL_NR(DRM_I810_FSTATUS)] = { i810_fstatus, 1, 0 },
  1126. [DRM_IOCTL_NR(DRM_I810_OV0FLIP)] = { i810_ov0_flip, 1, 0 },
  1127. [DRM_IOCTL_NR(DRM_I810_MC)] = { i810_dma_mc, 1, 1 },
  1128. [DRM_IOCTL_NR(DRM_I810_RSTATUS)] = { i810_rstatus, 1, 0 },
  1129. [DRM_IOCTL_NR(DRM_I810_FLIP)] = { i810_flip_bufs, 1, 0 }
  1130. };
  1131. int i810_max_ioctl = DRM_ARRAY_SIZE(i810_ioctls);