irq.c 10 KB

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  1. /*
  2. * Platform dependent support for SGI SN
  3. *
  4. * This file is subject to the terms and conditions of the GNU General Public
  5. * License. See the file "COPYING" in the main directory of this archive
  6. * for more details.
  7. *
  8. * Copyright (c) 2000-2004 Silicon Graphics, Inc. All Rights Reserved.
  9. */
  10. #include <linux/irq.h>
  11. #include <asm/sn/intr.h>
  12. #include <asm/sn/addrs.h>
  13. #include <asm/sn/arch.h>
  14. #include "xtalk/xwidgetdev.h"
  15. #include <asm/sn/pcibus_provider_defs.h>
  16. #include <asm/sn/pcidev.h>
  17. #include "pci/pcibr_provider.h"
  18. #include <asm/sn/shub_mmr.h>
  19. #include <asm/sn/sn_sal.h>
  20. static void force_interrupt(int irq);
  21. static void register_intr_pda(struct sn_irq_info *sn_irq_info);
  22. static void unregister_intr_pda(struct sn_irq_info *sn_irq_info);
  23. extern int sn_force_interrupt_flag;
  24. extern int sn_ioif_inited;
  25. struct sn_irq_info **sn_irq;
  26. static inline uint64_t sn_intr_alloc(nasid_t local_nasid, int local_widget,
  27. u64 sn_irq_info,
  28. int req_irq, nasid_t req_nasid,
  29. int req_slice)
  30. {
  31. struct ia64_sal_retval ret_stuff;
  32. ret_stuff.status = 0;
  33. ret_stuff.v0 = 0;
  34. SAL_CALL_NOLOCK(ret_stuff, (u64) SN_SAL_IOIF_INTERRUPT,
  35. (u64) SAL_INTR_ALLOC, (u64) local_nasid,
  36. (u64) local_widget, (u64) sn_irq_info, (u64) req_irq,
  37. (u64) req_nasid, (u64) req_slice);
  38. return ret_stuff.status;
  39. }
  40. static inline void sn_intr_free(nasid_t local_nasid, int local_widget,
  41. struct sn_irq_info *sn_irq_info)
  42. {
  43. struct ia64_sal_retval ret_stuff;
  44. ret_stuff.status = 0;
  45. ret_stuff.v0 = 0;
  46. SAL_CALL_NOLOCK(ret_stuff, (u64) SN_SAL_IOIF_INTERRUPT,
  47. (u64) SAL_INTR_FREE, (u64) local_nasid,
  48. (u64) local_widget, (u64) sn_irq_info->irq_irq,
  49. (u64) sn_irq_info->irq_cookie, 0, 0);
  50. }
  51. static unsigned int sn_startup_irq(unsigned int irq)
  52. {
  53. return 0;
  54. }
  55. static void sn_shutdown_irq(unsigned int irq)
  56. {
  57. }
  58. static void sn_disable_irq(unsigned int irq)
  59. {
  60. }
  61. static void sn_enable_irq(unsigned int irq)
  62. {
  63. }
  64. static void sn_ack_irq(unsigned int irq)
  65. {
  66. uint64_t event_occurred, mask = 0;
  67. int nasid;
  68. irq = irq & 0xff;
  69. nasid = get_nasid();
  70. event_occurred =
  71. HUB_L((uint64_t *) GLOBAL_MMR_ADDR(nasid, SH_EVENT_OCCURRED));
  72. mask = event_occurred & SH_ALL_INT_MASK;
  73. HUB_S((uint64_t *) GLOBAL_MMR_ADDR(nasid, SH_EVENT_OCCURRED_ALIAS),
  74. mask);
  75. __set_bit(irq, (volatile void *)pda->sn_in_service_ivecs);
  76. move_irq(irq);
  77. }
  78. static void sn_end_irq(unsigned int irq)
  79. {
  80. int nasid;
  81. int ivec;
  82. uint64_t event_occurred;
  83. ivec = irq & 0xff;
  84. if (ivec == SGI_UART_VECTOR) {
  85. nasid = get_nasid();
  86. event_occurred = HUB_L((uint64_t *) GLOBAL_MMR_ADDR
  87. (nasid, SH_EVENT_OCCURRED));
  88. /* If the UART bit is set here, we may have received an
  89. * interrupt from the UART that the driver missed. To
  90. * make sure, we IPI ourselves to force us to look again.
  91. */
  92. if (event_occurred & SH_EVENT_OCCURRED_UART_INT_MASK) {
  93. platform_send_ipi(smp_processor_id(), SGI_UART_VECTOR,
  94. IA64_IPI_DM_INT, 0);
  95. }
  96. }
  97. __clear_bit(ivec, (volatile void *)pda->sn_in_service_ivecs);
  98. if (sn_force_interrupt_flag)
  99. force_interrupt(irq);
  100. }
  101. static void sn_set_affinity_irq(unsigned int irq, cpumask_t mask)
  102. {
  103. struct sn_irq_info *sn_irq_info = sn_irq[irq];
  104. struct sn_irq_info *tmp_sn_irq_info;
  105. int cpuid, cpuphys;
  106. nasid_t t_nasid; /* nasid to target */
  107. int t_slice; /* slice to target */
  108. /* allocate a temp sn_irq_info struct to get new target info */
  109. tmp_sn_irq_info = kmalloc(sizeof(*tmp_sn_irq_info), GFP_KERNEL);
  110. if (!tmp_sn_irq_info)
  111. return;
  112. cpuid = first_cpu(mask);
  113. cpuphys = cpu_physical_id(cpuid);
  114. t_nasid = cpuid_to_nasid(cpuid);
  115. t_slice = cpuid_to_slice(cpuid);
  116. while (sn_irq_info) {
  117. int status;
  118. int local_widget;
  119. uint64_t bridge = (uint64_t) sn_irq_info->irq_bridge;
  120. nasid_t local_nasid = NASID_GET(bridge);
  121. if (!bridge)
  122. break; /* irq is not a device interrupt */
  123. if (local_nasid & 1)
  124. local_widget = TIO_SWIN_WIDGETNUM(bridge);
  125. else
  126. local_widget = SWIN_WIDGETNUM(bridge);
  127. /* Free the old PROM sn_irq_info structure */
  128. sn_intr_free(local_nasid, local_widget, sn_irq_info);
  129. /* allocate a new PROM sn_irq_info struct */
  130. status = sn_intr_alloc(local_nasid, local_widget,
  131. __pa(tmp_sn_irq_info), irq, t_nasid,
  132. t_slice);
  133. if (status == 0) {
  134. /* Update kernels sn_irq_info with new target info */
  135. unregister_intr_pda(sn_irq_info);
  136. sn_irq_info->irq_cpuid = cpuid;
  137. sn_irq_info->irq_nasid = t_nasid;
  138. sn_irq_info->irq_slice = t_slice;
  139. sn_irq_info->irq_xtalkaddr =
  140. tmp_sn_irq_info->irq_xtalkaddr;
  141. sn_irq_info->irq_cookie = tmp_sn_irq_info->irq_cookie;
  142. register_intr_pda(sn_irq_info);
  143. if (IS_PCI_BRIDGE_ASIC(sn_irq_info->irq_bridge_type)) {
  144. pcibr_change_devices_irq(sn_irq_info);
  145. }
  146. sn_irq_info = sn_irq_info->irq_next;
  147. #ifdef CONFIG_SMP
  148. set_irq_affinity_info((irq & 0xff), cpuphys, 0);
  149. #endif
  150. } else {
  151. break; /* snp_affinity failed the intr_alloc */
  152. }
  153. }
  154. kfree(tmp_sn_irq_info);
  155. }
  156. struct hw_interrupt_type irq_type_sn = {
  157. "SN hub",
  158. sn_startup_irq,
  159. sn_shutdown_irq,
  160. sn_enable_irq,
  161. sn_disable_irq,
  162. sn_ack_irq,
  163. sn_end_irq,
  164. sn_set_affinity_irq
  165. };
  166. unsigned int sn_local_vector_to_irq(u8 vector)
  167. {
  168. return (CPU_VECTOR_TO_IRQ(smp_processor_id(), vector));
  169. }
  170. void sn_irq_init(void)
  171. {
  172. int i;
  173. irq_desc_t *base_desc = irq_desc;
  174. for (i = 0; i < NR_IRQS; i++) {
  175. if (base_desc[i].handler == &no_irq_type) {
  176. base_desc[i].handler = &irq_type_sn;
  177. }
  178. }
  179. }
  180. static void register_intr_pda(struct sn_irq_info *sn_irq_info)
  181. {
  182. int irq = sn_irq_info->irq_irq;
  183. int cpu = sn_irq_info->irq_cpuid;
  184. if (pdacpu(cpu)->sn_last_irq < irq) {
  185. pdacpu(cpu)->sn_last_irq = irq;
  186. }
  187. if (pdacpu(cpu)->sn_first_irq == 0 || pdacpu(cpu)->sn_first_irq > irq) {
  188. pdacpu(cpu)->sn_first_irq = irq;
  189. }
  190. }
  191. static void unregister_intr_pda(struct sn_irq_info *sn_irq_info)
  192. {
  193. int irq = sn_irq_info->irq_irq;
  194. int cpu = sn_irq_info->irq_cpuid;
  195. struct sn_irq_info *tmp_irq_info;
  196. int i, foundmatch;
  197. if (pdacpu(cpu)->sn_last_irq == irq) {
  198. foundmatch = 0;
  199. for (i = pdacpu(cpu)->sn_last_irq - 1; i; i--) {
  200. tmp_irq_info = sn_irq[i];
  201. while (tmp_irq_info) {
  202. if (tmp_irq_info->irq_cpuid == cpu) {
  203. foundmatch++;
  204. break;
  205. }
  206. tmp_irq_info = tmp_irq_info->irq_next;
  207. }
  208. if (foundmatch) {
  209. break;
  210. }
  211. }
  212. pdacpu(cpu)->sn_last_irq = i;
  213. }
  214. if (pdacpu(cpu)->sn_first_irq == irq) {
  215. foundmatch = 0;
  216. for (i = pdacpu(cpu)->sn_first_irq + 1; i < NR_IRQS; i++) {
  217. tmp_irq_info = sn_irq[i];
  218. while (tmp_irq_info) {
  219. if (tmp_irq_info->irq_cpuid == cpu) {
  220. foundmatch++;
  221. break;
  222. }
  223. tmp_irq_info = tmp_irq_info->irq_next;
  224. }
  225. if (foundmatch) {
  226. break;
  227. }
  228. }
  229. pdacpu(cpu)->sn_first_irq = ((i == NR_IRQS) ? 0 : i);
  230. }
  231. }
  232. struct sn_irq_info *sn_irq_alloc(nasid_t local_nasid, int local_widget, int irq,
  233. nasid_t nasid, int slice)
  234. {
  235. struct sn_irq_info *sn_irq_info;
  236. int status;
  237. sn_irq_info = kmalloc(sizeof(*sn_irq_info), GFP_KERNEL);
  238. if (sn_irq_info == NULL)
  239. return NULL;
  240. memset(sn_irq_info, 0x0, sizeof(*sn_irq_info));
  241. status =
  242. sn_intr_alloc(local_nasid, local_widget, __pa(sn_irq_info), irq,
  243. nasid, slice);
  244. if (status) {
  245. kfree(sn_irq_info);
  246. return NULL;
  247. } else {
  248. return sn_irq_info;
  249. }
  250. }
  251. void sn_irq_free(struct sn_irq_info *sn_irq_info)
  252. {
  253. uint64_t bridge = (uint64_t) sn_irq_info->irq_bridge;
  254. nasid_t local_nasid = NASID_GET(bridge);
  255. int local_widget;
  256. if (local_nasid & 1) /* tio check */
  257. local_widget = TIO_SWIN_WIDGETNUM(bridge);
  258. else
  259. local_widget = SWIN_WIDGETNUM(bridge);
  260. sn_intr_free(local_nasid, local_widget, sn_irq_info);
  261. kfree(sn_irq_info);
  262. }
  263. void sn_irq_fixup(struct pci_dev *pci_dev, struct sn_irq_info *sn_irq_info)
  264. {
  265. nasid_t nasid = sn_irq_info->irq_nasid;
  266. int slice = sn_irq_info->irq_slice;
  267. int cpu = nasid_slice_to_cpuid(nasid, slice);
  268. sn_irq_info->irq_cpuid = cpu;
  269. sn_irq_info->irq_pciioinfo = SN_PCIDEV_INFO(pci_dev);
  270. /* link it into the sn_irq[irq] list */
  271. sn_irq_info->irq_next = sn_irq[sn_irq_info->irq_irq];
  272. sn_irq[sn_irq_info->irq_irq] = sn_irq_info;
  273. (void)register_intr_pda(sn_irq_info);
  274. }
  275. static void force_interrupt(int irq)
  276. {
  277. struct sn_irq_info *sn_irq_info;
  278. if (!sn_ioif_inited)
  279. return;
  280. sn_irq_info = sn_irq[irq];
  281. while (sn_irq_info) {
  282. if (IS_PCI_BRIDGE_ASIC(sn_irq_info->irq_bridge_type) &&
  283. (sn_irq_info->irq_bridge != NULL)) {
  284. pcibr_force_interrupt(sn_irq_info);
  285. }
  286. sn_irq_info = sn_irq_info->irq_next;
  287. }
  288. }
  289. /*
  290. * Check for lost interrupts. If the PIC int_status reg. says that
  291. * an interrupt has been sent, but not handled, and the interrupt
  292. * is not pending in either the cpu irr regs or in the soft irr regs,
  293. * and the interrupt is not in service, then the interrupt may have
  294. * been lost. Force an interrupt on that pin. It is possible that
  295. * the interrupt is in flight, so we may generate a spurious interrupt,
  296. * but we should never miss a real lost interrupt.
  297. */
  298. static void sn_check_intr(int irq, struct sn_irq_info *sn_irq_info)
  299. {
  300. uint64_t regval;
  301. int irr_reg_num;
  302. int irr_bit;
  303. uint64_t irr_reg;
  304. struct pcidev_info *pcidev_info;
  305. struct pcibus_info *pcibus_info;
  306. pcidev_info = (struct pcidev_info *)sn_irq_info->irq_pciioinfo;
  307. if (!pcidev_info)
  308. return;
  309. pcibus_info =
  310. (struct pcibus_info *)pcidev_info->pdi_host_pcidev_info->
  311. pdi_pcibus_info;
  312. regval = pcireg_intr_status_get(pcibus_info);
  313. irr_reg_num = irq_to_vector(irq) / 64;
  314. irr_bit = irq_to_vector(irq) % 64;
  315. switch (irr_reg_num) {
  316. case 0:
  317. irr_reg = ia64_getreg(_IA64_REG_CR_IRR0);
  318. break;
  319. case 1:
  320. irr_reg = ia64_getreg(_IA64_REG_CR_IRR1);
  321. break;
  322. case 2:
  323. irr_reg = ia64_getreg(_IA64_REG_CR_IRR2);
  324. break;
  325. case 3:
  326. irr_reg = ia64_getreg(_IA64_REG_CR_IRR3);
  327. break;
  328. }
  329. if (!test_bit(irr_bit, &irr_reg)) {
  330. if (!test_bit(irq, pda->sn_soft_irr)) {
  331. if (!test_bit(irq, pda->sn_in_service_ivecs)) {
  332. regval &= 0xff;
  333. if (sn_irq_info->irq_int_bit & regval &
  334. sn_irq_info->irq_last_intr) {
  335. regval &=
  336. ~(sn_irq_info->
  337. irq_int_bit & regval);
  338. pcibr_force_interrupt(sn_irq_info);
  339. }
  340. }
  341. }
  342. }
  343. sn_irq_info->irq_last_intr = regval;
  344. }
  345. void sn_lb_int_war_check(void)
  346. {
  347. int i;
  348. if (!sn_ioif_inited || pda->sn_first_irq == 0)
  349. return;
  350. for (i = pda->sn_first_irq; i <= pda->sn_last_irq; i++) {
  351. struct sn_irq_info *sn_irq_info = sn_irq[i];
  352. while (sn_irq_info) {
  353. /* Only call for PCI bridges that are fully initialized. */
  354. if (IS_PCI_BRIDGE_ASIC(sn_irq_info->irq_bridge_type) &&
  355. (sn_irq_info->irq_bridge != NULL)) {
  356. sn_check_intr(i, sn_irq_info);
  357. }
  358. sn_irq_info = sn_irq_info->irq_next;
  359. }
  360. }
  361. }