sun4d_smp.c 10 KB

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  1. /* Sparc SS1000/SC2000 SMP support.
  2. *
  3. * Copyright (C) 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
  4. *
  5. * Based on sun4m's smp.c, which is:
  6. * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
  7. */
  8. #include <linux/clockchips.h>
  9. #include <linux/interrupt.h>
  10. #include <linux/profile.h>
  11. #include <linux/delay.h>
  12. #include <linux/cpu.h>
  13. #include <asm/cacheflush.h>
  14. #include <asm/switch_to.h>
  15. #include <asm/tlbflush.h>
  16. #include <asm/timer.h>
  17. #include <asm/sbi.h>
  18. #include <asm/mmu.h>
  19. #include "kernel.h"
  20. #include "irq.h"
  21. #define IRQ_CROSS_CALL 15
  22. static volatile int smp_processors_ready;
  23. static int smp_highest_cpu;
  24. static inline unsigned long sun4d_swap(volatile unsigned long *ptr, unsigned long val)
  25. {
  26. __asm__ __volatile__("swap [%1], %0\n\t" :
  27. "=&r" (val), "=&r" (ptr) :
  28. "0" (val), "1" (ptr));
  29. return val;
  30. }
  31. static void smp4d_ipi_init(void);
  32. static unsigned char cpu_leds[32];
  33. static inline void show_leds(int cpuid)
  34. {
  35. cpuid &= 0x1e;
  36. __asm__ __volatile__ ("stba %0, [%1] %2" : :
  37. "r" ((cpu_leds[cpuid] << 4) | cpu_leds[cpuid+1]),
  38. "r" (ECSR_BASE(cpuid) | BB_LEDS),
  39. "i" (ASI_M_CTL));
  40. }
  41. void __cpuinit smp4d_callin(void)
  42. {
  43. int cpuid = hard_smp4d_processor_id();
  44. unsigned long flags;
  45. /* Show we are alive */
  46. cpu_leds[cpuid] = 0x6;
  47. show_leds(cpuid);
  48. /* Enable level15 interrupt, disable level14 interrupt for now */
  49. cc_set_imsk((cc_get_imsk() & ~0x8000) | 0x4000);
  50. local_flush_cache_all();
  51. local_flush_tlb_all();
  52. notify_cpu_starting(cpuid);
  53. /*
  54. * Unblock the master CPU _only_ when the scheduler state
  55. * of all secondary CPUs will be up-to-date, so after
  56. * the SMP initialization the master will be just allowed
  57. * to call the scheduler code.
  58. */
  59. /* Get our local ticker going. */
  60. register_percpu_ce(cpuid);
  61. calibrate_delay();
  62. smp_store_cpu_info(cpuid);
  63. local_flush_cache_all();
  64. local_flush_tlb_all();
  65. /* Allow master to continue. */
  66. sun4d_swap((unsigned long *)&cpu_callin_map[cpuid], 1);
  67. local_flush_cache_all();
  68. local_flush_tlb_all();
  69. while ((unsigned long)current_set[cpuid] < PAGE_OFFSET)
  70. barrier();
  71. while (current_set[cpuid]->cpu != cpuid)
  72. barrier();
  73. /* Fix idle thread fields. */
  74. __asm__ __volatile__("ld [%0], %%g6\n\t"
  75. : : "r" (&current_set[cpuid])
  76. : "memory" /* paranoid */);
  77. cpu_leds[cpuid] = 0x9;
  78. show_leds(cpuid);
  79. /* Attach to the address space of init_task. */
  80. atomic_inc(&init_mm.mm_count);
  81. current->active_mm = &init_mm;
  82. local_flush_cache_all();
  83. local_flush_tlb_all();
  84. local_irq_enable(); /* We don't allow PIL 14 yet */
  85. while (!cpumask_test_cpu(cpuid, &smp_commenced_mask))
  86. barrier();
  87. spin_lock_irqsave(&sun4d_imsk_lock, flags);
  88. cc_set_imsk(cc_get_imsk() & ~0x4000); /* Allow PIL 14 as well */
  89. spin_unlock_irqrestore(&sun4d_imsk_lock, flags);
  90. set_cpu_online(cpuid, true);
  91. }
  92. /*
  93. * Cycle through the processors asking the PROM to start each one.
  94. */
  95. void __init smp4d_boot_cpus(void)
  96. {
  97. smp4d_ipi_init();
  98. if (boot_cpu_id)
  99. current_set[0] = NULL;
  100. local_flush_cache_all();
  101. }
  102. int __cpuinit smp4d_boot_one_cpu(int i)
  103. {
  104. unsigned long *entry = &sun4d_cpu_startup;
  105. struct task_struct *p;
  106. int timeout;
  107. int cpu_node;
  108. cpu_find_by_instance(i, &cpu_node, NULL);
  109. /* Cook up an idler for this guy. */
  110. p = fork_idle(i);
  111. current_set[i] = task_thread_info(p);
  112. /*
  113. * Initialize the contexts table
  114. * Since the call to prom_startcpu() trashes the structure,
  115. * we need to re-initialize it for each cpu
  116. */
  117. smp_penguin_ctable.which_io = 0;
  118. smp_penguin_ctable.phys_addr = (unsigned int) srmmu_ctx_table_phys;
  119. smp_penguin_ctable.reg_size = 0;
  120. /* whirrr, whirrr, whirrrrrrrrr... */
  121. printk(KERN_INFO "Starting CPU %d at %p\n", i, entry);
  122. local_flush_cache_all();
  123. prom_startcpu(cpu_node,
  124. &smp_penguin_ctable, 0, (char *)entry);
  125. printk(KERN_INFO "prom_startcpu returned :)\n");
  126. /* wheee... it's going... */
  127. for (timeout = 0; timeout < 10000; timeout++) {
  128. if (cpu_callin_map[i])
  129. break;
  130. udelay(200);
  131. }
  132. if (!(cpu_callin_map[i])) {
  133. printk(KERN_ERR "Processor %d is stuck.\n", i);
  134. return -ENODEV;
  135. }
  136. local_flush_cache_all();
  137. return 0;
  138. }
  139. void __init smp4d_smp_done(void)
  140. {
  141. int i, first;
  142. int *prev;
  143. /* setup cpu list for irq rotation */
  144. first = 0;
  145. prev = &first;
  146. for_each_online_cpu(i) {
  147. *prev = i;
  148. prev = &cpu_data(i).next;
  149. }
  150. *prev = first;
  151. local_flush_cache_all();
  152. /* Ok, they are spinning and ready to go. */
  153. smp_processors_ready = 1;
  154. sun4d_distribute_irqs();
  155. }
  156. /* Memory structure giving interrupt handler information about IPI generated */
  157. struct sun4d_ipi_work {
  158. int single;
  159. int msk;
  160. int resched;
  161. };
  162. static DEFINE_PER_CPU_SHARED_ALIGNED(struct sun4d_ipi_work, sun4d_ipi_work);
  163. /* Initialize IPIs on the SUN4D SMP machine */
  164. static void __init smp4d_ipi_init(void)
  165. {
  166. int cpu;
  167. struct sun4d_ipi_work *work;
  168. printk(KERN_INFO "smp4d: setup IPI at IRQ %d\n", SUN4D_IPI_IRQ);
  169. for_each_possible_cpu(cpu) {
  170. work = &per_cpu(sun4d_ipi_work, cpu);
  171. work->single = work->msk = work->resched = 0;
  172. }
  173. }
  174. void sun4d_ipi_interrupt(void)
  175. {
  176. struct sun4d_ipi_work *work = &__get_cpu_var(sun4d_ipi_work);
  177. if (work->single) {
  178. work->single = 0;
  179. smp_call_function_single_interrupt();
  180. }
  181. if (work->msk) {
  182. work->msk = 0;
  183. smp_call_function_interrupt();
  184. }
  185. if (work->resched) {
  186. work->resched = 0;
  187. smp_resched_interrupt();
  188. }
  189. }
  190. static void smp4d_ipi_single(int cpu)
  191. {
  192. struct sun4d_ipi_work *work = &per_cpu(sun4d_ipi_work, cpu);
  193. /* Mark work */
  194. work->single = 1;
  195. /* Generate IRQ on the CPU */
  196. sun4d_send_ipi(cpu, SUN4D_IPI_IRQ);
  197. }
  198. static void smp4d_ipi_mask_one(int cpu)
  199. {
  200. struct sun4d_ipi_work *work = &per_cpu(sun4d_ipi_work, cpu);
  201. /* Mark work */
  202. work->msk = 1;
  203. /* Generate IRQ on the CPU */
  204. sun4d_send_ipi(cpu, SUN4D_IPI_IRQ);
  205. }
  206. static void smp4d_ipi_resched(int cpu)
  207. {
  208. struct sun4d_ipi_work *work = &per_cpu(sun4d_ipi_work, cpu);
  209. /* Mark work */
  210. work->resched = 1;
  211. /* Generate IRQ on the CPU (any IRQ will cause resched) */
  212. sun4d_send_ipi(cpu, SUN4D_IPI_IRQ);
  213. }
  214. static struct smp_funcall {
  215. smpfunc_t func;
  216. unsigned long arg1;
  217. unsigned long arg2;
  218. unsigned long arg3;
  219. unsigned long arg4;
  220. unsigned long arg5;
  221. unsigned char processors_in[NR_CPUS]; /* Set when ipi entered. */
  222. unsigned char processors_out[NR_CPUS]; /* Set when ipi exited. */
  223. } ccall_info __attribute__((aligned(8)));
  224. static DEFINE_SPINLOCK(cross_call_lock);
  225. /* Cross calls must be serialized, at least currently. */
  226. static void smp4d_cross_call(smpfunc_t func, cpumask_t mask, unsigned long arg1,
  227. unsigned long arg2, unsigned long arg3,
  228. unsigned long arg4)
  229. {
  230. if (smp_processors_ready) {
  231. register int high = smp_highest_cpu;
  232. unsigned long flags;
  233. spin_lock_irqsave(&cross_call_lock, flags);
  234. {
  235. /*
  236. * If you make changes here, make sure
  237. * gcc generates proper code...
  238. */
  239. register smpfunc_t f asm("i0") = func;
  240. register unsigned long a1 asm("i1") = arg1;
  241. register unsigned long a2 asm("i2") = arg2;
  242. register unsigned long a3 asm("i3") = arg3;
  243. register unsigned long a4 asm("i4") = arg4;
  244. register unsigned long a5 asm("i5") = 0;
  245. __asm__ __volatile__(
  246. "std %0, [%6]\n\t"
  247. "std %2, [%6 + 8]\n\t"
  248. "std %4, [%6 + 16]\n\t" : :
  249. "r"(f), "r"(a1), "r"(a2), "r"(a3), "r"(a4), "r"(a5),
  250. "r" (&ccall_info.func));
  251. }
  252. /* Init receive/complete mapping, plus fire the IPI's off. */
  253. {
  254. register int i;
  255. cpumask_clear_cpu(smp_processor_id(), &mask);
  256. cpumask_and(&mask, cpu_online_mask, &mask);
  257. for (i = 0; i <= high; i++) {
  258. if (cpumask_test_cpu(i, &mask)) {
  259. ccall_info.processors_in[i] = 0;
  260. ccall_info.processors_out[i] = 0;
  261. sun4d_send_ipi(i, IRQ_CROSS_CALL);
  262. }
  263. }
  264. }
  265. {
  266. register int i;
  267. i = 0;
  268. do {
  269. if (!cpumask_test_cpu(i, &mask))
  270. continue;
  271. while (!ccall_info.processors_in[i])
  272. barrier();
  273. } while (++i <= high);
  274. i = 0;
  275. do {
  276. if (!cpumask_test_cpu(i, &mask))
  277. continue;
  278. while (!ccall_info.processors_out[i])
  279. barrier();
  280. } while (++i <= high);
  281. }
  282. spin_unlock_irqrestore(&cross_call_lock, flags);
  283. }
  284. }
  285. /* Running cross calls. */
  286. void smp4d_cross_call_irq(void)
  287. {
  288. int i = hard_smp4d_processor_id();
  289. ccall_info.processors_in[i] = 1;
  290. ccall_info.func(ccall_info.arg1, ccall_info.arg2, ccall_info.arg3,
  291. ccall_info.arg4, ccall_info.arg5);
  292. ccall_info.processors_out[i] = 1;
  293. }
  294. void smp4d_percpu_timer_interrupt(struct pt_regs *regs)
  295. {
  296. struct pt_regs *old_regs;
  297. int cpu = hard_smp4d_processor_id();
  298. struct clock_event_device *ce;
  299. static int cpu_tick[NR_CPUS];
  300. static char led_mask[] = { 0xe, 0xd, 0xb, 0x7, 0xb, 0xd };
  301. old_regs = set_irq_regs(regs);
  302. bw_get_prof_limit(cpu);
  303. bw_clear_intr_mask(0, 1); /* INTR_TABLE[0] & 1 is Profile IRQ */
  304. cpu_tick[cpu]++;
  305. if (!(cpu_tick[cpu] & 15)) {
  306. if (cpu_tick[cpu] == 0x60)
  307. cpu_tick[cpu] = 0;
  308. cpu_leds[cpu] = led_mask[cpu_tick[cpu] >> 4];
  309. show_leds(cpu);
  310. }
  311. ce = &per_cpu(sparc32_clockevent, cpu);
  312. irq_enter();
  313. ce->event_handler(ce);
  314. irq_exit();
  315. set_irq_regs(old_regs);
  316. }
  317. void __init smp4d_blackbox_id(unsigned *addr)
  318. {
  319. int rd = *addr & 0x3e000000;
  320. addr[0] = 0xc0800800 | rd; /* lda [%g0] ASI_M_VIKING_TMP1, reg */
  321. addr[1] = 0x01000000; /* nop */
  322. addr[2] = 0x01000000; /* nop */
  323. }
  324. void __init smp4d_blackbox_current(unsigned *addr)
  325. {
  326. int rd = *addr & 0x3e000000;
  327. addr[0] = 0xc0800800 | rd; /* lda [%g0] ASI_M_VIKING_TMP1, reg */
  328. addr[2] = 0x81282002 | rd | (rd >> 11); /* sll reg, 2, reg */
  329. addr[4] = 0x01000000; /* nop */
  330. }
  331. void __init sun4d_init_smp(void)
  332. {
  333. int i;
  334. /* Patch ipi15 trap table */
  335. t_nmi[1] = t_nmi[1] + (linux_trap_ipi15_sun4d - linux_trap_ipi15_sun4m);
  336. /* And set btfixup... */
  337. BTFIXUPSET_BLACKBOX(hard_smp_processor_id, smp4d_blackbox_id);
  338. BTFIXUPSET_BLACKBOX(load_current, smp4d_blackbox_current);
  339. BTFIXUPSET_CALL(smp_cross_call, smp4d_cross_call, BTFIXUPCALL_NORM);
  340. BTFIXUPSET_CALL(__hard_smp_processor_id, __smp4d_processor_id, BTFIXUPCALL_NORM);
  341. BTFIXUPSET_CALL(smp_ipi_resched, smp4d_ipi_resched, BTFIXUPCALL_NORM);
  342. BTFIXUPSET_CALL(smp_ipi_single, smp4d_ipi_single, BTFIXUPCALL_NORM);
  343. BTFIXUPSET_CALL(smp_ipi_mask_one, smp4d_ipi_mask_one, BTFIXUPCALL_NORM);
  344. for (i = 0; i < NR_CPUS; i++) {
  345. ccall_info.processors_in[i] = 1;
  346. ccall_info.processors_out[i] = 1;
  347. }
  348. }