phy.c 60 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2009-2012 Realtek Corporation.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of version 2 of the GNU General Public License as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc.,
  16. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17. *
  18. * The full GNU General Public License is included in this distribution in the
  19. * file called LICENSE.
  20. *
  21. * Contact Information:
  22. * wlanfae <wlanfae@realtek.com>
  23. * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24. * Hsinchu 300, Taiwan.
  25. *
  26. * Larry Finger <Larry.Finger@lwfinger.net>
  27. *
  28. *****************************************************************************/
  29. #include "../wifi.h"
  30. #include "../pci.h"
  31. #include "../ps.h"
  32. #include "reg.h"
  33. #include "def.h"
  34. #include "phy.h"
  35. #include "rf.h"
  36. #include "dm.h"
  37. #include "table.h"
  38. /* static forward definitions */
  39. static u32 _phy_fw_rf_serial_read(struct ieee80211_hw *hw,
  40. enum radio_path rfpath, u32 offset);
  41. static void _phy_fw_rf_serial_write(struct ieee80211_hw *hw,
  42. enum radio_path rfpath,
  43. u32 offset, u32 data);
  44. static u32 _phy_rf_serial_read(struct ieee80211_hw *hw,
  45. enum radio_path rfpath, u32 offset);
  46. static void _phy_rf_serial_write(struct ieee80211_hw *hw,
  47. enum radio_path rfpath, u32 offset, u32 data);
  48. static u32 _phy_calculate_bit_shift(u32 bitmask);
  49. static bool _phy_bb8192c_config_parafile(struct ieee80211_hw *hw);
  50. static bool _phy_cfg_mac_w_header(struct ieee80211_hw *hw);
  51. static bool _phy_cfg_bb_w_header(struct ieee80211_hw *hw, u8 configtype);
  52. static bool _phy_cfg_bb_w_pgheader(struct ieee80211_hw *hw, u8 configtype);
  53. static void _phy_init_bb_rf_reg_def(struct ieee80211_hw *hw);
  54. static bool _phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable,
  55. u32 cmdtableidx, u32 cmdtablesz,
  56. enum swchnlcmd_id cmdid,
  57. u32 para1, u32 para2,
  58. u32 msdelay);
  59. static bool _phy_sw_chnl_step_by_step(struct ieee80211_hw *hw, u8 channel,
  60. u8 *stage, u8 *step, u32 *delay);
  61. static u8 _phy_dbm_to_txpwr_Idx(struct ieee80211_hw *hw,
  62. enum wireless_mode wirelessmode,
  63. long power_indbm);
  64. static long _phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw,
  65. enum wireless_mode wirelessmode, u8 txpwridx);
  66. static void rtl8723ae_phy_set_io(struct ieee80211_hw *hw);
  67. u32 rtl8723ae_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr,
  68. u32 bitmask)
  69. {
  70. struct rtl_priv *rtlpriv = rtl_priv(hw);
  71. u32 returnvalue, originalvalue, bitshift;
  72. RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
  73. "regaddr(%#x), bitmask(%#x)\n", regaddr, bitmask);
  74. originalvalue = rtl_read_dword(rtlpriv, regaddr);
  75. bitshift = _phy_calculate_bit_shift(bitmask);
  76. returnvalue = (originalvalue & bitmask) >> bitshift;
  77. RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
  78. "BBR MASK=0x%x Addr[0x%x]=0x%x\n", bitmask, regaddr,
  79. originalvalue);
  80. return returnvalue;
  81. }
  82. void rtl8723ae_phy_set_bb_reg(struct ieee80211_hw *hw,
  83. u32 regaddr, u32 bitmask, u32 data)
  84. {
  85. struct rtl_priv *rtlpriv = rtl_priv(hw);
  86. u32 originalvalue, bitshift;
  87. RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
  88. "regaddr(%#x), bitmask(%#x), data(%#x)\n", regaddr,
  89. bitmask, data);
  90. if (bitmask != MASKDWORD) {
  91. originalvalue = rtl_read_dword(rtlpriv, regaddr);
  92. bitshift = _phy_calculate_bit_shift(bitmask);
  93. data = ((originalvalue & (~bitmask)) | (data << bitshift));
  94. }
  95. rtl_write_dword(rtlpriv, regaddr, data);
  96. RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
  97. "regaddr(%#x), bitmask(%#x), data(%#x)\n",
  98. regaddr, bitmask, data);
  99. }
  100. u32 rtl8723ae_phy_query_rf_reg(struct ieee80211_hw *hw,
  101. enum radio_path rfpath, u32 regaddr, u32 bitmask)
  102. {
  103. struct rtl_priv *rtlpriv = rtl_priv(hw);
  104. u32 original_value, readback_value, bitshift;
  105. struct rtl_phy *rtlphy = &(rtlpriv->phy);
  106. unsigned long flags;
  107. RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
  108. "regaddr(%#x), rfpath(%#x), bitmask(%#x)\n",
  109. regaddr, rfpath, bitmask);
  110. spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags);
  111. if (rtlphy->rf_mode != RF_OP_BY_FW)
  112. original_value = _phy_rf_serial_read(hw, rfpath, regaddr);
  113. else
  114. original_value = _phy_fw_rf_serial_read(hw, rfpath, regaddr);
  115. bitshift = _phy_calculate_bit_shift(bitmask);
  116. readback_value = (original_value & bitmask) >> bitshift;
  117. spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags);
  118. RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
  119. "regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n",
  120. regaddr, rfpath, bitmask, original_value);
  121. return readback_value;
  122. }
  123. void rtl8723ae_phy_set_rf_reg(struct ieee80211_hw *hw,
  124. enum radio_path rfpath,
  125. u32 regaddr, u32 bitmask, u32 data)
  126. {
  127. struct rtl_priv *rtlpriv = rtl_priv(hw);
  128. struct rtl_phy *rtlphy = &(rtlpriv->phy);
  129. u32 original_value, bitshift;
  130. unsigned long flags;
  131. RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
  132. "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
  133. regaddr, bitmask, data, rfpath);
  134. spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags);
  135. if (rtlphy->rf_mode != RF_OP_BY_FW) {
  136. if (bitmask != RFREG_OFFSET_MASK) {
  137. original_value = _phy_rf_serial_read(hw, rfpath,
  138. regaddr);
  139. bitshift = _phy_calculate_bit_shift(bitmask);
  140. data = ((original_value & (~bitmask)) |
  141. (data << bitshift));
  142. }
  143. _phy_rf_serial_write(hw, rfpath, regaddr, data);
  144. } else {
  145. if (bitmask != RFREG_OFFSET_MASK) {
  146. original_value = _phy_fw_rf_serial_read(hw, rfpath,
  147. regaddr);
  148. bitshift = _phy_calculate_bit_shift(bitmask);
  149. data = ((original_value & (~bitmask)) |
  150. (data << bitshift));
  151. }
  152. _phy_fw_rf_serial_write(hw, rfpath, regaddr, data);
  153. }
  154. spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags);
  155. RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
  156. "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
  157. regaddr, bitmask, data, rfpath);
  158. }
  159. static u32 _phy_fw_rf_serial_read(struct ieee80211_hw *hw,
  160. enum radio_path rfpath, u32 offset)
  161. {
  162. RT_ASSERT(false, "deprecated!\n");
  163. return 0;
  164. }
  165. static void _phy_fw_rf_serial_write(struct ieee80211_hw *hw,
  166. enum radio_path rfpath,
  167. u32 offset, u32 data)
  168. {
  169. RT_ASSERT(false, "deprecated!\n");
  170. }
  171. static u32 _phy_rf_serial_read(struct ieee80211_hw *hw,
  172. enum radio_path rfpath, u32 offset)
  173. {
  174. struct rtl_priv *rtlpriv = rtl_priv(hw);
  175. struct rtl_phy *rtlphy = &(rtlpriv->phy);
  176. struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
  177. u32 newoffset;
  178. u32 tmplong, tmplong2;
  179. u8 rfpi_enable = 0;
  180. u32 retvalue;
  181. offset &= 0x3f;
  182. newoffset = offset;
  183. if (RT_CANNOT_IO(hw)) {
  184. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "return all one\n");
  185. return 0xFFFFFFFF;
  186. }
  187. tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD);
  188. if (rfpath == RF90_PATH_A)
  189. tmplong2 = tmplong;
  190. else
  191. tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD);
  192. tmplong2 = (tmplong2 & (~BLSSIREADADDRESS)) |
  193. (newoffset << 23) | BLSSIREADEDGE;
  194. rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
  195. tmplong & (~BLSSIREADEDGE));
  196. mdelay(1);
  197. rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2);
  198. mdelay(1);
  199. rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
  200. tmplong | BLSSIREADEDGE);
  201. mdelay(1);
  202. if (rfpath == RF90_PATH_A)
  203. rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1,
  204. BIT(8));
  205. else if (rfpath == RF90_PATH_B)
  206. rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1,
  207. BIT(8));
  208. if (rfpi_enable)
  209. retvalue = rtl_get_bbreg(hw, pphyreg->rf_rbpi,
  210. BLSSIREADBACKDATA);
  211. else
  212. retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb,
  213. BLSSIREADBACKDATA);
  214. RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "RFR-%d Addr[0x%x]=0x%x\n",
  215. rfpath, pphyreg->rf_rb, retvalue);
  216. return retvalue;
  217. }
  218. static void _phy_rf_serial_write(struct ieee80211_hw *hw,
  219. enum radio_path rfpath, u32 offset, u32 data)
  220. {
  221. u32 data_and_addr;
  222. u32 newoffset;
  223. struct rtl_priv *rtlpriv = rtl_priv(hw);
  224. struct rtl_phy *rtlphy = &(rtlpriv->phy);
  225. struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
  226. if (RT_CANNOT_IO(hw)) {
  227. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "stop\n");
  228. return;
  229. }
  230. offset &= 0x3f;
  231. newoffset = offset;
  232. data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff;
  233. rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr);
  234. RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "RFW-%d Addr[0x%x]=0x%x\n",
  235. rfpath, pphyreg->rf3wire_offset, data_and_addr);
  236. }
  237. static u32 _phy_calculate_bit_shift(u32 bitmask)
  238. {
  239. u32 i;
  240. for (i = 0; i <= 31; i++) {
  241. if (((bitmask >> i) & 0x1) == 1)
  242. break;
  243. }
  244. return i;
  245. }
  246. static void _rtl8723ae_phy_bb_config_1t(struct ieee80211_hw *hw)
  247. {
  248. rtl_set_bbreg(hw, RFPGA0_TXINFO, 0x3, 0x2);
  249. rtl_set_bbreg(hw, RFPGA1_TXINFO, 0x300033, 0x200022);
  250. rtl_set_bbreg(hw, RCCK0_AFESETTING, MASKBYTE3, 0x45);
  251. rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x23);
  252. rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, 0x30, 0x1);
  253. rtl_set_bbreg(hw, 0xe74, 0x0c000000, 0x2);
  254. rtl_set_bbreg(hw, 0xe78, 0x0c000000, 0x2);
  255. rtl_set_bbreg(hw, 0xe7c, 0x0c000000, 0x2);
  256. rtl_set_bbreg(hw, 0xe80, 0x0c000000, 0x2);
  257. rtl_set_bbreg(hw, 0xe88, 0x0c000000, 0x2);
  258. }
  259. bool rtl8723ae_phy_mac_config(struct ieee80211_hw *hw)
  260. {
  261. struct rtl_priv *rtlpriv = rtl_priv(hw);
  262. bool rtstatus = _phy_cfg_mac_w_header(hw);
  263. rtl_write_byte(rtlpriv, 0x04CA, 0x0A);
  264. return rtstatus;
  265. }
  266. bool rtl8723ae_phy_bb_config(struct ieee80211_hw *hw)
  267. {
  268. bool rtstatus = true;
  269. struct rtl_priv *rtlpriv = rtl_priv(hw);
  270. u8 tmpu1b;
  271. u8 reg_hwparafile = 1;
  272. _phy_init_bb_rf_reg_def(hw);
  273. /* 1. 0x28[1] = 1 */
  274. tmpu1b = rtl_read_byte(rtlpriv, REG_AFE_PLL_CTRL);
  275. udelay(2);
  276. rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, (tmpu1b|BIT(1)));
  277. udelay(2);
  278. /* 2. 0x29[7:0] = 0xFF */
  279. rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL+1, 0xff);
  280. udelay(2);
  281. /* 3. 0x02[1:0] = 2b'11 */
  282. tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN);
  283. rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, (tmpu1b |
  284. FEN_BB_GLB_RSTn | FEN_BBRSTB));
  285. /* 4. 0x25[6] = 0 */
  286. tmpu1b = rtl_read_byte(rtlpriv, REG_AFE_XTAL_CTRL+1);
  287. rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL+1, (tmpu1b&(~BIT(6))));
  288. /* 5. 0x24[20] = 0 Advised by SD3 Alex Wang. 2011.02.09. */
  289. tmpu1b = rtl_read_byte(rtlpriv, REG_AFE_XTAL_CTRL+2);
  290. rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL+2, (tmpu1b&(~BIT(4))));
  291. /* 6. 0x1f[7:0] = 0x07 */
  292. rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x07);
  293. if (reg_hwparafile == 1)
  294. rtstatus = _phy_bb8192c_config_parafile(hw);
  295. return rtstatus;
  296. }
  297. bool rtl8723ae_phy_rf_config(struct ieee80211_hw *hw)
  298. {
  299. return rtl8723ae_phy_rf6052_config(hw);
  300. }
  301. static bool _phy_bb8192c_config_parafile(struct ieee80211_hw *hw)
  302. {
  303. struct rtl_priv *rtlpriv = rtl_priv(hw);
  304. struct rtl_phy *rtlphy = &(rtlpriv->phy);
  305. struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
  306. bool rtstatus;
  307. RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "==>\n");
  308. rtstatus = _phy_cfg_bb_w_header(hw, BASEBAND_CONFIG_PHY_REG);
  309. if (rtstatus != true) {
  310. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Write BB Reg Fail!!");
  311. return false;
  312. }
  313. if (rtlphy->rf_type == RF_1T2R) {
  314. _rtl8723ae_phy_bb_config_1t(hw);
  315. RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Config to 1T!!\n");
  316. }
  317. if (rtlefuse->autoload_failflag == false) {
  318. rtlphy->pwrgroup_cnt = 0;
  319. rtstatus = _phy_cfg_bb_w_pgheader(hw, BASEBAND_CONFIG_PHY_REG);
  320. }
  321. if (rtstatus != true) {
  322. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "BB_PG Reg Fail!!");
  323. return false;
  324. }
  325. rtstatus = _phy_cfg_bb_w_header(hw, BASEBAND_CONFIG_AGC_TAB);
  326. if (rtstatus != true) {
  327. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "AGC Table Fail\n");
  328. return false;
  329. }
  330. rtlphy->cck_high_power = (bool) (rtl_get_bbreg(hw,
  331. RFPGA0_XA_HSSIPARAMETER2, 0x200));
  332. return true;
  333. }
  334. static bool _phy_cfg_mac_w_header(struct ieee80211_hw *hw)
  335. {
  336. struct rtl_priv *rtlpriv = rtl_priv(hw);
  337. u32 i;
  338. u32 arraylength;
  339. u32 *ptrarray;
  340. RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Read Rtl723MACPHY_Array\n");
  341. arraylength = RTL8723E_MACARRAYLENGTH;
  342. ptrarray = RTL8723EMAC_ARRAY;
  343. RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
  344. "Img:RTL8192CEMAC_2T_ARRAY\n");
  345. for (i = 0; i < arraylength; i = i + 2)
  346. rtl_write_byte(rtlpriv, ptrarray[i], (u8) ptrarray[i + 1]);
  347. return true;
  348. }
  349. static bool _phy_cfg_bb_w_header(struct ieee80211_hw *hw, u8 configtype)
  350. {
  351. int i;
  352. u32 *phy_regarray_table;
  353. u32 *agctab_array_table;
  354. u16 phy_reg_arraylen, agctab_arraylen;
  355. struct rtl_priv *rtlpriv = rtl_priv(hw);
  356. agctab_arraylen = RTL8723E_AGCTAB_1TARRAYLENGTH;
  357. agctab_array_table = RTL8723EAGCTAB_1TARRAY;
  358. phy_reg_arraylen = RTL8723E_PHY_REG_1TARRAY_LENGTH;
  359. phy_regarray_table = RTL8723EPHY_REG_1TARRAY;
  360. if (configtype == BASEBAND_CONFIG_PHY_REG) {
  361. for (i = 0; i < phy_reg_arraylen; i = i + 2) {
  362. if (phy_regarray_table[i] == 0xfe)
  363. mdelay(50);
  364. else if (phy_regarray_table[i] == 0xfd)
  365. mdelay(5);
  366. else if (phy_regarray_table[i] == 0xfc)
  367. mdelay(1);
  368. else if (phy_regarray_table[i] == 0xfb)
  369. udelay(50);
  370. else if (phy_regarray_table[i] == 0xfa)
  371. udelay(5);
  372. else if (phy_regarray_table[i] == 0xf9)
  373. udelay(1);
  374. rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD,
  375. phy_regarray_table[i + 1]);
  376. udelay(1);
  377. RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
  378. "The phy_regarray_table[0] is %x"
  379. " Rtl819XPHY_REGArray[1] is %x\n",
  380. phy_regarray_table[i],
  381. phy_regarray_table[i + 1]);
  382. }
  383. } else if (configtype == BASEBAND_CONFIG_AGC_TAB) {
  384. for (i = 0; i < agctab_arraylen; i = i + 2) {
  385. rtl_set_bbreg(hw, agctab_array_table[i], MASKDWORD,
  386. agctab_array_table[i + 1]);
  387. udelay(1);
  388. RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
  389. "The agctab_array_table[0] is "
  390. "%x Rtl819XPHY_REGArray[1] is %x\n",
  391. agctab_array_table[i],
  392. agctab_array_table[i + 1]);
  393. }
  394. }
  395. return true;
  396. }
  397. static void _st_pwrIdx_dfrate_off(struct ieee80211_hw *hw, u32 regaddr,
  398. u32 bitmask, u32 data)
  399. {
  400. struct rtl_priv *rtlpriv = rtl_priv(hw);
  401. struct rtl_phy *rtlphy = &(rtlpriv->phy);
  402. switch (regaddr) {
  403. case RTXAGC_A_RATE18_06:
  404. rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][0] = data;
  405. RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
  406. "MCSTxPowerLevelOriginalOffset[%d][0] = 0x%x\n",
  407. rtlphy->pwrgroup_cnt,
  408. rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][0]);
  409. break;
  410. case RTXAGC_A_RATE54_24:
  411. rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][1] = data;
  412. RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
  413. "MCSTxPowerLevelOriginalOffset[%d][1] = 0x%x\n",
  414. rtlphy->pwrgroup_cnt,
  415. rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][1]);
  416. break;
  417. case RTXAGC_A_CCK1_MCS32:
  418. rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][6] = data;
  419. RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
  420. "MCSTxPowerLevelOriginalOffset[%d][6] = 0x%x\n",
  421. rtlphy->pwrgroup_cnt,
  422. rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][6]);
  423. break;
  424. case RTXAGC_B_CCK11_A_CCK2_11:
  425. if (bitmask == 0xffffff00) {
  426. rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][7] = data;
  427. RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
  428. "MCSTxPowerLevelOriginalOffset[%d][7] = 0x%x\n",
  429. rtlphy->pwrgroup_cnt,
  430. rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][7]);
  431. }
  432. if (bitmask == 0x000000ff) {
  433. rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][15] = data;
  434. RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
  435. "MCSTxPowerLevelOriginalOffset[%d][15] = 0x%x\n",
  436. rtlphy->pwrgroup_cnt,
  437. rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][15]);
  438. }
  439. break;
  440. case RTXAGC_A_MCS03_MCS00:
  441. rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][2] = data;
  442. RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
  443. "MCSTxPowerLevelOriginalOffset[%d][2] = 0x%x\n",
  444. rtlphy->pwrgroup_cnt,
  445. rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][2]);
  446. break;
  447. case RTXAGC_A_MCS07_MCS04:
  448. rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][3] = data;
  449. RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
  450. "MCSTxPowerLevelOriginalOffset[%d][3] = 0x%x\n",
  451. rtlphy->pwrgroup_cnt,
  452. rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][3]);
  453. break;
  454. case RTXAGC_A_MCS11_MCS08:
  455. rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][4] = data;
  456. RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
  457. "MCSTxPowerLevelOriginalOffset[%d][4] = 0x%x\n",
  458. rtlphy->pwrgroup_cnt,
  459. rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][4]);
  460. break;
  461. case RTXAGC_A_MCS15_MCS12:
  462. rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][5] = data;
  463. RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
  464. "MCSTxPowerLevelOriginalOffset[%d][5] = 0x%x\n",
  465. rtlphy->pwrgroup_cnt,
  466. rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][5]);
  467. break;
  468. case RTXAGC_B_RATE18_06:
  469. rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][8] = data;
  470. RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
  471. "MCSTxPowerLevelOriginalOffset[%d][8] = 0x%x\n",
  472. rtlphy->pwrgroup_cnt,
  473. rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][8]);
  474. break;
  475. case RTXAGC_B_RATE54_24:
  476. rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][9] = data;
  477. RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
  478. "MCSTxPowerLevelOriginalOffset[%d][9] = 0x%x\n",
  479. rtlphy->pwrgroup_cnt,
  480. rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][9]);
  481. break;
  482. case RTXAGC_B_CCK1_55_MCS32:
  483. rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][14] = data;
  484. RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
  485. "MCSTxPowerLevelOriginalOffset[%d][14] = 0x%x\n",
  486. rtlphy->pwrgroup_cnt,
  487. rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][14]);
  488. break;
  489. case RTXAGC_B_MCS03_MCS00:
  490. rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][10] = data;
  491. RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
  492. "MCSTxPowerLevelOriginalOffset[%d][10] = 0x%x\n",
  493. rtlphy->pwrgroup_cnt,
  494. rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][10]);
  495. break;
  496. case RTXAGC_B_MCS07_MCS04:
  497. rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][11] = data;
  498. RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
  499. "MCSTxPowerLevelOriginalOffset[%d][11] = 0x%x\n",
  500. rtlphy->pwrgroup_cnt,
  501. rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][11]);
  502. break;
  503. case RTXAGC_B_MCS11_MCS08:
  504. rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][12] = data;
  505. RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
  506. "MCSTxPowerLevelOriginalOffset[%d][12] = 0x%x\n",
  507. rtlphy->pwrgroup_cnt,
  508. rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][12]);
  509. break;
  510. case RTXAGC_B_MCS15_MCS12:
  511. rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][13] = data;
  512. RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
  513. "MCSTxPowerLevelOriginalOffset[%d][13] = 0x%x\n",
  514. rtlphy->pwrgroup_cnt,
  515. rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][13]);
  516. rtlphy->pwrgroup_cnt++;
  517. break;
  518. }
  519. }
  520. static bool _phy_cfg_bb_w_pgheader(struct ieee80211_hw *hw, u8 configtype)
  521. {
  522. struct rtl_priv *rtlpriv = rtl_priv(hw);
  523. int i;
  524. u32 *phy_regarray_table_pg;
  525. u16 phy_regarray_pg_len;
  526. phy_regarray_pg_len = RTL8723E_PHY_REG_ARRAY_PGLENGTH;
  527. phy_regarray_table_pg = RTL8723EPHY_REG_ARRAY_PG;
  528. if (configtype == BASEBAND_CONFIG_PHY_REG) {
  529. for (i = 0; i < phy_regarray_pg_len; i = i + 3) {
  530. if (phy_regarray_table_pg[i] == 0xfe)
  531. mdelay(50);
  532. else if (phy_regarray_table_pg[i] == 0xfd)
  533. mdelay(5);
  534. else if (phy_regarray_table_pg[i] == 0xfc)
  535. mdelay(1);
  536. else if (phy_regarray_table_pg[i] == 0xfb)
  537. udelay(50);
  538. else if (phy_regarray_table_pg[i] == 0xfa)
  539. udelay(5);
  540. else if (phy_regarray_table_pg[i] == 0xf9)
  541. udelay(1);
  542. _st_pwrIdx_dfrate_off(hw, phy_regarray_table_pg[i],
  543. phy_regarray_table_pg[i + 1],
  544. phy_regarray_table_pg[i + 2]);
  545. }
  546. } else {
  547. RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
  548. "configtype != BaseBand_Config_PHY_REG\n");
  549. }
  550. return true;
  551. }
  552. bool rtl8723ae_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
  553. enum radio_path rfpath)
  554. {
  555. struct rtl_priv *rtlpriv = rtl_priv(hw);
  556. int i;
  557. u32 *radioa_array_table;
  558. u16 radioa_arraylen;
  559. radioa_arraylen = Rtl8723ERADIOA_1TARRAYLENGTH;
  560. radioa_array_table = RTL8723E_RADIOA_1TARRAY;
  561. switch (rfpath) {
  562. case RF90_PATH_A:
  563. for (i = 0; i < radioa_arraylen; i = i + 2) {
  564. if (radioa_array_table[i] == 0xfe)
  565. mdelay(50);
  566. else if (radioa_array_table[i] == 0xfd)
  567. mdelay(5);
  568. else if (radioa_array_table[i] == 0xfc)
  569. mdelay(1);
  570. else if (radioa_array_table[i] == 0xfb)
  571. udelay(50);
  572. else if (radioa_array_table[i] == 0xfa)
  573. udelay(5);
  574. else if (radioa_array_table[i] == 0xf9)
  575. udelay(1);
  576. else {
  577. rtl_set_rfreg(hw, rfpath, radioa_array_table[i],
  578. RFREG_OFFSET_MASK,
  579. radioa_array_table[i + 1]);
  580. udelay(1);
  581. }
  582. }
  583. break;
  584. case RF90_PATH_B:
  585. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  586. "switch case not process\n");
  587. break;
  588. case RF90_PATH_C:
  589. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  590. "switch case not process\n");
  591. break;
  592. case RF90_PATH_D:
  593. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  594. "switch case not process\n");
  595. break;
  596. }
  597. return true;
  598. }
  599. void rtl8723ae_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw)
  600. {
  601. struct rtl_priv *rtlpriv = rtl_priv(hw);
  602. struct rtl_phy *rtlphy = &(rtlpriv->phy);
  603. rtlphy->default_initialgain[0] =
  604. (u8) rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0);
  605. rtlphy->default_initialgain[1] =
  606. (u8) rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0);
  607. rtlphy->default_initialgain[2] =
  608. (u8) rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, MASKBYTE0);
  609. rtlphy->default_initialgain[3] =
  610. (u8) rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0);
  611. RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
  612. "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x\n",
  613. rtlphy->default_initialgain[0],
  614. rtlphy->default_initialgain[1],
  615. rtlphy->default_initialgain[2],
  616. rtlphy->default_initialgain[3]);
  617. rtlphy->framesync = (u8) rtl_get_bbreg(hw,
  618. ROFDM0_RXDETECTOR3, MASKBYTE0);
  619. rtlphy->framesync_c34 = rtl_get_bbreg(hw,
  620. ROFDM0_RXDETECTOR2, MASKDWORD);
  621. RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
  622. "Default framesync (0x%x) = 0x%x\n",
  623. ROFDM0_RXDETECTOR3, rtlphy->framesync);
  624. }
  625. static void _phy_init_bb_rf_reg_def(struct ieee80211_hw *hw)
  626. {
  627. struct rtl_priv *rtlpriv = rtl_priv(hw);
  628. struct rtl_phy *rtlphy = &(rtlpriv->phy);
  629. rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW;
  630. rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW;
  631. rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW;
  632. rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW;
  633. rtlphy->phyreg_def[RF90_PATH_A].rfintfi = RFPGA0_XAB_RFINTERFACERB;
  634. rtlphy->phyreg_def[RF90_PATH_B].rfintfi = RFPGA0_XAB_RFINTERFACERB;
  635. rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB;
  636. rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB;
  637. rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE;
  638. rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE;
  639. rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE;
  640. rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE;
  641. rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset =
  642. RFPGA0_XA_LSSIPARAMETER;
  643. rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset =
  644. RFPGA0_XB_LSSIPARAMETER;
  645. rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = rFPGA0_XAB_RFPARAMETER;
  646. rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = rFPGA0_XAB_RFPARAMETER;
  647. rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = rFPGA0_XCD_RFPARAMETER;
  648. rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = rFPGA0_XCD_RFPARAMETER;
  649. rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE;
  650. rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE;
  651. rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE;
  652. rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE;
  653. rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para1 = RFPGA0_XA_HSSIPARAMETER1;
  654. rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1;
  655. rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2;
  656. rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2;
  657. rtlphy->phyreg_def[RF90_PATH_A].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL;
  658. rtlphy->phyreg_def[RF90_PATH_B].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL;
  659. rtlphy->phyreg_def[RF90_PATH_C].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL;
  660. rtlphy->phyreg_def[RF90_PATH_D].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL;
  661. rtlphy->phyreg_def[RF90_PATH_A].rfagc_control1 = ROFDM0_XAAGCCORE1;
  662. rtlphy->phyreg_def[RF90_PATH_B].rfagc_control1 = ROFDM0_XBAGCCORE1;
  663. rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1;
  664. rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1;
  665. rtlphy->phyreg_def[RF90_PATH_A].rfagc_control2 = ROFDM0_XAAGCCORE2;
  666. rtlphy->phyreg_def[RF90_PATH_B].rfagc_control2 = ROFDM0_XBAGCCORE2;
  667. rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2;
  668. rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2;
  669. rtlphy->phyreg_def[RF90_PATH_A].rfrxiq_imbal = ROFDM0_XARXIQIMBALANCE;
  670. rtlphy->phyreg_def[RF90_PATH_B].rfrxiq_imbal = ROFDM0_XBRXIQIMBALANCE;
  671. rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbal = ROFDM0_XCRXIQIMBANLANCE;
  672. rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbal = ROFDM0_XDRXIQIMBALANCE;
  673. rtlphy->phyreg_def[RF90_PATH_A].rfrx_afe = ROFDM0_XARXAFE;
  674. rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE;
  675. rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE;
  676. rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE;
  677. rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbal = ROFDM0_XATXIQIMBALANCE;
  678. rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbal = ROFDM0_XBTXIQIMBALANCE;
  679. rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbal = ROFDM0_XCTXIQIMBALANCE;
  680. rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbal = ROFDM0_XDTXIQIMBALANCE;
  681. rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATXAFE;
  682. rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTXAFE;
  683. rtlphy->phyreg_def[RF90_PATH_C].rftx_afe = ROFDM0_XCTXAFE;
  684. rtlphy->phyreg_def[RF90_PATH_D].rftx_afe = ROFDM0_XDTXAFE;
  685. rtlphy->phyreg_def[RF90_PATH_A].rf_rb = RFPGA0_XA_LSSIREADBACK;
  686. rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RFPGA0_XB_LSSIREADBACK;
  687. rtlphy->phyreg_def[RF90_PATH_C].rf_rb = RFPGA0_XC_LSSIREADBACK;
  688. rtlphy->phyreg_def[RF90_PATH_D].rf_rb = RFPGA0_XD_LSSIREADBACK;
  689. rtlphy->phyreg_def[RF90_PATH_A].rf_rbpi = TRANSCEIVEA_HSPI_READBACK;
  690. rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = TRANSCEIVEB_HSPI_READBACK;
  691. }
  692. void rtl8723ae_phy_get_txpower_level(struct ieee80211_hw *hw, long *powerlevel)
  693. {
  694. struct rtl_priv *rtlpriv = rtl_priv(hw);
  695. struct rtl_phy *rtlphy = &(rtlpriv->phy);
  696. struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
  697. u8 txpwr_level;
  698. long txpwr_dbm;
  699. txpwr_level = rtlphy->cur_cck_txpwridx;
  700. txpwr_dbm = _phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_B, txpwr_level);
  701. txpwr_level = rtlphy->cur_ofdm24g_txpwridx +
  702. rtlefuse->legacy_ht_txpowerdiff;
  703. if (_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_G, txpwr_level) > txpwr_dbm)
  704. txpwr_dbm = _phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_G,
  705. txpwr_level);
  706. txpwr_level = rtlphy->cur_ofdm24g_txpwridx;
  707. if (_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_N_24G, txpwr_level) >
  708. txpwr_dbm)
  709. txpwr_dbm = _phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_N_24G,
  710. txpwr_level);
  711. *powerlevel = txpwr_dbm;
  712. }
  713. static void _rtl8723ae_get_txpower_index(struct ieee80211_hw *hw, u8 channel,
  714. u8 *cckpowerlevel, u8 *ofdmpowerlevel)
  715. {
  716. struct rtl_priv *rtlpriv = rtl_priv(hw);
  717. struct rtl_phy *rtlphy = &(rtlpriv->phy);
  718. struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
  719. u8 index = (channel - 1);
  720. cckpowerlevel[RF90_PATH_A] =
  721. rtlefuse->txpwrlevel_cck[RF90_PATH_A][index];
  722. cckpowerlevel[RF90_PATH_B] =
  723. rtlefuse->txpwrlevel_cck[RF90_PATH_B][index];
  724. if (get_rf_type(rtlphy) == RF_1T2R || get_rf_type(rtlphy) == RF_1T1R) {
  725. ofdmpowerlevel[RF90_PATH_A] =
  726. rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_A][index];
  727. ofdmpowerlevel[RF90_PATH_B] =
  728. rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_B][index];
  729. } else if (get_rf_type(rtlphy) == RF_2T2R) {
  730. ofdmpowerlevel[RF90_PATH_A] =
  731. rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_A][index];
  732. ofdmpowerlevel[RF90_PATH_B] =
  733. rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_B][index];
  734. }
  735. }
  736. static void _rtl8723ae_ccxpower_index_check(struct ieee80211_hw *hw,
  737. u8 channel, u8 *cckpowerlevel,
  738. u8 *ofdmpowerlevel)
  739. {
  740. struct rtl_priv *rtlpriv = rtl_priv(hw);
  741. struct rtl_phy *rtlphy = &(rtlpriv->phy);
  742. rtlphy->cur_cck_txpwridx = cckpowerlevel[0];
  743. rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0];
  744. }
  745. void rtl8723ae_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel)
  746. {
  747. struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
  748. u8 cckpowerlevel[2], ofdmpowerlevel[2];
  749. if (rtlefuse->txpwr_fromeprom == false)
  750. return;
  751. _rtl8723ae_get_txpower_index(hw, channel, &cckpowerlevel[0],
  752. &ofdmpowerlevel[0]);
  753. _rtl8723ae_ccxpower_index_check(hw, channel, &cckpowerlevel[0],
  754. &ofdmpowerlevel[0]);
  755. rtl8723ae_phy_rf6052_set_cck_txpower(hw, &cckpowerlevel[0]);
  756. rtl8723ae_phy_rf6052_set_ofdm_txpower(hw, &ofdmpowerlevel[0], channel);
  757. }
  758. bool rtl8723ae_phy_update_txpower_dbm(struct ieee80211_hw *hw, long power_indbm)
  759. {
  760. struct rtl_priv *rtlpriv = rtl_priv(hw);
  761. struct rtl_phy *rtlphy = &(rtlpriv->phy);
  762. struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
  763. u8 idx;
  764. u8 rf_path;
  765. u8 ccktxpwridx = _phy_dbm_to_txpwr_Idx(hw, WIRELESS_MODE_B,
  766. power_indbm);
  767. u8 ofdmtxpwridx = _phy_dbm_to_txpwr_Idx(hw, WIRELESS_MODE_N_24G,
  768. power_indbm);
  769. if (ofdmtxpwridx - rtlefuse->legacy_ht_txpowerdiff > 0)
  770. ofdmtxpwridx -= rtlefuse->legacy_ht_txpowerdiff;
  771. else
  772. ofdmtxpwridx = 0;
  773. RT_TRACE(rtlpriv, COMP_TXAGC, DBG_TRACE,
  774. "%lx dBm, ccktxpwridx = %d, ofdmtxpwridx = %d\n",
  775. power_indbm, ccktxpwridx, ofdmtxpwridx);
  776. for (idx = 0; idx < 14; idx++) {
  777. for (rf_path = 0; rf_path < 2; rf_path++) {
  778. rtlefuse->txpwrlevel_cck[rf_path][idx] = ccktxpwridx;
  779. rtlefuse->txpwrlevel_ht40_1s[rf_path][idx] =
  780. ofdmtxpwridx;
  781. rtlefuse->txpwrlevel_ht40_2s[rf_path][idx] =
  782. ofdmtxpwridx;
  783. }
  784. }
  785. rtl8723ae_phy_set_txpower_level(hw, rtlphy->current_channel);
  786. return true;
  787. }
  788. static u8 _phy_dbm_to_txpwr_Idx(struct ieee80211_hw *hw,
  789. enum wireless_mode wirelessmode,
  790. long power_indbm)
  791. {
  792. u8 txpwridx;
  793. long offset;
  794. switch (wirelessmode) {
  795. case WIRELESS_MODE_B:
  796. offset = -7;
  797. break;
  798. case WIRELESS_MODE_G:
  799. case WIRELESS_MODE_N_24G:
  800. offset = -8;
  801. break;
  802. default:
  803. offset = -8;
  804. break;
  805. }
  806. if ((power_indbm - offset) > 0)
  807. txpwridx = (u8) ((power_indbm - offset) * 2);
  808. else
  809. txpwridx = 0;
  810. if (txpwridx > MAX_TXPWR_IDX_NMODE_92S)
  811. txpwridx = MAX_TXPWR_IDX_NMODE_92S;
  812. return txpwridx;
  813. }
  814. static long _phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw,
  815. enum wireless_mode wirelessmode, u8 txpwridx)
  816. {
  817. long offset;
  818. long pwrout_dbm;
  819. switch (wirelessmode) {
  820. case WIRELESS_MODE_B:
  821. offset = -7;
  822. break;
  823. case WIRELESS_MODE_G:
  824. case WIRELESS_MODE_N_24G:
  825. offset = -8;
  826. break;
  827. default:
  828. offset = -8;
  829. break;
  830. }
  831. pwrout_dbm = txpwridx / 2 + offset;
  832. return pwrout_dbm;
  833. }
  834. void rtl8723ae_phy_set_bw_mode_callback(struct ieee80211_hw *hw)
  835. {
  836. struct rtl_priv *rtlpriv = rtl_priv(hw);
  837. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  838. struct rtl_phy *rtlphy = &(rtlpriv->phy);
  839. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  840. u8 reg_bw_opmode;
  841. u8 reg_prsr_rsc;
  842. RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE,
  843. "Switch to %s bandwidth\n",
  844. rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
  845. "20MHz" : "40MHz");
  846. if (is_hal_stop(rtlhal)) {
  847. rtlphy->set_bwmode_inprogress = false;
  848. return;
  849. }
  850. reg_bw_opmode = rtl_read_byte(rtlpriv, REG_BWOPMODE);
  851. reg_prsr_rsc = rtl_read_byte(rtlpriv, REG_RRSR + 2);
  852. switch (rtlphy->current_chan_bw) {
  853. case HT_CHANNEL_WIDTH_20:
  854. reg_bw_opmode |= BW_OPMODE_20MHZ;
  855. rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
  856. break;
  857. case HT_CHANNEL_WIDTH_20_40:
  858. reg_bw_opmode &= ~BW_OPMODE_20MHZ;
  859. rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
  860. reg_prsr_rsc =
  861. (reg_prsr_rsc & 0x90) | (mac->cur_40_prime_sc << 5);
  862. rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_prsr_rsc);
  863. break;
  864. default:
  865. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  866. "unknown bandwidth: %#X\n", rtlphy->current_chan_bw);
  867. break;
  868. }
  869. switch (rtlphy->current_chan_bw) {
  870. case HT_CHANNEL_WIDTH_20:
  871. rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0);
  872. rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0);
  873. rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1);
  874. break;
  875. case HT_CHANNEL_WIDTH_20_40:
  876. rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1);
  877. rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1);
  878. rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCK_SIDEBAND,
  879. (mac->cur_40_prime_sc >> 1));
  880. rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc);
  881. rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 0);
  882. rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)),
  883. (mac->cur_40_prime_sc ==
  884. HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
  885. break;
  886. default:
  887. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  888. "unknown bandwidth: %#X\n", rtlphy->current_chan_bw);
  889. break;
  890. }
  891. rtl8723ae_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
  892. rtlphy->set_bwmode_inprogress = false;
  893. RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n");
  894. }
  895. void rtl8723ae_phy_set_bw_mode(struct ieee80211_hw *hw,
  896. enum nl80211_channel_type ch_type)
  897. {
  898. struct rtl_priv *rtlpriv = rtl_priv(hw);
  899. struct rtl_phy *rtlphy = &(rtlpriv->phy);
  900. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  901. u8 tmp_bw = rtlphy->current_chan_bw;
  902. if (rtlphy->set_bwmode_inprogress)
  903. return;
  904. rtlphy->set_bwmode_inprogress = true;
  905. if ((!is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) {
  906. rtl8723ae_phy_set_bw_mode_callback(hw);
  907. } else {
  908. RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
  909. "FALSE driver sleep or unload\n");
  910. rtlphy->set_bwmode_inprogress = false;
  911. rtlphy->current_chan_bw = tmp_bw;
  912. }
  913. }
  914. void rtl8723ae_phy_sw_chnl_callback(struct ieee80211_hw *hw)
  915. {
  916. struct rtl_priv *rtlpriv = rtl_priv(hw);
  917. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  918. struct rtl_phy *rtlphy = &(rtlpriv->phy);
  919. u32 delay;
  920. RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE,
  921. "switch to channel%d\n", rtlphy->current_channel);
  922. if (is_hal_stop(rtlhal))
  923. return;
  924. do {
  925. if (!rtlphy->sw_chnl_inprogress)
  926. break;
  927. if (!_phy_sw_chnl_step_by_step
  928. (hw, rtlphy->current_channel, &rtlphy->sw_chnl_stage,
  929. &rtlphy->sw_chnl_step, &delay)) {
  930. if (delay > 0)
  931. mdelay(delay);
  932. else
  933. continue;
  934. } else {
  935. rtlphy->sw_chnl_inprogress = false;
  936. }
  937. break;
  938. } while (true);
  939. RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n");
  940. }
  941. u8 rtl8723ae_phy_sw_chnl(struct ieee80211_hw *hw)
  942. {
  943. struct rtl_priv *rtlpriv = rtl_priv(hw);
  944. struct rtl_phy *rtlphy = &(rtlpriv->phy);
  945. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  946. if (rtlphy->sw_chnl_inprogress)
  947. return 0;
  948. if (rtlphy->set_bwmode_inprogress)
  949. return 0;
  950. RT_ASSERT((rtlphy->current_channel <= 14),
  951. "WIRELESS_MODE_G but channel>14");
  952. rtlphy->sw_chnl_inprogress = true;
  953. rtlphy->sw_chnl_stage = 0;
  954. rtlphy->sw_chnl_step = 0;
  955. if (!(is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) {
  956. rtl8723ae_phy_sw_chnl_callback(hw);
  957. RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD,
  958. "sw_chnl_inprogress false schedule workitem\n");
  959. rtlphy->sw_chnl_inprogress = false;
  960. } else {
  961. RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD,
  962. "sw_chnl_inprogress false driver sleep or unload\n");
  963. rtlphy->sw_chnl_inprogress = false;
  964. }
  965. return 1;
  966. }
  967. static void _rtl8723ae_phy_sw_rf_seting(struct ieee80211_hw *hw, u8 channel)
  968. {
  969. struct rtl_priv *rtlpriv = rtl_priv(hw);
  970. struct rtl_phy *rtlphy = &(rtlpriv->phy);
  971. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  972. if (IS_81xxC_VENDOR_UMC_B_CUT(rtlhal->version)) {
  973. if (channel == 6 && rtlphy->current_chan_bw ==
  974. HT_CHANNEL_WIDTH_20)
  975. rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD,
  976. 0x00255);
  977. else{
  978. u32 backupRF0x1A = (u32)rtl_get_rfreg(hw, RF90_PATH_A,
  979. RF_RX_G1, RFREG_OFFSET_MASK);
  980. rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD,
  981. backupRF0x1A);
  982. }
  983. }
  984. }
  985. static bool _phy_sw_chnl_step_by_step(struct ieee80211_hw *hw, u8 channel,
  986. u8 *stage, u8 *step, u32 *delay)
  987. {
  988. struct rtl_priv *rtlpriv = rtl_priv(hw);
  989. struct rtl_phy *rtlphy = &(rtlpriv->phy);
  990. struct swchnlcmd precommoncmd[MAX_PRECMD_CNT];
  991. u32 precommoncmdcnt;
  992. struct swchnlcmd postcommoncmd[MAX_POSTCMD_CNT];
  993. u32 postcommoncmdcnt;
  994. struct swchnlcmd rfdependcmd[MAX_RFDEPENDCMD_CNT];
  995. u32 rfdependcmdcnt;
  996. struct swchnlcmd *currentcmd = NULL;
  997. u8 rfpath;
  998. u8 num_total_rfpath = rtlphy->num_total_rfpath;
  999. precommoncmdcnt = 0;
  1000. _phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
  1001. MAX_PRECMD_CNT, CMDID_SET_TXPOWEROWER_LEVEL,
  1002. 0, 0, 0);
  1003. _phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
  1004. MAX_PRECMD_CNT, CMDID_END, 0, 0, 0);
  1005. postcommoncmdcnt = 0;
  1006. _phy_set_sw_chnl_cmdarray(postcommoncmd, postcommoncmdcnt++,
  1007. MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0);
  1008. rfdependcmdcnt = 0;
  1009. RT_ASSERT((channel >= 1 && channel <= 14),
  1010. "illegal channel for Zebra: %d\n", channel);
  1011. _phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
  1012. MAX_RFDEPENDCMD_CNT, CMDID_RF_WRITEREG,
  1013. RF_CHNLBW, channel, 10);
  1014. _phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
  1015. MAX_RFDEPENDCMD_CNT, CMDID_END, 0, 0, 0);
  1016. do {
  1017. switch (*stage) {
  1018. case 0:
  1019. currentcmd = &precommoncmd[*step];
  1020. break;
  1021. case 1:
  1022. currentcmd = &rfdependcmd[*step];
  1023. break;
  1024. case 2:
  1025. currentcmd = &postcommoncmd[*step];
  1026. break;
  1027. }
  1028. if (currentcmd->cmdid == CMDID_END) {
  1029. if ((*stage) == 2) {
  1030. return true;
  1031. } else {
  1032. (*stage)++;
  1033. (*step) = 0;
  1034. continue;
  1035. }
  1036. }
  1037. switch (currentcmd->cmdid) {
  1038. case CMDID_SET_TXPOWEROWER_LEVEL:
  1039. rtl8723ae_phy_set_txpower_level(hw, channel);
  1040. break;
  1041. case CMDID_WRITEPORT_ULONG:
  1042. rtl_write_dword(rtlpriv, currentcmd->para1,
  1043. currentcmd->para2);
  1044. break;
  1045. case CMDID_WRITEPORT_USHORT:
  1046. rtl_write_word(rtlpriv, currentcmd->para1,
  1047. (u16) currentcmd->para2);
  1048. break;
  1049. case CMDID_WRITEPORT_UCHAR:
  1050. rtl_write_byte(rtlpriv, currentcmd->para1,
  1051. (u8) currentcmd->para2);
  1052. break;
  1053. case CMDID_RF_WRITEREG:
  1054. for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) {
  1055. rtlphy->rfreg_chnlval[rfpath] =
  1056. ((rtlphy->rfreg_chnlval[rfpath] &
  1057. 0xfffffc00) | currentcmd->para2);
  1058. rtl_set_rfreg(hw, (enum radio_path)rfpath,
  1059. currentcmd->para1,
  1060. RFREG_OFFSET_MASK,
  1061. rtlphy->rfreg_chnlval[rfpath]);
  1062. }
  1063. _rtl8723ae_phy_sw_rf_seting(hw, channel);
  1064. break;
  1065. default:
  1066. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  1067. "switch case not process\n");
  1068. break;
  1069. }
  1070. break;
  1071. } while (true);
  1072. (*delay) = currentcmd->msdelay;
  1073. (*step)++;
  1074. return false;
  1075. }
  1076. static bool _phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable,
  1077. u32 cmdtableidx, u32 cmdtablesz,
  1078. enum swchnlcmd_id cmdid, u32 para1,
  1079. u32 para2, u32 msdelay)
  1080. {
  1081. struct swchnlcmd *pcmd;
  1082. if (cmdtable == NULL) {
  1083. RT_ASSERT(false, "cmdtable cannot be NULL.\n");
  1084. return false;
  1085. }
  1086. if (cmdtableidx >= cmdtablesz)
  1087. return false;
  1088. pcmd = cmdtable + cmdtableidx;
  1089. pcmd->cmdid = cmdid;
  1090. pcmd->para1 = para1;
  1091. pcmd->para2 = para2;
  1092. pcmd->msdelay = msdelay;
  1093. return true;
  1094. }
  1095. static u8 _rtl8723ae_phy_path_a_iqk(struct ieee80211_hw *hw, bool config_pathb)
  1096. {
  1097. u32 reg_eac, reg_e94, reg_e9c, reg_ea4;
  1098. u8 result = 0x00;
  1099. rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c1f);
  1100. rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c1f);
  1101. rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140102);
  1102. rtl_set_bbreg(hw, 0xe3c, MASKDWORD,
  1103. config_pathb ? 0x28160202 : 0x28160502);
  1104. if (config_pathb) {
  1105. rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x10008c22);
  1106. rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x10008c22);
  1107. rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140102);
  1108. rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x28160202);
  1109. }
  1110. rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x001028d1);
  1111. rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000);
  1112. rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000);
  1113. mdelay(IQK_DELAY_TIME);
  1114. reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
  1115. reg_e94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD);
  1116. reg_e9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD);
  1117. reg_ea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD);
  1118. if (!(reg_eac & BIT(28)) &&
  1119. (((reg_e94 & 0x03FF0000) >> 16) != 0x142) &&
  1120. (((reg_e9c & 0x03FF0000) >> 16) != 0x42))
  1121. result |= 0x01;
  1122. else
  1123. return result;
  1124. if (!(reg_eac & BIT(27)) &&
  1125. (((reg_ea4 & 0x03FF0000) >> 16) != 0x132) &&
  1126. (((reg_eac & 0x03FF0000) >> 16) != 0x36))
  1127. result |= 0x02;
  1128. return result;
  1129. }
  1130. static u8 _rtl8723ae_phy_path_b_iqk(struct ieee80211_hw *hw)
  1131. {
  1132. u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc;
  1133. u8 result = 0x00;
  1134. rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000002);
  1135. rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000000);
  1136. mdelay(IQK_DELAY_TIME);
  1137. reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
  1138. reg_eb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD);
  1139. reg_ebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD);
  1140. reg_ec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD);
  1141. reg_ecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD);
  1142. if (!(reg_eac & BIT(31)) &&
  1143. (((reg_eb4 & 0x03FF0000) >> 16) != 0x142) &&
  1144. (((reg_ebc & 0x03FF0000) >> 16) != 0x42))
  1145. result |= 0x01;
  1146. else
  1147. return result;
  1148. if (!(reg_eac & BIT(30)) &&
  1149. (((reg_ec4 & 0x03FF0000) >> 16) != 0x132) &&
  1150. (((reg_ecc & 0x03FF0000) >> 16) != 0x36))
  1151. result |= 0x02;
  1152. return result;
  1153. }
  1154. static void phy_path_a_fill_iqk_matrix(struct ieee80211_hw *hw, bool iqk_ok,
  1155. long result[][8], u8 final_candidate,
  1156. bool btxonly)
  1157. {
  1158. u32 oldval_0, x, tx0_a, reg;
  1159. long y, tx0_c;
  1160. if (final_candidate == 0xFF) {
  1161. return;
  1162. } else if (iqk_ok) {
  1163. oldval_0 = (rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
  1164. MASKDWORD) >> 22) & 0x3FF;
  1165. x = result[final_candidate][0];
  1166. if ((x & 0x00000200) != 0)
  1167. x = x | 0xFFFFFC00;
  1168. tx0_a = (x * oldval_0) >> 8;
  1169. rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x3FF, tx0_a);
  1170. rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(31),
  1171. ((x * oldval_0 >> 7) & 0x1));
  1172. y = result[final_candidate][1];
  1173. if ((y & 0x00000200) != 0)
  1174. y = y | 0xFFFFFC00;
  1175. tx0_c = (y * oldval_0) >> 8;
  1176. rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000,
  1177. ((tx0_c & 0x3C0) >> 6));
  1178. rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x003F0000,
  1179. (tx0_c & 0x3F));
  1180. rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(29),
  1181. ((y * oldval_0 >> 7) & 0x1));
  1182. if (btxonly)
  1183. return;
  1184. reg = result[final_candidate][2];
  1185. rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg);
  1186. reg = result[final_candidate][3] & 0x3F;
  1187. rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg);
  1188. reg = (result[final_candidate][3] >> 6) & 0xF;
  1189. rtl_set_bbreg(hw, 0xca0, 0xF0000000, reg);
  1190. }
  1191. }
  1192. static void phy_save_adda_regs(struct ieee80211_hw *hw,
  1193. u32 *addareg, u32 *addabackup,
  1194. u32 registernum)
  1195. {
  1196. u32 i;
  1197. for (i = 0; i < registernum; i++)
  1198. addabackup[i] = rtl_get_bbreg(hw, addareg[i], MASKDWORD);
  1199. }
  1200. static void phy_save_mac_regs(struct ieee80211_hw *hw, u32 *macreg,
  1201. u32 *macbackup)
  1202. {
  1203. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1204. u32 i;
  1205. for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
  1206. macbackup[i] = rtl_read_byte(rtlpriv, macreg[i]);
  1207. macbackup[i] = rtl_read_dword(rtlpriv, macreg[i]);
  1208. }
  1209. static void phy_reload_adda_regs(struct ieee80211_hw *hw, u32 *addareg,
  1210. u32 *addabackup, u32 regiesternum)
  1211. {
  1212. u32 i;
  1213. for (i = 0; i < regiesternum; i++)
  1214. rtl_set_bbreg(hw, addareg[i], MASKDWORD, addabackup[i]);
  1215. }
  1216. static void phy_reload_mac_regs(struct ieee80211_hw *hw, u32 *macreg,
  1217. u32 *macbackup)
  1218. {
  1219. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1220. u32 i;
  1221. for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
  1222. rtl_write_byte(rtlpriv, macreg[i], (u8) macbackup[i]);
  1223. rtl_write_dword(rtlpriv, macreg[i], macbackup[i]);
  1224. }
  1225. static void _rtl8723ae_phy_path_adda_on(struct ieee80211_hw *hw,
  1226. u32 *addareg, bool is_patha_on,
  1227. bool is2t)
  1228. {
  1229. u32 pathOn;
  1230. u32 i;
  1231. pathOn = is_patha_on ? 0x04db25a4 : 0x0b1b25a4;
  1232. if (false == is2t) {
  1233. pathOn = 0x0bdb25a0;
  1234. rtl_set_bbreg(hw, addareg[0], MASKDWORD, 0x0b1b25a0);
  1235. } else {
  1236. rtl_set_bbreg(hw, addareg[0], MASKDWORD, pathOn);
  1237. }
  1238. for (i = 1; i < IQK_ADDA_REG_NUM; i++)
  1239. rtl_set_bbreg(hw, addareg[i], MASKDWORD, pathOn);
  1240. }
  1241. static void _rtl8723ae_phy_mac_setting_calibration(struct ieee80211_hw *hw,
  1242. u32 *macreg, u32 *macbackup)
  1243. {
  1244. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1245. u32 i = 0;
  1246. rtl_write_byte(rtlpriv, macreg[i], 0x3F);
  1247. for (i = 1; i < (IQK_MAC_REG_NUM - 1); i++)
  1248. rtl_write_byte(rtlpriv, macreg[i],
  1249. (u8) (macbackup[i] & (~BIT(3))));
  1250. rtl_write_byte(rtlpriv, macreg[i], (u8) (macbackup[i] & (~BIT(5))));
  1251. }
  1252. static void _rtl8723ae_phy_path_a_standby(struct ieee80211_hw *hw)
  1253. {
  1254. rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0);
  1255. rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000);
  1256. rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
  1257. }
  1258. static void _rtl8723ae_phy_pi_mode_switch(struct ieee80211_hw *hw, bool pi_mode)
  1259. {
  1260. u32 mode;
  1261. mode = pi_mode ? 0x01000100 : 0x01000000;
  1262. rtl_set_bbreg(hw, 0x820, MASKDWORD, mode);
  1263. rtl_set_bbreg(hw, 0x828, MASKDWORD, mode);
  1264. }
  1265. static bool phy_simularity_comp(struct ieee80211_hw *hw, long result[][8],
  1266. u8 c1, u8 c2)
  1267. {
  1268. u32 i, j, diff, simularity_bitmap, bound;
  1269. u8 final_candidate[2] = { 0xFF, 0xFF };
  1270. bool bresult = true;
  1271. bound = 4;
  1272. simularity_bitmap = 0;
  1273. for (i = 0; i < bound; i++) {
  1274. diff = (result[c1][i] > result[c2][i]) ?
  1275. (result[c1][i] - result[c2][i]) :
  1276. (result[c2][i] - result[c1][i]);
  1277. if (diff > MAX_TOLERANCE) {
  1278. if ((i == 2 || i == 6) && !simularity_bitmap) {
  1279. if (result[c1][i] + result[c1][i + 1] == 0)
  1280. final_candidate[(i / 4)] = c2;
  1281. else if (result[c2][i] + result[c2][i + 1] == 0)
  1282. final_candidate[(i / 4)] = c1;
  1283. else
  1284. simularity_bitmap = simularity_bitmap |
  1285. (1 << i);
  1286. } else
  1287. simularity_bitmap =
  1288. simularity_bitmap | (1 << i);
  1289. }
  1290. }
  1291. if (simularity_bitmap == 0) {
  1292. for (i = 0; i < (bound / 4); i++) {
  1293. if (final_candidate[i] != 0xFF) {
  1294. for (j = i * 4; j < (i + 1) * 4 - 2; j++)
  1295. result[3][j] =
  1296. result[final_candidate[i]][j];
  1297. bresult = false;
  1298. }
  1299. }
  1300. return bresult;
  1301. } else if (!(simularity_bitmap & 0x0F)) {
  1302. for (i = 0; i < 4; i++)
  1303. result[3][i] = result[c1][i];
  1304. return false;
  1305. } else {
  1306. return false;
  1307. }
  1308. }
  1309. static void _rtl8723ae_phy_iq_calibrate(struct ieee80211_hw *hw,
  1310. long result[][8], u8 t, bool is2t)
  1311. {
  1312. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1313. struct rtl_phy *rtlphy = &(rtlpriv->phy);
  1314. u32 i;
  1315. u8 patha_ok, pathb_ok;
  1316. u32 adda_reg[IQK_ADDA_REG_NUM] = {
  1317. 0x85c, 0xe6c, 0xe70, 0xe74,
  1318. 0xe78, 0xe7c, 0xe80, 0xe84,
  1319. 0xe88, 0xe8c, 0xed0, 0xed4,
  1320. 0xed8, 0xedc, 0xee0, 0xeec
  1321. };
  1322. u32 iqk_mac_reg[IQK_MAC_REG_NUM] = {
  1323. 0x522, 0x550, 0x551, 0x040
  1324. };
  1325. const u32 retrycount = 2;
  1326. if (t == 0) {
  1327. phy_save_adda_regs(hw, adda_reg, rtlphy->adda_backup, 16);
  1328. phy_save_mac_regs(hw, iqk_mac_reg, rtlphy->iqk_mac_backup);
  1329. }
  1330. _rtl8723ae_phy_path_adda_on(hw, adda_reg, true, is2t);
  1331. if (t == 0) {
  1332. rtlphy->rfpi_enable = (u8) rtl_get_bbreg(hw,
  1333. RFPGA0_XA_HSSIPARAMETER1,
  1334. BIT(8));
  1335. }
  1336. if (!rtlphy->rfpi_enable)
  1337. _rtl8723ae_phy_pi_mode_switch(hw, true);
  1338. if (t == 0) {
  1339. rtlphy->reg_c04 = rtl_get_bbreg(hw, 0xc04, MASKDWORD);
  1340. rtlphy->reg_c08 = rtl_get_bbreg(hw, 0xc08, MASKDWORD);
  1341. rtlphy->reg_874 = rtl_get_bbreg(hw, 0x874, MASKDWORD);
  1342. }
  1343. rtl_set_bbreg(hw, 0xc04, MASKDWORD, 0x03a05600);
  1344. rtl_set_bbreg(hw, 0xc08, MASKDWORD, 0x000800e4);
  1345. rtl_set_bbreg(hw, 0x874, MASKDWORD, 0x22204000);
  1346. if (is2t) {
  1347. rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000);
  1348. rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00010000);
  1349. }
  1350. _rtl8723ae_phy_mac_setting_calibration(hw, iqk_mac_reg,
  1351. rtlphy->iqk_mac_backup);
  1352. rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x00080000);
  1353. if (is2t)
  1354. rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x00080000);
  1355. rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
  1356. rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x01007c00);
  1357. rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800);
  1358. for (i = 0; i < retrycount; i++) {
  1359. patha_ok = _rtl8723ae_phy_path_a_iqk(hw, is2t);
  1360. if (patha_ok == 0x03) {
  1361. result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) &
  1362. 0x3FF0000) >> 16;
  1363. result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) &
  1364. 0x3FF0000) >> 16;
  1365. result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) &
  1366. 0x3FF0000) >> 16;
  1367. result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) &
  1368. 0x3FF0000) >> 16;
  1369. break;
  1370. } else if (i == (retrycount - 1) && patha_ok == 0x01)
  1371. result[t][0] = (rtl_get_bbreg(hw, 0xe94,
  1372. MASKDWORD) & 0x3FF0000) >> 16;
  1373. result[t][1] =
  1374. (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & 0x3FF0000) >> 16;
  1375. }
  1376. if (is2t) {
  1377. _rtl8723ae_phy_path_a_standby(hw);
  1378. _rtl8723ae_phy_path_adda_on(hw, adda_reg, false, is2t);
  1379. for (i = 0; i < retrycount; i++) {
  1380. pathb_ok = _rtl8723ae_phy_path_b_iqk(hw);
  1381. if (pathb_ok == 0x03) {
  1382. result[t][4] =
  1383. (rtl_get_bbreg(hw, 0xeb4, MASKDWORD) &
  1384. 0x3FF0000) >> 16;
  1385. result[t][5] =
  1386. (rtl_get_bbreg(hw, 0xebc, MASKDWORD) &
  1387. 0x3FF0000) >> 16;
  1388. result[t][6] =
  1389. (rtl_get_bbreg(hw, 0xec4, MASKDWORD) &
  1390. 0x3FF0000) >> 16;
  1391. result[t][7] =
  1392. (rtl_get_bbreg(hw, 0xecc, MASKDWORD) &
  1393. 0x3FF0000) >> 16;
  1394. break;
  1395. } else if (i == (retrycount - 1) && pathb_ok == 0x01) {
  1396. result[t][4] =
  1397. (rtl_get_bbreg(hw, 0xeb4, MASKDWORD) &
  1398. 0x3FF0000) >> 16;
  1399. }
  1400. result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) &
  1401. 0x3FF0000) >> 16;
  1402. }
  1403. }
  1404. rtl_set_bbreg(hw, 0xc04, MASKDWORD, rtlphy->reg_c04);
  1405. rtl_set_bbreg(hw, 0x874, MASKDWORD, rtlphy->reg_874);
  1406. rtl_set_bbreg(hw, 0xc08, MASKDWORD, rtlphy->reg_c08);
  1407. rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0);
  1408. rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00032ed3);
  1409. if (is2t)
  1410. rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00032ed3);
  1411. if (t != 0) {
  1412. if (!rtlphy->rfpi_enable)
  1413. _rtl8723ae_phy_pi_mode_switch(hw, false);
  1414. phy_reload_adda_regs(hw, adda_reg, rtlphy->adda_backup, 16);
  1415. phy_reload_mac_regs(hw, iqk_mac_reg, rtlphy->iqk_mac_backup);
  1416. }
  1417. }
  1418. static void _rtl8723ae_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t)
  1419. {
  1420. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1421. u8 tmpreg;
  1422. u32 rf_a_mode = 0, rf_b_mode = 0, lc_cal;
  1423. tmpreg = rtl_read_byte(rtlpriv, 0xd03);
  1424. if ((tmpreg & 0x70) != 0)
  1425. rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F);
  1426. else
  1427. rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
  1428. if ((tmpreg & 0x70) != 0) {
  1429. rf_a_mode = rtl_get_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS);
  1430. if (is2t)
  1431. rf_b_mode = rtl_get_rfreg(hw, RF90_PATH_B, 0x00,
  1432. MASK12BITS);
  1433. rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS,
  1434. (rf_a_mode & 0x8FFFF) | 0x10000);
  1435. if (is2t)
  1436. rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,
  1437. (rf_b_mode & 0x8FFFF) | 0x10000);
  1438. }
  1439. lc_cal = rtl_get_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS);
  1440. rtl_set_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS, lc_cal | 0x08000);
  1441. mdelay(100);
  1442. if ((tmpreg & 0x70) != 0) {
  1443. rtl_write_byte(rtlpriv, 0xd03, tmpreg);
  1444. rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, rf_a_mode);
  1445. if (is2t)
  1446. rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,
  1447. rf_b_mode);
  1448. } else {
  1449. rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
  1450. }
  1451. }
  1452. static void _rtl8723ae_phy_set_rfpath_switch(struct ieee80211_hw *hw,
  1453. bool bmain, bool is2t)
  1454. {
  1455. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  1456. if (is_hal_stop(rtlhal)) {
  1457. rtl_set_bbreg(hw, REG_LEDCFG0, BIT(23), 0x01);
  1458. rtl_set_bbreg(hw, rFPGA0_XAB_RFPARAMETER, BIT(13), 0x01);
  1459. }
  1460. if (is2t) {
  1461. if (bmain)
  1462. rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
  1463. BIT(5) | BIT(6), 0x1);
  1464. else
  1465. rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
  1466. BIT(5) | BIT(6), 0x2);
  1467. } else {
  1468. if (bmain)
  1469. rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 0x300, 0x2);
  1470. else
  1471. rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 0x300, 0x1);
  1472. }
  1473. }
  1474. #undef IQK_ADDA_REG_NUM
  1475. #undef IQK_DELAY_TIME
  1476. void rtl8723ae_phy_iq_calibrate(struct ieee80211_hw *hw, bool recovery)
  1477. {
  1478. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1479. struct rtl_phy *rtlphy = &(rtlpriv->phy);
  1480. long result[4][8];
  1481. u8 i, final_candidate;
  1482. bool patha_ok, pathb_ok;
  1483. long reg_e94, reg_e9c, reg_ea4, reg_eb4, reg_ebc, reg_tmp = 0;
  1484. bool is12simular, is13simular, is23simular;
  1485. bool start_conttx = false, singletone = false;
  1486. u32 iqk_bb_reg[10] = {
  1487. ROFDM0_XARXIQIMBALANCE,
  1488. ROFDM0_XBRXIQIMBALANCE,
  1489. ROFDM0_ECCATHRESHOLD,
  1490. ROFDM0_AGCRSSITABLE,
  1491. ROFDM0_XATXIQIMBALANCE,
  1492. ROFDM0_XBTXIQIMBALANCE,
  1493. ROFDM0_XCTXIQIMBALANCE,
  1494. ROFDM0_XCTXAFE,
  1495. ROFDM0_XDTXAFE,
  1496. ROFDM0_RXIQEXTANTA
  1497. };
  1498. if (recovery) {
  1499. phy_reload_adda_regs(hw, iqk_bb_reg, rtlphy->iqk_bb_backup, 10);
  1500. return;
  1501. }
  1502. if (start_conttx || singletone)
  1503. return;
  1504. for (i = 0; i < 8; i++) {
  1505. result[0][i] = 0;
  1506. result[1][i] = 0;
  1507. result[2][i] = 0;
  1508. result[3][i] = 0;
  1509. }
  1510. final_candidate = 0xff;
  1511. patha_ok = false;
  1512. pathb_ok = false;
  1513. is12simular = false;
  1514. is23simular = false;
  1515. is13simular = false;
  1516. for (i = 0; i < 3; i++) {
  1517. _rtl8723ae_phy_iq_calibrate(hw, result, i, false);
  1518. if (i == 1) {
  1519. is12simular = phy_simularity_comp(hw, result, 0, 1);
  1520. if (is12simular) {
  1521. final_candidate = 0;
  1522. break;
  1523. }
  1524. }
  1525. if (i == 2) {
  1526. is13simular = phy_simularity_comp(hw, result, 0, 2);
  1527. if (is13simular) {
  1528. final_candidate = 0;
  1529. break;
  1530. }
  1531. is23simular = phy_simularity_comp(hw, result, 1, 2);
  1532. if (is23simular) {
  1533. final_candidate = 1;
  1534. } else {
  1535. for (i = 0; i < 8; i++)
  1536. reg_tmp += result[3][i];
  1537. if (reg_tmp != 0)
  1538. final_candidate = 3;
  1539. else
  1540. final_candidate = 0xFF;
  1541. }
  1542. }
  1543. }
  1544. for (i = 0; i < 4; i++) {
  1545. reg_e94 = result[i][0];
  1546. reg_e9c = result[i][1];
  1547. reg_ea4 = result[i][2];
  1548. reg_eb4 = result[i][4];
  1549. reg_ebc = result[i][5];
  1550. }
  1551. if (final_candidate != 0xff) {
  1552. rtlphy->reg_e94 = reg_e94 = result[final_candidate][0];
  1553. rtlphy->reg_e9c = reg_e9c = result[final_candidate][1];
  1554. reg_ea4 = result[final_candidate][2];
  1555. rtlphy->reg_eb4 = reg_eb4 = result[final_candidate][4];
  1556. rtlphy->reg_ebc = reg_ebc = result[final_candidate][5];
  1557. patha_ok = pathb_ok = true;
  1558. } else {
  1559. rtlphy->reg_e94 = rtlphy->reg_eb4 = 0x100;
  1560. rtlphy->reg_e9c = rtlphy->reg_ebc = 0x0;
  1561. }
  1562. if (reg_e94 != 0) /*&&(reg_ea4 != 0) */
  1563. phy_path_a_fill_iqk_matrix(hw, patha_ok, result,
  1564. final_candidate, (reg_ea4 == 0));
  1565. phy_save_adda_regs(hw, iqk_bb_reg, rtlphy->iqk_bb_backup, 10);
  1566. }
  1567. void rtl8723ae_phy_lc_calibrate(struct ieee80211_hw *hw)
  1568. {
  1569. bool start_conttx = false, singletone = false;
  1570. if (start_conttx || singletone)
  1571. return;
  1572. _rtl8723ae_phy_lc_calibrate(hw, false);
  1573. }
  1574. void rtl8723ae_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain)
  1575. {
  1576. _rtl8723ae_phy_set_rfpath_switch(hw, bmain, false);
  1577. }
  1578. bool rtl8723ae_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype)
  1579. {
  1580. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1581. struct rtl_phy *rtlphy = &(rtlpriv->phy);
  1582. bool postprocessing = false;
  1583. RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
  1584. "-->IO Cmd(%#x), set_io_inprogress(%d)\n",
  1585. iotype, rtlphy->set_io_inprogress);
  1586. do {
  1587. switch (iotype) {
  1588. case IO_CMD_RESUME_DM_BY_SCAN:
  1589. RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
  1590. "[IO CMD] Resume DM after scan.\n");
  1591. postprocessing = true;
  1592. break;
  1593. case IO_CMD_PAUSE_DM_BY_SCAN:
  1594. RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
  1595. "[IO CMD] Pause DM before scan.\n");
  1596. postprocessing = true;
  1597. break;
  1598. default:
  1599. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  1600. "switch case not process\n");
  1601. break;
  1602. }
  1603. } while (false);
  1604. if (postprocessing && !rtlphy->set_io_inprogress) {
  1605. rtlphy->set_io_inprogress = true;
  1606. rtlphy->current_io_type = iotype;
  1607. } else {
  1608. return false;
  1609. }
  1610. rtl8723ae_phy_set_io(hw);
  1611. RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, "<--IO Type(%#x)\n", iotype);
  1612. return true;
  1613. }
  1614. static void rtl8723ae_phy_set_io(struct ieee80211_hw *hw)
  1615. {
  1616. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1617. struct rtl_phy *rtlphy = &(rtlpriv->phy);
  1618. struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
  1619. RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
  1620. "--->Cmd(%#x), set_io_inprogress(%d)\n",
  1621. rtlphy->current_io_type, rtlphy->set_io_inprogress);
  1622. switch (rtlphy->current_io_type) {
  1623. case IO_CMD_RESUME_DM_BY_SCAN:
  1624. dm_digtable->cur_igvalue = rtlphy->initgain_backup.xaagccore1;
  1625. rtl8723ae_dm_write_dig(hw);
  1626. rtl8723ae_phy_set_txpower_level(hw, rtlphy->current_channel);
  1627. break;
  1628. case IO_CMD_PAUSE_DM_BY_SCAN:
  1629. rtlphy->initgain_backup.xaagccore1 = dm_digtable->cur_igvalue;
  1630. dm_digtable->cur_igvalue = 0x17;
  1631. rtl8723ae_dm_write_dig(hw);
  1632. break;
  1633. default:
  1634. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  1635. "switch case not process\n");
  1636. break;
  1637. }
  1638. rtlphy->set_io_inprogress = false;
  1639. RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
  1640. "<---(%#x)\n", rtlphy->current_io_type);
  1641. }
  1642. static void rtl8723ae_phy_set_rf_on(struct ieee80211_hw *hw)
  1643. {
  1644. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1645. rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
  1646. rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
  1647. rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);
  1648. rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
  1649. rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
  1650. rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
  1651. }
  1652. static void _rtl8723ae_phy_set_rf_sleep(struct ieee80211_hw *hw)
  1653. {
  1654. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1655. u32 u4b_tmp;
  1656. u8 delay = 5;
  1657. rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
  1658. rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
  1659. rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
  1660. u4b_tmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
  1661. while (u4b_tmp != 0 && delay > 0) {
  1662. rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x0);
  1663. rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
  1664. rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
  1665. u4b_tmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
  1666. delay--;
  1667. }
  1668. if (delay == 0) {
  1669. rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);
  1670. rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
  1671. rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
  1672. rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
  1673. RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
  1674. "Switch RF timeout !!!.\n");
  1675. return;
  1676. }
  1677. rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
  1678. rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22);
  1679. }
  1680. static bool _rtl8723ae_phy_set_rf_power_state(struct ieee80211_hw *hw,
  1681. enum rf_pwrstate rfpwr_state)
  1682. {
  1683. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1684. struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
  1685. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  1686. struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
  1687. struct rtl8192_tx_ring *ring = NULL;
  1688. bool bresult = true;
  1689. u8 i, queue_id;
  1690. switch (rfpwr_state) {
  1691. case ERFON:
  1692. if ((ppsc->rfpwr_state == ERFOFF) &&
  1693. RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
  1694. bool rtstatus;
  1695. u32 InitializeCount = 0;
  1696. do {
  1697. InitializeCount++;
  1698. RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
  1699. "IPS Set eRf nic enable\n");
  1700. rtstatus = rtl_ps_enable_nic(hw);
  1701. } while ((rtstatus != true) && (InitializeCount < 10));
  1702. RT_CLEAR_PS_LEVEL(ppsc,
  1703. RT_RF_OFF_LEVL_HALT_NIC);
  1704. } else {
  1705. RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
  1706. "Set ERFON sleeped:%d ms\n",
  1707. jiffies_to_msecs(jiffies -
  1708. ppsc->last_sleep_jiffies));
  1709. ppsc->last_awake_jiffies = jiffies;
  1710. rtl8723ae_phy_set_rf_on(hw);
  1711. }
  1712. if (mac->link_state == MAC80211_LINKED) {
  1713. rtlpriv->cfg->ops->led_control(hw,
  1714. LED_CTL_LINK);
  1715. } else {
  1716. rtlpriv->cfg->ops->led_control(hw,
  1717. LED_CTL_NO_LINK);
  1718. }
  1719. break;
  1720. case ERFOFF:
  1721. if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) {
  1722. RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
  1723. "IPS Set eRf nic disable\n");
  1724. rtl_ps_disable_nic(hw);
  1725. RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
  1726. } else {
  1727. if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) {
  1728. rtlpriv->cfg->ops->led_control(hw,
  1729. LED_CTL_NO_LINK);
  1730. } else {
  1731. rtlpriv->cfg->ops->led_control(hw,
  1732. LED_CTL_POWER_OFF);
  1733. }
  1734. }
  1735. break;
  1736. case ERFSLEEP:
  1737. if (ppsc->rfpwr_state == ERFOFF)
  1738. break;
  1739. for (queue_id = 0, i = 0;
  1740. queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
  1741. ring = &pcipriv->dev.tx_ring[queue_id];
  1742. if (skb_queue_len(&ring->queue) == 0) {
  1743. queue_id++;
  1744. continue;
  1745. } else {
  1746. RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
  1747. "eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n",
  1748. (i + 1), queue_id,
  1749. skb_queue_len(&ring->queue));
  1750. udelay(10);
  1751. i++;
  1752. }
  1753. if (i >= MAX_DOZE_WAITING_TIMES_9x) {
  1754. RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
  1755. "\n ERFSLEEP: %d times TcbBusyQueue[%d] = %d !\n",
  1756. MAX_DOZE_WAITING_TIMES_9x,
  1757. queue_id,
  1758. skb_queue_len(&ring->queue));
  1759. break;
  1760. }
  1761. }
  1762. RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
  1763. "Set ERFSLEEP awaked:%d ms\n",
  1764. jiffies_to_msecs(jiffies - ppsc->last_awake_jiffies));
  1765. ppsc->last_sleep_jiffies = jiffies;
  1766. _rtl8723ae_phy_set_rf_sleep(hw);
  1767. break;
  1768. default:
  1769. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  1770. "switch case not processed\n");
  1771. bresult = false;
  1772. break;
  1773. }
  1774. if (bresult)
  1775. ppsc->rfpwr_state = rfpwr_state;
  1776. return bresult;
  1777. }
  1778. bool rtl8723ae_phy_set_rf_power_state(struct ieee80211_hw *hw,
  1779. enum rf_pwrstate rfpwr_state)
  1780. {
  1781. struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
  1782. bool bresult = false;
  1783. if (rfpwr_state == ppsc->rfpwr_state)
  1784. return bresult;
  1785. bresult = _rtl8723ae_phy_set_rf_power_state(hw, rfpwr_state);
  1786. return bresult;
  1787. }