mac.c 26 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2009-2012 Realtek Corporation. All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of version 2 of the GNU General Public License as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc.,
  16. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17. *
  18. * The full GNU General Public License is included in this distribution in the
  19. * file called LICENSE.
  20. *
  21. * Contact Information:
  22. * wlanfae <wlanfae@realtek.com>
  23. * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24. * Hsinchu 300, Taiwan.
  25. *
  26. * Larry Finger <Larry.Finger@lwfinger.net>
  27. *
  28. ****************************************************************************/
  29. #include "../wifi.h"
  30. #include "../pci.h"
  31. #include "../usb.h"
  32. #include "../ps.h"
  33. #include "../cam.h"
  34. #include "../stats.h"
  35. #include "reg.h"
  36. #include "def.h"
  37. #include "phy.h"
  38. #include "rf.h"
  39. #include "dm.h"
  40. #include "mac.h"
  41. #include "trx.h"
  42. #include <linux/module.h>
  43. /* macro to shorten lines */
  44. #define LINK_Q ui_link_quality
  45. #define RX_EVM rx_evm_percentage
  46. #define RX_SIGQ rx_mimo_sig_qual
  47. void rtl92c_read_chip_version(struct ieee80211_hw *hw)
  48. {
  49. struct rtl_priv *rtlpriv = rtl_priv(hw);
  50. struct rtl_phy *rtlphy = &(rtlpriv->phy);
  51. struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
  52. enum version_8192c chip_version = VERSION_UNKNOWN;
  53. const char *versionid;
  54. u32 value32;
  55. value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
  56. if (value32 & TRP_VAUX_EN) {
  57. chip_version = (value32 & TYPE_ID) ? VERSION_TEST_CHIP_92C :
  58. VERSION_TEST_CHIP_88C;
  59. } else {
  60. /* Normal mass production chip. */
  61. chip_version = NORMAL_CHIP;
  62. chip_version |= ((value32 & TYPE_ID) ? CHIP_92C : 0);
  63. chip_version |= ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : 0);
  64. /* RTL8723 with BT function. */
  65. chip_version |= ((value32 & BT_FUNC) ? CHIP_8723 : 0);
  66. if (IS_VENDOR_UMC(chip_version))
  67. chip_version |= ((value32 & CHIP_VER_RTL_MASK) ?
  68. CHIP_VENDOR_UMC_B_CUT : 0);
  69. if (IS_92C_SERIAL(chip_version)) {
  70. value32 = rtl_read_dword(rtlpriv, REG_HPON_FSM);
  71. chip_version |= ((CHIP_BONDING_IDENTIFIER(value32) ==
  72. CHIP_BONDING_92C_1T2R) ? CHIP_92C_1T2R : 0);
  73. } else if (IS_8723_SERIES(chip_version)) {
  74. value32 = rtl_read_dword(rtlpriv, REG_GPIO_OUTSTS);
  75. chip_version |= ((value32 & RF_RL_ID) ?
  76. CHIP_8723_DRV_REV : 0);
  77. }
  78. }
  79. rtlhal->version = (enum version_8192c)chip_version;
  80. pr_info("Chip version 0x%x\n", chip_version);
  81. switch (rtlhal->version) {
  82. case VERSION_NORMAL_TSMC_CHIP_92C_1T2R:
  83. versionid = "NORMAL_B_CHIP_92C";
  84. break;
  85. case VERSION_NORMAL_TSMC_CHIP_92C:
  86. versionid = "NORMAL_TSMC_CHIP_92C";
  87. break;
  88. case VERSION_NORMAL_TSMC_CHIP_88C:
  89. versionid = "NORMAL_TSMC_CHIP_88C";
  90. break;
  91. case VERSION_NORMAL_UMC_CHIP_92C_1T2R_A_CUT:
  92. versionid = "NORMAL_UMC_CHIP_i92C_1T2R_A_CUT";
  93. break;
  94. case VERSION_NORMAL_UMC_CHIP_92C_A_CUT:
  95. versionid = "NORMAL_UMC_CHIP_92C_A_CUT";
  96. break;
  97. case VERSION_NORMAL_UMC_CHIP_88C_A_CUT:
  98. versionid = "NORMAL_UMC_CHIP_88C_A_CUT";
  99. break;
  100. case VERSION_NORMAL_UMC_CHIP_92C_1T2R_B_CUT:
  101. versionid = "NORMAL_UMC_CHIP_92C_1T2R_B_CUT";
  102. break;
  103. case VERSION_NORMAL_UMC_CHIP_92C_B_CUT:
  104. versionid = "NORMAL_UMC_CHIP_92C_B_CUT";
  105. break;
  106. case VERSION_NORMAL_UMC_CHIP_88C_B_CUT:
  107. versionid = "NORMAL_UMC_CHIP_88C_B_CUT";
  108. break;
  109. case VERSION_NORMA_UMC_CHIP_8723_1T1R_A_CUT:
  110. versionid = "NORMAL_UMC_CHIP_8723_1T1R_A_CUT";
  111. break;
  112. case VERSION_NORMA_UMC_CHIP_8723_1T1R_B_CUT:
  113. versionid = "NORMAL_UMC_CHIP_8723_1T1R_B_CUT";
  114. break;
  115. case VERSION_TEST_CHIP_92C:
  116. versionid = "TEST_CHIP_92C";
  117. break;
  118. case VERSION_TEST_CHIP_88C:
  119. versionid = "TEST_CHIP_88C";
  120. break;
  121. default:
  122. versionid = "UNKNOWN";
  123. break;
  124. }
  125. RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
  126. "Chip Version ID: %s\n", versionid);
  127. if (IS_92C_SERIAL(rtlhal->version))
  128. rtlphy->rf_type =
  129. (IS_92C_1T2R(rtlhal->version)) ? RF_1T2R : RF_2T2R;
  130. else
  131. rtlphy->rf_type = RF_1T1R;
  132. RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
  133. "Chip RF Type: %s\n",
  134. rtlphy->rf_type == RF_2T2R ? "RF_2T2R" : "RF_1T1R");
  135. if (get_rf_type(rtlphy) == RF_1T1R)
  136. rtlpriv->dm.rfpath_rxenable[0] = true;
  137. else
  138. rtlpriv->dm.rfpath_rxenable[0] =
  139. rtlpriv->dm.rfpath_rxenable[1] = true;
  140. RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",
  141. rtlhal->version);
  142. }
  143. /**
  144. * writeLLT - LLT table write access
  145. * @io: io callback
  146. * @address: LLT logical address.
  147. * @data: LLT data content
  148. *
  149. * Realtek hardware access function.
  150. *
  151. */
  152. bool rtl92c_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
  153. {
  154. struct rtl_priv *rtlpriv = rtl_priv(hw);
  155. bool status = true;
  156. long count = 0;
  157. u32 value = _LLT_INIT_ADDR(address) |
  158. _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS);
  159. rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
  160. do {
  161. value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
  162. if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
  163. break;
  164. if (count > POLLING_LLT_THRESHOLD) {
  165. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  166. "Failed to polling write LLT done at address %d! _LLT_OP_VALUE(%x)\n",
  167. address, _LLT_OP_VALUE(value));
  168. status = false;
  169. break;
  170. }
  171. } while (++count);
  172. return status;
  173. }
  174. /**
  175. * rtl92c_init_LLT_table - Init LLT table
  176. * @io: io callback
  177. * @boundary:
  178. *
  179. * Realtek hardware access function.
  180. *
  181. */
  182. bool rtl92c_init_llt_table(struct ieee80211_hw *hw, u32 boundary)
  183. {
  184. bool rst = true;
  185. u32 i;
  186. for (i = 0; i < (boundary - 1); i++) {
  187. rst = rtl92c_llt_write(hw, i , i + 1);
  188. if (true != rst) {
  189. pr_err("===> %s #1 fail\n", __func__);
  190. return rst;
  191. }
  192. }
  193. /* end of list */
  194. rst = rtl92c_llt_write(hw, (boundary - 1), 0xFF);
  195. if (true != rst) {
  196. pr_err("===> %s #2 fail\n", __func__);
  197. return rst;
  198. }
  199. /* Make the other pages as ring buffer
  200. * This ring buffer is used as beacon buffer if we config this MAC
  201. * as two MAC transfer.
  202. * Otherwise used as local loopback buffer.
  203. */
  204. for (i = boundary; i < LLT_LAST_ENTRY_OF_TX_PKT_BUFFER; i++) {
  205. rst = rtl92c_llt_write(hw, i, (i + 1));
  206. if (true != rst) {
  207. pr_err("===> %s #3 fail\n", __func__);
  208. return rst;
  209. }
  210. }
  211. /* Let last entry point to the start entry of ring buffer */
  212. rst = rtl92c_llt_write(hw, LLT_LAST_ENTRY_OF_TX_PKT_BUFFER, boundary);
  213. if (true != rst) {
  214. pr_err("===> %s #4 fail\n", __func__);
  215. return rst;
  216. }
  217. return rst;
  218. }
  219. void rtl92c_set_key(struct ieee80211_hw *hw, u32 key_index,
  220. u8 *p_macaddr, bool is_group, u8 enc_algo,
  221. bool is_wepkey, bool clear_all)
  222. {
  223. struct rtl_priv *rtlpriv = rtl_priv(hw);
  224. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  225. struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
  226. u8 *macaddr = p_macaddr;
  227. u32 entry_id = 0;
  228. bool is_pairwise = false;
  229. static u8 cam_const_addr[4][6] = {
  230. {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
  231. {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
  232. {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
  233. {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
  234. };
  235. static u8 cam_const_broad[] = {
  236. 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
  237. };
  238. if (clear_all) {
  239. u8 idx = 0;
  240. u8 cam_offset = 0;
  241. u8 clear_number = 5;
  242. RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
  243. for (idx = 0; idx < clear_number; idx++) {
  244. rtl_cam_mark_invalid(hw, cam_offset + idx);
  245. rtl_cam_empty_entry(hw, cam_offset + idx);
  246. if (idx < 5) {
  247. memset(rtlpriv->sec.key_buf[idx], 0,
  248. MAX_KEY_LEN);
  249. rtlpriv->sec.key_len[idx] = 0;
  250. }
  251. }
  252. } else {
  253. switch (enc_algo) {
  254. case WEP40_ENCRYPTION:
  255. enc_algo = CAM_WEP40;
  256. break;
  257. case WEP104_ENCRYPTION:
  258. enc_algo = CAM_WEP104;
  259. break;
  260. case TKIP_ENCRYPTION:
  261. enc_algo = CAM_TKIP;
  262. break;
  263. case AESCCMP_ENCRYPTION:
  264. enc_algo = CAM_AES;
  265. break;
  266. default:
  267. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  268. "illegal switch case\n");
  269. enc_algo = CAM_TKIP;
  270. break;
  271. }
  272. if (is_wepkey || rtlpriv->sec.use_defaultkey) {
  273. macaddr = cam_const_addr[key_index];
  274. entry_id = key_index;
  275. } else {
  276. if (is_group) {
  277. macaddr = cam_const_broad;
  278. entry_id = key_index;
  279. } else {
  280. if (mac->opmode == NL80211_IFTYPE_AP ||
  281. mac->opmode == NL80211_IFTYPE_MESH_POINT) {
  282. entry_id = rtl_cam_get_free_entry(hw,
  283. p_macaddr);
  284. if (entry_id >= TOTAL_CAM_ENTRY) {
  285. RT_TRACE(rtlpriv, COMP_SEC,
  286. DBG_EMERG,
  287. "Can not find free hw security cam entry\n");
  288. return;
  289. }
  290. } else {
  291. entry_id = CAM_PAIRWISE_KEY_POSITION;
  292. }
  293. key_index = PAIRWISE_KEYIDX;
  294. is_pairwise = true;
  295. }
  296. }
  297. if (rtlpriv->sec.key_len[key_index] == 0) {
  298. RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
  299. "delete one entry\n");
  300. if (mac->opmode == NL80211_IFTYPE_AP ||
  301. mac->opmode == NL80211_IFTYPE_MESH_POINT)
  302. rtl_cam_del_entry(hw, p_macaddr);
  303. rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
  304. } else {
  305. RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
  306. "The insert KEY length is %d\n",
  307. rtlpriv->sec.key_len[PAIRWISE_KEYIDX]);
  308. RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
  309. "The insert KEY is %x %x\n",
  310. rtlpriv->sec.key_buf[0][0],
  311. rtlpriv->sec.key_buf[0][1]);
  312. RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
  313. "add one entry\n");
  314. if (is_pairwise) {
  315. RT_PRINT_DATA(rtlpriv, COMP_SEC, DBG_LOUD,
  316. "Pairwise Key content",
  317. rtlpriv->sec.pairwise_key,
  318. rtlpriv->sec.
  319. key_len[PAIRWISE_KEYIDX]);
  320. RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
  321. "set Pairwise key\n");
  322. rtl_cam_add_one_entry(hw, macaddr, key_index,
  323. entry_id, enc_algo,
  324. CAM_CONFIG_NO_USEDK,
  325. rtlpriv->sec.
  326. key_buf[key_index]);
  327. } else {
  328. RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
  329. "set group key\n");
  330. if (mac->opmode == NL80211_IFTYPE_ADHOC) {
  331. rtl_cam_add_one_entry(hw,
  332. rtlefuse->dev_addr,
  333. PAIRWISE_KEYIDX,
  334. CAM_PAIRWISE_KEY_POSITION,
  335. enc_algo,
  336. CAM_CONFIG_NO_USEDK,
  337. rtlpriv->sec.key_buf
  338. [entry_id]);
  339. }
  340. rtl_cam_add_one_entry(hw, macaddr, key_index,
  341. entry_id, enc_algo,
  342. CAM_CONFIG_NO_USEDK,
  343. rtlpriv->sec.key_buf[entry_id]);
  344. }
  345. }
  346. }
  347. }
  348. u32 rtl92c_get_txdma_status(struct ieee80211_hw *hw)
  349. {
  350. struct rtl_priv *rtlpriv = rtl_priv(hw);
  351. return rtl_read_dword(rtlpriv, REG_TXDMA_STATUS);
  352. }
  353. void rtl92c_enable_interrupt(struct ieee80211_hw *hw)
  354. {
  355. struct rtl_priv *rtlpriv = rtl_priv(hw);
  356. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  357. struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  358. struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
  359. if (IS_HARDWARE_TYPE_8192CE(rtlhal)) {
  360. rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] &
  361. 0xFFFFFFFF);
  362. rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] &
  363. 0xFFFFFFFF);
  364. } else {
  365. rtl_write_dword(rtlpriv, REG_HIMR, rtlusb->irq_mask[0] &
  366. 0xFFFFFFFF);
  367. rtl_write_dword(rtlpriv, REG_HIMRE, rtlusb->irq_mask[1] &
  368. 0xFFFFFFFF);
  369. }
  370. }
  371. void rtl92c_init_interrupt(struct ieee80211_hw *hw)
  372. {
  373. rtl92c_enable_interrupt(hw);
  374. }
  375. void rtl92c_disable_interrupt(struct ieee80211_hw *hw)
  376. {
  377. struct rtl_priv *rtlpriv = rtl_priv(hw);
  378. rtl_write_dword(rtlpriv, REG_HIMR, IMR8190_DISABLED);
  379. rtl_write_dword(rtlpriv, REG_HIMRE, IMR8190_DISABLED);
  380. }
  381. void rtl92c_set_qos(struct ieee80211_hw *hw, int aci)
  382. {
  383. struct rtl_priv *rtlpriv = rtl_priv(hw);
  384. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  385. u32 u4b_ac_param;
  386. rtl92c_dm_init_edca_turbo(hw);
  387. u4b_ac_param = (u32) mac->ac[aci].aifs;
  388. u4b_ac_param |=
  389. ((u32) le16_to_cpu(mac->ac[aci].cw_min) & 0xF) <<
  390. AC_PARAM_ECW_MIN_OFFSET;
  391. u4b_ac_param |=
  392. ((u32) le16_to_cpu(mac->ac[aci].cw_max) & 0xF) <<
  393. AC_PARAM_ECW_MAX_OFFSET;
  394. u4b_ac_param |= (u32) le16_to_cpu(mac->ac[aci].tx_op) <<
  395. AC_PARAM_TXOP_OFFSET;
  396. RT_TRACE(rtlpriv, COMP_QOS, DBG_LOUD, "queue:%x, ac_param:%x\n",
  397. aci, u4b_ac_param);
  398. switch (aci) {
  399. case AC1_BK:
  400. rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, u4b_ac_param);
  401. break;
  402. case AC0_BE:
  403. rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, u4b_ac_param);
  404. break;
  405. case AC2_VI:
  406. rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, u4b_ac_param);
  407. break;
  408. case AC3_VO:
  409. rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, u4b_ac_param);
  410. break;
  411. default:
  412. RT_ASSERT(false, "invalid aci: %d !\n", aci);
  413. break;
  414. }
  415. }
  416. /*-------------------------------------------------------------------------
  417. * HW MAC Address
  418. *-------------------------------------------------------------------------*/
  419. void rtl92c_set_mac_addr(struct ieee80211_hw *hw, const u8 *addr)
  420. {
  421. u32 i;
  422. struct rtl_priv *rtlpriv = rtl_priv(hw);
  423. for (i = 0 ; i < ETH_ALEN ; i++)
  424. rtl_write_byte(rtlpriv, (REG_MACID + i), *(addr+i));
  425. RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG,
  426. "MAC Address: %02X-%02X-%02X-%02X-%02X-%02X\n",
  427. rtl_read_byte(rtlpriv, REG_MACID),
  428. rtl_read_byte(rtlpriv, REG_MACID+1),
  429. rtl_read_byte(rtlpriv, REG_MACID+2),
  430. rtl_read_byte(rtlpriv, REG_MACID+3),
  431. rtl_read_byte(rtlpriv, REG_MACID+4),
  432. rtl_read_byte(rtlpriv, REG_MACID+5));
  433. }
  434. void rtl92c_init_driver_info_size(struct ieee80211_hw *hw, u8 size)
  435. {
  436. struct rtl_priv *rtlpriv = rtl_priv(hw);
  437. rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, size);
  438. }
  439. int rtl92c_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
  440. {
  441. u8 value;
  442. struct rtl_priv *rtlpriv = rtl_priv(hw);
  443. switch (type) {
  444. case NL80211_IFTYPE_UNSPECIFIED:
  445. value = NT_NO_LINK;
  446. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
  447. "Set Network type to NO LINK!\n");
  448. break;
  449. case NL80211_IFTYPE_ADHOC:
  450. value = NT_LINK_AD_HOC;
  451. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
  452. "Set Network type to Ad Hoc!\n");
  453. break;
  454. case NL80211_IFTYPE_STATION:
  455. value = NT_LINK_AP;
  456. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
  457. "Set Network type to STA!\n");
  458. break;
  459. case NL80211_IFTYPE_AP:
  460. value = NT_AS_AP;
  461. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
  462. "Set Network type to AP!\n");
  463. break;
  464. default:
  465. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
  466. "Network type %d not supported!\n", type);
  467. return -EOPNOTSUPP;
  468. }
  469. rtl_write_byte(rtlpriv, (REG_CR + 2), value);
  470. return 0;
  471. }
  472. void rtl92c_init_network_type(struct ieee80211_hw *hw)
  473. {
  474. rtl92c_set_network_type(hw, NL80211_IFTYPE_UNSPECIFIED);
  475. }
  476. void rtl92c_init_adaptive_ctrl(struct ieee80211_hw *hw)
  477. {
  478. u16 value16;
  479. u32 value32;
  480. struct rtl_priv *rtlpriv = rtl_priv(hw);
  481. /* Response Rate Set */
  482. value32 = rtl_read_dword(rtlpriv, REG_RRSR);
  483. value32 &= ~RATE_BITMAP_ALL;
  484. value32 |= RATE_RRSR_CCK_ONLY_1M;
  485. rtl_write_dword(rtlpriv, REG_RRSR, value32);
  486. /* SIFS (used in NAV) */
  487. value16 = _SPEC_SIFS_CCK(0x10) | _SPEC_SIFS_OFDM(0x10);
  488. rtl_write_word(rtlpriv, REG_SPEC_SIFS, value16);
  489. /* Retry Limit */
  490. value16 = _LRL(0x30) | _SRL(0x30);
  491. rtl_write_dword(rtlpriv, REG_RL, value16);
  492. }
  493. void rtl92c_init_rate_fallback(struct ieee80211_hw *hw)
  494. {
  495. struct rtl_priv *rtlpriv = rtl_priv(hw);
  496. /* Set Data Auto Rate Fallback Retry Count register. */
  497. rtl_write_dword(rtlpriv, REG_DARFRC, 0x00000000);
  498. rtl_write_dword(rtlpriv, REG_DARFRC+4, 0x10080404);
  499. rtl_write_dword(rtlpriv, REG_RARFRC, 0x04030201);
  500. rtl_write_dword(rtlpriv, REG_RARFRC+4, 0x08070605);
  501. }
  502. static void rtl92c_set_cck_sifs(struct ieee80211_hw *hw, u8 trx_sifs,
  503. u8 ctx_sifs)
  504. {
  505. struct rtl_priv *rtlpriv = rtl_priv(hw);
  506. rtl_write_byte(rtlpriv, REG_SIFS_CCK, trx_sifs);
  507. rtl_write_byte(rtlpriv, (REG_SIFS_CCK + 1), ctx_sifs);
  508. }
  509. static void rtl92c_set_ofdm_sifs(struct ieee80211_hw *hw, u8 trx_sifs,
  510. u8 ctx_sifs)
  511. {
  512. struct rtl_priv *rtlpriv = rtl_priv(hw);
  513. rtl_write_byte(rtlpriv, REG_SIFS_OFDM, trx_sifs);
  514. rtl_write_byte(rtlpriv, (REG_SIFS_OFDM + 1), ctx_sifs);
  515. }
  516. void rtl92c_init_edca_param(struct ieee80211_hw *hw,
  517. u16 queue, u16 txop, u8 cw_min, u8 cw_max, u8 aifs)
  518. {
  519. /* sequence: VO, VI, BE, BK ==> the same as 92C hardware design.
  520. * referenc : enum nl80211_txq_q or ieee80211_set_wmm_default function.
  521. */
  522. u32 value;
  523. struct rtl_priv *rtlpriv = rtl_priv(hw);
  524. value = (u32)aifs;
  525. value |= ((u32)cw_min & 0xF) << 8;
  526. value |= ((u32)cw_max & 0xF) << 12;
  527. value |= (u32)txop << 16;
  528. /* 92C hardware register sequence is the same as queue number. */
  529. rtl_write_dword(rtlpriv, (REG_EDCA_VO_PARAM + (queue * 4)), value);
  530. }
  531. void rtl92c_init_edca(struct ieee80211_hw *hw)
  532. {
  533. u16 value16;
  534. struct rtl_priv *rtlpriv = rtl_priv(hw);
  535. /* disable EDCCA count down, to reduce collison and retry */
  536. value16 = rtl_read_word(rtlpriv, REG_RD_CTRL);
  537. value16 |= DIS_EDCA_CNT_DWN;
  538. rtl_write_word(rtlpriv, REG_RD_CTRL, value16);
  539. /* Update SIFS timing. ??????????
  540. * pHalData->SifsTime = 0x0e0e0a0a; */
  541. rtl92c_set_cck_sifs(hw, 0xa, 0xa);
  542. rtl92c_set_ofdm_sifs(hw, 0xe, 0xe);
  543. /* Set CCK/OFDM SIFS to be 10us. */
  544. rtl_write_word(rtlpriv, REG_SIFS_CCK, 0x0a0a);
  545. rtl_write_word(rtlpriv, REG_SIFS_OFDM, 0x1010);
  546. rtl_write_word(rtlpriv, REG_PROT_MODE_CTRL, 0x0204);
  547. rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x014004);
  548. /* TXOP */
  549. rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, 0x005EA42B);
  550. rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0x0000A44F);
  551. rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x005EA324);
  552. rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x002FA226);
  553. /* PIFS */
  554. rtl_write_byte(rtlpriv, REG_PIFS, 0x1C);
  555. /* AGGR BREAK TIME Register */
  556. rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16);
  557. rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0040);
  558. rtl_write_byte(rtlpriv, REG_BCNDMATIM, 0x02);
  559. rtl_write_byte(rtlpriv, REG_ATIMWND, 0x02);
  560. }
  561. void rtl92c_init_ampdu_aggregation(struct ieee80211_hw *hw)
  562. {
  563. struct rtl_priv *rtlpriv = rtl_priv(hw);
  564. rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0x99997631);
  565. rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16);
  566. /* init AMPDU aggregation number, tuning for Tx's TP, */
  567. rtl_write_word(rtlpriv, 0x4CA, 0x0708);
  568. }
  569. void rtl92c_init_beacon_max_error(struct ieee80211_hw *hw, bool infra_mode)
  570. {
  571. struct rtl_priv *rtlpriv = rtl_priv(hw);
  572. rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xFF);
  573. }
  574. void rtl92c_init_rdg_setting(struct ieee80211_hw *hw)
  575. {
  576. struct rtl_priv *rtlpriv = rtl_priv(hw);
  577. rtl_write_byte(rtlpriv, REG_RD_CTRL, 0xFF);
  578. rtl_write_word(rtlpriv, REG_RD_NAV_NXT, 0x200);
  579. rtl_write_byte(rtlpriv, REG_RD_RESP_PKT_TH, 0x05);
  580. }
  581. void rtl92c_init_retry_function(struct ieee80211_hw *hw)
  582. {
  583. u8 value8;
  584. struct rtl_priv *rtlpriv = rtl_priv(hw);
  585. value8 = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL);
  586. value8 |= EN_AMPDU_RTY_NEW;
  587. rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL, value8);
  588. /* Set ACK timeout */
  589. rtl_write_byte(rtlpriv, REG_ACKTO, 0x40);
  590. }
  591. void rtl92c_init_beacon_parameters(struct ieee80211_hw *hw,
  592. enum version_8192c version)
  593. {
  594. struct rtl_priv *rtlpriv = rtl_priv(hw);
  595. struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
  596. rtl_write_word(rtlpriv, REG_TBTT_PROHIBIT, 0x6404);/* ms */
  597. rtl_write_byte(rtlpriv, REG_DRVERLYINT, DRIVER_EARLY_INT_TIME);/*ms*/
  598. rtl_write_byte(rtlpriv, REG_BCNDMATIM, BCN_DMA_ATIME_INT_TIME);
  599. if (IS_NORMAL_CHIP(rtlhal->version))
  600. rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660F);
  601. else
  602. rtl_write_word(rtlpriv, REG_BCNTCFG, 0x66FF);
  603. }
  604. void rtl92c_disable_fast_edca(struct ieee80211_hw *hw)
  605. {
  606. struct rtl_priv *rtlpriv = rtl_priv(hw);
  607. rtl_write_word(rtlpriv, REG_FAST_EDCA_CTRL, 0);
  608. }
  609. void rtl92c_set_min_space(struct ieee80211_hw *hw, bool is2T)
  610. {
  611. struct rtl_priv *rtlpriv = rtl_priv(hw);
  612. u8 value = is2T ? MAX_MSS_DENSITY_2T : MAX_MSS_DENSITY_1T;
  613. rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, value);
  614. }
  615. u16 rtl92c_get_mgt_filter(struct ieee80211_hw *hw)
  616. {
  617. struct rtl_priv *rtlpriv = rtl_priv(hw);
  618. return rtl_read_word(rtlpriv, REG_RXFLTMAP0);
  619. }
  620. void rtl92c_set_mgt_filter(struct ieee80211_hw *hw, u16 filter)
  621. {
  622. struct rtl_priv *rtlpriv = rtl_priv(hw);
  623. rtl_write_word(rtlpriv, REG_RXFLTMAP0, filter);
  624. }
  625. u16 rtl92c_get_ctrl_filter(struct ieee80211_hw *hw)
  626. {
  627. struct rtl_priv *rtlpriv = rtl_priv(hw);
  628. return rtl_read_word(rtlpriv, REG_RXFLTMAP1);
  629. }
  630. void rtl92c_set_ctrl_filter(struct ieee80211_hw *hw, u16 filter)
  631. {
  632. struct rtl_priv *rtlpriv = rtl_priv(hw);
  633. rtl_write_word(rtlpriv, REG_RXFLTMAP1, filter);
  634. }
  635. u16 rtl92c_get_data_filter(struct ieee80211_hw *hw)
  636. {
  637. struct rtl_priv *rtlpriv = rtl_priv(hw);
  638. return rtl_read_word(rtlpriv, REG_RXFLTMAP2);
  639. }
  640. void rtl92c_set_data_filter(struct ieee80211_hw *hw, u16 filter)
  641. {
  642. struct rtl_priv *rtlpriv = rtl_priv(hw);
  643. rtl_write_word(rtlpriv, REG_RXFLTMAP2, filter);
  644. }
  645. /*==============================================================*/
  646. static u8 _rtl92c_query_rxpwrpercentage(char antpower)
  647. {
  648. if ((antpower <= -100) || (antpower >= 20))
  649. return 0;
  650. else if (antpower >= 0)
  651. return 100;
  652. else
  653. return 100 + antpower;
  654. }
  655. static u8 _rtl92c_evm_db_to_percentage(char value)
  656. {
  657. char ret_val;
  658. ret_val = value;
  659. if (ret_val >= 0)
  660. ret_val = 0;
  661. if (ret_val <= -33)
  662. ret_val = -33;
  663. ret_val = 0 - ret_val;
  664. ret_val *= 3;
  665. if (ret_val == 99)
  666. ret_val = 100;
  667. return ret_val;
  668. }
  669. static long _rtl92c_signal_scale_mapping(struct ieee80211_hw *hw,
  670. long currsig)
  671. {
  672. long retsig;
  673. if (currsig >= 61 && currsig <= 100)
  674. retsig = 90 + ((currsig - 60) / 4);
  675. else if (currsig >= 41 && currsig <= 60)
  676. retsig = 78 + ((currsig - 40) / 2);
  677. else if (currsig >= 31 && currsig <= 40)
  678. retsig = 66 + (currsig - 30);
  679. else if (currsig >= 21 && currsig <= 30)
  680. retsig = 54 + (currsig - 20);
  681. else if (currsig >= 5 && currsig <= 20)
  682. retsig = 42 + (((currsig - 5) * 2) / 3);
  683. else if (currsig == 4)
  684. retsig = 36;
  685. else if (currsig == 3)
  686. retsig = 27;
  687. else if (currsig == 2)
  688. retsig = 18;
  689. else if (currsig == 1)
  690. retsig = 9;
  691. else
  692. retsig = currsig;
  693. return retsig;
  694. }
  695. static void _rtl92c_query_rxphystatus(struct ieee80211_hw *hw,
  696. struct rtl_stats *pstats,
  697. struct rx_desc_92c *pdesc,
  698. struct rx_fwinfo_92c *p_drvinfo,
  699. bool packet_match_bssid,
  700. bool packet_toself,
  701. bool packet_beacon)
  702. {
  703. struct rtl_priv *rtlpriv = rtl_priv(hw);
  704. struct rtl_phy *rtlphy = &(rtlpriv->phy);
  705. struct phy_sts_cck_8192s_t *cck_buf;
  706. s8 rx_pwr_all = 0, rx_pwr[4];
  707. u8 rf_rx_num = 0, evm, pwdb_all;
  708. u8 i, max_spatial_stream;
  709. u32 rssi, total_rssi = 0;
  710. bool in_powersavemode = false;
  711. bool is_cck_rate;
  712. is_cck_rate = RX_HAL_IS_CCK_RATE(pdesc);
  713. pstats->packet_matchbssid = packet_match_bssid;
  714. pstats->packet_toself = packet_toself;
  715. pstats->is_cck = is_cck_rate;
  716. pstats->packet_beacon = packet_beacon;
  717. pstats->is_cck = is_cck_rate;
  718. pstats->RX_SIGQ[0] = -1;
  719. pstats->RX_SIGQ[1] = -1;
  720. if (is_cck_rate) {
  721. u8 report, cck_highpwr;
  722. cck_buf = (struct phy_sts_cck_8192s_t *)p_drvinfo;
  723. if (!in_powersavemode)
  724. cck_highpwr = rtlphy->cck_high_power;
  725. else
  726. cck_highpwr = false;
  727. if (!cck_highpwr) {
  728. u8 cck_agc_rpt = cck_buf->cck_agc_rpt;
  729. report = cck_buf->cck_agc_rpt & 0xc0;
  730. report = report >> 6;
  731. switch (report) {
  732. case 0x3:
  733. rx_pwr_all = -46 - (cck_agc_rpt & 0x3e);
  734. break;
  735. case 0x2:
  736. rx_pwr_all = -26 - (cck_agc_rpt & 0x3e);
  737. break;
  738. case 0x1:
  739. rx_pwr_all = -12 - (cck_agc_rpt & 0x3e);
  740. break;
  741. case 0x0:
  742. rx_pwr_all = 16 - (cck_agc_rpt & 0x3e);
  743. break;
  744. }
  745. } else {
  746. u8 cck_agc_rpt = cck_buf->cck_agc_rpt;
  747. report = p_drvinfo->cfosho[0] & 0x60;
  748. report = report >> 5;
  749. switch (report) {
  750. case 0x3:
  751. rx_pwr_all = -46 - ((cck_agc_rpt & 0x1f) << 1);
  752. break;
  753. case 0x2:
  754. rx_pwr_all = -26 - ((cck_agc_rpt & 0x1f) << 1);
  755. break;
  756. case 0x1:
  757. rx_pwr_all = -12 - ((cck_agc_rpt & 0x1f) << 1);
  758. break;
  759. case 0x0:
  760. rx_pwr_all = 16 - ((cck_agc_rpt & 0x1f) << 1);
  761. break;
  762. }
  763. }
  764. pwdb_all = _rtl92c_query_rxpwrpercentage(rx_pwr_all);
  765. pstats->rx_pwdb_all = pwdb_all;
  766. pstats->recvsignalpower = rx_pwr_all;
  767. if (packet_match_bssid) {
  768. u8 sq;
  769. if (pstats->rx_pwdb_all > 40)
  770. sq = 100;
  771. else {
  772. sq = cck_buf->sq_rpt;
  773. if (sq > 64)
  774. sq = 0;
  775. else if (sq < 20)
  776. sq = 100;
  777. else
  778. sq = ((64 - sq) * 100) / 44;
  779. }
  780. pstats->signalquality = sq;
  781. pstats->RX_SIGQ[0] = sq;
  782. pstats->RX_SIGQ[1] = -1;
  783. }
  784. } else {
  785. rtlpriv->dm.rfpath_rxenable[0] =
  786. rtlpriv->dm.rfpath_rxenable[1] = true;
  787. for (i = RF90_PATH_A; i < RF90_PATH_MAX; i++) {
  788. if (rtlpriv->dm.rfpath_rxenable[i])
  789. rf_rx_num++;
  790. rx_pwr[i] =
  791. ((p_drvinfo->gain_trsw[i] & 0x3f) * 2) - 110;
  792. rssi = _rtl92c_query_rxpwrpercentage(rx_pwr[i]);
  793. total_rssi += rssi;
  794. rtlpriv->stats.rx_snr_db[i] =
  795. (long)(p_drvinfo->rxsnr[i] / 2);
  796. if (packet_match_bssid)
  797. pstats->rx_mimo_signalstrength[i] = (u8) rssi;
  798. }
  799. rx_pwr_all = ((p_drvinfo->pwdb_all >> 1) & 0x7f) - 110;
  800. pwdb_all = _rtl92c_query_rxpwrpercentage(rx_pwr_all);
  801. pstats->rx_pwdb_all = pwdb_all;
  802. pstats->rxpower = rx_pwr_all;
  803. pstats->recvsignalpower = rx_pwr_all;
  804. if (GET_RX_DESC_RX_MCS(pdesc) &&
  805. GET_RX_DESC_RX_MCS(pdesc) >= DESC92_RATEMCS8 &&
  806. GET_RX_DESC_RX_MCS(pdesc) <= DESC92_RATEMCS15)
  807. max_spatial_stream = 2;
  808. else
  809. max_spatial_stream = 1;
  810. for (i = 0; i < max_spatial_stream; i++) {
  811. evm = _rtl92c_evm_db_to_percentage(p_drvinfo->rxevm[i]);
  812. if (packet_match_bssid) {
  813. if (i == 0)
  814. pstats->signalquality =
  815. (u8) (evm & 0xff);
  816. pstats->RX_SIGQ[i] =
  817. (u8) (evm & 0xff);
  818. }
  819. }
  820. }
  821. if (is_cck_rate)
  822. pstats->signalstrength =
  823. (u8) (_rtl92c_signal_scale_mapping(hw, pwdb_all));
  824. else if (rf_rx_num != 0)
  825. pstats->signalstrength =
  826. (u8) (_rtl92c_signal_scale_mapping
  827. (hw, total_rssi /= rf_rx_num));
  828. }
  829. void rtl92c_translate_rx_signal_stuff(struct ieee80211_hw *hw,
  830. struct sk_buff *skb,
  831. struct rtl_stats *pstats,
  832. struct rx_desc_92c *pdesc,
  833. struct rx_fwinfo_92c *p_drvinfo)
  834. {
  835. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  836. struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
  837. struct ieee80211_hdr *hdr;
  838. u8 *tmp_buf;
  839. u8 *praddr;
  840. __le16 fc;
  841. u16 type, cpu_fc;
  842. bool packet_matchbssid, packet_toself, packet_beacon = false;
  843. tmp_buf = skb->data + pstats->rx_drvinfo_size + pstats->rx_bufshift;
  844. hdr = (struct ieee80211_hdr *)tmp_buf;
  845. fc = hdr->frame_control;
  846. cpu_fc = le16_to_cpu(fc);
  847. type = WLAN_FC_GET_TYPE(fc);
  848. praddr = hdr->addr1;
  849. packet_matchbssid =
  850. ((IEEE80211_FTYPE_CTL != type) &&
  851. ether_addr_equal(mac->bssid,
  852. (cpu_fc & IEEE80211_FCTL_TODS) ? hdr->addr1 :
  853. (cpu_fc & IEEE80211_FCTL_FROMDS) ? hdr->addr2 :
  854. hdr->addr3) &&
  855. (!pstats->hwerror) && (!pstats->crc) && (!pstats->icv));
  856. packet_toself = packet_matchbssid &&
  857. ether_addr_equal(praddr, rtlefuse->dev_addr);
  858. if (ieee80211_is_beacon(fc))
  859. packet_beacon = true;
  860. _rtl92c_query_rxphystatus(hw, pstats, pdesc, p_drvinfo,
  861. packet_matchbssid, packet_toself,
  862. packet_beacon);
  863. rtl_process_phyinfo(hw, tmp_buf, pstats);
  864. }