dm_common.c 50 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2009-2012 Realtek Corporation.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of version 2 of the GNU General Public License as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc.,
  16. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17. *
  18. * The full GNU General Public License is included in this distribution in the
  19. * file called LICENSE.
  20. *
  21. * Contact Information:
  22. * wlanfae <wlanfae@realtek.com>
  23. * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24. * Hsinchu 300, Taiwan.
  25. *
  26. * Larry Finger <Larry.Finger@lwfinger.net>
  27. *
  28. *****************************************************************************/
  29. #include <linux/export.h>
  30. #include "dm_common.h"
  31. #include "phy_common.h"
  32. #include "../pci.h"
  33. #include "../base.h"
  34. #define BT_RSSI_STATE_NORMAL_POWER BIT_OFFSET_LEN_MASK_32(0, 1)
  35. #define BT_RSSI_STATE_AMDPU_OFF BIT_OFFSET_LEN_MASK_32(1, 1)
  36. #define BT_RSSI_STATE_SPECIAL_LOW BIT_OFFSET_LEN_MASK_32(2, 1)
  37. #define BT_RSSI_STATE_BG_EDCA_LOW BIT_OFFSET_LEN_MASK_32(3, 1)
  38. #define BT_RSSI_STATE_TXPOWER_LOW BIT_OFFSET_LEN_MASK_32(4, 1)
  39. #define RTLPRIV (struct rtl_priv *)
  40. #define GET_UNDECORATED_AVERAGE_RSSI(_priv) \
  41. ((RTLPRIV(_priv))->mac80211.opmode == \
  42. NL80211_IFTYPE_ADHOC) ? \
  43. ((RTLPRIV(_priv))->dm.entry_min_undec_sm_pwdb) : \
  44. ((RTLPRIV(_priv))->dm.undec_sm_pwdb)
  45. static const u32 ofdmswing_table[OFDM_TABLE_SIZE] = {
  46. 0x7f8001fe,
  47. 0x788001e2,
  48. 0x71c001c7,
  49. 0x6b8001ae,
  50. 0x65400195,
  51. 0x5fc0017f,
  52. 0x5a400169,
  53. 0x55400155,
  54. 0x50800142,
  55. 0x4c000130,
  56. 0x47c0011f,
  57. 0x43c0010f,
  58. 0x40000100,
  59. 0x3c8000f2,
  60. 0x390000e4,
  61. 0x35c000d7,
  62. 0x32c000cb,
  63. 0x300000c0,
  64. 0x2d4000b5,
  65. 0x2ac000ab,
  66. 0x288000a2,
  67. 0x26000098,
  68. 0x24000090,
  69. 0x22000088,
  70. 0x20000080,
  71. 0x1e400079,
  72. 0x1c800072,
  73. 0x1b00006c,
  74. 0x19800066,
  75. 0x18000060,
  76. 0x16c0005b,
  77. 0x15800056,
  78. 0x14400051,
  79. 0x1300004c,
  80. 0x12000048,
  81. 0x11000044,
  82. 0x10000040,
  83. };
  84. static const u8 cckswing_table_ch1ch13[CCK_TABLE_SIZE][8] = {
  85. {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04},
  86. {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04},
  87. {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03},
  88. {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03},
  89. {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03},
  90. {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03},
  91. {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03},
  92. {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03},
  93. {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02},
  94. {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02},
  95. {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02},
  96. {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02},
  97. {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02},
  98. {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02},
  99. {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02},
  100. {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02},
  101. {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01},
  102. {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02},
  103. {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01},
  104. {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},
  105. {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},
  106. {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01},
  107. {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01},
  108. {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01},
  109. {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01},
  110. {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01},
  111. {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01},
  112. {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01},
  113. {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01},
  114. {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01},
  115. {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01},
  116. {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},
  117. {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}
  118. };
  119. static const u8 cckswing_table_ch14[CCK_TABLE_SIZE][8] = {
  120. {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00},
  121. {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00},
  122. {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00},
  123. {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00},
  124. {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00},
  125. {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00},
  126. {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00},
  127. {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00},
  128. {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00},
  129. {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00},
  130. {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00},
  131. {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00},
  132. {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00},
  133. {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00},
  134. {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00},
  135. {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00},
  136. {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00},
  137. {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00},
  138. {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00},
  139. {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},
  140. {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},
  141. {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00},
  142. {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00},
  143. {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},
  144. {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},
  145. {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00},
  146. {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},
  147. {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},
  148. {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},
  149. {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},
  150. {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},
  151. {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},
  152. {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}
  153. };
  154. static void rtl92c_dm_diginit(struct ieee80211_hw *hw)
  155. {
  156. struct rtl_priv *rtlpriv = rtl_priv(hw);
  157. struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
  158. dm_digtable->dig_enable_flag = true;
  159. dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
  160. dm_digtable->cur_igvalue = 0x20;
  161. dm_digtable->pre_igvalue = 0x0;
  162. dm_digtable->cursta_cstate = DIG_STA_DISCONNECT;
  163. dm_digtable->presta_cstate = DIG_STA_DISCONNECT;
  164. dm_digtable->curmultista_cstate = DIG_MULTISTA_DISCONNECT;
  165. dm_digtable->rssi_lowthresh = DM_DIG_THRESH_LOW;
  166. dm_digtable->rssi_highthresh = DM_DIG_THRESH_HIGH;
  167. dm_digtable->fa_lowthresh = DM_FALSEALARM_THRESH_LOW;
  168. dm_digtable->fa_highthresh = DM_FALSEALARM_THRESH_HIGH;
  169. dm_digtable->rx_gain_max = DM_DIG_MAX;
  170. dm_digtable->rx_gain_min = DM_DIG_MIN;
  171. dm_digtable->back_val = DM_DIG_BACKOFF_DEFAULT;
  172. dm_digtable->back_range_max = DM_DIG_BACKOFF_MAX;
  173. dm_digtable->back_range_min = DM_DIG_BACKOFF_MIN;
  174. dm_digtable->pre_cck_pd_state = CCK_PD_STAGE_MAX;
  175. dm_digtable->cur_cck_pd_state = CCK_PD_STAGE_MAX;
  176. }
  177. static u8 rtl92c_dm_initial_gain_min_pwdb(struct ieee80211_hw *hw)
  178. {
  179. struct rtl_priv *rtlpriv = rtl_priv(hw);
  180. struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
  181. long rssi_val_min = 0;
  182. if ((dm_digtable->curmultista_cstate == DIG_MULTISTA_CONNECT) &&
  183. (dm_digtable->cursta_cstate == DIG_STA_CONNECT)) {
  184. if (rtlpriv->dm.entry_min_undec_sm_pwdb != 0)
  185. rssi_val_min =
  186. (rtlpriv->dm.entry_min_undec_sm_pwdb >
  187. rtlpriv->dm.undec_sm_pwdb) ?
  188. rtlpriv->dm.undec_sm_pwdb :
  189. rtlpriv->dm.entry_min_undec_sm_pwdb;
  190. else
  191. rssi_val_min = rtlpriv->dm.undec_sm_pwdb;
  192. } else if (dm_digtable->cursta_cstate == DIG_STA_CONNECT ||
  193. dm_digtable->cursta_cstate == DIG_STA_BEFORE_CONNECT) {
  194. rssi_val_min = rtlpriv->dm.undec_sm_pwdb;
  195. } else if (dm_digtable->curmultista_cstate == DIG_MULTISTA_CONNECT) {
  196. rssi_val_min = rtlpriv->dm.entry_min_undec_sm_pwdb;
  197. }
  198. return (u8) rssi_val_min;
  199. }
  200. static void rtl92c_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw)
  201. {
  202. u32 ret_value;
  203. struct rtl_priv *rtlpriv = rtl_priv(hw);
  204. struct false_alarm_statistics *falsealm_cnt = &(rtlpriv->falsealm_cnt);
  205. ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER1, MASKDWORD);
  206. falsealm_cnt->cnt_parity_fail = ((ret_value & 0xffff0000) >> 16);
  207. ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER2, MASKDWORD);
  208. falsealm_cnt->cnt_rate_illegal = (ret_value & 0xffff);
  209. falsealm_cnt->cnt_crc8_fail = ((ret_value & 0xffff0000) >> 16);
  210. ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER3, MASKDWORD);
  211. falsealm_cnt->cnt_mcs_fail = (ret_value & 0xffff);
  212. falsealm_cnt->cnt_ofdm_fail = falsealm_cnt->cnt_parity_fail +
  213. falsealm_cnt->cnt_rate_illegal +
  214. falsealm_cnt->cnt_crc8_fail + falsealm_cnt->cnt_mcs_fail;
  215. rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, BIT(14), 1);
  216. ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERLOWER, MASKBYTE0);
  217. falsealm_cnt->cnt_cck_fail = ret_value;
  218. ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERUPPER, MASKBYTE3);
  219. falsealm_cnt->cnt_cck_fail += (ret_value & 0xff) << 8;
  220. falsealm_cnt->cnt_all = (falsealm_cnt->cnt_parity_fail +
  221. falsealm_cnt->cnt_rate_illegal +
  222. falsealm_cnt->cnt_crc8_fail +
  223. falsealm_cnt->cnt_mcs_fail +
  224. falsealm_cnt->cnt_cck_fail);
  225. rtl_set_bbreg(hw, ROFDM1_LSTF, 0x08000000, 1);
  226. rtl_set_bbreg(hw, ROFDM1_LSTF, 0x08000000, 0);
  227. rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, 0x0000c000, 0);
  228. rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, 0x0000c000, 2);
  229. RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
  230. "cnt_parity_fail = %d, cnt_rate_illegal = %d, cnt_crc8_fail = %d, cnt_mcs_fail = %d\n",
  231. falsealm_cnt->cnt_parity_fail,
  232. falsealm_cnt->cnt_rate_illegal,
  233. falsealm_cnt->cnt_crc8_fail, falsealm_cnt->cnt_mcs_fail);
  234. RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
  235. "cnt_ofdm_fail = %x, cnt_cck_fail = %x, cnt_all = %x\n",
  236. falsealm_cnt->cnt_ofdm_fail,
  237. falsealm_cnt->cnt_cck_fail, falsealm_cnt->cnt_all);
  238. }
  239. static void rtl92c_dm_ctrl_initgain_by_fa(struct ieee80211_hw *hw)
  240. {
  241. struct rtl_priv *rtlpriv = rtl_priv(hw);
  242. struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
  243. u8 value_igi = dm_digtable->cur_igvalue;
  244. if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH0)
  245. value_igi--;
  246. else if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH1)
  247. value_igi += 0;
  248. else if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH2)
  249. value_igi++;
  250. else if (rtlpriv->falsealm_cnt.cnt_all >= DM_DIG_FA_TH2)
  251. value_igi += 2;
  252. if (value_igi > DM_DIG_FA_UPPER)
  253. value_igi = DM_DIG_FA_UPPER;
  254. else if (value_igi < DM_DIG_FA_LOWER)
  255. value_igi = DM_DIG_FA_LOWER;
  256. if (rtlpriv->falsealm_cnt.cnt_all > 10000)
  257. value_igi = 0x32;
  258. dm_digtable->cur_igvalue = value_igi;
  259. rtl92c_dm_write_dig(hw);
  260. }
  261. static void rtl92c_dm_ctrl_initgain_by_rssi(struct ieee80211_hw *hw)
  262. {
  263. struct rtl_priv *rtlpriv = rtl_priv(hw);
  264. struct dig_t *digtable = &rtlpriv->dm_digtable;
  265. if (rtlpriv->falsealm_cnt.cnt_all > digtable->fa_highthresh) {
  266. if ((digtable->back_val - 2) < digtable->back_range_min)
  267. digtable->back_val = digtable->back_range_min;
  268. else
  269. digtable->back_val -= 2;
  270. } else if (rtlpriv->falsealm_cnt.cnt_all < digtable->fa_lowthresh) {
  271. if ((digtable->back_val + 2) > digtable->back_range_max)
  272. digtable->back_val = digtable->back_range_max;
  273. else
  274. digtable->back_val += 2;
  275. }
  276. if ((digtable->rssi_val_min + 10 - digtable->back_val) >
  277. digtable->rx_gain_max)
  278. digtable->cur_igvalue = digtable->rx_gain_max;
  279. else if ((digtable->rssi_val_min + 10 -
  280. digtable->back_val) < digtable->rx_gain_min)
  281. digtable->cur_igvalue = digtable->rx_gain_min;
  282. else
  283. digtable->cur_igvalue = digtable->rssi_val_min + 10 -
  284. digtable->back_val;
  285. RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
  286. "rssi_val_min = %x back_val %x\n",
  287. digtable->rssi_val_min, digtable->back_val);
  288. rtl92c_dm_write_dig(hw);
  289. }
  290. static void rtl92c_dm_initial_gain_multi_sta(struct ieee80211_hw *hw)
  291. {
  292. static u8 initialized; /* initialized to false */
  293. struct rtl_priv *rtlpriv = rtl_priv(hw);
  294. struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
  295. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  296. long rssi_strength = rtlpriv->dm.entry_min_undec_sm_pwdb;
  297. bool multi_sta = false;
  298. if (mac->opmode == NL80211_IFTYPE_ADHOC)
  299. multi_sta = true;
  300. if (!multi_sta ||
  301. dm_digtable->cursta_cstate != DIG_STA_DISCONNECT) {
  302. initialized = false;
  303. dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
  304. return;
  305. } else if (initialized == false) {
  306. initialized = true;
  307. dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_0;
  308. dm_digtable->cur_igvalue = 0x20;
  309. rtl92c_dm_write_dig(hw);
  310. }
  311. if (dm_digtable->curmultista_cstate == DIG_MULTISTA_CONNECT) {
  312. if ((rssi_strength < dm_digtable->rssi_lowthresh) &&
  313. (dm_digtable->dig_ext_port_stage != DIG_EXT_PORT_STAGE_1)) {
  314. if (dm_digtable->dig_ext_port_stage ==
  315. DIG_EXT_PORT_STAGE_2) {
  316. dm_digtable->cur_igvalue = 0x20;
  317. rtl92c_dm_write_dig(hw);
  318. }
  319. dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_1;
  320. } else if (rssi_strength > dm_digtable->rssi_highthresh) {
  321. dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_2;
  322. rtl92c_dm_ctrl_initgain_by_fa(hw);
  323. }
  324. } else if (dm_digtable->dig_ext_port_stage != DIG_EXT_PORT_STAGE_0) {
  325. dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_0;
  326. dm_digtable->cur_igvalue = 0x20;
  327. rtl92c_dm_write_dig(hw);
  328. }
  329. RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
  330. "curmultista_cstate = %x dig_ext_port_stage %x\n",
  331. dm_digtable->curmultista_cstate,
  332. dm_digtable->dig_ext_port_stage);
  333. }
  334. static void rtl92c_dm_initial_gain_sta(struct ieee80211_hw *hw)
  335. {
  336. struct rtl_priv *rtlpriv = rtl_priv(hw);
  337. struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
  338. RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
  339. "presta_cstate = %x, cursta_cstate = %x\n",
  340. dm_digtable->presta_cstate, dm_digtable->cursta_cstate);
  341. if (dm_digtable->presta_cstate == dm_digtable->cursta_cstate ||
  342. dm_digtable->cursta_cstate == DIG_STA_BEFORE_CONNECT ||
  343. dm_digtable->cursta_cstate == DIG_STA_CONNECT) {
  344. if (dm_digtable->cursta_cstate != DIG_STA_DISCONNECT) {
  345. dm_digtable->rssi_val_min =
  346. rtl92c_dm_initial_gain_min_pwdb(hw);
  347. rtl92c_dm_ctrl_initgain_by_rssi(hw);
  348. }
  349. } else {
  350. dm_digtable->rssi_val_min = 0;
  351. dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
  352. dm_digtable->back_val = DM_DIG_BACKOFF_DEFAULT;
  353. dm_digtable->cur_igvalue = 0x20;
  354. dm_digtable->pre_igvalue = 0;
  355. rtl92c_dm_write_dig(hw);
  356. }
  357. }
  358. static void rtl92c_dm_cck_packet_detection_thresh(struct ieee80211_hw *hw)
  359. {
  360. struct rtl_priv *rtlpriv = rtl_priv(hw);
  361. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  362. struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
  363. if (dm_digtable->cursta_cstate == DIG_STA_CONNECT) {
  364. dm_digtable->rssi_val_min = rtl92c_dm_initial_gain_min_pwdb(hw);
  365. if (dm_digtable->pre_cck_pd_state == CCK_PD_STAGE_LowRssi) {
  366. if (dm_digtable->rssi_val_min <= 25)
  367. dm_digtable->cur_cck_pd_state =
  368. CCK_PD_STAGE_LowRssi;
  369. else
  370. dm_digtable->cur_cck_pd_state =
  371. CCK_PD_STAGE_HighRssi;
  372. } else {
  373. if (dm_digtable->rssi_val_min <= 20)
  374. dm_digtable->cur_cck_pd_state =
  375. CCK_PD_STAGE_LowRssi;
  376. else
  377. dm_digtable->cur_cck_pd_state =
  378. CCK_PD_STAGE_HighRssi;
  379. }
  380. } else {
  381. dm_digtable->cur_cck_pd_state = CCK_PD_STAGE_MAX;
  382. }
  383. if (dm_digtable->pre_cck_pd_state != dm_digtable->cur_cck_pd_state) {
  384. if (dm_digtable->cur_cck_pd_state == CCK_PD_STAGE_LowRssi) {
  385. if (rtlpriv->falsealm_cnt.cnt_cck_fail > 800)
  386. dm_digtable->cur_cck_fa_state =
  387. CCK_FA_STAGE_High;
  388. else
  389. dm_digtable->cur_cck_fa_state = CCK_FA_STAGE_Low;
  390. if (dm_digtable->pre_cck_fa_state !=
  391. dm_digtable->cur_cck_fa_state) {
  392. if (dm_digtable->cur_cck_fa_state ==
  393. CCK_FA_STAGE_Low)
  394. rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2,
  395. 0x83);
  396. else
  397. rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2,
  398. 0xcd);
  399. dm_digtable->pre_cck_fa_state =
  400. dm_digtable->cur_cck_fa_state;
  401. }
  402. rtl_set_bbreg(hw, RCCK0_SYSTEM, MASKBYTE1, 0x40);
  403. if (IS_92C_SERIAL(rtlhal->version))
  404. rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT,
  405. MASKBYTE2, 0xd7);
  406. } else {
  407. rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0xcd);
  408. rtl_set_bbreg(hw, RCCK0_SYSTEM, MASKBYTE1, 0x47);
  409. if (IS_92C_SERIAL(rtlhal->version))
  410. rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT,
  411. MASKBYTE2, 0xd3);
  412. }
  413. dm_digtable->pre_cck_pd_state = dm_digtable->cur_cck_pd_state;
  414. }
  415. RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE, "CCKPDStage=%x\n",
  416. dm_digtable->cur_cck_pd_state);
  417. RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE, "is92C=%x\n",
  418. IS_92C_SERIAL(rtlhal->version));
  419. }
  420. static void rtl92c_dm_ctrl_initgain_by_twoport(struct ieee80211_hw *hw)
  421. {
  422. struct rtl_priv *rtlpriv = rtl_priv(hw);
  423. struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
  424. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  425. if (mac->act_scanning)
  426. return;
  427. if (mac->link_state >= MAC80211_LINKED)
  428. dm_digtable->cursta_cstate = DIG_STA_CONNECT;
  429. else
  430. dm_digtable->cursta_cstate = DIG_STA_DISCONNECT;
  431. rtl92c_dm_initial_gain_sta(hw);
  432. rtl92c_dm_initial_gain_multi_sta(hw);
  433. rtl92c_dm_cck_packet_detection_thresh(hw);
  434. dm_digtable->presta_cstate = dm_digtable->cursta_cstate;
  435. }
  436. static void rtl92c_dm_dig(struct ieee80211_hw *hw)
  437. {
  438. struct rtl_priv *rtlpriv = rtl_priv(hw);
  439. struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
  440. if (rtlpriv->dm.dm_initialgain_enable == false)
  441. return;
  442. if (dm_digtable->dig_enable_flag == false)
  443. return;
  444. rtl92c_dm_ctrl_initgain_by_twoport(hw);
  445. }
  446. static void rtl92c_dm_init_dynamic_txpower(struct ieee80211_hw *hw)
  447. {
  448. struct rtl_priv *rtlpriv = rtl_priv(hw);
  449. rtlpriv->dm.dynamic_txpower_enable = false;
  450. rtlpriv->dm.last_dtp_lvl = TXHIGHPWRLEVEL_NORMAL;
  451. rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
  452. }
  453. void rtl92c_dm_write_dig(struct ieee80211_hw *hw)
  454. {
  455. struct rtl_priv *rtlpriv = rtl_priv(hw);
  456. struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
  457. RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
  458. "cur_igvalue = 0x%x, pre_igvalue = 0x%x, back_val = %d\n",
  459. dm_digtable->cur_igvalue, dm_digtable->pre_igvalue,
  460. dm_digtable->back_val);
  461. dm_digtable->cur_igvalue += 2;
  462. if (dm_digtable->cur_igvalue > 0x3f)
  463. dm_digtable->cur_igvalue = 0x3f;
  464. if (dm_digtable->pre_igvalue != dm_digtable->cur_igvalue) {
  465. rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, 0x7f,
  466. dm_digtable->cur_igvalue);
  467. rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, 0x7f,
  468. dm_digtable->cur_igvalue);
  469. dm_digtable->pre_igvalue = dm_digtable->cur_igvalue;
  470. }
  471. }
  472. EXPORT_SYMBOL(rtl92c_dm_write_dig);
  473. static void rtl92c_dm_pwdb_monitor(struct ieee80211_hw *hw)
  474. {
  475. }
  476. void rtl92c_dm_init_edca_turbo(struct ieee80211_hw *hw)
  477. {
  478. struct rtl_priv *rtlpriv = rtl_priv(hw);
  479. rtlpriv->dm.current_turbo_edca = false;
  480. rtlpriv->dm.is_any_nonbepkts = false;
  481. rtlpriv->dm.is_cur_rdlstate = false;
  482. }
  483. EXPORT_SYMBOL(rtl92c_dm_init_edca_turbo);
  484. static void rtl92c_dm_check_edca_turbo(struct ieee80211_hw *hw)
  485. {
  486. struct rtl_priv *rtlpriv = rtl_priv(hw);
  487. struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
  488. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  489. static u64 last_txok_cnt;
  490. static u64 last_rxok_cnt;
  491. static u32 last_bt_edca_ul;
  492. static u32 last_bt_edca_dl;
  493. u64 cur_txok_cnt = 0;
  494. u64 cur_rxok_cnt = 0;
  495. u32 edca_be_ul = 0x5ea42b;
  496. u32 edca_be_dl = 0x5ea42b;
  497. bool bt_change_edca = false;
  498. if ((last_bt_edca_ul != rtlpcipriv->bt_coexist.bt_edca_ul) ||
  499. (last_bt_edca_dl != rtlpcipriv->bt_coexist.bt_edca_dl)) {
  500. rtlpriv->dm.current_turbo_edca = false;
  501. last_bt_edca_ul = rtlpcipriv->bt_coexist.bt_edca_ul;
  502. last_bt_edca_dl = rtlpcipriv->bt_coexist.bt_edca_dl;
  503. }
  504. if (rtlpcipriv->bt_coexist.bt_edca_ul != 0) {
  505. edca_be_ul = rtlpcipriv->bt_coexist.bt_edca_ul;
  506. bt_change_edca = true;
  507. }
  508. if (rtlpcipriv->bt_coexist.bt_edca_dl != 0) {
  509. edca_be_ul = rtlpcipriv->bt_coexist.bt_edca_dl;
  510. bt_change_edca = true;
  511. }
  512. if (mac->link_state != MAC80211_LINKED) {
  513. rtlpriv->dm.current_turbo_edca = false;
  514. return;
  515. }
  516. if ((!mac->ht_enable) && (!rtlpcipriv->bt_coexist.bt_coexistence)) {
  517. if (!(edca_be_ul & 0xffff0000))
  518. edca_be_ul |= 0x005e0000;
  519. if (!(edca_be_dl & 0xffff0000))
  520. edca_be_dl |= 0x005e0000;
  521. }
  522. if ((bt_change_edca) || ((!rtlpriv->dm.is_any_nonbepkts) &&
  523. (!rtlpriv->dm.disable_framebursting))) {
  524. cur_txok_cnt = rtlpriv->stats.txbytesunicast - last_txok_cnt;
  525. cur_rxok_cnt = rtlpriv->stats.rxbytesunicast - last_rxok_cnt;
  526. if (cur_rxok_cnt > 4 * cur_txok_cnt) {
  527. if (!rtlpriv->dm.is_cur_rdlstate ||
  528. !rtlpriv->dm.current_turbo_edca) {
  529. rtl_write_dword(rtlpriv,
  530. REG_EDCA_BE_PARAM,
  531. edca_be_dl);
  532. rtlpriv->dm.is_cur_rdlstate = true;
  533. }
  534. } else {
  535. if (rtlpriv->dm.is_cur_rdlstate ||
  536. !rtlpriv->dm.current_turbo_edca) {
  537. rtl_write_dword(rtlpriv,
  538. REG_EDCA_BE_PARAM,
  539. edca_be_ul);
  540. rtlpriv->dm.is_cur_rdlstate = false;
  541. }
  542. }
  543. rtlpriv->dm.current_turbo_edca = true;
  544. } else {
  545. if (rtlpriv->dm.current_turbo_edca) {
  546. u8 tmp = AC0_BE;
  547. rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM,
  548. &tmp);
  549. rtlpriv->dm.current_turbo_edca = false;
  550. }
  551. }
  552. rtlpriv->dm.is_any_nonbepkts = false;
  553. last_txok_cnt = rtlpriv->stats.txbytesunicast;
  554. last_rxok_cnt = rtlpriv->stats.rxbytesunicast;
  555. }
  556. static void rtl92c_dm_txpower_tracking_callback_thermalmeter(struct ieee80211_hw
  557. *hw)
  558. {
  559. struct rtl_priv *rtlpriv = rtl_priv(hw);
  560. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  561. struct rtl_phy *rtlphy = &(rtlpriv->phy);
  562. struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
  563. u8 thermalvalue, delta, delta_lck, delta_iqk;
  564. long ele_a, ele_d, temp_cck, val_x, value32;
  565. long val_y, ele_c = 0;
  566. u8 ofdm_index[2], ofdm_index_old[2] = {0, 0}, cck_index_old = 0;
  567. s8 cck_index = 0;
  568. int i;
  569. bool is2t = IS_92C_SERIAL(rtlhal->version);
  570. s8 txpwr_level[3] = {0, 0, 0};
  571. u8 ofdm_min_index = 6, rf;
  572. rtlpriv->dm.txpower_trackinginit = true;
  573. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  574. "rtl92c_dm_txpower_tracking_callback_thermalmeter\n");
  575. thermalvalue = (u8) rtl_get_rfreg(hw, RF90_PATH_A, RF_T_METER, 0x1f);
  576. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  577. "Readback Thermal Meter = 0x%x pre thermal meter 0x%x eeprom_thermalmeter 0x%x\n",
  578. thermalvalue, rtlpriv->dm.thermalvalue,
  579. rtlefuse->eeprom_thermalmeter);
  580. rtl92c_phy_ap_calibrate(hw, (thermalvalue -
  581. rtlefuse->eeprom_thermalmeter));
  582. if (is2t)
  583. rf = 2;
  584. else
  585. rf = 1;
  586. if (thermalvalue) {
  587. ele_d = rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
  588. MASKDWORD) & MASKOFDM_D;
  589. for (i = 0; i < OFDM_TABLE_LENGTH; i++) {
  590. if (ele_d == (ofdmswing_table[i] & MASKOFDM_D)) {
  591. ofdm_index_old[0] = (u8) i;
  592. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  593. "Initial pathA ele_d reg0x%x = 0x%lx, ofdm_index=0x%x\n",
  594. ROFDM0_XATXIQIMBALANCE,
  595. ele_d, ofdm_index_old[0]);
  596. break;
  597. }
  598. }
  599. if (is2t) {
  600. ele_d = rtl_get_bbreg(hw, ROFDM0_XBTXIQIMBALANCE,
  601. MASKDWORD) & MASKOFDM_D;
  602. for (i = 0; i < OFDM_TABLE_LENGTH; i++) {
  603. if (ele_d == (ofdmswing_table[i] &
  604. MASKOFDM_D)) {
  605. ofdm_index_old[1] = (u8) i;
  606. RT_TRACE(rtlpriv, COMP_POWER_TRACKING,
  607. DBG_LOUD,
  608. "Initial pathB ele_d reg0x%x = 0x%lx, ofdm_index=0x%x\n",
  609. ROFDM0_XBTXIQIMBALANCE, ele_d,
  610. ofdm_index_old[1]);
  611. break;
  612. }
  613. }
  614. }
  615. temp_cck =
  616. rtl_get_bbreg(hw, RCCK0_TXFILTER2, MASKDWORD) & MASKCCK;
  617. for (i = 0; i < CCK_TABLE_LENGTH; i++) {
  618. if (rtlpriv->dm.cck_inch14) {
  619. if (memcmp((void *)&temp_cck,
  620. (void *)&cckswing_table_ch14[i][2],
  621. 4) == 0) {
  622. cck_index_old = (u8) i;
  623. RT_TRACE(rtlpriv, COMP_POWER_TRACKING,
  624. DBG_LOUD,
  625. "Initial reg0x%x = 0x%lx, cck_index=0x%x, ch 14 %d\n",
  626. RCCK0_TXFILTER2, temp_cck,
  627. cck_index_old,
  628. rtlpriv->dm.cck_inch14);
  629. break;
  630. }
  631. } else {
  632. if (memcmp((void *)&temp_cck,
  633. (void *)
  634. &cckswing_table_ch1ch13[i][2],
  635. 4) == 0) {
  636. cck_index_old = (u8) i;
  637. RT_TRACE(rtlpriv, COMP_POWER_TRACKING,
  638. DBG_LOUD,
  639. "Initial reg0x%x = 0x%lx, cck_index=0x%x, ch14 %d\n",
  640. RCCK0_TXFILTER2, temp_cck,
  641. cck_index_old,
  642. rtlpriv->dm.cck_inch14);
  643. break;
  644. }
  645. }
  646. }
  647. if (!rtlpriv->dm.thermalvalue) {
  648. rtlpriv->dm.thermalvalue =
  649. rtlefuse->eeprom_thermalmeter;
  650. rtlpriv->dm.thermalvalue_lck = thermalvalue;
  651. rtlpriv->dm.thermalvalue_iqk = thermalvalue;
  652. for (i = 0; i < rf; i++)
  653. rtlpriv->dm.ofdm_index[i] = ofdm_index_old[i];
  654. rtlpriv->dm.cck_index = cck_index_old;
  655. }
  656. delta = (thermalvalue > rtlpriv->dm.thermalvalue) ?
  657. (thermalvalue - rtlpriv->dm.thermalvalue) :
  658. (rtlpriv->dm.thermalvalue - thermalvalue);
  659. delta_lck = (thermalvalue > rtlpriv->dm.thermalvalue_lck) ?
  660. (thermalvalue - rtlpriv->dm.thermalvalue_lck) :
  661. (rtlpriv->dm.thermalvalue_lck - thermalvalue);
  662. delta_iqk = (thermalvalue > rtlpriv->dm.thermalvalue_iqk) ?
  663. (thermalvalue - rtlpriv->dm.thermalvalue_iqk) :
  664. (rtlpriv->dm.thermalvalue_iqk - thermalvalue);
  665. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  666. "Readback Thermal Meter = 0x%x pre thermal meter 0x%x eeprom_thermalmeter 0x%x delta 0x%x delta_lck 0x%x delta_iqk 0x%x\n",
  667. thermalvalue, rtlpriv->dm.thermalvalue,
  668. rtlefuse->eeprom_thermalmeter, delta, delta_lck,
  669. delta_iqk);
  670. if (delta_lck > 1) {
  671. rtlpriv->dm.thermalvalue_lck = thermalvalue;
  672. rtl92c_phy_lc_calibrate(hw);
  673. }
  674. if (delta > 0 && rtlpriv->dm.txpower_track_control) {
  675. if (thermalvalue > rtlpriv->dm.thermalvalue) {
  676. for (i = 0; i < rf; i++)
  677. rtlpriv->dm.ofdm_index[i] -= delta;
  678. rtlpriv->dm.cck_index -= delta;
  679. } else {
  680. for (i = 0; i < rf; i++)
  681. rtlpriv->dm.ofdm_index[i] += delta;
  682. rtlpriv->dm.cck_index += delta;
  683. }
  684. if (is2t) {
  685. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  686. "temp OFDM_A_index=0x%x, OFDM_B_index=0x%x, cck_index=0x%x\n",
  687. rtlpriv->dm.ofdm_index[0],
  688. rtlpriv->dm.ofdm_index[1],
  689. rtlpriv->dm.cck_index);
  690. } else {
  691. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  692. "temp OFDM_A_index=0x%x, cck_index=0x%x\n",
  693. rtlpriv->dm.ofdm_index[0],
  694. rtlpriv->dm.cck_index);
  695. }
  696. if (thermalvalue > rtlefuse->eeprom_thermalmeter) {
  697. for (i = 0; i < rf; i++)
  698. ofdm_index[i] =
  699. rtlpriv->dm.ofdm_index[i]
  700. + 1;
  701. cck_index = rtlpriv->dm.cck_index + 1;
  702. } else {
  703. for (i = 0; i < rf; i++)
  704. ofdm_index[i] =
  705. rtlpriv->dm.ofdm_index[i];
  706. cck_index = rtlpriv->dm.cck_index;
  707. }
  708. for (i = 0; i < rf; i++) {
  709. if (txpwr_level[i] >= 0 &&
  710. txpwr_level[i] <= 26) {
  711. if (thermalvalue >
  712. rtlefuse->eeprom_thermalmeter) {
  713. if (delta < 5)
  714. ofdm_index[i] -= 1;
  715. else
  716. ofdm_index[i] -= 2;
  717. } else if (delta > 5 && thermalvalue <
  718. rtlefuse->
  719. eeprom_thermalmeter) {
  720. ofdm_index[i] += 1;
  721. }
  722. } else if (txpwr_level[i] >= 27 &&
  723. txpwr_level[i] <= 32
  724. && thermalvalue >
  725. rtlefuse->eeprom_thermalmeter) {
  726. if (delta < 5)
  727. ofdm_index[i] -= 1;
  728. else
  729. ofdm_index[i] -= 2;
  730. } else if (txpwr_level[i] >= 32 &&
  731. txpwr_level[i] <= 38 &&
  732. thermalvalue >
  733. rtlefuse->eeprom_thermalmeter
  734. && delta > 5) {
  735. ofdm_index[i] -= 1;
  736. }
  737. }
  738. if (txpwr_level[i] >= 0 && txpwr_level[i] <= 26) {
  739. if (thermalvalue >
  740. rtlefuse->eeprom_thermalmeter) {
  741. if (delta < 5)
  742. cck_index -= 1;
  743. else
  744. cck_index -= 2;
  745. } else if (delta > 5 && thermalvalue <
  746. rtlefuse->eeprom_thermalmeter) {
  747. cck_index += 1;
  748. }
  749. } else if (txpwr_level[i] >= 27 &&
  750. txpwr_level[i] <= 32 &&
  751. thermalvalue >
  752. rtlefuse->eeprom_thermalmeter) {
  753. if (delta < 5)
  754. cck_index -= 1;
  755. else
  756. cck_index -= 2;
  757. } else if (txpwr_level[i] >= 32 &&
  758. txpwr_level[i] <= 38 &&
  759. thermalvalue > rtlefuse->eeprom_thermalmeter
  760. && delta > 5) {
  761. cck_index -= 1;
  762. }
  763. for (i = 0; i < rf; i++) {
  764. if (ofdm_index[i] > OFDM_TABLE_SIZE - 1)
  765. ofdm_index[i] = OFDM_TABLE_SIZE - 1;
  766. else if (ofdm_index[i] < ofdm_min_index)
  767. ofdm_index[i] = ofdm_min_index;
  768. }
  769. if (cck_index > CCK_TABLE_SIZE - 1)
  770. cck_index = CCK_TABLE_SIZE - 1;
  771. else if (cck_index < 0)
  772. cck_index = 0;
  773. if (is2t) {
  774. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  775. "new OFDM_A_index=0x%x, OFDM_B_index=0x%x, cck_index=0x%x\n",
  776. ofdm_index[0], ofdm_index[1],
  777. cck_index);
  778. } else {
  779. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  780. "new OFDM_A_index=0x%x, cck_index=0x%x\n",
  781. ofdm_index[0], cck_index);
  782. }
  783. }
  784. if (rtlpriv->dm.txpower_track_control && delta != 0) {
  785. ele_d =
  786. (ofdmswing_table[ofdm_index[0]] & 0xFFC00000) >> 22;
  787. val_x = rtlphy->reg_e94;
  788. val_y = rtlphy->reg_e9c;
  789. if (val_x != 0) {
  790. if ((val_x & 0x00000200) != 0)
  791. val_x = val_x | 0xFFFFFC00;
  792. ele_a = ((val_x * ele_d) >> 8) & 0x000003FF;
  793. if ((val_y & 0x00000200) != 0)
  794. val_y = val_y | 0xFFFFFC00;
  795. ele_c = ((val_y * ele_d) >> 8) & 0x000003FF;
  796. value32 = (ele_d << 22) |
  797. ((ele_c & 0x3F) << 16) | ele_a;
  798. rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
  799. MASKDWORD, value32);
  800. value32 = (ele_c & 0x000003C0) >> 6;
  801. rtl_set_bbreg(hw, ROFDM0_XCTXAFE, MASKH4BITS,
  802. value32);
  803. value32 = ((val_x * ele_d) >> 7) & 0x01;
  804. rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
  805. BIT(31), value32);
  806. value32 = ((val_y * ele_d) >> 7) & 0x01;
  807. rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
  808. BIT(29), value32);
  809. } else {
  810. rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
  811. MASKDWORD,
  812. ofdmswing_table[ofdm_index[0]]);
  813. rtl_set_bbreg(hw, ROFDM0_XCTXAFE, MASKH4BITS,
  814. 0x00);
  815. rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
  816. BIT(31) | BIT(29), 0x00);
  817. }
  818. if (!rtlpriv->dm.cck_inch14) {
  819. rtl_write_byte(rtlpriv, 0xa22,
  820. cckswing_table_ch1ch13[cck_index]
  821. [0]);
  822. rtl_write_byte(rtlpriv, 0xa23,
  823. cckswing_table_ch1ch13[cck_index]
  824. [1]);
  825. rtl_write_byte(rtlpriv, 0xa24,
  826. cckswing_table_ch1ch13[cck_index]
  827. [2]);
  828. rtl_write_byte(rtlpriv, 0xa25,
  829. cckswing_table_ch1ch13[cck_index]
  830. [3]);
  831. rtl_write_byte(rtlpriv, 0xa26,
  832. cckswing_table_ch1ch13[cck_index]
  833. [4]);
  834. rtl_write_byte(rtlpriv, 0xa27,
  835. cckswing_table_ch1ch13[cck_index]
  836. [5]);
  837. rtl_write_byte(rtlpriv, 0xa28,
  838. cckswing_table_ch1ch13[cck_index]
  839. [6]);
  840. rtl_write_byte(rtlpriv, 0xa29,
  841. cckswing_table_ch1ch13[cck_index]
  842. [7]);
  843. } else {
  844. rtl_write_byte(rtlpriv, 0xa22,
  845. cckswing_table_ch14[cck_index]
  846. [0]);
  847. rtl_write_byte(rtlpriv, 0xa23,
  848. cckswing_table_ch14[cck_index]
  849. [1]);
  850. rtl_write_byte(rtlpriv, 0xa24,
  851. cckswing_table_ch14[cck_index]
  852. [2]);
  853. rtl_write_byte(rtlpriv, 0xa25,
  854. cckswing_table_ch14[cck_index]
  855. [3]);
  856. rtl_write_byte(rtlpriv, 0xa26,
  857. cckswing_table_ch14[cck_index]
  858. [4]);
  859. rtl_write_byte(rtlpriv, 0xa27,
  860. cckswing_table_ch14[cck_index]
  861. [5]);
  862. rtl_write_byte(rtlpriv, 0xa28,
  863. cckswing_table_ch14[cck_index]
  864. [6]);
  865. rtl_write_byte(rtlpriv, 0xa29,
  866. cckswing_table_ch14[cck_index]
  867. [7]);
  868. }
  869. if (is2t) {
  870. ele_d = (ofdmswing_table[ofdm_index[1]] &
  871. 0xFFC00000) >> 22;
  872. val_x = rtlphy->reg_eb4;
  873. val_y = rtlphy->reg_ebc;
  874. if (val_x != 0) {
  875. if ((val_x & 0x00000200) != 0)
  876. val_x = val_x | 0xFFFFFC00;
  877. ele_a = ((val_x * ele_d) >> 8) &
  878. 0x000003FF;
  879. if ((val_y & 0x00000200) != 0)
  880. val_y = val_y | 0xFFFFFC00;
  881. ele_c = ((val_y * ele_d) >> 8) &
  882. 0x00003FF;
  883. value32 = (ele_d << 22) |
  884. ((ele_c & 0x3F) << 16) | ele_a;
  885. rtl_set_bbreg(hw,
  886. ROFDM0_XBTXIQIMBALANCE,
  887. MASKDWORD, value32);
  888. value32 = (ele_c & 0x000003C0) >> 6;
  889. rtl_set_bbreg(hw, ROFDM0_XDTXAFE,
  890. MASKH4BITS, value32);
  891. value32 = ((val_x * ele_d) >> 7) & 0x01;
  892. rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
  893. BIT(27), value32);
  894. value32 = ((val_y * ele_d) >> 7) & 0x01;
  895. rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
  896. BIT(25), value32);
  897. } else {
  898. rtl_set_bbreg(hw,
  899. ROFDM0_XBTXIQIMBALANCE,
  900. MASKDWORD,
  901. ofdmswing_table[ofdm_index
  902. [1]]);
  903. rtl_set_bbreg(hw, ROFDM0_XDTXAFE,
  904. MASKH4BITS, 0x00);
  905. rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
  906. BIT(27) | BIT(25), 0x00);
  907. }
  908. }
  909. }
  910. if (delta_iqk > 3) {
  911. rtlpriv->dm.thermalvalue_iqk = thermalvalue;
  912. rtl92c_phy_iq_calibrate(hw, false);
  913. }
  914. if (rtlpriv->dm.txpower_track_control)
  915. rtlpriv->dm.thermalvalue = thermalvalue;
  916. }
  917. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, "<===\n");
  918. }
  919. static void rtl92c_dm_initialize_txpower_tracking_thermalmeter(
  920. struct ieee80211_hw *hw)
  921. {
  922. struct rtl_priv *rtlpriv = rtl_priv(hw);
  923. rtlpriv->dm.txpower_tracking = true;
  924. rtlpriv->dm.txpower_trackinginit = false;
  925. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  926. "pMgntInfo->txpower_tracking = %d\n",
  927. rtlpriv->dm.txpower_tracking);
  928. }
  929. static void rtl92c_dm_initialize_txpower_tracking(struct ieee80211_hw *hw)
  930. {
  931. rtl92c_dm_initialize_txpower_tracking_thermalmeter(hw);
  932. }
  933. static void rtl92c_dm_txpower_tracking_directcall(struct ieee80211_hw *hw)
  934. {
  935. rtl92c_dm_txpower_tracking_callback_thermalmeter(hw);
  936. }
  937. static void rtl92c_dm_check_txpower_tracking_thermal_meter(
  938. struct ieee80211_hw *hw)
  939. {
  940. struct rtl_priv *rtlpriv = rtl_priv(hw);
  941. static u8 tm_trigger;
  942. if (!rtlpriv->dm.txpower_tracking)
  943. return;
  944. if (!tm_trigger) {
  945. rtl_set_rfreg(hw, RF90_PATH_A, RF_T_METER, RFREG_OFFSET_MASK,
  946. 0x60);
  947. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  948. "Trigger 92S Thermal Meter!!\n");
  949. tm_trigger = 1;
  950. return;
  951. } else {
  952. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  953. "Schedule TxPowerTracking direct call!!\n");
  954. rtl92c_dm_txpower_tracking_directcall(hw);
  955. tm_trigger = 0;
  956. }
  957. }
  958. void rtl92c_dm_check_txpower_tracking(struct ieee80211_hw *hw)
  959. {
  960. rtl92c_dm_check_txpower_tracking_thermal_meter(hw);
  961. }
  962. EXPORT_SYMBOL(rtl92c_dm_check_txpower_tracking);
  963. void rtl92c_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw)
  964. {
  965. struct rtl_priv *rtlpriv = rtl_priv(hw);
  966. struct rate_adaptive *p_ra = &(rtlpriv->ra);
  967. p_ra->ratr_state = DM_RATR_STA_INIT;
  968. p_ra->pre_ratr_state = DM_RATR_STA_INIT;
  969. if (rtlpriv->dm.dm_type == DM_TYPE_BYDRIVER)
  970. rtlpriv->dm.useramask = true;
  971. else
  972. rtlpriv->dm.useramask = false;
  973. }
  974. EXPORT_SYMBOL(rtl92c_dm_init_rate_adaptive_mask);
  975. static void rtl92c_dm_init_dynamic_bb_powersaving(struct ieee80211_hw *hw)
  976. {
  977. struct rtl_priv *rtlpriv = rtl_priv(hw);
  978. struct ps_t *dm_pstable = &rtlpriv->dm_pstable;
  979. dm_pstable->pre_ccastate = CCA_MAX;
  980. dm_pstable->cur_ccasate = CCA_MAX;
  981. dm_pstable->pre_rfstate = RF_MAX;
  982. dm_pstable->cur_rfstate = RF_MAX;
  983. dm_pstable->rssi_val_min = 0;
  984. }
  985. void rtl92c_dm_rf_saving(struct ieee80211_hw *hw, u8 bforce_in_normal)
  986. {
  987. struct rtl_priv *rtlpriv = rtl_priv(hw);
  988. struct ps_t *dm_pstable = &rtlpriv->dm_pstable;
  989. static u8 initialize;
  990. static u32 reg_874, reg_c70, reg_85c, reg_a74;
  991. if (initialize == 0) {
  992. reg_874 = (rtl_get_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
  993. MASKDWORD) & 0x1CC000) >> 14;
  994. reg_c70 = (rtl_get_bbreg(hw, ROFDM0_AGCPARAMETER1,
  995. MASKDWORD) & BIT(3)) >> 3;
  996. reg_85c = (rtl_get_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL,
  997. MASKDWORD) & 0xFF000000) >> 24;
  998. reg_a74 = (rtl_get_bbreg(hw, 0xa74, MASKDWORD) & 0xF000) >> 12;
  999. initialize = 1;
  1000. }
  1001. if (!bforce_in_normal) {
  1002. if (dm_pstable->rssi_val_min != 0) {
  1003. if (dm_pstable->pre_rfstate == RF_NORMAL) {
  1004. if (dm_pstable->rssi_val_min >= 30)
  1005. dm_pstable->cur_rfstate = RF_SAVE;
  1006. else
  1007. dm_pstable->cur_rfstate = RF_NORMAL;
  1008. } else {
  1009. if (dm_pstable->rssi_val_min <= 25)
  1010. dm_pstable->cur_rfstate = RF_NORMAL;
  1011. else
  1012. dm_pstable->cur_rfstate = RF_SAVE;
  1013. }
  1014. } else {
  1015. dm_pstable->cur_rfstate = RF_MAX;
  1016. }
  1017. } else {
  1018. dm_pstable->cur_rfstate = RF_NORMAL;
  1019. }
  1020. if (dm_pstable->pre_rfstate != dm_pstable->cur_rfstate) {
  1021. if (dm_pstable->cur_rfstate == RF_SAVE) {
  1022. rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
  1023. 0x1C0000, 0x2);
  1024. rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, BIT(3), 0);
  1025. rtl_set_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL,
  1026. 0xFF000000, 0x63);
  1027. rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
  1028. 0xC000, 0x2);
  1029. rtl_set_bbreg(hw, 0xa74, 0xF000, 0x3);
  1030. rtl_set_bbreg(hw, 0x818, BIT(28), 0x0);
  1031. rtl_set_bbreg(hw, 0x818, BIT(28), 0x1);
  1032. } else {
  1033. rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
  1034. 0x1CC000, reg_874);
  1035. rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, BIT(3),
  1036. reg_c70);
  1037. rtl_set_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL, 0xFF000000,
  1038. reg_85c);
  1039. rtl_set_bbreg(hw, 0xa74, 0xF000, reg_a74);
  1040. rtl_set_bbreg(hw, 0x818, BIT(28), 0x0);
  1041. }
  1042. dm_pstable->pre_rfstate = dm_pstable->cur_rfstate;
  1043. }
  1044. }
  1045. EXPORT_SYMBOL(rtl92c_dm_rf_saving);
  1046. static void rtl92c_dm_dynamic_bb_powersaving(struct ieee80211_hw *hw)
  1047. {
  1048. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1049. struct ps_t *dm_pstable = &rtlpriv->dm_pstable;
  1050. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  1051. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  1052. if (((mac->link_state == MAC80211_NOLINK)) &&
  1053. (rtlpriv->dm.entry_min_undec_sm_pwdb == 0)) {
  1054. dm_pstable->rssi_val_min = 0;
  1055. RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD, "Not connected to any\n");
  1056. }
  1057. if (mac->link_state == MAC80211_LINKED) {
  1058. if (mac->opmode == NL80211_IFTYPE_ADHOC) {
  1059. dm_pstable->rssi_val_min =
  1060. rtlpriv->dm.entry_min_undec_sm_pwdb;
  1061. RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD,
  1062. "AP Client PWDB = 0x%lx\n",
  1063. dm_pstable->rssi_val_min);
  1064. } else {
  1065. dm_pstable->rssi_val_min = rtlpriv->dm.undec_sm_pwdb;
  1066. RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD,
  1067. "STA Default Port PWDB = 0x%lx\n",
  1068. dm_pstable->rssi_val_min);
  1069. }
  1070. } else {
  1071. dm_pstable->rssi_val_min =
  1072. rtlpriv->dm.entry_min_undec_sm_pwdb;
  1073. RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD,
  1074. "AP Ext Port PWDB = 0x%lx\n",
  1075. dm_pstable->rssi_val_min);
  1076. }
  1077. if (IS_92C_SERIAL(rtlhal->version))
  1078. ;/* rtl92c_dm_1r_cca(hw); */
  1079. else
  1080. rtl92c_dm_rf_saving(hw, false);
  1081. }
  1082. void rtl92c_dm_init(struct ieee80211_hw *hw)
  1083. {
  1084. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1085. rtlpriv->dm.dm_type = DM_TYPE_BYDRIVER;
  1086. rtl92c_dm_diginit(hw);
  1087. rtl92c_dm_init_dynamic_txpower(hw);
  1088. rtl92c_dm_init_edca_turbo(hw);
  1089. rtl92c_dm_init_rate_adaptive_mask(hw);
  1090. rtl92c_dm_initialize_txpower_tracking(hw);
  1091. rtl92c_dm_init_dynamic_bb_powersaving(hw);
  1092. }
  1093. EXPORT_SYMBOL(rtl92c_dm_init);
  1094. void rtl92c_dm_dynamic_txpower(struct ieee80211_hw *hw)
  1095. {
  1096. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1097. struct rtl_phy *rtlphy = &(rtlpriv->phy);
  1098. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  1099. long undec_sm_pwdb;
  1100. if (!rtlpriv->dm.dynamic_txpower_enable)
  1101. return;
  1102. if (rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) {
  1103. rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
  1104. return;
  1105. }
  1106. if ((mac->link_state < MAC80211_LINKED) &&
  1107. (rtlpriv->dm.entry_min_undec_sm_pwdb == 0)) {
  1108. RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
  1109. "Not connected to any\n");
  1110. rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
  1111. rtlpriv->dm.last_dtp_lvl = TXHIGHPWRLEVEL_NORMAL;
  1112. return;
  1113. }
  1114. if (mac->link_state >= MAC80211_LINKED) {
  1115. if (mac->opmode == NL80211_IFTYPE_ADHOC) {
  1116. undec_sm_pwdb = rtlpriv->dm.entry_min_undec_sm_pwdb;
  1117. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
  1118. "AP Client PWDB = 0x%lx\n",
  1119. undec_sm_pwdb);
  1120. } else {
  1121. undec_sm_pwdb = rtlpriv->dm.undec_sm_pwdb;
  1122. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
  1123. "STA Default Port PWDB = 0x%lx\n",
  1124. undec_sm_pwdb);
  1125. }
  1126. } else {
  1127. undec_sm_pwdb = rtlpriv->dm.entry_min_undec_sm_pwdb;
  1128. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
  1129. "AP Ext Port PWDB = 0x%lx\n",
  1130. undec_sm_pwdb);
  1131. }
  1132. if (undec_sm_pwdb >= TX_POWER_NEAR_FIELD_THRESH_LVL2) {
  1133. rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_LEVEL1;
  1134. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
  1135. "TXHIGHPWRLEVEL_LEVEL1 (TxPwr=0x0)\n");
  1136. } else if ((undec_sm_pwdb < (TX_POWER_NEAR_FIELD_THRESH_LVL2 - 3)) &&
  1137. (undec_sm_pwdb >= TX_POWER_NEAR_FIELD_THRESH_LVL1)) {
  1138. rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_LEVEL1;
  1139. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
  1140. "TXHIGHPWRLEVEL_LEVEL1 (TxPwr=0x10)\n");
  1141. } else if (undec_sm_pwdb < (TX_POWER_NEAR_FIELD_THRESH_LVL1 - 5)) {
  1142. rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
  1143. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
  1144. "TXHIGHPWRLEVEL_NORMAL\n");
  1145. }
  1146. if ((rtlpriv->dm.dynamic_txhighpower_lvl != rtlpriv->dm.last_dtp_lvl)) {
  1147. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
  1148. "PHY_SetTxPowerLevel8192S() Channel = %d\n",
  1149. rtlphy->current_channel);
  1150. rtl92c_phy_set_txpower_level(hw, rtlphy->current_channel);
  1151. }
  1152. rtlpriv->dm.last_dtp_lvl = rtlpriv->dm.dynamic_txhighpower_lvl;
  1153. }
  1154. void rtl92c_dm_watchdog(struct ieee80211_hw *hw)
  1155. {
  1156. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1157. struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
  1158. bool fw_current_inpsmode = false;
  1159. bool fw_ps_awake = true;
  1160. rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
  1161. (u8 *) (&fw_current_inpsmode));
  1162. rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FWLPS_RF_ON,
  1163. (u8 *) (&fw_ps_awake));
  1164. if (ppsc->p2p_ps_info.p2p_ps_mode)
  1165. fw_ps_awake = false;
  1166. if ((ppsc->rfpwr_state == ERFON) && ((!fw_current_inpsmode) &&
  1167. fw_ps_awake)
  1168. && (!ppsc->rfchange_inprogress)) {
  1169. rtl92c_dm_pwdb_monitor(hw);
  1170. rtl92c_dm_dig(hw);
  1171. rtl92c_dm_false_alarm_counter_statistics(hw);
  1172. rtl92c_dm_dynamic_bb_powersaving(hw);
  1173. rtl92c_dm_dynamic_txpower(hw);
  1174. rtl92c_dm_check_txpower_tracking(hw);
  1175. /* rtl92c_dm_refresh_rate_adaptive_mask(hw); */
  1176. rtl92c_dm_bt_coexist(hw);
  1177. rtl92c_dm_check_edca_turbo(hw);
  1178. }
  1179. }
  1180. EXPORT_SYMBOL(rtl92c_dm_watchdog);
  1181. u8 rtl92c_bt_rssi_state_change(struct ieee80211_hw *hw)
  1182. {
  1183. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1184. struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
  1185. long undec_sm_pwdb;
  1186. u8 curr_bt_rssi_state = 0x00;
  1187. if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
  1188. undec_sm_pwdb = GET_UNDECORATED_AVERAGE_RSSI(rtlpriv);
  1189. } else {
  1190. if (rtlpriv->dm.entry_min_undec_sm_pwdb == 0)
  1191. undec_sm_pwdb = 100;
  1192. else
  1193. undec_sm_pwdb = rtlpriv->dm.entry_min_undec_sm_pwdb;
  1194. }
  1195. /* Check RSSI to determine HighPower/NormalPower state for
  1196. * BT coexistence. */
  1197. if (undec_sm_pwdb >= 67)
  1198. curr_bt_rssi_state &= (~BT_RSSI_STATE_NORMAL_POWER);
  1199. else if (undec_sm_pwdb < 62)
  1200. curr_bt_rssi_state |= BT_RSSI_STATE_NORMAL_POWER;
  1201. /* Check RSSI to determine AMPDU setting for BT coexistence. */
  1202. if (undec_sm_pwdb >= 40)
  1203. curr_bt_rssi_state &= (~BT_RSSI_STATE_AMDPU_OFF);
  1204. else if (undec_sm_pwdb <= 32)
  1205. curr_bt_rssi_state |= BT_RSSI_STATE_AMDPU_OFF;
  1206. /* Marked RSSI state. It will be used to determine BT coexistence
  1207. * setting later. */
  1208. if (undec_sm_pwdb < 35)
  1209. curr_bt_rssi_state |= BT_RSSI_STATE_SPECIAL_LOW;
  1210. else
  1211. curr_bt_rssi_state &= (~BT_RSSI_STATE_SPECIAL_LOW);
  1212. /* Set Tx Power according to BT status. */
  1213. if (undec_sm_pwdb >= 30)
  1214. curr_bt_rssi_state |= BT_RSSI_STATE_TXPOWER_LOW;
  1215. else if (undec_sm_pwdb < 25)
  1216. curr_bt_rssi_state &= (~BT_RSSI_STATE_TXPOWER_LOW);
  1217. /* Check BT state related to BT_Idle in B/G mode. */
  1218. if (undec_sm_pwdb < 15)
  1219. curr_bt_rssi_state |= BT_RSSI_STATE_BG_EDCA_LOW;
  1220. else
  1221. curr_bt_rssi_state &= (~BT_RSSI_STATE_BG_EDCA_LOW);
  1222. if (curr_bt_rssi_state != rtlpcipriv->bt_coexist.bt_rssi_state) {
  1223. rtlpcipriv->bt_coexist.bt_rssi_state = curr_bt_rssi_state;
  1224. return true;
  1225. } else {
  1226. return false;
  1227. }
  1228. }
  1229. EXPORT_SYMBOL(rtl92c_bt_rssi_state_change);
  1230. static bool rtl92c_bt_state_change(struct ieee80211_hw *hw)
  1231. {
  1232. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1233. struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
  1234. u32 polling, ratio_tx, ratio_pri;
  1235. u32 bt_tx, bt_pri;
  1236. u8 bt_state;
  1237. u8 cur_service_type;
  1238. if (rtlpriv->mac80211.link_state < MAC80211_LINKED)
  1239. return false;
  1240. bt_state = rtl_read_byte(rtlpriv, 0x4fd);
  1241. bt_tx = rtl_read_dword(rtlpriv, 0x488);
  1242. bt_tx = bt_tx & 0x00ffffff;
  1243. bt_pri = rtl_read_dword(rtlpriv, 0x48c);
  1244. bt_pri = bt_pri & 0x00ffffff;
  1245. polling = rtl_read_dword(rtlpriv, 0x490);
  1246. if (bt_tx == 0xffffffff && bt_pri == 0xffffffff &&
  1247. polling == 0xffffffff && bt_state == 0xff)
  1248. return false;
  1249. bt_state &= BIT_OFFSET_LEN_MASK_32(0, 1);
  1250. if (bt_state != rtlpcipriv->bt_coexist.bt_cur_state) {
  1251. rtlpcipriv->bt_coexist.bt_cur_state = bt_state;
  1252. if (rtlpcipriv->bt_coexist.reg_bt_sco == 3) {
  1253. rtlpcipriv->bt_coexist.bt_service = BT_IDLE;
  1254. bt_state = bt_state |
  1255. ((rtlpcipriv->bt_coexist.bt_ant_isolation == 1) ?
  1256. 0 : BIT_OFFSET_LEN_MASK_32(1, 1)) |
  1257. BIT_OFFSET_LEN_MASK_32(2, 1);
  1258. rtl_write_byte(rtlpriv, 0x4fd, bt_state);
  1259. }
  1260. return true;
  1261. }
  1262. ratio_tx = bt_tx * 1000 / polling;
  1263. ratio_pri = bt_pri * 1000 / polling;
  1264. rtlpcipriv->bt_coexist.ratio_tx = ratio_tx;
  1265. rtlpcipriv->bt_coexist.ratio_pri = ratio_pri;
  1266. if (bt_state && rtlpcipriv->bt_coexist.reg_bt_sco == 3) {
  1267. if ((ratio_tx < 30) && (ratio_pri < 30))
  1268. cur_service_type = BT_IDLE;
  1269. else if ((ratio_pri > 110) && (ratio_pri < 250))
  1270. cur_service_type = BT_SCO;
  1271. else if ((ratio_tx >= 200) && (ratio_pri >= 200))
  1272. cur_service_type = BT_BUSY;
  1273. else if ((ratio_tx >= 350) && (ratio_tx < 500))
  1274. cur_service_type = BT_OTHERBUSY;
  1275. else if (ratio_tx >= 500)
  1276. cur_service_type = BT_PAN;
  1277. else
  1278. cur_service_type = BT_OTHER_ACTION;
  1279. if (cur_service_type != rtlpcipriv->bt_coexist.bt_service) {
  1280. rtlpcipriv->bt_coexist.bt_service = cur_service_type;
  1281. bt_state = bt_state |
  1282. ((rtlpcipriv->bt_coexist.bt_ant_isolation == 1) ?
  1283. 0 : BIT_OFFSET_LEN_MASK_32(1, 1)) |
  1284. ((rtlpcipriv->bt_coexist.bt_service != BT_IDLE) ?
  1285. 0 : BIT_OFFSET_LEN_MASK_32(2, 1));
  1286. /* Add interrupt migration when bt is not ini
  1287. * idle state (no traffic). */
  1288. if (rtlpcipriv->bt_coexist.bt_service != BT_IDLE) {
  1289. rtl_write_word(rtlpriv, 0x504, 0x0ccc);
  1290. rtl_write_byte(rtlpriv, 0x506, 0x54);
  1291. rtl_write_byte(rtlpriv, 0x507, 0x54);
  1292. } else {
  1293. rtl_write_byte(rtlpriv, 0x506, 0x00);
  1294. rtl_write_byte(rtlpriv, 0x507, 0x00);
  1295. }
  1296. rtl_write_byte(rtlpriv, 0x4fd, bt_state);
  1297. return true;
  1298. }
  1299. }
  1300. return false;
  1301. }
  1302. static bool rtl92c_bt_wifi_connect_change(struct ieee80211_hw *hw)
  1303. {
  1304. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1305. static bool media_connect;
  1306. if (rtlpriv->mac80211.link_state < MAC80211_LINKED) {
  1307. media_connect = false;
  1308. } else {
  1309. if (!media_connect) {
  1310. media_connect = true;
  1311. return true;
  1312. }
  1313. media_connect = true;
  1314. }
  1315. return false;
  1316. }
  1317. static void rtl92c_bt_set_normal(struct ieee80211_hw *hw)
  1318. {
  1319. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1320. struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
  1321. if (rtlpcipriv->bt_coexist.bt_service == BT_OTHERBUSY) {
  1322. rtlpcipriv->bt_coexist.bt_edca_ul = 0x5ea72b;
  1323. rtlpcipriv->bt_coexist.bt_edca_dl = 0x5ea72b;
  1324. } else if (rtlpcipriv->bt_coexist.bt_service == BT_BUSY) {
  1325. rtlpcipriv->bt_coexist.bt_edca_ul = 0x5eb82f;
  1326. rtlpcipriv->bt_coexist.bt_edca_dl = 0x5eb82f;
  1327. } else if (rtlpcipriv->bt_coexist.bt_service == BT_SCO) {
  1328. if (rtlpcipriv->bt_coexist.ratio_tx > 160) {
  1329. rtlpcipriv->bt_coexist.bt_edca_ul = 0x5ea72f;
  1330. rtlpcipriv->bt_coexist.bt_edca_dl = 0x5ea72f;
  1331. } else {
  1332. rtlpcipriv->bt_coexist.bt_edca_ul = 0x5ea32b;
  1333. rtlpcipriv->bt_coexist.bt_edca_dl = 0x5ea42b;
  1334. }
  1335. } else {
  1336. rtlpcipriv->bt_coexist.bt_edca_ul = 0;
  1337. rtlpcipriv->bt_coexist.bt_edca_dl = 0;
  1338. }
  1339. if ((rtlpcipriv->bt_coexist.bt_service != BT_IDLE) &&
  1340. (rtlpriv->mac80211.mode == WIRELESS_MODE_G ||
  1341. (rtlpriv->mac80211.mode == (WIRELESS_MODE_G | WIRELESS_MODE_B))) &&
  1342. (rtlpcipriv->bt_coexist.bt_rssi_state &
  1343. BT_RSSI_STATE_BG_EDCA_LOW)) {
  1344. rtlpcipriv->bt_coexist.bt_edca_ul = 0x5eb82b;
  1345. rtlpcipriv->bt_coexist.bt_edca_dl = 0x5eb82b;
  1346. }
  1347. }
  1348. static void rtl92c_bt_ant_isolation(struct ieee80211_hw *hw, u8 tmp1byte)
  1349. {
  1350. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1351. struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
  1352. /* Only enable HW BT coexist when BT in "Busy" state. */
  1353. if (rtlpriv->mac80211.vendor == PEER_CISCO &&
  1354. rtlpcipriv->bt_coexist.bt_service == BT_OTHER_ACTION) {
  1355. rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0);
  1356. } else {
  1357. if ((rtlpcipriv->bt_coexist.bt_service == BT_BUSY) &&
  1358. (rtlpcipriv->bt_coexist.bt_rssi_state &
  1359. BT_RSSI_STATE_NORMAL_POWER)) {
  1360. rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0);
  1361. } else if ((rtlpcipriv->bt_coexist.bt_service ==
  1362. BT_OTHER_ACTION) && (rtlpriv->mac80211.mode <
  1363. WIRELESS_MODE_N_24G) &&
  1364. (rtlpcipriv->bt_coexist.bt_rssi_state &
  1365. BT_RSSI_STATE_SPECIAL_LOW)) {
  1366. rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0);
  1367. } else if (rtlpcipriv->bt_coexist.bt_service == BT_PAN) {
  1368. rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, tmp1byte);
  1369. } else {
  1370. rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, tmp1byte);
  1371. }
  1372. }
  1373. if (rtlpcipriv->bt_coexist.bt_service == BT_PAN)
  1374. rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x10100);
  1375. else
  1376. rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x0);
  1377. if (rtlpcipriv->bt_coexist.bt_rssi_state &
  1378. BT_RSSI_STATE_NORMAL_POWER) {
  1379. rtl92c_bt_set_normal(hw);
  1380. } else {
  1381. rtlpcipriv->bt_coexist.bt_edca_ul = 0;
  1382. rtlpcipriv->bt_coexist.bt_edca_dl = 0;
  1383. }
  1384. if (rtlpcipriv->bt_coexist.bt_service != BT_IDLE) {
  1385. rtlpriv->cfg->ops->set_rfreg(hw,
  1386. RF90_PATH_A,
  1387. 0x1e,
  1388. 0xf0, 0xf);
  1389. } else {
  1390. rtlpriv->cfg->ops->set_rfreg(hw,
  1391. RF90_PATH_A, 0x1e, 0xf0,
  1392. rtlpcipriv->bt_coexist.bt_rfreg_origin_1e);
  1393. }
  1394. if (!rtlpriv->dm.dynamic_txpower_enable) {
  1395. if (rtlpcipriv->bt_coexist.bt_service != BT_IDLE) {
  1396. if (rtlpcipriv->bt_coexist.bt_rssi_state &
  1397. BT_RSSI_STATE_TXPOWER_LOW) {
  1398. rtlpriv->dm.dynamic_txhighpower_lvl =
  1399. TXHIGHPWRLEVEL_BT2;
  1400. } else {
  1401. rtlpriv->dm.dynamic_txhighpower_lvl =
  1402. TXHIGHPWRLEVEL_BT1;
  1403. }
  1404. } else {
  1405. rtlpriv->dm.dynamic_txhighpower_lvl =
  1406. TXHIGHPWRLEVEL_NORMAL;
  1407. }
  1408. rtl92c_phy_set_txpower_level(hw,
  1409. rtlpriv->phy.current_channel);
  1410. }
  1411. }
  1412. static void rtl92c_check_bt_change(struct ieee80211_hw *hw)
  1413. {
  1414. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1415. struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
  1416. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  1417. u8 tmp1byte = 0;
  1418. if (IS_81xxC_VENDOR_UMC_B_CUT(rtlhal->version) &&
  1419. rtlpcipriv->bt_coexist.bt_coexistence)
  1420. tmp1byte |= BIT(5);
  1421. if (rtlpcipriv->bt_coexist.bt_cur_state) {
  1422. if (rtlpcipriv->bt_coexist.bt_ant_isolation)
  1423. rtl92c_bt_ant_isolation(hw, tmp1byte);
  1424. } else {
  1425. rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, tmp1byte);
  1426. rtlpriv->cfg->ops->set_rfreg(hw, RF90_PATH_A, 0x1e, 0xf0,
  1427. rtlpcipriv->bt_coexist.bt_rfreg_origin_1e);
  1428. rtlpcipriv->bt_coexist.bt_edca_ul = 0;
  1429. rtlpcipriv->bt_coexist.bt_edca_dl = 0;
  1430. }
  1431. }
  1432. void rtl92c_dm_bt_coexist(struct ieee80211_hw *hw)
  1433. {
  1434. struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
  1435. bool wifi_connect_change;
  1436. bool bt_state_change;
  1437. bool rssi_state_change;
  1438. if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
  1439. (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4)) {
  1440. wifi_connect_change = rtl92c_bt_wifi_connect_change(hw);
  1441. bt_state_change = rtl92c_bt_state_change(hw);
  1442. rssi_state_change = rtl92c_bt_rssi_state_change(hw);
  1443. if (wifi_connect_change || bt_state_change || rssi_state_change)
  1444. rtl92c_check_bt_change(hw);
  1445. }
  1446. }
  1447. EXPORT_SYMBOL(rtl92c_dm_bt_coexist);