main.c 58 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914191519161917191819191920192119221923192419251926192719281929193019311932193319341935193619371938193919401941194219431944194519461947194819491950195119521953195419551956195719581959196019611962196319641965196619671968196919701971197219731974197519761977197819791980198119821983198419851986198719881989199019911992199319941995199619971998199920002001200220032004200520062007200820092010201120122013201420152016201720182019202020212022202320242025202620272028202920302031203220332034203520362037203820392040204120422043204420452046204720482049205020512052205320542055205620572058205920602061206220632064206520662067206820692070207120722073207420752076207720782079208020812082208320842085208620872088208920902091209220932094209520962097209820992100210121022103210421052106210721082109211021112112211321142115211621172118211921202121212221232124212521262127212821292130213121322133213421352136213721382139214021412142214321442145214621472148214921502151215221532154215521562157215821592160216121622163216421652166216721682169217021712172217321742175217621772178217921802181218221832184218521862187218821892190219121922193219421952196219721982199220022012202220322042205220622072208220922102211221222132214221522162217221822192220222122222223222422252226222722282229223022312232223322342235223622372238223922402241224222432244224522462247224822492250225122522253225422552256225722582259226022612262226322642265226622672268226922702271227222732274227522762277227822792280228122822283228422852286228722882289229022912292229322942295229622972298229923002301230223032304230523062307230823092310231123122313231423152316231723182319232023212322232323242325232623272328232923302331233223332334233523362337233823392340234123422343234423452346234723482349235023512352235323542355235623572358235923602361236223632364236523662367236823692370237123722373237423752376237723782379238023812382238323842385238623872388238923902391239223932394
  1. /*
  2. * Copyright (c) 2008-2011 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include <linux/nl80211.h>
  17. #include <linux/delay.h>
  18. #include "ath9k.h"
  19. #include "btcoex.h"
  20. static void ath9k_set_assoc_state(struct ath_softc *sc,
  21. struct ieee80211_vif *vif);
  22. u8 ath9k_parse_mpdudensity(u8 mpdudensity)
  23. {
  24. /*
  25. * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
  26. * 0 for no restriction
  27. * 1 for 1/4 us
  28. * 2 for 1/2 us
  29. * 3 for 1 us
  30. * 4 for 2 us
  31. * 5 for 4 us
  32. * 6 for 8 us
  33. * 7 for 16 us
  34. */
  35. switch (mpdudensity) {
  36. case 0:
  37. return 0;
  38. case 1:
  39. case 2:
  40. case 3:
  41. /* Our lower layer calculations limit our precision to
  42. 1 microsecond */
  43. return 1;
  44. case 4:
  45. return 2;
  46. case 5:
  47. return 4;
  48. case 6:
  49. return 8;
  50. case 7:
  51. return 16;
  52. default:
  53. return 0;
  54. }
  55. }
  56. static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq)
  57. {
  58. bool pending = false;
  59. spin_lock_bh(&txq->axq_lock);
  60. if (txq->axq_depth || !list_empty(&txq->axq_acq))
  61. pending = true;
  62. spin_unlock_bh(&txq->axq_lock);
  63. return pending;
  64. }
  65. static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
  66. {
  67. unsigned long flags;
  68. bool ret;
  69. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  70. ret = ath9k_hw_setpower(sc->sc_ah, mode);
  71. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  72. return ret;
  73. }
  74. void ath9k_ps_wakeup(struct ath_softc *sc)
  75. {
  76. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  77. unsigned long flags;
  78. enum ath9k_power_mode power_mode;
  79. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  80. if (++sc->ps_usecount != 1)
  81. goto unlock;
  82. power_mode = sc->sc_ah->power_mode;
  83. ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
  84. /*
  85. * While the hardware is asleep, the cycle counters contain no
  86. * useful data. Better clear them now so that they don't mess up
  87. * survey data results.
  88. */
  89. if (power_mode != ATH9K_PM_AWAKE) {
  90. spin_lock(&common->cc_lock);
  91. ath_hw_cycle_counters_update(common);
  92. memset(&common->cc_survey, 0, sizeof(common->cc_survey));
  93. memset(&common->cc_ani, 0, sizeof(common->cc_ani));
  94. spin_unlock(&common->cc_lock);
  95. }
  96. unlock:
  97. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  98. }
  99. void ath9k_ps_restore(struct ath_softc *sc)
  100. {
  101. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  102. enum ath9k_power_mode mode;
  103. unsigned long flags;
  104. bool reset;
  105. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  106. if (--sc->ps_usecount != 0)
  107. goto unlock;
  108. if (sc->ps_idle) {
  109. ath9k_hw_setrxabort(sc->sc_ah, 1);
  110. ath9k_hw_stopdmarecv(sc->sc_ah, &reset);
  111. mode = ATH9K_PM_FULL_SLEEP;
  112. } else if (sc->ps_enabled &&
  113. !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
  114. PS_WAIT_FOR_CAB |
  115. PS_WAIT_FOR_PSPOLL_DATA |
  116. PS_WAIT_FOR_TX_ACK |
  117. PS_WAIT_FOR_ANI))) {
  118. mode = ATH9K_PM_NETWORK_SLEEP;
  119. if (ath9k_hw_btcoex_is_enabled(sc->sc_ah))
  120. ath9k_btcoex_stop_gen_timer(sc);
  121. } else {
  122. goto unlock;
  123. }
  124. spin_lock(&common->cc_lock);
  125. ath_hw_cycle_counters_update(common);
  126. spin_unlock(&common->cc_lock);
  127. ath9k_hw_setpower(sc->sc_ah, mode);
  128. unlock:
  129. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  130. }
  131. static void __ath_cancel_work(struct ath_softc *sc)
  132. {
  133. cancel_work_sync(&sc->paprd_work);
  134. cancel_work_sync(&sc->hw_check_work);
  135. cancel_delayed_work_sync(&sc->tx_complete_work);
  136. cancel_delayed_work_sync(&sc->hw_pll_work);
  137. #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
  138. if (ath9k_hw_mci_is_enabled(sc->sc_ah))
  139. cancel_work_sync(&sc->mci_work);
  140. #endif
  141. }
  142. static void ath_cancel_work(struct ath_softc *sc)
  143. {
  144. __ath_cancel_work(sc);
  145. cancel_work_sync(&sc->hw_reset_work);
  146. }
  147. static void ath_restart_work(struct ath_softc *sc)
  148. {
  149. ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
  150. if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9330(sc->sc_ah))
  151. ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work,
  152. msecs_to_jiffies(ATH_PLL_WORK_INTERVAL));
  153. ath_start_rx_poll(sc, 3);
  154. ath_start_ani(sc);
  155. }
  156. static bool ath_prepare_reset(struct ath_softc *sc)
  157. {
  158. struct ath_hw *ah = sc->sc_ah;
  159. bool ret = true;
  160. ieee80211_stop_queues(sc->hw);
  161. sc->hw_busy_count = 0;
  162. ath_stop_ani(sc);
  163. del_timer_sync(&sc->rx_poll_timer);
  164. ath9k_hw_disable_interrupts(ah);
  165. if (!ath_drain_all_txq(sc))
  166. ret = false;
  167. if (!ath_stoprecv(sc))
  168. ret = false;
  169. return ret;
  170. }
  171. static bool ath_complete_reset(struct ath_softc *sc, bool start)
  172. {
  173. struct ath_hw *ah = sc->sc_ah;
  174. struct ath_common *common = ath9k_hw_common(ah);
  175. unsigned long flags;
  176. int i;
  177. if (ath_startrecv(sc) != 0) {
  178. ath_err(common, "Unable to restart recv logic\n");
  179. return false;
  180. }
  181. ath9k_cmn_update_txpow(ah, sc->curtxpow,
  182. sc->config.txpowlimit, &sc->curtxpow);
  183. clear_bit(SC_OP_HW_RESET, &sc->sc_flags);
  184. ath9k_hw_set_interrupts(ah);
  185. ath9k_hw_enable_interrupts(ah);
  186. if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) && start) {
  187. if (!test_bit(SC_OP_BEACONS, &sc->sc_flags))
  188. goto work;
  189. if (ah->opmode == NL80211_IFTYPE_STATION &&
  190. test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
  191. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  192. sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
  193. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  194. } else {
  195. ath9k_set_beacon(sc);
  196. }
  197. work:
  198. ath_restart_work(sc);
  199. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  200. if (!ATH_TXQ_SETUP(sc, i))
  201. continue;
  202. spin_lock_bh(&sc->tx.txq[i].axq_lock);
  203. ath_txq_schedule(sc, &sc->tx.txq[i]);
  204. spin_unlock_bh(&sc->tx.txq[i].axq_lock);
  205. }
  206. }
  207. ieee80211_wake_queues(sc->hw);
  208. return true;
  209. }
  210. static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan)
  211. {
  212. struct ath_hw *ah = sc->sc_ah;
  213. struct ath_common *common = ath9k_hw_common(ah);
  214. struct ath9k_hw_cal_data *caldata = NULL;
  215. bool fastcc = true;
  216. int r;
  217. __ath_cancel_work(sc);
  218. tasklet_disable(&sc->intr_tq);
  219. spin_lock_bh(&sc->sc_pcu_lock);
  220. if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)) {
  221. fastcc = false;
  222. caldata = &sc->caldata;
  223. }
  224. if (!hchan) {
  225. fastcc = false;
  226. hchan = ah->curchan;
  227. }
  228. if (!ath_prepare_reset(sc))
  229. fastcc = false;
  230. ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n",
  231. hchan->channel, IS_CHAN_HT40(hchan), fastcc);
  232. r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
  233. if (r) {
  234. ath_err(common,
  235. "Unable to reset channel, reset status %d\n", r);
  236. ath9k_hw_enable_interrupts(ah);
  237. ath9k_queue_reset(sc, RESET_TYPE_BB_HANG);
  238. goto out;
  239. }
  240. if (ath9k_hw_mci_is_enabled(sc->sc_ah) &&
  241. (sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
  242. ath9k_mci_set_txpower(sc, true, false);
  243. if (!ath_complete_reset(sc, true))
  244. r = -EIO;
  245. out:
  246. spin_unlock_bh(&sc->sc_pcu_lock);
  247. tasklet_enable(&sc->intr_tq);
  248. return r;
  249. }
  250. /*
  251. * Set/change channels. If the channel is really being changed, it's done
  252. * by reseting the chip. To accomplish this we must first cleanup any pending
  253. * DMA, then restart stuff.
  254. */
  255. static int ath_set_channel(struct ath_softc *sc, struct cfg80211_chan_def *chandef)
  256. {
  257. struct ath_hw *ah = sc->sc_ah;
  258. struct ath_common *common = ath9k_hw_common(ah);
  259. struct ieee80211_hw *hw = sc->hw;
  260. struct ath9k_channel *hchan;
  261. struct ieee80211_channel *chan = chandef->chan;
  262. unsigned long flags;
  263. bool offchannel;
  264. int pos = chan->hw_value;
  265. int old_pos = -1;
  266. int r;
  267. if (test_bit(SC_OP_INVALID, &sc->sc_flags))
  268. return -EIO;
  269. offchannel = !!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL);
  270. if (ah->curchan)
  271. old_pos = ah->curchan - &ah->channels[0];
  272. ath_dbg(common, CONFIG, "Set channel: %d MHz width: %d\n",
  273. chan->center_freq, chandef->width);
  274. /* update survey stats for the old channel before switching */
  275. spin_lock_irqsave(&common->cc_lock, flags);
  276. ath_update_survey_stats(sc);
  277. spin_unlock_irqrestore(&common->cc_lock, flags);
  278. ath9k_cmn_get_channel(hw, ah, chandef);
  279. /*
  280. * If the operating channel changes, change the survey in-use flags
  281. * along with it.
  282. * Reset the survey data for the new channel, unless we're switching
  283. * back to the operating channel from an off-channel operation.
  284. */
  285. if (!offchannel && sc->cur_survey != &sc->survey[pos]) {
  286. if (sc->cur_survey)
  287. sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE;
  288. sc->cur_survey = &sc->survey[pos];
  289. memset(sc->cur_survey, 0, sizeof(struct survey_info));
  290. sc->cur_survey->filled |= SURVEY_INFO_IN_USE;
  291. } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) {
  292. memset(&sc->survey[pos], 0, sizeof(struct survey_info));
  293. }
  294. hchan = &sc->sc_ah->channels[pos];
  295. r = ath_reset_internal(sc, hchan);
  296. if (r)
  297. return r;
  298. /*
  299. * The most recent snapshot of channel->noisefloor for the old
  300. * channel is only available after the hardware reset. Copy it to
  301. * the survey stats now.
  302. */
  303. if (old_pos >= 0)
  304. ath_update_survey_nf(sc, old_pos);
  305. /*
  306. * Enable radar pulse detection if on a DFS channel. Spectral
  307. * scanning and radar detection can not be used concurrently.
  308. */
  309. if (hw->conf.radar_enabled) {
  310. u32 rxfilter;
  311. /* set HW specific DFS configuration */
  312. ath9k_hw_set_radar_params(ah);
  313. rxfilter = ath9k_hw_getrxfilter(ah);
  314. rxfilter |= ATH9K_RX_FILTER_PHYRADAR |
  315. ATH9K_RX_FILTER_PHYERR;
  316. ath9k_hw_setrxfilter(ah, rxfilter);
  317. ath_dbg(common, DFS, "DFS enabled at freq %d\n",
  318. chan->center_freq);
  319. } else {
  320. /* perform spectral scan if requested. */
  321. if (test_bit(SC_OP_SCANNING, &sc->sc_flags) &&
  322. sc->spectral_mode == SPECTRAL_CHANSCAN)
  323. ath9k_spectral_scan_trigger(hw);
  324. }
  325. return 0;
  326. }
  327. static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta,
  328. struct ieee80211_vif *vif)
  329. {
  330. struct ath_node *an;
  331. an = (struct ath_node *)sta->drv_priv;
  332. an->sc = sc;
  333. an->sta = sta;
  334. an->vif = vif;
  335. ath_tx_node_init(sc, an);
  336. if (sta->ht_cap.ht_supported) {
  337. an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
  338. sta->ht_cap.ampdu_factor);
  339. an->mpdudensity = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density);
  340. }
  341. }
  342. static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
  343. {
  344. struct ath_node *an = (struct ath_node *)sta->drv_priv;
  345. ath_tx_node_cleanup(sc, an);
  346. }
  347. void ath9k_tasklet(unsigned long data)
  348. {
  349. struct ath_softc *sc = (struct ath_softc *)data;
  350. struct ath_hw *ah = sc->sc_ah;
  351. struct ath_common *common = ath9k_hw_common(ah);
  352. enum ath_reset_type type;
  353. unsigned long flags;
  354. u32 status = sc->intrstatus;
  355. u32 rxmask;
  356. ath9k_ps_wakeup(sc);
  357. spin_lock(&sc->sc_pcu_lock);
  358. if ((status & ATH9K_INT_FATAL) ||
  359. (status & ATH9K_INT_BB_WATCHDOG)) {
  360. if (status & ATH9K_INT_FATAL)
  361. type = RESET_TYPE_FATAL_INT;
  362. else
  363. type = RESET_TYPE_BB_WATCHDOG;
  364. ath9k_queue_reset(sc, type);
  365. /*
  366. * Increment the ref. counter here so that
  367. * interrupts are enabled in the reset routine.
  368. */
  369. atomic_inc(&ah->intr_ref_cnt);
  370. ath_dbg(common, ANY, "FATAL: Skipping interrupts\n");
  371. goto out;
  372. }
  373. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  374. if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
  375. /*
  376. * TSF sync does not look correct; remain awake to sync with
  377. * the next Beacon.
  378. */
  379. ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n");
  380. sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
  381. }
  382. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  383. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  384. rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
  385. ATH9K_INT_RXORN);
  386. else
  387. rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
  388. if (status & rxmask) {
  389. /* Check for high priority Rx first */
  390. if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
  391. (status & ATH9K_INT_RXHP))
  392. ath_rx_tasklet(sc, 0, true);
  393. ath_rx_tasklet(sc, 0, false);
  394. }
  395. if (status & ATH9K_INT_TX) {
  396. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  397. ath_tx_edma_tasklet(sc);
  398. else
  399. ath_tx_tasklet(sc);
  400. }
  401. ath9k_btcoex_handle_interrupt(sc, status);
  402. /* re-enable hardware interrupt */
  403. ath9k_hw_enable_interrupts(ah);
  404. out:
  405. spin_unlock(&sc->sc_pcu_lock);
  406. ath9k_ps_restore(sc);
  407. }
  408. irqreturn_t ath_isr(int irq, void *dev)
  409. {
  410. #define SCHED_INTR ( \
  411. ATH9K_INT_FATAL | \
  412. ATH9K_INT_BB_WATCHDOG | \
  413. ATH9K_INT_RXORN | \
  414. ATH9K_INT_RXEOL | \
  415. ATH9K_INT_RX | \
  416. ATH9K_INT_RXLP | \
  417. ATH9K_INT_RXHP | \
  418. ATH9K_INT_TX | \
  419. ATH9K_INT_BMISS | \
  420. ATH9K_INT_CST | \
  421. ATH9K_INT_TSFOOR | \
  422. ATH9K_INT_GENTIMER | \
  423. ATH9K_INT_MCI)
  424. struct ath_softc *sc = dev;
  425. struct ath_hw *ah = sc->sc_ah;
  426. struct ath_common *common = ath9k_hw_common(ah);
  427. enum ath9k_int status;
  428. bool sched = false;
  429. /*
  430. * The hardware is not ready/present, don't
  431. * touch anything. Note this can happen early
  432. * on if the IRQ is shared.
  433. */
  434. if (test_bit(SC_OP_INVALID, &sc->sc_flags))
  435. return IRQ_NONE;
  436. /* shared irq, not for us */
  437. if (!ath9k_hw_intrpend(ah))
  438. return IRQ_NONE;
  439. if (test_bit(SC_OP_HW_RESET, &sc->sc_flags)) {
  440. ath9k_hw_kill_interrupts(ah);
  441. return IRQ_HANDLED;
  442. }
  443. /*
  444. * Figure out the reason(s) for the interrupt. Note
  445. * that the hal returns a pseudo-ISR that may include
  446. * bits we haven't explicitly enabled so we mask the
  447. * value to insure we only process bits we requested.
  448. */
  449. ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
  450. status &= ah->imask; /* discard unasked-for bits */
  451. /*
  452. * If there are no status bits set, then this interrupt was not
  453. * for me (should have been caught above).
  454. */
  455. if (!status)
  456. return IRQ_NONE;
  457. /* Cache the status */
  458. sc->intrstatus = status;
  459. if (status & SCHED_INTR)
  460. sched = true;
  461. /*
  462. * If a FATAL or RXORN interrupt is received, we have to reset the
  463. * chip immediately.
  464. */
  465. if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
  466. !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
  467. goto chip_reset;
  468. if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
  469. (status & ATH9K_INT_BB_WATCHDOG)) {
  470. spin_lock(&common->cc_lock);
  471. ath_hw_cycle_counters_update(common);
  472. ar9003_hw_bb_watchdog_dbg_info(ah);
  473. spin_unlock(&common->cc_lock);
  474. goto chip_reset;
  475. }
  476. #ifdef CONFIG_PM_SLEEP
  477. if (status & ATH9K_INT_BMISS) {
  478. if (atomic_read(&sc->wow_sleep_proc_intr) == 0) {
  479. ath_dbg(common, ANY, "during WoW we got a BMISS\n");
  480. atomic_inc(&sc->wow_got_bmiss_intr);
  481. atomic_dec(&sc->wow_sleep_proc_intr);
  482. }
  483. }
  484. #endif
  485. if (status & ATH9K_INT_SWBA)
  486. tasklet_schedule(&sc->bcon_tasklet);
  487. if (status & ATH9K_INT_TXURN)
  488. ath9k_hw_updatetxtriglevel(ah, true);
  489. if (status & ATH9K_INT_RXEOL) {
  490. ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
  491. ath9k_hw_set_interrupts(ah);
  492. }
  493. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
  494. if (status & ATH9K_INT_TIM_TIMER) {
  495. if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
  496. goto chip_reset;
  497. /* Clear RxAbort bit so that we can
  498. * receive frames */
  499. ath9k_setpower(sc, ATH9K_PM_AWAKE);
  500. spin_lock(&sc->sc_pm_lock);
  501. ath9k_hw_setrxabort(sc->sc_ah, 0);
  502. sc->ps_flags |= PS_WAIT_FOR_BEACON;
  503. spin_unlock(&sc->sc_pm_lock);
  504. }
  505. chip_reset:
  506. ath_debug_stat_interrupt(sc, status);
  507. if (sched) {
  508. /* turn off every interrupt */
  509. ath9k_hw_disable_interrupts(ah);
  510. tasklet_schedule(&sc->intr_tq);
  511. }
  512. return IRQ_HANDLED;
  513. #undef SCHED_INTR
  514. }
  515. static int ath_reset(struct ath_softc *sc)
  516. {
  517. int r;
  518. ath9k_ps_wakeup(sc);
  519. r = ath_reset_internal(sc, NULL);
  520. ath9k_ps_restore(sc);
  521. return r;
  522. }
  523. void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type)
  524. {
  525. #ifdef CONFIG_ATH9K_DEBUGFS
  526. RESET_STAT_INC(sc, type);
  527. #endif
  528. set_bit(SC_OP_HW_RESET, &sc->sc_flags);
  529. ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
  530. }
  531. void ath_reset_work(struct work_struct *work)
  532. {
  533. struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work);
  534. ath_reset(sc);
  535. }
  536. /**********************/
  537. /* mac80211 callbacks */
  538. /**********************/
  539. static int ath9k_start(struct ieee80211_hw *hw)
  540. {
  541. struct ath_softc *sc = hw->priv;
  542. struct ath_hw *ah = sc->sc_ah;
  543. struct ath_common *common = ath9k_hw_common(ah);
  544. struct ieee80211_channel *curchan = hw->conf.chandef.chan;
  545. struct ath9k_channel *init_channel;
  546. int r;
  547. ath_dbg(common, CONFIG,
  548. "Starting driver with initial channel: %d MHz\n",
  549. curchan->center_freq);
  550. ath9k_ps_wakeup(sc);
  551. mutex_lock(&sc->mutex);
  552. init_channel = ath9k_cmn_get_channel(hw, ah, &hw->conf.chandef);
  553. /* Reset SERDES registers */
  554. ath9k_hw_configpcipowersave(ah, false);
  555. /*
  556. * The basic interface to setting the hardware in a good
  557. * state is ``reset''. On return the hardware is known to
  558. * be powered up and with interrupts disabled. This must
  559. * be followed by initialization of the appropriate bits
  560. * and then setup of the interrupt mask.
  561. */
  562. spin_lock_bh(&sc->sc_pcu_lock);
  563. atomic_set(&ah->intr_ref_cnt, -1);
  564. r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
  565. if (r) {
  566. ath_err(common,
  567. "Unable to reset hardware; reset status %d (freq %u MHz)\n",
  568. r, curchan->center_freq);
  569. ah->reset_power_on = false;
  570. }
  571. /* Setup our intr mask. */
  572. ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
  573. ATH9K_INT_RXORN | ATH9K_INT_FATAL |
  574. ATH9K_INT_GLOBAL;
  575. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  576. ah->imask |= ATH9K_INT_RXHP |
  577. ATH9K_INT_RXLP |
  578. ATH9K_INT_BB_WATCHDOG;
  579. else
  580. ah->imask |= ATH9K_INT_RX;
  581. ah->imask |= ATH9K_INT_GTT;
  582. if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
  583. ah->imask |= ATH9K_INT_CST;
  584. ath_mci_enable(sc);
  585. clear_bit(SC_OP_INVALID, &sc->sc_flags);
  586. sc->sc_ah->is_monitoring = false;
  587. if (!ath_complete_reset(sc, false))
  588. ah->reset_power_on = false;
  589. if (ah->led_pin >= 0) {
  590. ath9k_hw_cfg_output(ah, ah->led_pin,
  591. AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
  592. ath9k_hw_set_gpio(ah, ah->led_pin, 0);
  593. }
  594. /*
  595. * Reset key cache to sane defaults (all entries cleared) instead of
  596. * semi-random values after suspend/resume.
  597. */
  598. ath9k_cmn_init_crypto(sc->sc_ah);
  599. spin_unlock_bh(&sc->sc_pcu_lock);
  600. mutex_unlock(&sc->mutex);
  601. ath9k_ps_restore(sc);
  602. return 0;
  603. }
  604. static void ath9k_tx(struct ieee80211_hw *hw,
  605. struct ieee80211_tx_control *control,
  606. struct sk_buff *skb)
  607. {
  608. struct ath_softc *sc = hw->priv;
  609. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  610. struct ath_tx_control txctl;
  611. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
  612. unsigned long flags;
  613. if (sc->ps_enabled) {
  614. /*
  615. * mac80211 does not set PM field for normal data frames, so we
  616. * need to update that based on the current PS mode.
  617. */
  618. if (ieee80211_is_data(hdr->frame_control) &&
  619. !ieee80211_is_nullfunc(hdr->frame_control) &&
  620. !ieee80211_has_pm(hdr->frame_control)) {
  621. ath_dbg(common, PS,
  622. "Add PM=1 for a TX frame while in PS mode\n");
  623. hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
  624. }
  625. }
  626. if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) {
  627. /*
  628. * We are using PS-Poll and mac80211 can request TX while in
  629. * power save mode. Need to wake up hardware for the TX to be
  630. * completed and if needed, also for RX of buffered frames.
  631. */
  632. ath9k_ps_wakeup(sc);
  633. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  634. if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
  635. ath9k_hw_setrxabort(sc->sc_ah, 0);
  636. if (ieee80211_is_pspoll(hdr->frame_control)) {
  637. ath_dbg(common, PS,
  638. "Sending PS-Poll to pick a buffered frame\n");
  639. sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
  640. } else {
  641. ath_dbg(common, PS, "Wake up to complete TX\n");
  642. sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
  643. }
  644. /*
  645. * The actual restore operation will happen only after
  646. * the ps_flags bit is cleared. We are just dropping
  647. * the ps_usecount here.
  648. */
  649. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  650. ath9k_ps_restore(sc);
  651. }
  652. /*
  653. * Cannot tx while the hardware is in full sleep, it first needs a full
  654. * chip reset to recover from that
  655. */
  656. if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) {
  657. ath_err(common, "TX while HW is in FULL_SLEEP mode\n");
  658. goto exit;
  659. }
  660. memset(&txctl, 0, sizeof(struct ath_tx_control));
  661. txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
  662. txctl.sta = control->sta;
  663. ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb);
  664. if (ath_tx_start(hw, skb, &txctl) != 0) {
  665. ath_dbg(common, XMIT, "TX failed\n");
  666. TX_STAT_INC(txctl.txq->axq_qnum, txfailed);
  667. goto exit;
  668. }
  669. return;
  670. exit:
  671. ieee80211_free_txskb(hw, skb);
  672. }
  673. static void ath9k_stop(struct ieee80211_hw *hw)
  674. {
  675. struct ath_softc *sc = hw->priv;
  676. struct ath_hw *ah = sc->sc_ah;
  677. struct ath_common *common = ath9k_hw_common(ah);
  678. bool prev_idle;
  679. mutex_lock(&sc->mutex);
  680. ath_cancel_work(sc);
  681. del_timer_sync(&sc->rx_poll_timer);
  682. if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
  683. ath_dbg(common, ANY, "Device not present\n");
  684. mutex_unlock(&sc->mutex);
  685. return;
  686. }
  687. /* Ensure HW is awake when we try to shut it down. */
  688. ath9k_ps_wakeup(sc);
  689. spin_lock_bh(&sc->sc_pcu_lock);
  690. /* prevent tasklets to enable interrupts once we disable them */
  691. ah->imask &= ~ATH9K_INT_GLOBAL;
  692. /* make sure h/w will not generate any interrupt
  693. * before setting the invalid flag. */
  694. ath9k_hw_disable_interrupts(ah);
  695. spin_unlock_bh(&sc->sc_pcu_lock);
  696. /* we can now sync irq and kill any running tasklets, since we already
  697. * disabled interrupts and not holding a spin lock */
  698. synchronize_irq(sc->irq);
  699. tasklet_kill(&sc->intr_tq);
  700. tasklet_kill(&sc->bcon_tasklet);
  701. prev_idle = sc->ps_idle;
  702. sc->ps_idle = true;
  703. spin_lock_bh(&sc->sc_pcu_lock);
  704. if (ah->led_pin >= 0) {
  705. ath9k_hw_set_gpio(ah, ah->led_pin, 1);
  706. ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
  707. }
  708. ath_prepare_reset(sc);
  709. if (sc->rx.frag) {
  710. dev_kfree_skb_any(sc->rx.frag);
  711. sc->rx.frag = NULL;
  712. }
  713. if (!ah->curchan)
  714. ah->curchan = ath9k_cmn_get_channel(hw, ah, &hw->conf.chandef);
  715. ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
  716. ath9k_hw_phy_disable(ah);
  717. ath9k_hw_configpcipowersave(ah, true);
  718. spin_unlock_bh(&sc->sc_pcu_lock);
  719. ath9k_ps_restore(sc);
  720. set_bit(SC_OP_INVALID, &sc->sc_flags);
  721. sc->ps_idle = prev_idle;
  722. mutex_unlock(&sc->mutex);
  723. ath_dbg(common, CONFIG, "Driver halt\n");
  724. }
  725. static bool ath9k_uses_beacons(int type)
  726. {
  727. switch (type) {
  728. case NL80211_IFTYPE_AP:
  729. case NL80211_IFTYPE_ADHOC:
  730. case NL80211_IFTYPE_MESH_POINT:
  731. return true;
  732. default:
  733. return false;
  734. }
  735. }
  736. static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
  737. {
  738. struct ath9k_vif_iter_data *iter_data = data;
  739. int i;
  740. if (iter_data->has_hw_macaddr) {
  741. for (i = 0; i < ETH_ALEN; i++)
  742. iter_data->mask[i] &=
  743. ~(iter_data->hw_macaddr[i] ^ mac[i]);
  744. } else {
  745. memcpy(iter_data->hw_macaddr, mac, ETH_ALEN);
  746. iter_data->has_hw_macaddr = true;
  747. }
  748. switch (vif->type) {
  749. case NL80211_IFTYPE_AP:
  750. iter_data->naps++;
  751. break;
  752. case NL80211_IFTYPE_STATION:
  753. iter_data->nstations++;
  754. break;
  755. case NL80211_IFTYPE_ADHOC:
  756. iter_data->nadhocs++;
  757. break;
  758. case NL80211_IFTYPE_MESH_POINT:
  759. iter_data->nmeshes++;
  760. break;
  761. case NL80211_IFTYPE_WDS:
  762. iter_data->nwds++;
  763. break;
  764. default:
  765. break;
  766. }
  767. }
  768. static void ath9k_sta_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
  769. {
  770. struct ath_softc *sc = data;
  771. struct ath_vif *avp = (void *)vif->drv_priv;
  772. if (vif->type != NL80211_IFTYPE_STATION)
  773. return;
  774. if (avp->primary_sta_vif)
  775. ath9k_set_assoc_state(sc, vif);
  776. }
  777. /* Called with sc->mutex held. */
  778. void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
  779. struct ieee80211_vif *vif,
  780. struct ath9k_vif_iter_data *iter_data)
  781. {
  782. struct ath_softc *sc = hw->priv;
  783. struct ath_hw *ah = sc->sc_ah;
  784. struct ath_common *common = ath9k_hw_common(ah);
  785. /*
  786. * Use the hardware MAC address as reference, the hardware uses it
  787. * together with the BSSID mask when matching addresses.
  788. */
  789. memset(iter_data, 0, sizeof(*iter_data));
  790. memset(&iter_data->mask, 0xff, ETH_ALEN);
  791. if (vif)
  792. ath9k_vif_iter(iter_data, vif->addr, vif);
  793. /* Get list of all active MAC addresses */
  794. ieee80211_iterate_active_interfaces_atomic(
  795. sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
  796. ath9k_vif_iter, iter_data);
  797. memcpy(common->macaddr, iter_data->hw_macaddr, ETH_ALEN);
  798. }
  799. /* Called with sc->mutex held. */
  800. static void ath9k_calculate_summary_state(struct ieee80211_hw *hw,
  801. struct ieee80211_vif *vif)
  802. {
  803. struct ath_softc *sc = hw->priv;
  804. struct ath_hw *ah = sc->sc_ah;
  805. struct ath_common *common = ath9k_hw_common(ah);
  806. struct ath9k_vif_iter_data iter_data;
  807. enum nl80211_iftype old_opmode = ah->opmode;
  808. ath9k_calculate_iter_data(hw, vif, &iter_data);
  809. memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
  810. ath_hw_setbssidmask(common);
  811. if (iter_data.naps > 0) {
  812. ath9k_hw_set_tsfadjust(ah, true);
  813. ah->opmode = NL80211_IFTYPE_AP;
  814. } else {
  815. ath9k_hw_set_tsfadjust(ah, false);
  816. if (iter_data.nmeshes)
  817. ah->opmode = NL80211_IFTYPE_MESH_POINT;
  818. else if (iter_data.nwds)
  819. ah->opmode = NL80211_IFTYPE_AP;
  820. else if (iter_data.nadhocs)
  821. ah->opmode = NL80211_IFTYPE_ADHOC;
  822. else
  823. ah->opmode = NL80211_IFTYPE_STATION;
  824. }
  825. ath9k_hw_setopmode(ah);
  826. if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0)
  827. ah->imask |= ATH9K_INT_TSFOOR;
  828. else
  829. ah->imask &= ~ATH9K_INT_TSFOOR;
  830. ath9k_hw_set_interrupts(ah);
  831. /*
  832. * If we are changing the opmode to STATION,
  833. * a beacon sync needs to be done.
  834. */
  835. if (ah->opmode == NL80211_IFTYPE_STATION &&
  836. old_opmode == NL80211_IFTYPE_AP &&
  837. test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
  838. ieee80211_iterate_active_interfaces_atomic(
  839. sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
  840. ath9k_sta_vif_iter, sc);
  841. }
  842. }
  843. static int ath9k_add_interface(struct ieee80211_hw *hw,
  844. struct ieee80211_vif *vif)
  845. {
  846. struct ath_softc *sc = hw->priv;
  847. struct ath_hw *ah = sc->sc_ah;
  848. struct ath_common *common = ath9k_hw_common(ah);
  849. struct ath_vif *avp = (void *)vif->drv_priv;
  850. struct ath_node *an = &avp->mcast_node;
  851. mutex_lock(&sc->mutex);
  852. ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type);
  853. sc->nvifs++;
  854. ath9k_ps_wakeup(sc);
  855. ath9k_calculate_summary_state(hw, vif);
  856. ath9k_ps_restore(sc);
  857. if (ath9k_uses_beacons(vif->type))
  858. ath9k_beacon_assign_slot(sc, vif);
  859. an->sc = sc;
  860. an->sta = NULL;
  861. an->vif = vif;
  862. an->no_ps_filter = true;
  863. ath_tx_node_init(sc, an);
  864. mutex_unlock(&sc->mutex);
  865. return 0;
  866. }
  867. static int ath9k_change_interface(struct ieee80211_hw *hw,
  868. struct ieee80211_vif *vif,
  869. enum nl80211_iftype new_type,
  870. bool p2p)
  871. {
  872. struct ath_softc *sc = hw->priv;
  873. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  874. ath_dbg(common, CONFIG, "Change Interface\n");
  875. mutex_lock(&sc->mutex);
  876. if (ath9k_uses_beacons(vif->type))
  877. ath9k_beacon_remove_slot(sc, vif);
  878. vif->type = new_type;
  879. vif->p2p = p2p;
  880. ath9k_ps_wakeup(sc);
  881. ath9k_calculate_summary_state(hw, vif);
  882. ath9k_ps_restore(sc);
  883. if (ath9k_uses_beacons(vif->type))
  884. ath9k_beacon_assign_slot(sc, vif);
  885. mutex_unlock(&sc->mutex);
  886. return 0;
  887. }
  888. static void ath9k_remove_interface(struct ieee80211_hw *hw,
  889. struct ieee80211_vif *vif)
  890. {
  891. struct ath_softc *sc = hw->priv;
  892. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  893. struct ath_vif *avp = (void *)vif->drv_priv;
  894. ath_dbg(common, CONFIG, "Detach Interface\n");
  895. mutex_lock(&sc->mutex);
  896. sc->nvifs--;
  897. if (ath9k_uses_beacons(vif->type))
  898. ath9k_beacon_remove_slot(sc, vif);
  899. if (sc->csa_vif == vif)
  900. sc->csa_vif = NULL;
  901. ath9k_ps_wakeup(sc);
  902. ath9k_calculate_summary_state(hw, NULL);
  903. ath9k_ps_restore(sc);
  904. ath_tx_node_cleanup(sc, &avp->mcast_node);
  905. mutex_unlock(&sc->mutex);
  906. }
  907. static void ath9k_enable_ps(struct ath_softc *sc)
  908. {
  909. struct ath_hw *ah = sc->sc_ah;
  910. struct ath_common *common = ath9k_hw_common(ah);
  911. sc->ps_enabled = true;
  912. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
  913. if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
  914. ah->imask |= ATH9K_INT_TIM_TIMER;
  915. ath9k_hw_set_interrupts(ah);
  916. }
  917. ath9k_hw_setrxabort(ah, 1);
  918. }
  919. ath_dbg(common, PS, "PowerSave enabled\n");
  920. }
  921. static void ath9k_disable_ps(struct ath_softc *sc)
  922. {
  923. struct ath_hw *ah = sc->sc_ah;
  924. struct ath_common *common = ath9k_hw_common(ah);
  925. sc->ps_enabled = false;
  926. ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
  927. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
  928. ath9k_hw_setrxabort(ah, 0);
  929. sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
  930. PS_WAIT_FOR_CAB |
  931. PS_WAIT_FOR_PSPOLL_DATA |
  932. PS_WAIT_FOR_TX_ACK);
  933. if (ah->imask & ATH9K_INT_TIM_TIMER) {
  934. ah->imask &= ~ATH9K_INT_TIM_TIMER;
  935. ath9k_hw_set_interrupts(ah);
  936. }
  937. }
  938. ath_dbg(common, PS, "PowerSave disabled\n");
  939. }
  940. void ath9k_spectral_scan_trigger(struct ieee80211_hw *hw)
  941. {
  942. struct ath_softc *sc = hw->priv;
  943. struct ath_hw *ah = sc->sc_ah;
  944. struct ath_common *common = ath9k_hw_common(ah);
  945. u32 rxfilter;
  946. if (!ath9k_hw_ops(ah)->spectral_scan_trigger) {
  947. ath_err(common, "spectrum analyzer not implemented on this hardware\n");
  948. return;
  949. }
  950. ath9k_ps_wakeup(sc);
  951. rxfilter = ath9k_hw_getrxfilter(ah);
  952. ath9k_hw_setrxfilter(ah, rxfilter |
  953. ATH9K_RX_FILTER_PHYRADAR |
  954. ATH9K_RX_FILTER_PHYERR);
  955. /* TODO: usually this should not be neccesary, but for some reason
  956. * (or in some mode?) the trigger must be called after the
  957. * configuration, otherwise the register will have its values reset
  958. * (on my ar9220 to value 0x01002310)
  959. */
  960. ath9k_spectral_scan_config(hw, sc->spectral_mode);
  961. ath9k_hw_ops(ah)->spectral_scan_trigger(ah);
  962. ath9k_ps_restore(sc);
  963. }
  964. int ath9k_spectral_scan_config(struct ieee80211_hw *hw,
  965. enum spectral_mode spectral_mode)
  966. {
  967. struct ath_softc *sc = hw->priv;
  968. struct ath_hw *ah = sc->sc_ah;
  969. struct ath_common *common = ath9k_hw_common(ah);
  970. if (!ath9k_hw_ops(ah)->spectral_scan_trigger) {
  971. ath_err(common, "spectrum analyzer not implemented on this hardware\n");
  972. return -1;
  973. }
  974. switch (spectral_mode) {
  975. case SPECTRAL_DISABLED:
  976. sc->spec_config.enabled = 0;
  977. break;
  978. case SPECTRAL_BACKGROUND:
  979. /* send endless samples.
  980. * TODO: is this really useful for "background"?
  981. */
  982. sc->spec_config.endless = 1;
  983. sc->spec_config.enabled = 1;
  984. break;
  985. case SPECTRAL_CHANSCAN:
  986. case SPECTRAL_MANUAL:
  987. sc->spec_config.endless = 0;
  988. sc->spec_config.enabled = 1;
  989. break;
  990. default:
  991. return -1;
  992. }
  993. ath9k_ps_wakeup(sc);
  994. ath9k_hw_ops(ah)->spectral_scan_config(ah, &sc->spec_config);
  995. ath9k_ps_restore(sc);
  996. sc->spectral_mode = spectral_mode;
  997. return 0;
  998. }
  999. static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
  1000. {
  1001. struct ath_softc *sc = hw->priv;
  1002. struct ath_hw *ah = sc->sc_ah;
  1003. struct ath_common *common = ath9k_hw_common(ah);
  1004. struct ieee80211_conf *conf = &hw->conf;
  1005. bool reset_channel = false;
  1006. ath9k_ps_wakeup(sc);
  1007. mutex_lock(&sc->mutex);
  1008. if (changed & IEEE80211_CONF_CHANGE_IDLE) {
  1009. sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
  1010. if (sc->ps_idle) {
  1011. ath_cancel_work(sc);
  1012. ath9k_stop_btcoex(sc);
  1013. } else {
  1014. ath9k_start_btcoex(sc);
  1015. /*
  1016. * The chip needs a reset to properly wake up from
  1017. * full sleep
  1018. */
  1019. reset_channel = ah->chip_fullsleep;
  1020. }
  1021. }
  1022. /*
  1023. * We just prepare to enable PS. We have to wait until our AP has
  1024. * ACK'd our null data frame to disable RX otherwise we'll ignore
  1025. * those ACKs and end up retransmitting the same null data frames.
  1026. * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
  1027. */
  1028. if (changed & IEEE80211_CONF_CHANGE_PS) {
  1029. unsigned long flags;
  1030. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  1031. if (conf->flags & IEEE80211_CONF_PS)
  1032. ath9k_enable_ps(sc);
  1033. else
  1034. ath9k_disable_ps(sc);
  1035. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  1036. }
  1037. if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
  1038. if (conf->flags & IEEE80211_CONF_MONITOR) {
  1039. ath_dbg(common, CONFIG, "Monitor mode is enabled\n");
  1040. sc->sc_ah->is_monitoring = true;
  1041. } else {
  1042. ath_dbg(common, CONFIG, "Monitor mode is disabled\n");
  1043. sc->sc_ah->is_monitoring = false;
  1044. }
  1045. }
  1046. if ((changed & IEEE80211_CONF_CHANGE_CHANNEL) || reset_channel) {
  1047. if (ath_set_channel(sc, &hw->conf.chandef) < 0) {
  1048. ath_err(common, "Unable to set channel\n");
  1049. mutex_unlock(&sc->mutex);
  1050. ath9k_ps_restore(sc);
  1051. return -EINVAL;
  1052. }
  1053. }
  1054. if (changed & IEEE80211_CONF_CHANGE_POWER) {
  1055. ath_dbg(common, CONFIG, "Set power: %d\n", conf->power_level);
  1056. sc->config.txpowlimit = 2 * conf->power_level;
  1057. ath9k_cmn_update_txpow(ah, sc->curtxpow,
  1058. sc->config.txpowlimit, &sc->curtxpow);
  1059. }
  1060. mutex_unlock(&sc->mutex);
  1061. ath9k_ps_restore(sc);
  1062. return 0;
  1063. }
  1064. #define SUPPORTED_FILTERS \
  1065. (FIF_PROMISC_IN_BSS | \
  1066. FIF_ALLMULTI | \
  1067. FIF_CONTROL | \
  1068. FIF_PSPOLL | \
  1069. FIF_OTHER_BSS | \
  1070. FIF_BCN_PRBRESP_PROMISC | \
  1071. FIF_PROBE_REQ | \
  1072. FIF_FCSFAIL)
  1073. /* FIXME: sc->sc_full_reset ? */
  1074. static void ath9k_configure_filter(struct ieee80211_hw *hw,
  1075. unsigned int changed_flags,
  1076. unsigned int *total_flags,
  1077. u64 multicast)
  1078. {
  1079. struct ath_softc *sc = hw->priv;
  1080. u32 rfilt;
  1081. changed_flags &= SUPPORTED_FILTERS;
  1082. *total_flags &= SUPPORTED_FILTERS;
  1083. sc->rx.rxfilter = *total_flags;
  1084. ath9k_ps_wakeup(sc);
  1085. rfilt = ath_calcrxfilter(sc);
  1086. ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
  1087. ath9k_ps_restore(sc);
  1088. ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n",
  1089. rfilt);
  1090. }
  1091. static int ath9k_sta_add(struct ieee80211_hw *hw,
  1092. struct ieee80211_vif *vif,
  1093. struct ieee80211_sta *sta)
  1094. {
  1095. struct ath_softc *sc = hw->priv;
  1096. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1097. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1098. struct ieee80211_key_conf ps_key = { };
  1099. int key;
  1100. ath_node_attach(sc, sta, vif);
  1101. if (vif->type != NL80211_IFTYPE_AP &&
  1102. vif->type != NL80211_IFTYPE_AP_VLAN)
  1103. return 0;
  1104. key = ath_key_config(common, vif, sta, &ps_key);
  1105. if (key > 0)
  1106. an->ps_key = key;
  1107. return 0;
  1108. }
  1109. static void ath9k_del_ps_key(struct ath_softc *sc,
  1110. struct ieee80211_vif *vif,
  1111. struct ieee80211_sta *sta)
  1112. {
  1113. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1114. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1115. struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key };
  1116. if (!an->ps_key)
  1117. return;
  1118. ath_key_delete(common, &ps_key);
  1119. an->ps_key = 0;
  1120. }
  1121. static int ath9k_sta_remove(struct ieee80211_hw *hw,
  1122. struct ieee80211_vif *vif,
  1123. struct ieee80211_sta *sta)
  1124. {
  1125. struct ath_softc *sc = hw->priv;
  1126. ath9k_del_ps_key(sc, vif, sta);
  1127. ath_node_detach(sc, sta);
  1128. return 0;
  1129. }
  1130. static void ath9k_sta_notify(struct ieee80211_hw *hw,
  1131. struct ieee80211_vif *vif,
  1132. enum sta_notify_cmd cmd,
  1133. struct ieee80211_sta *sta)
  1134. {
  1135. struct ath_softc *sc = hw->priv;
  1136. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1137. switch (cmd) {
  1138. case STA_NOTIFY_SLEEP:
  1139. an->sleeping = true;
  1140. ath_tx_aggr_sleep(sta, sc, an);
  1141. break;
  1142. case STA_NOTIFY_AWAKE:
  1143. an->sleeping = false;
  1144. ath_tx_aggr_wakeup(sc, an);
  1145. break;
  1146. }
  1147. }
  1148. static int ath9k_conf_tx(struct ieee80211_hw *hw,
  1149. struct ieee80211_vif *vif, u16 queue,
  1150. const struct ieee80211_tx_queue_params *params)
  1151. {
  1152. struct ath_softc *sc = hw->priv;
  1153. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1154. struct ath_txq *txq;
  1155. struct ath9k_tx_queue_info qi;
  1156. int ret = 0;
  1157. if (queue >= IEEE80211_NUM_ACS)
  1158. return 0;
  1159. txq = sc->tx.txq_map[queue];
  1160. ath9k_ps_wakeup(sc);
  1161. mutex_lock(&sc->mutex);
  1162. memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
  1163. qi.tqi_aifs = params->aifs;
  1164. qi.tqi_cwmin = params->cw_min;
  1165. qi.tqi_cwmax = params->cw_max;
  1166. qi.tqi_burstTime = params->txop * 32;
  1167. ath_dbg(common, CONFIG,
  1168. "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
  1169. queue, txq->axq_qnum, params->aifs, params->cw_min,
  1170. params->cw_max, params->txop);
  1171. ath_update_max_aggr_framelen(sc, queue, qi.tqi_burstTime);
  1172. ret = ath_txq_update(sc, txq->axq_qnum, &qi);
  1173. if (ret)
  1174. ath_err(common, "TXQ Update failed\n");
  1175. mutex_unlock(&sc->mutex);
  1176. ath9k_ps_restore(sc);
  1177. return ret;
  1178. }
  1179. static int ath9k_set_key(struct ieee80211_hw *hw,
  1180. enum set_key_cmd cmd,
  1181. struct ieee80211_vif *vif,
  1182. struct ieee80211_sta *sta,
  1183. struct ieee80211_key_conf *key)
  1184. {
  1185. struct ath_softc *sc = hw->priv;
  1186. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1187. int ret = 0;
  1188. if (ath9k_modparam_nohwcrypt)
  1189. return -ENOSPC;
  1190. if ((vif->type == NL80211_IFTYPE_ADHOC ||
  1191. vif->type == NL80211_IFTYPE_MESH_POINT) &&
  1192. (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
  1193. key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
  1194. !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
  1195. /*
  1196. * For now, disable hw crypto for the RSN IBSS group keys. This
  1197. * could be optimized in the future to use a modified key cache
  1198. * design to support per-STA RX GTK, but until that gets
  1199. * implemented, use of software crypto for group addressed
  1200. * frames is a acceptable to allow RSN IBSS to be used.
  1201. */
  1202. return -EOPNOTSUPP;
  1203. }
  1204. mutex_lock(&sc->mutex);
  1205. ath9k_ps_wakeup(sc);
  1206. ath_dbg(common, CONFIG, "Set HW Key\n");
  1207. switch (cmd) {
  1208. case SET_KEY:
  1209. if (sta)
  1210. ath9k_del_ps_key(sc, vif, sta);
  1211. ret = ath_key_config(common, vif, sta, key);
  1212. if (ret >= 0) {
  1213. key->hw_key_idx = ret;
  1214. /* push IV and Michael MIC generation to stack */
  1215. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  1216. if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
  1217. key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
  1218. if (sc->sc_ah->sw_mgmt_crypto &&
  1219. key->cipher == WLAN_CIPHER_SUITE_CCMP)
  1220. key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
  1221. ret = 0;
  1222. }
  1223. break;
  1224. case DISABLE_KEY:
  1225. ath_key_delete(common, key);
  1226. break;
  1227. default:
  1228. ret = -EINVAL;
  1229. }
  1230. ath9k_ps_restore(sc);
  1231. mutex_unlock(&sc->mutex);
  1232. return ret;
  1233. }
  1234. static void ath9k_set_assoc_state(struct ath_softc *sc,
  1235. struct ieee80211_vif *vif)
  1236. {
  1237. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1238. struct ath_vif *avp = (void *)vif->drv_priv;
  1239. struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
  1240. unsigned long flags;
  1241. set_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags);
  1242. avp->primary_sta_vif = true;
  1243. /*
  1244. * Set the AID, BSSID and do beacon-sync only when
  1245. * the HW opmode is STATION.
  1246. *
  1247. * But the primary bit is set above in any case.
  1248. */
  1249. if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION)
  1250. return;
  1251. memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
  1252. common->curaid = bss_conf->aid;
  1253. ath9k_hw_write_associd(sc->sc_ah);
  1254. sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
  1255. sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
  1256. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  1257. sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
  1258. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  1259. if (ath9k_hw_mci_is_enabled(sc->sc_ah))
  1260. ath9k_mci_update_wlan_channels(sc, false);
  1261. ath_dbg(common, CONFIG,
  1262. "Primary Station interface: %pM, BSSID: %pM\n",
  1263. vif->addr, common->curbssid);
  1264. }
  1265. static void ath9k_bss_assoc_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
  1266. {
  1267. struct ath_softc *sc = data;
  1268. struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
  1269. if (test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags))
  1270. return;
  1271. if (bss_conf->assoc)
  1272. ath9k_set_assoc_state(sc, vif);
  1273. }
  1274. static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
  1275. struct ieee80211_vif *vif,
  1276. struct ieee80211_bss_conf *bss_conf,
  1277. u32 changed)
  1278. {
  1279. #define CHECK_ANI \
  1280. (BSS_CHANGED_ASSOC | \
  1281. BSS_CHANGED_IBSS | \
  1282. BSS_CHANGED_BEACON_ENABLED)
  1283. struct ath_softc *sc = hw->priv;
  1284. struct ath_hw *ah = sc->sc_ah;
  1285. struct ath_common *common = ath9k_hw_common(ah);
  1286. struct ath_vif *avp = (void *)vif->drv_priv;
  1287. int slottime;
  1288. ath9k_ps_wakeup(sc);
  1289. mutex_lock(&sc->mutex);
  1290. if (changed & BSS_CHANGED_ASSOC) {
  1291. ath_dbg(common, CONFIG, "BSSID %pM Changed ASSOC %d\n",
  1292. bss_conf->bssid, bss_conf->assoc);
  1293. if (avp->primary_sta_vif && !bss_conf->assoc) {
  1294. clear_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags);
  1295. avp->primary_sta_vif = false;
  1296. if (ah->opmode == NL80211_IFTYPE_STATION)
  1297. clear_bit(SC_OP_BEACONS, &sc->sc_flags);
  1298. }
  1299. ieee80211_iterate_active_interfaces_atomic(
  1300. sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
  1301. ath9k_bss_assoc_iter, sc);
  1302. if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags) &&
  1303. ah->opmode == NL80211_IFTYPE_STATION) {
  1304. memset(common->curbssid, 0, ETH_ALEN);
  1305. common->curaid = 0;
  1306. ath9k_hw_write_associd(sc->sc_ah);
  1307. if (ath9k_hw_mci_is_enabled(sc->sc_ah))
  1308. ath9k_mci_update_wlan_channels(sc, true);
  1309. }
  1310. }
  1311. if (changed & BSS_CHANGED_IBSS) {
  1312. memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
  1313. common->curaid = bss_conf->aid;
  1314. ath9k_hw_write_associd(sc->sc_ah);
  1315. }
  1316. if ((changed & BSS_CHANGED_BEACON_ENABLED) ||
  1317. (changed & BSS_CHANGED_BEACON_INT)) {
  1318. if (ah->opmode == NL80211_IFTYPE_AP &&
  1319. bss_conf->enable_beacon)
  1320. ath9k_set_tsfadjust(sc, vif);
  1321. if (ath9k_allow_beacon_config(sc, vif))
  1322. ath9k_beacon_config(sc, vif, changed);
  1323. }
  1324. if (changed & BSS_CHANGED_ERP_SLOT) {
  1325. if (bss_conf->use_short_slot)
  1326. slottime = 9;
  1327. else
  1328. slottime = 20;
  1329. if (vif->type == NL80211_IFTYPE_AP) {
  1330. /*
  1331. * Defer update, so that connected stations can adjust
  1332. * their settings at the same time.
  1333. * See beacon.c for more details
  1334. */
  1335. sc->beacon.slottime = slottime;
  1336. sc->beacon.updateslot = UPDATE;
  1337. } else {
  1338. ah->slottime = slottime;
  1339. ath9k_hw_init_global_settings(ah);
  1340. }
  1341. }
  1342. if (changed & CHECK_ANI)
  1343. ath_check_ani(sc);
  1344. mutex_unlock(&sc->mutex);
  1345. ath9k_ps_restore(sc);
  1346. #undef CHECK_ANI
  1347. }
  1348. static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
  1349. {
  1350. struct ath_softc *sc = hw->priv;
  1351. u64 tsf;
  1352. mutex_lock(&sc->mutex);
  1353. ath9k_ps_wakeup(sc);
  1354. tsf = ath9k_hw_gettsf64(sc->sc_ah);
  1355. ath9k_ps_restore(sc);
  1356. mutex_unlock(&sc->mutex);
  1357. return tsf;
  1358. }
  1359. static void ath9k_set_tsf(struct ieee80211_hw *hw,
  1360. struct ieee80211_vif *vif,
  1361. u64 tsf)
  1362. {
  1363. struct ath_softc *sc = hw->priv;
  1364. mutex_lock(&sc->mutex);
  1365. ath9k_ps_wakeup(sc);
  1366. ath9k_hw_settsf64(sc->sc_ah, tsf);
  1367. ath9k_ps_restore(sc);
  1368. mutex_unlock(&sc->mutex);
  1369. }
  1370. static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
  1371. {
  1372. struct ath_softc *sc = hw->priv;
  1373. mutex_lock(&sc->mutex);
  1374. ath9k_ps_wakeup(sc);
  1375. ath9k_hw_reset_tsf(sc->sc_ah);
  1376. ath9k_ps_restore(sc);
  1377. mutex_unlock(&sc->mutex);
  1378. }
  1379. static int ath9k_ampdu_action(struct ieee80211_hw *hw,
  1380. struct ieee80211_vif *vif,
  1381. enum ieee80211_ampdu_mlme_action action,
  1382. struct ieee80211_sta *sta,
  1383. u16 tid, u16 *ssn, u8 buf_size)
  1384. {
  1385. struct ath_softc *sc = hw->priv;
  1386. bool flush = false;
  1387. int ret = 0;
  1388. mutex_lock(&sc->mutex);
  1389. switch (action) {
  1390. case IEEE80211_AMPDU_RX_START:
  1391. break;
  1392. case IEEE80211_AMPDU_RX_STOP:
  1393. break;
  1394. case IEEE80211_AMPDU_TX_START:
  1395. ath9k_ps_wakeup(sc);
  1396. ret = ath_tx_aggr_start(sc, sta, tid, ssn);
  1397. if (!ret)
  1398. ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  1399. ath9k_ps_restore(sc);
  1400. break;
  1401. case IEEE80211_AMPDU_TX_STOP_FLUSH:
  1402. case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
  1403. flush = true;
  1404. case IEEE80211_AMPDU_TX_STOP_CONT:
  1405. ath9k_ps_wakeup(sc);
  1406. ath_tx_aggr_stop(sc, sta, tid);
  1407. if (!flush)
  1408. ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  1409. ath9k_ps_restore(sc);
  1410. break;
  1411. case IEEE80211_AMPDU_TX_OPERATIONAL:
  1412. ath9k_ps_wakeup(sc);
  1413. ath_tx_aggr_resume(sc, sta, tid);
  1414. ath9k_ps_restore(sc);
  1415. break;
  1416. default:
  1417. ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
  1418. }
  1419. mutex_unlock(&sc->mutex);
  1420. return ret;
  1421. }
  1422. static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
  1423. struct survey_info *survey)
  1424. {
  1425. struct ath_softc *sc = hw->priv;
  1426. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1427. struct ieee80211_supported_band *sband;
  1428. struct ieee80211_channel *chan;
  1429. unsigned long flags;
  1430. int pos;
  1431. spin_lock_irqsave(&common->cc_lock, flags);
  1432. if (idx == 0)
  1433. ath_update_survey_stats(sc);
  1434. sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ];
  1435. if (sband && idx >= sband->n_channels) {
  1436. idx -= sband->n_channels;
  1437. sband = NULL;
  1438. }
  1439. if (!sband)
  1440. sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ];
  1441. if (!sband || idx >= sband->n_channels) {
  1442. spin_unlock_irqrestore(&common->cc_lock, flags);
  1443. return -ENOENT;
  1444. }
  1445. chan = &sband->channels[idx];
  1446. pos = chan->hw_value;
  1447. memcpy(survey, &sc->survey[pos], sizeof(*survey));
  1448. survey->channel = chan;
  1449. spin_unlock_irqrestore(&common->cc_lock, flags);
  1450. return 0;
  1451. }
  1452. static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
  1453. {
  1454. struct ath_softc *sc = hw->priv;
  1455. struct ath_hw *ah = sc->sc_ah;
  1456. mutex_lock(&sc->mutex);
  1457. ah->coverage_class = coverage_class;
  1458. ath9k_ps_wakeup(sc);
  1459. ath9k_hw_init_global_settings(ah);
  1460. ath9k_ps_restore(sc);
  1461. mutex_unlock(&sc->mutex);
  1462. }
  1463. static void ath9k_flush(struct ieee80211_hw *hw, u32 queues, bool drop)
  1464. {
  1465. struct ath_softc *sc = hw->priv;
  1466. struct ath_hw *ah = sc->sc_ah;
  1467. struct ath_common *common = ath9k_hw_common(ah);
  1468. int timeout = 200; /* ms */
  1469. int i, j;
  1470. bool drain_txq;
  1471. mutex_lock(&sc->mutex);
  1472. cancel_delayed_work_sync(&sc->tx_complete_work);
  1473. if (ah->ah_flags & AH_UNPLUGGED) {
  1474. ath_dbg(common, ANY, "Device has been unplugged!\n");
  1475. mutex_unlock(&sc->mutex);
  1476. return;
  1477. }
  1478. if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
  1479. ath_dbg(common, ANY, "Device not present\n");
  1480. mutex_unlock(&sc->mutex);
  1481. return;
  1482. }
  1483. for (j = 0; j < timeout; j++) {
  1484. bool npend = false;
  1485. if (j)
  1486. usleep_range(1000, 2000);
  1487. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  1488. if (!ATH_TXQ_SETUP(sc, i))
  1489. continue;
  1490. npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]);
  1491. if (npend)
  1492. break;
  1493. }
  1494. if (!npend)
  1495. break;
  1496. }
  1497. if (drop) {
  1498. ath9k_ps_wakeup(sc);
  1499. spin_lock_bh(&sc->sc_pcu_lock);
  1500. drain_txq = ath_drain_all_txq(sc);
  1501. spin_unlock_bh(&sc->sc_pcu_lock);
  1502. if (!drain_txq)
  1503. ath_reset(sc);
  1504. ath9k_ps_restore(sc);
  1505. ieee80211_wake_queues(hw);
  1506. }
  1507. ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0);
  1508. mutex_unlock(&sc->mutex);
  1509. }
  1510. static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
  1511. {
  1512. struct ath_softc *sc = hw->priv;
  1513. int i;
  1514. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  1515. if (!ATH_TXQ_SETUP(sc, i))
  1516. continue;
  1517. if (ath9k_has_pending_frames(sc, &sc->tx.txq[i]))
  1518. return true;
  1519. }
  1520. return false;
  1521. }
  1522. static int ath9k_tx_last_beacon(struct ieee80211_hw *hw)
  1523. {
  1524. struct ath_softc *sc = hw->priv;
  1525. struct ath_hw *ah = sc->sc_ah;
  1526. struct ieee80211_vif *vif;
  1527. struct ath_vif *avp;
  1528. struct ath_buf *bf;
  1529. struct ath_tx_status ts;
  1530. bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
  1531. int status;
  1532. vif = sc->beacon.bslot[0];
  1533. if (!vif)
  1534. return 0;
  1535. if (!vif->bss_conf.enable_beacon)
  1536. return 0;
  1537. avp = (void *)vif->drv_priv;
  1538. if (!sc->beacon.tx_processed && !edma) {
  1539. tasklet_disable(&sc->bcon_tasklet);
  1540. bf = avp->av_bcbuf;
  1541. if (!bf || !bf->bf_mpdu)
  1542. goto skip;
  1543. status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts);
  1544. if (status == -EINPROGRESS)
  1545. goto skip;
  1546. sc->beacon.tx_processed = true;
  1547. sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
  1548. skip:
  1549. tasklet_enable(&sc->bcon_tasklet);
  1550. }
  1551. return sc->beacon.tx_last;
  1552. }
  1553. static int ath9k_get_stats(struct ieee80211_hw *hw,
  1554. struct ieee80211_low_level_stats *stats)
  1555. {
  1556. struct ath_softc *sc = hw->priv;
  1557. struct ath_hw *ah = sc->sc_ah;
  1558. struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats;
  1559. stats->dot11ACKFailureCount = mib_stats->ackrcv_bad;
  1560. stats->dot11RTSFailureCount = mib_stats->rts_bad;
  1561. stats->dot11FCSErrorCount = mib_stats->fcs_bad;
  1562. stats->dot11RTSSuccessCount = mib_stats->rts_good;
  1563. return 0;
  1564. }
  1565. static u32 fill_chainmask(u32 cap, u32 new)
  1566. {
  1567. u32 filled = 0;
  1568. int i;
  1569. for (i = 0; cap && new; i++, cap >>= 1) {
  1570. if (!(cap & BIT(0)))
  1571. continue;
  1572. if (new & BIT(0))
  1573. filled |= BIT(i);
  1574. new >>= 1;
  1575. }
  1576. return filled;
  1577. }
  1578. static bool validate_antenna_mask(struct ath_hw *ah, u32 val)
  1579. {
  1580. if (AR_SREV_9300_20_OR_LATER(ah))
  1581. return true;
  1582. switch (val & 0x7) {
  1583. case 0x1:
  1584. case 0x3:
  1585. case 0x7:
  1586. return true;
  1587. case 0x2:
  1588. return (ah->caps.rx_chainmask == 1);
  1589. default:
  1590. return false;
  1591. }
  1592. }
  1593. static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
  1594. {
  1595. struct ath_softc *sc = hw->priv;
  1596. struct ath_hw *ah = sc->sc_ah;
  1597. if (ah->caps.rx_chainmask != 1)
  1598. rx_ant |= tx_ant;
  1599. if (!validate_antenna_mask(ah, rx_ant) || !tx_ant)
  1600. return -EINVAL;
  1601. sc->ant_rx = rx_ant;
  1602. sc->ant_tx = tx_ant;
  1603. if (ah->caps.rx_chainmask == 1)
  1604. return 0;
  1605. /* AR9100 runs into calibration issues if not all rx chains are enabled */
  1606. if (AR_SREV_9100(ah))
  1607. ah->rxchainmask = 0x7;
  1608. else
  1609. ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant);
  1610. ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant);
  1611. ath9k_reload_chainmask_settings(sc);
  1612. return 0;
  1613. }
  1614. static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
  1615. {
  1616. struct ath_softc *sc = hw->priv;
  1617. *tx_ant = sc->ant_tx;
  1618. *rx_ant = sc->ant_rx;
  1619. return 0;
  1620. }
  1621. #ifdef CONFIG_PM_SLEEP
  1622. static void ath9k_wow_map_triggers(struct ath_softc *sc,
  1623. struct cfg80211_wowlan *wowlan,
  1624. u32 *wow_triggers)
  1625. {
  1626. if (wowlan->disconnect)
  1627. *wow_triggers |= AH_WOW_LINK_CHANGE |
  1628. AH_WOW_BEACON_MISS;
  1629. if (wowlan->magic_pkt)
  1630. *wow_triggers |= AH_WOW_MAGIC_PATTERN_EN;
  1631. if (wowlan->n_patterns)
  1632. *wow_triggers |= AH_WOW_USER_PATTERN_EN;
  1633. sc->wow_enabled = *wow_triggers;
  1634. }
  1635. static void ath9k_wow_add_disassoc_deauth_pattern(struct ath_softc *sc)
  1636. {
  1637. struct ath_hw *ah = sc->sc_ah;
  1638. struct ath_common *common = ath9k_hw_common(ah);
  1639. int pattern_count = 0;
  1640. int i, byte_cnt;
  1641. u8 dis_deauth_pattern[MAX_PATTERN_SIZE];
  1642. u8 dis_deauth_mask[MAX_PATTERN_SIZE];
  1643. memset(dis_deauth_pattern, 0, MAX_PATTERN_SIZE);
  1644. memset(dis_deauth_mask, 0, MAX_PATTERN_SIZE);
  1645. /*
  1646. * Create Dissassociate / Deauthenticate packet filter
  1647. *
  1648. * 2 bytes 2 byte 6 bytes 6 bytes 6 bytes
  1649. * +--------------+----------+---------+--------+--------+----
  1650. * + Frame Control+ Duration + DA + SA + BSSID +
  1651. * +--------------+----------+---------+--------+--------+----
  1652. *
  1653. * The above is the management frame format for disassociate/
  1654. * deauthenticate pattern, from this we need to match the first byte
  1655. * of 'Frame Control' and DA, SA, and BSSID fields
  1656. * (skipping 2nd byte of FC and Duration feild.
  1657. *
  1658. * Disassociate pattern
  1659. * --------------------
  1660. * Frame control = 00 00 1010
  1661. * DA, SA, BSSID = x:x:x:x:x:x
  1662. * Pattern will be A0000000 | x:x:x:x:x:x | x:x:x:x:x:x
  1663. * | x:x:x:x:x:x -- 22 bytes
  1664. *
  1665. * Deauthenticate pattern
  1666. * ----------------------
  1667. * Frame control = 00 00 1100
  1668. * DA, SA, BSSID = x:x:x:x:x:x
  1669. * Pattern will be C0000000 | x:x:x:x:x:x | x:x:x:x:x:x
  1670. * | x:x:x:x:x:x -- 22 bytes
  1671. */
  1672. /* Create Disassociate Pattern first */
  1673. byte_cnt = 0;
  1674. /* Fill out the mask with all FF's */
  1675. for (i = 0; i < MAX_PATTERN_MASK_SIZE; i++)
  1676. dis_deauth_mask[i] = 0xff;
  1677. /* copy the first byte of frame control field */
  1678. dis_deauth_pattern[byte_cnt] = 0xa0;
  1679. byte_cnt++;
  1680. /* skip 2nd byte of frame control and Duration field */
  1681. byte_cnt += 3;
  1682. /*
  1683. * need not match the destination mac address, it can be a broadcast
  1684. * mac address or an unicast to this station
  1685. */
  1686. byte_cnt += 6;
  1687. /* copy the source mac address */
  1688. memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN);
  1689. byte_cnt += 6;
  1690. /* copy the bssid, its same as the source mac address */
  1691. memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN);
  1692. /* Create Disassociate pattern mask */
  1693. dis_deauth_mask[0] = 0xfe;
  1694. dis_deauth_mask[1] = 0x03;
  1695. dis_deauth_mask[2] = 0xc0;
  1696. ath_dbg(common, WOW, "Adding disassoc/deauth patterns for WoW\n");
  1697. ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask,
  1698. pattern_count, byte_cnt);
  1699. pattern_count++;
  1700. /*
  1701. * for de-authenticate pattern, only the first byte of the frame
  1702. * control field gets changed from 0xA0 to 0xC0
  1703. */
  1704. dis_deauth_pattern[0] = 0xC0;
  1705. ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask,
  1706. pattern_count, byte_cnt);
  1707. }
  1708. static void ath9k_wow_add_pattern(struct ath_softc *sc,
  1709. struct cfg80211_wowlan *wowlan)
  1710. {
  1711. struct ath_hw *ah = sc->sc_ah;
  1712. struct ath9k_wow_pattern *wow_pattern = NULL;
  1713. struct cfg80211_pkt_pattern *patterns = wowlan->patterns;
  1714. int mask_len;
  1715. s8 i = 0;
  1716. if (!wowlan->n_patterns)
  1717. return;
  1718. /*
  1719. * Add the new user configured patterns
  1720. */
  1721. for (i = 0; i < wowlan->n_patterns; i++) {
  1722. wow_pattern = kzalloc(sizeof(*wow_pattern), GFP_KERNEL);
  1723. if (!wow_pattern)
  1724. return;
  1725. /*
  1726. * TODO: convert the generic user space pattern to
  1727. * appropriate chip specific/802.11 pattern.
  1728. */
  1729. mask_len = DIV_ROUND_UP(wowlan->patterns[i].pattern_len, 8);
  1730. memset(wow_pattern->pattern_bytes, 0, MAX_PATTERN_SIZE);
  1731. memset(wow_pattern->mask_bytes, 0, MAX_PATTERN_SIZE);
  1732. memcpy(wow_pattern->pattern_bytes, patterns[i].pattern,
  1733. patterns[i].pattern_len);
  1734. memcpy(wow_pattern->mask_bytes, patterns[i].mask, mask_len);
  1735. wow_pattern->pattern_len = patterns[i].pattern_len;
  1736. /*
  1737. * just need to take care of deauth and disssoc pattern,
  1738. * make sure we don't overwrite them.
  1739. */
  1740. ath9k_hw_wow_apply_pattern(ah, wow_pattern->pattern_bytes,
  1741. wow_pattern->mask_bytes,
  1742. i + 2,
  1743. wow_pattern->pattern_len);
  1744. kfree(wow_pattern);
  1745. }
  1746. }
  1747. static int ath9k_suspend(struct ieee80211_hw *hw,
  1748. struct cfg80211_wowlan *wowlan)
  1749. {
  1750. struct ath_softc *sc = hw->priv;
  1751. struct ath_hw *ah = sc->sc_ah;
  1752. struct ath_common *common = ath9k_hw_common(ah);
  1753. u32 wow_triggers_enabled = 0;
  1754. int ret = 0;
  1755. mutex_lock(&sc->mutex);
  1756. ath_cancel_work(sc);
  1757. ath_stop_ani(sc);
  1758. del_timer_sync(&sc->rx_poll_timer);
  1759. if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
  1760. ath_dbg(common, ANY, "Device not present\n");
  1761. ret = -EINVAL;
  1762. goto fail_wow;
  1763. }
  1764. if (WARN_ON(!wowlan)) {
  1765. ath_dbg(common, WOW, "None of the WoW triggers enabled\n");
  1766. ret = -EINVAL;
  1767. goto fail_wow;
  1768. }
  1769. if (!device_can_wakeup(sc->dev)) {
  1770. ath_dbg(common, WOW, "device_can_wakeup failed, WoW is not enabled\n");
  1771. ret = 1;
  1772. goto fail_wow;
  1773. }
  1774. /*
  1775. * none of the sta vifs are associated
  1776. * and we are not currently handling multivif
  1777. * cases, for instance we have to seperately
  1778. * configure 'keep alive frame' for each
  1779. * STA.
  1780. */
  1781. if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
  1782. ath_dbg(common, WOW, "None of the STA vifs are associated\n");
  1783. ret = 1;
  1784. goto fail_wow;
  1785. }
  1786. if (sc->nvifs > 1) {
  1787. ath_dbg(common, WOW, "WoW for multivif is not yet supported\n");
  1788. ret = 1;
  1789. goto fail_wow;
  1790. }
  1791. ath9k_wow_map_triggers(sc, wowlan, &wow_triggers_enabled);
  1792. ath_dbg(common, WOW, "WoW triggers enabled 0x%x\n",
  1793. wow_triggers_enabled);
  1794. ath9k_ps_wakeup(sc);
  1795. ath9k_stop_btcoex(sc);
  1796. /*
  1797. * Enable wake up on recieving disassoc/deauth
  1798. * frame by default.
  1799. */
  1800. ath9k_wow_add_disassoc_deauth_pattern(sc);
  1801. if (wow_triggers_enabled & AH_WOW_USER_PATTERN_EN)
  1802. ath9k_wow_add_pattern(sc, wowlan);
  1803. spin_lock_bh(&sc->sc_pcu_lock);
  1804. /*
  1805. * To avoid false wake, we enable beacon miss interrupt only
  1806. * when we go to sleep. We save the current interrupt mask
  1807. * so we can restore it after the system wakes up
  1808. */
  1809. sc->wow_intr_before_sleep = ah->imask;
  1810. ah->imask &= ~ATH9K_INT_GLOBAL;
  1811. ath9k_hw_disable_interrupts(ah);
  1812. ah->imask = ATH9K_INT_BMISS | ATH9K_INT_GLOBAL;
  1813. ath9k_hw_set_interrupts(ah);
  1814. ath9k_hw_enable_interrupts(ah);
  1815. spin_unlock_bh(&sc->sc_pcu_lock);
  1816. /*
  1817. * we can now sync irq and kill any running tasklets, since we already
  1818. * disabled interrupts and not holding a spin lock
  1819. */
  1820. synchronize_irq(sc->irq);
  1821. tasklet_kill(&sc->intr_tq);
  1822. ath9k_hw_wow_enable(ah, wow_triggers_enabled);
  1823. ath9k_ps_restore(sc);
  1824. ath_dbg(common, ANY, "WoW enabled in ath9k\n");
  1825. atomic_inc(&sc->wow_sleep_proc_intr);
  1826. fail_wow:
  1827. mutex_unlock(&sc->mutex);
  1828. return ret;
  1829. }
  1830. static int ath9k_resume(struct ieee80211_hw *hw)
  1831. {
  1832. struct ath_softc *sc = hw->priv;
  1833. struct ath_hw *ah = sc->sc_ah;
  1834. struct ath_common *common = ath9k_hw_common(ah);
  1835. u32 wow_status;
  1836. mutex_lock(&sc->mutex);
  1837. ath9k_ps_wakeup(sc);
  1838. spin_lock_bh(&sc->sc_pcu_lock);
  1839. ath9k_hw_disable_interrupts(ah);
  1840. ah->imask = sc->wow_intr_before_sleep;
  1841. ath9k_hw_set_interrupts(ah);
  1842. ath9k_hw_enable_interrupts(ah);
  1843. spin_unlock_bh(&sc->sc_pcu_lock);
  1844. wow_status = ath9k_hw_wow_wakeup(ah);
  1845. if (atomic_read(&sc->wow_got_bmiss_intr) == 0) {
  1846. /*
  1847. * some devices may not pick beacon miss
  1848. * as the reason they woke up so we add
  1849. * that here for that shortcoming.
  1850. */
  1851. wow_status |= AH_WOW_BEACON_MISS;
  1852. atomic_dec(&sc->wow_got_bmiss_intr);
  1853. ath_dbg(common, ANY, "Beacon miss interrupt picked up during WoW sleep\n");
  1854. }
  1855. atomic_dec(&sc->wow_sleep_proc_intr);
  1856. if (wow_status) {
  1857. ath_dbg(common, ANY, "Waking up due to WoW triggers %s with WoW status = %x\n",
  1858. ath9k_hw_wow_event_to_string(wow_status), wow_status);
  1859. }
  1860. ath_restart_work(sc);
  1861. ath9k_start_btcoex(sc);
  1862. ath9k_ps_restore(sc);
  1863. mutex_unlock(&sc->mutex);
  1864. return 0;
  1865. }
  1866. static void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled)
  1867. {
  1868. struct ath_softc *sc = hw->priv;
  1869. mutex_lock(&sc->mutex);
  1870. device_init_wakeup(sc->dev, 1);
  1871. device_set_wakeup_enable(sc->dev, enabled);
  1872. mutex_unlock(&sc->mutex);
  1873. }
  1874. #endif
  1875. static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
  1876. {
  1877. struct ath_softc *sc = hw->priv;
  1878. set_bit(SC_OP_SCANNING, &sc->sc_flags);
  1879. }
  1880. static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
  1881. {
  1882. struct ath_softc *sc = hw->priv;
  1883. clear_bit(SC_OP_SCANNING, &sc->sc_flags);
  1884. }
  1885. static void ath9k_channel_switch_beacon(struct ieee80211_hw *hw,
  1886. struct ieee80211_vif *vif,
  1887. struct cfg80211_chan_def *chandef)
  1888. {
  1889. struct ath_softc *sc = hw->priv;
  1890. /* mac80211 does not support CSA in multi-if cases (yet) */
  1891. if (WARN_ON(sc->csa_vif))
  1892. return;
  1893. sc->csa_vif = vif;
  1894. }
  1895. struct ieee80211_ops ath9k_ops = {
  1896. .tx = ath9k_tx,
  1897. .start = ath9k_start,
  1898. .stop = ath9k_stop,
  1899. .add_interface = ath9k_add_interface,
  1900. .change_interface = ath9k_change_interface,
  1901. .remove_interface = ath9k_remove_interface,
  1902. .config = ath9k_config,
  1903. .configure_filter = ath9k_configure_filter,
  1904. .sta_add = ath9k_sta_add,
  1905. .sta_remove = ath9k_sta_remove,
  1906. .sta_notify = ath9k_sta_notify,
  1907. .conf_tx = ath9k_conf_tx,
  1908. .bss_info_changed = ath9k_bss_info_changed,
  1909. .set_key = ath9k_set_key,
  1910. .get_tsf = ath9k_get_tsf,
  1911. .set_tsf = ath9k_set_tsf,
  1912. .reset_tsf = ath9k_reset_tsf,
  1913. .ampdu_action = ath9k_ampdu_action,
  1914. .get_survey = ath9k_get_survey,
  1915. .rfkill_poll = ath9k_rfkill_poll_state,
  1916. .set_coverage_class = ath9k_set_coverage_class,
  1917. .flush = ath9k_flush,
  1918. .tx_frames_pending = ath9k_tx_frames_pending,
  1919. .tx_last_beacon = ath9k_tx_last_beacon,
  1920. .release_buffered_frames = ath9k_release_buffered_frames,
  1921. .get_stats = ath9k_get_stats,
  1922. .set_antenna = ath9k_set_antenna,
  1923. .get_antenna = ath9k_get_antenna,
  1924. #ifdef CONFIG_PM_SLEEP
  1925. .suspend = ath9k_suspend,
  1926. .resume = ath9k_resume,
  1927. .set_wakeup = ath9k_set_wakeup,
  1928. #endif
  1929. #ifdef CONFIG_ATH9K_DEBUGFS
  1930. .get_et_sset_count = ath9k_get_et_sset_count,
  1931. .get_et_stats = ath9k_get_et_stats,
  1932. .get_et_strings = ath9k_get_et_strings,
  1933. #endif
  1934. #if defined(CONFIG_MAC80211_DEBUGFS) && defined(CONFIG_ATH9K_DEBUGFS)
  1935. .sta_add_debugfs = ath9k_sta_add_debugfs,
  1936. #endif
  1937. .sw_scan_start = ath9k_sw_scan_start,
  1938. .sw_scan_complete = ath9k_sw_scan_complete,
  1939. .channel_switch_beacon = ath9k_channel_switch_beacon,
  1940. };