at803x.c 6.2 KB

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  1. /*
  2. * drivers/net/phy/at803x.c
  3. *
  4. * Driver for Atheros 803x PHY
  5. *
  6. * Author: Matus Ujhelyi <ujhelyi.m@gmail.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of the GNU General Public License as published by the
  10. * Free Software Foundation; either version 2 of the License, or (at your
  11. * option) any later version.
  12. */
  13. #include <linux/phy.h>
  14. #include <linux/module.h>
  15. #include <linux/string.h>
  16. #include <linux/netdevice.h>
  17. #include <linux/etherdevice.h>
  18. #define AT803X_INTR_ENABLE 0x12
  19. #define AT803X_INTR_STATUS 0x13
  20. #define AT803X_WOL_ENABLE 0x01
  21. #define AT803X_DEVICE_ADDR 0x03
  22. #define AT803X_LOC_MAC_ADDR_0_15_OFFSET 0x804C
  23. #define AT803X_LOC_MAC_ADDR_16_31_OFFSET 0x804B
  24. #define AT803X_LOC_MAC_ADDR_32_47_OFFSET 0x804A
  25. #define AT803X_MMD_ACCESS_CONTROL 0x0D
  26. #define AT803X_MMD_ACCESS_CONTROL_DATA 0x0E
  27. #define AT803X_FUNC_DATA 0x4003
  28. #define AT803X_DEBUG_ADDR 0x1D
  29. #define AT803X_DEBUG_DATA 0x1E
  30. #define AT803X_DEBUG_SYSTEM_MODE_CTRL 0x05
  31. #define AT803X_DEBUG_RGMII_TX_CLK_DLY BIT(8)
  32. MODULE_DESCRIPTION("Atheros 803x PHY driver");
  33. MODULE_AUTHOR("Matus Ujhelyi");
  34. MODULE_LICENSE("GPL");
  35. static int at803x_set_wol(struct phy_device *phydev,
  36. struct ethtool_wolinfo *wol)
  37. {
  38. struct net_device *ndev = phydev->attached_dev;
  39. const u8 *mac;
  40. int ret;
  41. u32 value;
  42. unsigned int i, offsets[] = {
  43. AT803X_LOC_MAC_ADDR_32_47_OFFSET,
  44. AT803X_LOC_MAC_ADDR_16_31_OFFSET,
  45. AT803X_LOC_MAC_ADDR_0_15_OFFSET,
  46. };
  47. if (!ndev)
  48. return -ENODEV;
  49. if (wol->wolopts & WAKE_MAGIC) {
  50. mac = (const u8 *) ndev->dev_addr;
  51. if (!is_valid_ether_addr(mac))
  52. return -EFAULT;
  53. for (i = 0; i < 3; i++) {
  54. phy_write(phydev, AT803X_MMD_ACCESS_CONTROL,
  55. AT803X_DEVICE_ADDR);
  56. phy_write(phydev, AT803X_MMD_ACCESS_CONTROL_DATA,
  57. offsets[i]);
  58. phy_write(phydev, AT803X_MMD_ACCESS_CONTROL,
  59. AT803X_FUNC_DATA);
  60. phy_write(phydev, AT803X_MMD_ACCESS_CONTROL_DATA,
  61. mac[(i * 2) + 1] | (mac[(i * 2)] << 8));
  62. }
  63. value = phy_read(phydev, AT803X_INTR_ENABLE);
  64. value |= AT803X_WOL_ENABLE;
  65. ret = phy_write(phydev, AT803X_INTR_ENABLE, value);
  66. if (ret)
  67. return ret;
  68. value = phy_read(phydev, AT803X_INTR_STATUS);
  69. } else {
  70. value = phy_read(phydev, AT803X_INTR_ENABLE);
  71. value &= (~AT803X_WOL_ENABLE);
  72. ret = phy_write(phydev, AT803X_INTR_ENABLE, value);
  73. if (ret)
  74. return ret;
  75. value = phy_read(phydev, AT803X_INTR_STATUS);
  76. }
  77. return ret;
  78. }
  79. static void at803x_get_wol(struct phy_device *phydev,
  80. struct ethtool_wolinfo *wol)
  81. {
  82. u32 value;
  83. wol->supported = WAKE_MAGIC;
  84. wol->wolopts = 0;
  85. value = phy_read(phydev, AT803X_INTR_ENABLE);
  86. if (value & AT803X_WOL_ENABLE)
  87. wol->wolopts |= WAKE_MAGIC;
  88. }
  89. static int at803x_suspend(struct phy_device *phydev)
  90. {
  91. int value;
  92. int wol_enabled;
  93. mutex_lock(&phydev->lock);
  94. value = phy_read(phydev, AT803X_INTR_ENABLE);
  95. wol_enabled = value & AT803X_WOL_ENABLE;
  96. value = phy_read(phydev, MII_BMCR);
  97. if (wol_enabled)
  98. value |= BMCR_ISOLATE;
  99. else
  100. value |= BMCR_PDOWN;
  101. phy_write(phydev, MII_BMCR, value);
  102. mutex_unlock(&phydev->lock);
  103. return 0;
  104. }
  105. static int at803x_resume(struct phy_device *phydev)
  106. {
  107. int value;
  108. mutex_lock(&phydev->lock);
  109. value = phy_read(phydev, MII_BMCR);
  110. value &= ~(BMCR_PDOWN | BMCR_ISOLATE);
  111. phy_write(phydev, MII_BMCR, value);
  112. mutex_unlock(&phydev->lock);
  113. return 0;
  114. }
  115. static int at803x_config_init(struct phy_device *phydev)
  116. {
  117. int val;
  118. int ret;
  119. u32 features;
  120. features = SUPPORTED_TP | SUPPORTED_MII | SUPPORTED_AUI |
  121. SUPPORTED_FIBRE | SUPPORTED_BNC;
  122. val = phy_read(phydev, MII_BMSR);
  123. if (val < 0)
  124. return val;
  125. if (val & BMSR_ANEGCAPABLE)
  126. features |= SUPPORTED_Autoneg;
  127. if (val & BMSR_100FULL)
  128. features |= SUPPORTED_100baseT_Full;
  129. if (val & BMSR_100HALF)
  130. features |= SUPPORTED_100baseT_Half;
  131. if (val & BMSR_10FULL)
  132. features |= SUPPORTED_10baseT_Full;
  133. if (val & BMSR_10HALF)
  134. features |= SUPPORTED_10baseT_Half;
  135. if (val & BMSR_ESTATEN) {
  136. val = phy_read(phydev, MII_ESTATUS);
  137. if (val < 0)
  138. return val;
  139. if (val & ESTATUS_1000_TFULL)
  140. features |= SUPPORTED_1000baseT_Full;
  141. if (val & ESTATUS_1000_THALF)
  142. features |= SUPPORTED_1000baseT_Half;
  143. }
  144. phydev->supported = features;
  145. phydev->advertising = features;
  146. if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
  147. ret = phy_write(phydev, AT803X_DEBUG_ADDR,
  148. AT803X_DEBUG_SYSTEM_MODE_CTRL);
  149. if (ret)
  150. return ret;
  151. ret = phy_write(phydev, AT803X_DEBUG_DATA,
  152. AT803X_DEBUG_RGMII_TX_CLK_DLY);
  153. if (ret)
  154. return ret;
  155. }
  156. return 0;
  157. }
  158. static struct phy_driver at803x_driver[] = {
  159. {
  160. /* ATHEROS 8035 */
  161. .phy_id = 0x004dd072,
  162. .name = "Atheros 8035 ethernet",
  163. .phy_id_mask = 0xffffffef,
  164. .config_init = at803x_config_init,
  165. .set_wol = at803x_set_wol,
  166. .get_wol = at803x_get_wol,
  167. .suspend = at803x_suspend,
  168. .resume = at803x_resume,
  169. .features = PHY_GBIT_FEATURES,
  170. .flags = PHY_HAS_INTERRUPT,
  171. .config_aneg = genphy_config_aneg,
  172. .read_status = genphy_read_status,
  173. .driver = {
  174. .owner = THIS_MODULE,
  175. },
  176. }, {
  177. /* ATHEROS 8030 */
  178. .phy_id = 0x004dd076,
  179. .name = "Atheros 8030 ethernet",
  180. .phy_id_mask = 0xffffffef,
  181. .config_init = at803x_config_init,
  182. .set_wol = at803x_set_wol,
  183. .get_wol = at803x_get_wol,
  184. .suspend = at803x_suspend,
  185. .resume = at803x_resume,
  186. .features = PHY_GBIT_FEATURES,
  187. .flags = PHY_HAS_INTERRUPT,
  188. .config_aneg = genphy_config_aneg,
  189. .read_status = genphy_read_status,
  190. .driver = {
  191. .owner = THIS_MODULE,
  192. },
  193. }, {
  194. /* ATHEROS 8031 */
  195. .phy_id = 0x004dd074,
  196. .name = "Atheros 8031 ethernet",
  197. .phy_id_mask = 0xffffffef,
  198. .config_init = at803x_config_init,
  199. .set_wol = at803x_set_wol,
  200. .get_wol = at803x_get_wol,
  201. .suspend = at803x_suspend,
  202. .resume = at803x_resume,
  203. .features = PHY_GBIT_FEATURES,
  204. .flags = PHY_HAS_INTERRUPT,
  205. .config_aneg = genphy_config_aneg,
  206. .read_status = genphy_read_status,
  207. .driver = {
  208. .owner = THIS_MODULE,
  209. },
  210. } };
  211. static int __init atheros_init(void)
  212. {
  213. return phy_drivers_register(at803x_driver,
  214. ARRAY_SIZE(at803x_driver));
  215. }
  216. static void __exit atheros_exit(void)
  217. {
  218. return phy_drivers_unregister(at803x_driver,
  219. ARRAY_SIZE(at803x_driver));
  220. }
  221. module_init(atheros_init);
  222. module_exit(atheros_exit);
  223. static struct mdio_device_id __maybe_unused atheros_tbl[] = {
  224. { 0x004dd076, 0xffffffef },
  225. { 0x004dd074, 0xffffffef },
  226. { 0x004dd072, 0xffffffef },
  227. { }
  228. };
  229. MODULE_DEVICE_TABLE(mdio, atheros_tbl);