rx.c 28 KB

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  1. /****************************************************************************
  2. * Driver for Solarflare network controllers and boards
  3. * Copyright 2005-2006 Fen Systems Ltd.
  4. * Copyright 2005-2013 Solarflare Communications Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published
  8. * by the Free Software Foundation, incorporated herein by reference.
  9. */
  10. #include <linux/socket.h>
  11. #include <linux/in.h>
  12. #include <linux/slab.h>
  13. #include <linux/ip.h>
  14. #include <linux/ipv6.h>
  15. #include <linux/tcp.h>
  16. #include <linux/udp.h>
  17. #include <linux/prefetch.h>
  18. #include <linux/moduleparam.h>
  19. #include <linux/iommu.h>
  20. #include <net/ip.h>
  21. #include <net/checksum.h>
  22. #include "net_driver.h"
  23. #include "efx.h"
  24. #include "filter.h"
  25. #include "nic.h"
  26. #include "selftest.h"
  27. #include "workarounds.h"
  28. /* Preferred number of descriptors to fill at once */
  29. #define EFX_RX_PREFERRED_BATCH 8U
  30. /* Number of RX buffers to recycle pages for. When creating the RX page recycle
  31. * ring, this number is divided by the number of buffers per page to calculate
  32. * the number of pages to store in the RX page recycle ring.
  33. */
  34. #define EFX_RECYCLE_RING_SIZE_IOMMU 4096
  35. #define EFX_RECYCLE_RING_SIZE_NOIOMMU (2 * EFX_RX_PREFERRED_BATCH)
  36. /* Size of buffer allocated for skb header area. */
  37. #define EFX_SKB_HEADERS 128u
  38. /* This is the percentage fill level below which new RX descriptors
  39. * will be added to the RX descriptor ring.
  40. */
  41. static unsigned int rx_refill_threshold;
  42. /* Each packet can consume up to ceil(max_frame_len / buffer_size) buffers */
  43. #define EFX_RX_MAX_FRAGS DIV_ROUND_UP(EFX_MAX_FRAME_LEN(EFX_MAX_MTU), \
  44. EFX_RX_USR_BUF_SIZE)
  45. /*
  46. * RX maximum head room required.
  47. *
  48. * This must be at least 1 to prevent overflow, plus one packet-worth
  49. * to allow pipelined receives.
  50. */
  51. #define EFX_RXD_HEAD_ROOM (1 + EFX_RX_MAX_FRAGS)
  52. static inline u8 *efx_rx_buf_va(struct efx_rx_buffer *buf)
  53. {
  54. return page_address(buf->page) + buf->page_offset;
  55. }
  56. static inline u32 efx_rx_buf_hash(struct efx_nic *efx, const u8 *eh)
  57. {
  58. #if defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
  59. return __le32_to_cpup((const __le32 *)(eh + efx->rx_packet_hash_offset));
  60. #else
  61. const u8 *data = eh + efx->rx_packet_hash_offset;
  62. return (u32)data[0] |
  63. (u32)data[1] << 8 |
  64. (u32)data[2] << 16 |
  65. (u32)data[3] << 24;
  66. #endif
  67. }
  68. static inline struct efx_rx_buffer *
  69. efx_rx_buf_next(struct efx_rx_queue *rx_queue, struct efx_rx_buffer *rx_buf)
  70. {
  71. if (unlikely(rx_buf == efx_rx_buffer(rx_queue, rx_queue->ptr_mask)))
  72. return efx_rx_buffer(rx_queue, 0);
  73. else
  74. return rx_buf + 1;
  75. }
  76. static inline void efx_sync_rx_buffer(struct efx_nic *efx,
  77. struct efx_rx_buffer *rx_buf,
  78. unsigned int len)
  79. {
  80. dma_sync_single_for_cpu(&efx->pci_dev->dev, rx_buf->dma_addr, len,
  81. DMA_FROM_DEVICE);
  82. }
  83. void efx_rx_config_page_split(struct efx_nic *efx)
  84. {
  85. efx->rx_page_buf_step = ALIGN(efx->rx_dma_len + NET_IP_ALIGN,
  86. EFX_RX_BUF_ALIGNMENT);
  87. efx->rx_bufs_per_page = efx->rx_buffer_order ? 1 :
  88. ((PAGE_SIZE - sizeof(struct efx_rx_page_state)) /
  89. efx->rx_page_buf_step);
  90. efx->rx_buffer_truesize = (PAGE_SIZE << efx->rx_buffer_order) /
  91. efx->rx_bufs_per_page;
  92. efx->rx_pages_per_batch = DIV_ROUND_UP(EFX_RX_PREFERRED_BATCH,
  93. efx->rx_bufs_per_page);
  94. }
  95. /* Check the RX page recycle ring for a page that can be reused. */
  96. static struct page *efx_reuse_page(struct efx_rx_queue *rx_queue)
  97. {
  98. struct efx_nic *efx = rx_queue->efx;
  99. struct page *page;
  100. struct efx_rx_page_state *state;
  101. unsigned index;
  102. index = rx_queue->page_remove & rx_queue->page_ptr_mask;
  103. page = rx_queue->page_ring[index];
  104. if (page == NULL)
  105. return NULL;
  106. rx_queue->page_ring[index] = NULL;
  107. /* page_remove cannot exceed page_add. */
  108. if (rx_queue->page_remove != rx_queue->page_add)
  109. ++rx_queue->page_remove;
  110. /* If page_count is 1 then we hold the only reference to this page. */
  111. if (page_count(page) == 1) {
  112. ++rx_queue->page_recycle_count;
  113. return page;
  114. } else {
  115. state = page_address(page);
  116. dma_unmap_page(&efx->pci_dev->dev, state->dma_addr,
  117. PAGE_SIZE << efx->rx_buffer_order,
  118. DMA_FROM_DEVICE);
  119. put_page(page);
  120. ++rx_queue->page_recycle_failed;
  121. }
  122. return NULL;
  123. }
  124. /**
  125. * efx_init_rx_buffers - create EFX_RX_BATCH page-based RX buffers
  126. *
  127. * @rx_queue: Efx RX queue
  128. *
  129. * This allocates a batch of pages, maps them for DMA, and populates
  130. * struct efx_rx_buffers for each one. Return a negative error code or
  131. * 0 on success. If a single page can be used for multiple buffers,
  132. * then the page will either be inserted fully, or not at all.
  133. */
  134. static int efx_init_rx_buffers(struct efx_rx_queue *rx_queue)
  135. {
  136. struct efx_nic *efx = rx_queue->efx;
  137. struct efx_rx_buffer *rx_buf;
  138. struct page *page;
  139. unsigned int page_offset;
  140. struct efx_rx_page_state *state;
  141. dma_addr_t dma_addr;
  142. unsigned index, count;
  143. count = 0;
  144. do {
  145. page = efx_reuse_page(rx_queue);
  146. if (page == NULL) {
  147. page = alloc_pages(__GFP_COLD | __GFP_COMP | GFP_ATOMIC,
  148. efx->rx_buffer_order);
  149. if (unlikely(page == NULL))
  150. return -ENOMEM;
  151. dma_addr =
  152. dma_map_page(&efx->pci_dev->dev, page, 0,
  153. PAGE_SIZE << efx->rx_buffer_order,
  154. DMA_FROM_DEVICE);
  155. if (unlikely(dma_mapping_error(&efx->pci_dev->dev,
  156. dma_addr))) {
  157. __free_pages(page, efx->rx_buffer_order);
  158. return -EIO;
  159. }
  160. state = page_address(page);
  161. state->dma_addr = dma_addr;
  162. } else {
  163. state = page_address(page);
  164. dma_addr = state->dma_addr;
  165. }
  166. dma_addr += sizeof(struct efx_rx_page_state);
  167. page_offset = sizeof(struct efx_rx_page_state);
  168. do {
  169. index = rx_queue->added_count & rx_queue->ptr_mask;
  170. rx_buf = efx_rx_buffer(rx_queue, index);
  171. rx_buf->dma_addr = dma_addr + NET_IP_ALIGN;
  172. rx_buf->page = page;
  173. rx_buf->page_offset = page_offset + NET_IP_ALIGN;
  174. rx_buf->len = efx->rx_dma_len;
  175. rx_buf->flags = 0;
  176. ++rx_queue->added_count;
  177. get_page(page);
  178. dma_addr += efx->rx_page_buf_step;
  179. page_offset += efx->rx_page_buf_step;
  180. } while (page_offset + efx->rx_page_buf_step <= PAGE_SIZE);
  181. rx_buf->flags = EFX_RX_BUF_LAST_IN_PAGE;
  182. } while (++count < efx->rx_pages_per_batch);
  183. return 0;
  184. }
  185. /* Unmap a DMA-mapped page. This function is only called for the final RX
  186. * buffer in a page.
  187. */
  188. static void efx_unmap_rx_buffer(struct efx_nic *efx,
  189. struct efx_rx_buffer *rx_buf)
  190. {
  191. struct page *page = rx_buf->page;
  192. if (page) {
  193. struct efx_rx_page_state *state = page_address(page);
  194. dma_unmap_page(&efx->pci_dev->dev,
  195. state->dma_addr,
  196. PAGE_SIZE << efx->rx_buffer_order,
  197. DMA_FROM_DEVICE);
  198. }
  199. }
  200. static void efx_free_rx_buffer(struct efx_rx_buffer *rx_buf)
  201. {
  202. if (rx_buf->page) {
  203. put_page(rx_buf->page);
  204. rx_buf->page = NULL;
  205. }
  206. }
  207. /* Attempt to recycle the page if there is an RX recycle ring; the page can
  208. * only be added if this is the final RX buffer, to prevent pages being used in
  209. * the descriptor ring and appearing in the recycle ring simultaneously.
  210. */
  211. static void efx_recycle_rx_page(struct efx_channel *channel,
  212. struct efx_rx_buffer *rx_buf)
  213. {
  214. struct page *page = rx_buf->page;
  215. struct efx_rx_queue *rx_queue = efx_channel_get_rx_queue(channel);
  216. struct efx_nic *efx = rx_queue->efx;
  217. unsigned index;
  218. /* Only recycle the page after processing the final buffer. */
  219. if (!(rx_buf->flags & EFX_RX_BUF_LAST_IN_PAGE))
  220. return;
  221. index = rx_queue->page_add & rx_queue->page_ptr_mask;
  222. if (rx_queue->page_ring[index] == NULL) {
  223. unsigned read_index = rx_queue->page_remove &
  224. rx_queue->page_ptr_mask;
  225. /* The next slot in the recycle ring is available, but
  226. * increment page_remove if the read pointer currently
  227. * points here.
  228. */
  229. if (read_index == index)
  230. ++rx_queue->page_remove;
  231. rx_queue->page_ring[index] = page;
  232. ++rx_queue->page_add;
  233. return;
  234. }
  235. ++rx_queue->page_recycle_full;
  236. efx_unmap_rx_buffer(efx, rx_buf);
  237. put_page(rx_buf->page);
  238. }
  239. static void efx_fini_rx_buffer(struct efx_rx_queue *rx_queue,
  240. struct efx_rx_buffer *rx_buf)
  241. {
  242. /* Release the page reference we hold for the buffer. */
  243. if (rx_buf->page)
  244. put_page(rx_buf->page);
  245. /* If this is the last buffer in a page, unmap and free it. */
  246. if (rx_buf->flags & EFX_RX_BUF_LAST_IN_PAGE) {
  247. efx_unmap_rx_buffer(rx_queue->efx, rx_buf);
  248. efx_free_rx_buffer(rx_buf);
  249. }
  250. rx_buf->page = NULL;
  251. }
  252. /* Recycle the pages that are used by buffers that have just been received. */
  253. static void efx_recycle_rx_pages(struct efx_channel *channel,
  254. struct efx_rx_buffer *rx_buf,
  255. unsigned int n_frags)
  256. {
  257. struct efx_rx_queue *rx_queue = efx_channel_get_rx_queue(channel);
  258. do {
  259. efx_recycle_rx_page(channel, rx_buf);
  260. rx_buf = efx_rx_buf_next(rx_queue, rx_buf);
  261. } while (--n_frags);
  262. }
  263. static void efx_discard_rx_packet(struct efx_channel *channel,
  264. struct efx_rx_buffer *rx_buf,
  265. unsigned int n_frags)
  266. {
  267. struct efx_rx_queue *rx_queue = efx_channel_get_rx_queue(channel);
  268. efx_recycle_rx_pages(channel, rx_buf, n_frags);
  269. do {
  270. efx_free_rx_buffer(rx_buf);
  271. rx_buf = efx_rx_buf_next(rx_queue, rx_buf);
  272. } while (--n_frags);
  273. }
  274. /**
  275. * efx_fast_push_rx_descriptors - push new RX descriptors quickly
  276. * @rx_queue: RX descriptor queue
  277. *
  278. * This will aim to fill the RX descriptor queue up to
  279. * @rx_queue->@max_fill. If there is insufficient atomic
  280. * memory to do so, a slow fill will be scheduled.
  281. *
  282. * The caller must provide serialisation (none is used here). In practise,
  283. * this means this function must run from the NAPI handler, or be called
  284. * when NAPI is disabled.
  285. */
  286. void efx_fast_push_rx_descriptors(struct efx_rx_queue *rx_queue)
  287. {
  288. struct efx_nic *efx = rx_queue->efx;
  289. unsigned int fill_level, batch_size;
  290. int space, rc = 0;
  291. if (!rx_queue->refill_enabled)
  292. return;
  293. /* Calculate current fill level, and exit if we don't need to fill */
  294. fill_level = (rx_queue->added_count - rx_queue->removed_count);
  295. EFX_BUG_ON_PARANOID(fill_level > rx_queue->efx->rxq_entries);
  296. if (fill_level >= rx_queue->fast_fill_trigger)
  297. goto out;
  298. /* Record minimum fill level */
  299. if (unlikely(fill_level < rx_queue->min_fill)) {
  300. if (fill_level)
  301. rx_queue->min_fill = fill_level;
  302. }
  303. batch_size = efx->rx_pages_per_batch * efx->rx_bufs_per_page;
  304. space = rx_queue->max_fill - fill_level;
  305. EFX_BUG_ON_PARANOID(space < batch_size);
  306. netif_vdbg(rx_queue->efx, rx_status, rx_queue->efx->net_dev,
  307. "RX queue %d fast-filling descriptor ring from"
  308. " level %d to level %d\n",
  309. efx_rx_queue_index(rx_queue), fill_level,
  310. rx_queue->max_fill);
  311. do {
  312. rc = efx_init_rx_buffers(rx_queue);
  313. if (unlikely(rc)) {
  314. /* Ensure that we don't leave the rx queue empty */
  315. if (rx_queue->added_count == rx_queue->removed_count)
  316. efx_schedule_slow_fill(rx_queue);
  317. goto out;
  318. }
  319. } while ((space -= batch_size) >= batch_size);
  320. netif_vdbg(rx_queue->efx, rx_status, rx_queue->efx->net_dev,
  321. "RX queue %d fast-filled descriptor ring "
  322. "to level %d\n", efx_rx_queue_index(rx_queue),
  323. rx_queue->added_count - rx_queue->removed_count);
  324. out:
  325. if (rx_queue->notified_count != rx_queue->added_count)
  326. efx_nic_notify_rx_desc(rx_queue);
  327. }
  328. void efx_rx_slow_fill(unsigned long context)
  329. {
  330. struct efx_rx_queue *rx_queue = (struct efx_rx_queue *)context;
  331. /* Post an event to cause NAPI to run and refill the queue */
  332. efx_nic_generate_fill_event(rx_queue);
  333. ++rx_queue->slow_fill_count;
  334. }
  335. static void efx_rx_packet__check_len(struct efx_rx_queue *rx_queue,
  336. struct efx_rx_buffer *rx_buf,
  337. int len)
  338. {
  339. struct efx_nic *efx = rx_queue->efx;
  340. unsigned max_len = rx_buf->len - efx->type->rx_buffer_padding;
  341. if (likely(len <= max_len))
  342. return;
  343. /* The packet must be discarded, but this is only a fatal error
  344. * if the caller indicated it was
  345. */
  346. rx_buf->flags |= EFX_RX_PKT_DISCARD;
  347. if ((len > rx_buf->len) && EFX_WORKAROUND_8071(efx)) {
  348. if (net_ratelimit())
  349. netif_err(efx, rx_err, efx->net_dev,
  350. " RX queue %d seriously overlength "
  351. "RX event (0x%x > 0x%x+0x%x). Leaking\n",
  352. efx_rx_queue_index(rx_queue), len, max_len,
  353. efx->type->rx_buffer_padding);
  354. efx_schedule_reset(efx, RESET_TYPE_RX_RECOVERY);
  355. } else {
  356. if (net_ratelimit())
  357. netif_err(efx, rx_err, efx->net_dev,
  358. " RX queue %d overlength RX event "
  359. "(0x%x > 0x%x)\n",
  360. efx_rx_queue_index(rx_queue), len, max_len);
  361. }
  362. efx_rx_queue_channel(rx_queue)->n_rx_overlength++;
  363. }
  364. /* Pass a received packet up through GRO. GRO can handle pages
  365. * regardless of checksum state and skbs with a good checksum.
  366. */
  367. static void
  368. efx_rx_packet_gro(struct efx_channel *channel, struct efx_rx_buffer *rx_buf,
  369. unsigned int n_frags, u8 *eh)
  370. {
  371. struct napi_struct *napi = &channel->napi_str;
  372. gro_result_t gro_result;
  373. struct efx_nic *efx = channel->efx;
  374. struct sk_buff *skb;
  375. skb = napi_get_frags(napi);
  376. if (unlikely(!skb)) {
  377. while (n_frags--) {
  378. put_page(rx_buf->page);
  379. rx_buf->page = NULL;
  380. rx_buf = efx_rx_buf_next(&channel->rx_queue, rx_buf);
  381. }
  382. return;
  383. }
  384. if (efx->net_dev->features & NETIF_F_RXHASH)
  385. skb->rxhash = efx_rx_buf_hash(efx, eh);
  386. skb->ip_summed = ((rx_buf->flags & EFX_RX_PKT_CSUMMED) ?
  387. CHECKSUM_UNNECESSARY : CHECKSUM_NONE);
  388. for (;;) {
  389. skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
  390. rx_buf->page, rx_buf->page_offset,
  391. rx_buf->len);
  392. rx_buf->page = NULL;
  393. skb->len += rx_buf->len;
  394. if (skb_shinfo(skb)->nr_frags == n_frags)
  395. break;
  396. rx_buf = efx_rx_buf_next(&channel->rx_queue, rx_buf);
  397. }
  398. skb->data_len = skb->len;
  399. skb->truesize += n_frags * efx->rx_buffer_truesize;
  400. skb_record_rx_queue(skb, channel->rx_queue.core_index);
  401. gro_result = napi_gro_frags(napi);
  402. if (gro_result != GRO_DROP)
  403. channel->irq_mod_score += 2;
  404. }
  405. /* Allocate and construct an SKB around page fragments */
  406. static struct sk_buff *efx_rx_mk_skb(struct efx_channel *channel,
  407. struct efx_rx_buffer *rx_buf,
  408. unsigned int n_frags,
  409. u8 *eh, int hdr_len)
  410. {
  411. struct efx_nic *efx = channel->efx;
  412. struct sk_buff *skb;
  413. /* Allocate an SKB to store the headers */
  414. skb = netdev_alloc_skb(efx->net_dev, hdr_len + EFX_PAGE_SKB_ALIGN);
  415. if (unlikely(skb == NULL))
  416. return NULL;
  417. EFX_BUG_ON_PARANOID(rx_buf->len < hdr_len);
  418. skb_reserve(skb, EFX_PAGE_SKB_ALIGN);
  419. memcpy(__skb_put(skb, hdr_len), eh, hdr_len);
  420. /* Append the remaining page(s) onto the frag list */
  421. if (rx_buf->len > hdr_len) {
  422. rx_buf->page_offset += hdr_len;
  423. rx_buf->len -= hdr_len;
  424. for (;;) {
  425. skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
  426. rx_buf->page, rx_buf->page_offset,
  427. rx_buf->len);
  428. rx_buf->page = NULL;
  429. skb->len += rx_buf->len;
  430. skb->data_len += rx_buf->len;
  431. if (skb_shinfo(skb)->nr_frags == n_frags)
  432. break;
  433. rx_buf = efx_rx_buf_next(&channel->rx_queue, rx_buf);
  434. }
  435. } else {
  436. __free_pages(rx_buf->page, efx->rx_buffer_order);
  437. rx_buf->page = NULL;
  438. n_frags = 0;
  439. }
  440. skb->truesize += n_frags * efx->rx_buffer_truesize;
  441. /* Move past the ethernet header */
  442. skb->protocol = eth_type_trans(skb, efx->net_dev);
  443. return skb;
  444. }
  445. void efx_rx_packet(struct efx_rx_queue *rx_queue, unsigned int index,
  446. unsigned int n_frags, unsigned int len, u16 flags)
  447. {
  448. struct efx_nic *efx = rx_queue->efx;
  449. struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
  450. struct efx_rx_buffer *rx_buf;
  451. rx_buf = efx_rx_buffer(rx_queue, index);
  452. rx_buf->flags |= flags;
  453. /* Validate the number of fragments and completed length */
  454. if (n_frags == 1) {
  455. if (!(flags & EFX_RX_PKT_PREFIX_LEN))
  456. efx_rx_packet__check_len(rx_queue, rx_buf, len);
  457. } else if (unlikely(n_frags > EFX_RX_MAX_FRAGS) ||
  458. unlikely(len <= (n_frags - 1) * efx->rx_dma_len) ||
  459. unlikely(len > n_frags * efx->rx_dma_len) ||
  460. unlikely(!efx->rx_scatter)) {
  461. /* If this isn't an explicit discard request, either
  462. * the hardware or the driver is broken.
  463. */
  464. WARN_ON(!(len == 0 && rx_buf->flags & EFX_RX_PKT_DISCARD));
  465. rx_buf->flags |= EFX_RX_PKT_DISCARD;
  466. }
  467. netif_vdbg(efx, rx_status, efx->net_dev,
  468. "RX queue %d received ids %x-%x len %d %s%s\n",
  469. efx_rx_queue_index(rx_queue), index,
  470. (index + n_frags - 1) & rx_queue->ptr_mask, len,
  471. (rx_buf->flags & EFX_RX_PKT_CSUMMED) ? " [SUMMED]" : "",
  472. (rx_buf->flags & EFX_RX_PKT_DISCARD) ? " [DISCARD]" : "");
  473. /* Discard packet, if instructed to do so. Process the
  474. * previous receive first.
  475. */
  476. if (unlikely(rx_buf->flags & EFX_RX_PKT_DISCARD)) {
  477. efx_rx_flush_packet(channel);
  478. efx_discard_rx_packet(channel, rx_buf, n_frags);
  479. return;
  480. }
  481. if (n_frags == 1 && !(flags & EFX_RX_PKT_PREFIX_LEN))
  482. rx_buf->len = len;
  483. /* Release and/or sync the DMA mapping - assumes all RX buffers
  484. * consumed in-order per RX queue.
  485. */
  486. efx_sync_rx_buffer(efx, rx_buf, rx_buf->len);
  487. /* Prefetch nice and early so data will (hopefully) be in cache by
  488. * the time we look at it.
  489. */
  490. prefetch(efx_rx_buf_va(rx_buf));
  491. rx_buf->page_offset += efx->rx_prefix_size;
  492. rx_buf->len -= efx->rx_prefix_size;
  493. if (n_frags > 1) {
  494. /* Release/sync DMA mapping for additional fragments.
  495. * Fix length for last fragment.
  496. */
  497. unsigned int tail_frags = n_frags - 1;
  498. for (;;) {
  499. rx_buf = efx_rx_buf_next(rx_queue, rx_buf);
  500. if (--tail_frags == 0)
  501. break;
  502. efx_sync_rx_buffer(efx, rx_buf, efx->rx_dma_len);
  503. }
  504. rx_buf->len = len - (n_frags - 1) * efx->rx_dma_len;
  505. efx_sync_rx_buffer(efx, rx_buf, rx_buf->len);
  506. }
  507. /* All fragments have been DMA-synced, so recycle pages. */
  508. rx_buf = efx_rx_buffer(rx_queue, index);
  509. efx_recycle_rx_pages(channel, rx_buf, n_frags);
  510. /* Pipeline receives so that we give time for packet headers to be
  511. * prefetched into cache.
  512. */
  513. efx_rx_flush_packet(channel);
  514. channel->rx_pkt_n_frags = n_frags;
  515. channel->rx_pkt_index = index;
  516. }
  517. static void efx_rx_deliver(struct efx_channel *channel, u8 *eh,
  518. struct efx_rx_buffer *rx_buf,
  519. unsigned int n_frags)
  520. {
  521. struct sk_buff *skb;
  522. u16 hdr_len = min_t(u16, rx_buf->len, EFX_SKB_HEADERS);
  523. skb = efx_rx_mk_skb(channel, rx_buf, n_frags, eh, hdr_len);
  524. if (unlikely(skb == NULL)) {
  525. efx_free_rx_buffer(rx_buf);
  526. return;
  527. }
  528. skb_record_rx_queue(skb, channel->rx_queue.core_index);
  529. /* Set the SKB flags */
  530. skb_checksum_none_assert(skb);
  531. if (likely(rx_buf->flags & EFX_RX_PKT_CSUMMED))
  532. skb->ip_summed = CHECKSUM_UNNECESSARY;
  533. if (channel->type->receive_skb)
  534. if (channel->type->receive_skb(channel, skb))
  535. return;
  536. /* Pass the packet up */
  537. netif_receive_skb(skb);
  538. }
  539. /* Handle a received packet. Second half: Touches packet payload. */
  540. void __efx_rx_packet(struct efx_channel *channel)
  541. {
  542. struct efx_nic *efx = channel->efx;
  543. struct efx_rx_buffer *rx_buf =
  544. efx_rx_buffer(&channel->rx_queue, channel->rx_pkt_index);
  545. u8 *eh = efx_rx_buf_va(rx_buf);
  546. /* Read length from the prefix if necessary. This already
  547. * excludes the length of the prefix itself.
  548. */
  549. if (rx_buf->flags & EFX_RX_PKT_PREFIX_LEN)
  550. rx_buf->len = le16_to_cpup((__le16 *)
  551. (eh + efx->rx_packet_len_offset));
  552. /* If we're in loopback test, then pass the packet directly to the
  553. * loopback layer, and free the rx_buf here
  554. */
  555. if (unlikely(efx->loopback_selftest)) {
  556. efx_loopback_rx_packet(efx, eh, rx_buf->len);
  557. efx_free_rx_buffer(rx_buf);
  558. goto out;
  559. }
  560. if (unlikely(!(efx->net_dev->features & NETIF_F_RXCSUM)))
  561. rx_buf->flags &= ~EFX_RX_PKT_CSUMMED;
  562. if ((rx_buf->flags & EFX_RX_PKT_TCP) && !channel->type->receive_skb)
  563. efx_rx_packet_gro(channel, rx_buf, channel->rx_pkt_n_frags, eh);
  564. else
  565. efx_rx_deliver(channel, eh, rx_buf, channel->rx_pkt_n_frags);
  566. out:
  567. channel->rx_pkt_n_frags = 0;
  568. }
  569. int efx_probe_rx_queue(struct efx_rx_queue *rx_queue)
  570. {
  571. struct efx_nic *efx = rx_queue->efx;
  572. unsigned int entries;
  573. int rc;
  574. /* Create the smallest power-of-two aligned ring */
  575. entries = max(roundup_pow_of_two(efx->rxq_entries), EFX_MIN_DMAQ_SIZE);
  576. EFX_BUG_ON_PARANOID(entries > EFX_MAX_DMAQ_SIZE);
  577. rx_queue->ptr_mask = entries - 1;
  578. netif_dbg(efx, probe, efx->net_dev,
  579. "creating RX queue %d size %#x mask %#x\n",
  580. efx_rx_queue_index(rx_queue), efx->rxq_entries,
  581. rx_queue->ptr_mask);
  582. /* Allocate RX buffers */
  583. rx_queue->buffer = kcalloc(entries, sizeof(*rx_queue->buffer),
  584. GFP_KERNEL);
  585. if (!rx_queue->buffer)
  586. return -ENOMEM;
  587. rc = efx_nic_probe_rx(rx_queue);
  588. if (rc) {
  589. kfree(rx_queue->buffer);
  590. rx_queue->buffer = NULL;
  591. }
  592. return rc;
  593. }
  594. static void efx_init_rx_recycle_ring(struct efx_nic *efx,
  595. struct efx_rx_queue *rx_queue)
  596. {
  597. unsigned int bufs_in_recycle_ring, page_ring_size;
  598. /* Set the RX recycle ring size */
  599. #ifdef CONFIG_PPC64
  600. bufs_in_recycle_ring = EFX_RECYCLE_RING_SIZE_IOMMU;
  601. #else
  602. if (iommu_present(&pci_bus_type))
  603. bufs_in_recycle_ring = EFX_RECYCLE_RING_SIZE_IOMMU;
  604. else
  605. bufs_in_recycle_ring = EFX_RECYCLE_RING_SIZE_NOIOMMU;
  606. #endif /* CONFIG_PPC64 */
  607. page_ring_size = roundup_pow_of_two(bufs_in_recycle_ring /
  608. efx->rx_bufs_per_page);
  609. rx_queue->page_ring = kcalloc(page_ring_size,
  610. sizeof(*rx_queue->page_ring), GFP_KERNEL);
  611. rx_queue->page_ptr_mask = page_ring_size - 1;
  612. }
  613. void efx_init_rx_queue(struct efx_rx_queue *rx_queue)
  614. {
  615. struct efx_nic *efx = rx_queue->efx;
  616. unsigned int max_fill, trigger, max_trigger;
  617. netif_dbg(rx_queue->efx, drv, rx_queue->efx->net_dev,
  618. "initialising RX queue %d\n", efx_rx_queue_index(rx_queue));
  619. /* Initialise ptr fields */
  620. rx_queue->added_count = 0;
  621. rx_queue->notified_count = 0;
  622. rx_queue->removed_count = 0;
  623. rx_queue->min_fill = -1U;
  624. efx_init_rx_recycle_ring(efx, rx_queue);
  625. rx_queue->page_remove = 0;
  626. rx_queue->page_add = rx_queue->page_ptr_mask + 1;
  627. rx_queue->page_recycle_count = 0;
  628. rx_queue->page_recycle_failed = 0;
  629. rx_queue->page_recycle_full = 0;
  630. /* Initialise limit fields */
  631. max_fill = efx->rxq_entries - EFX_RXD_HEAD_ROOM;
  632. max_trigger =
  633. max_fill - efx->rx_pages_per_batch * efx->rx_bufs_per_page;
  634. if (rx_refill_threshold != 0) {
  635. trigger = max_fill * min(rx_refill_threshold, 100U) / 100U;
  636. if (trigger > max_trigger)
  637. trigger = max_trigger;
  638. } else {
  639. trigger = max_trigger;
  640. }
  641. rx_queue->max_fill = max_fill;
  642. rx_queue->fast_fill_trigger = trigger;
  643. rx_queue->refill_enabled = true;
  644. /* Set up RX descriptor ring */
  645. efx_nic_init_rx(rx_queue);
  646. }
  647. void efx_fini_rx_queue(struct efx_rx_queue *rx_queue)
  648. {
  649. int i;
  650. struct efx_nic *efx = rx_queue->efx;
  651. struct efx_rx_buffer *rx_buf;
  652. netif_dbg(rx_queue->efx, drv, rx_queue->efx->net_dev,
  653. "shutting down RX queue %d\n", efx_rx_queue_index(rx_queue));
  654. del_timer_sync(&rx_queue->slow_fill);
  655. /* Release RX buffers from the current read ptr to the write ptr */
  656. if (rx_queue->buffer) {
  657. for (i = rx_queue->removed_count; i < rx_queue->added_count;
  658. i++) {
  659. unsigned index = i & rx_queue->ptr_mask;
  660. rx_buf = efx_rx_buffer(rx_queue, index);
  661. efx_fini_rx_buffer(rx_queue, rx_buf);
  662. }
  663. }
  664. /* Unmap and release the pages in the recycle ring. Remove the ring. */
  665. for (i = 0; i <= rx_queue->page_ptr_mask; i++) {
  666. struct page *page = rx_queue->page_ring[i];
  667. struct efx_rx_page_state *state;
  668. if (page == NULL)
  669. continue;
  670. state = page_address(page);
  671. dma_unmap_page(&efx->pci_dev->dev, state->dma_addr,
  672. PAGE_SIZE << efx->rx_buffer_order,
  673. DMA_FROM_DEVICE);
  674. put_page(page);
  675. }
  676. kfree(rx_queue->page_ring);
  677. rx_queue->page_ring = NULL;
  678. }
  679. void efx_remove_rx_queue(struct efx_rx_queue *rx_queue)
  680. {
  681. netif_dbg(rx_queue->efx, drv, rx_queue->efx->net_dev,
  682. "destroying RX queue %d\n", efx_rx_queue_index(rx_queue));
  683. efx_nic_remove_rx(rx_queue);
  684. kfree(rx_queue->buffer);
  685. rx_queue->buffer = NULL;
  686. }
  687. module_param(rx_refill_threshold, uint, 0444);
  688. MODULE_PARM_DESC(rx_refill_threshold,
  689. "RX descriptor ring refill threshold (%)");
  690. #ifdef CONFIG_RFS_ACCEL
  691. int efx_filter_rfs(struct net_device *net_dev, const struct sk_buff *skb,
  692. u16 rxq_index, u32 flow_id)
  693. {
  694. struct efx_nic *efx = netdev_priv(net_dev);
  695. struct efx_channel *channel;
  696. struct efx_filter_spec spec;
  697. const __be16 *ports;
  698. __be16 ether_type;
  699. int nhoff;
  700. int rc;
  701. /* The core RPS/RFS code has already parsed and validated
  702. * VLAN, IP and transport headers. We assume they are in the
  703. * header area.
  704. */
  705. if (skb->protocol == htons(ETH_P_8021Q)) {
  706. const struct vlan_hdr *vh =
  707. (const struct vlan_hdr *)skb->data;
  708. /* We can't filter on the IP 5-tuple and the vlan
  709. * together, so just strip the vlan header and filter
  710. * on the IP part.
  711. */
  712. EFX_BUG_ON_PARANOID(skb_headlen(skb) < sizeof(*vh));
  713. ether_type = vh->h_vlan_encapsulated_proto;
  714. nhoff = sizeof(struct vlan_hdr);
  715. } else {
  716. ether_type = skb->protocol;
  717. nhoff = 0;
  718. }
  719. if (ether_type != htons(ETH_P_IP) && ether_type != htons(ETH_P_IPV6))
  720. return -EPROTONOSUPPORT;
  721. efx_filter_init_rx(&spec, EFX_FILTER_PRI_HINT,
  722. efx->rx_scatter ? EFX_FILTER_FLAG_RX_SCATTER : 0,
  723. rxq_index);
  724. spec.match_flags =
  725. EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_IP_PROTO |
  726. EFX_FILTER_MATCH_LOC_HOST | EFX_FILTER_MATCH_LOC_PORT |
  727. EFX_FILTER_MATCH_REM_HOST | EFX_FILTER_MATCH_REM_PORT;
  728. spec.ether_type = ether_type;
  729. if (ether_type == htons(ETH_P_IP)) {
  730. const struct iphdr *ip =
  731. (const struct iphdr *)(skb->data + nhoff);
  732. EFX_BUG_ON_PARANOID(skb_headlen(skb) < nhoff + sizeof(*ip));
  733. if (ip_is_fragment(ip))
  734. return -EPROTONOSUPPORT;
  735. spec.ip_proto = ip->protocol;
  736. spec.rem_host[0] = ip->saddr;
  737. spec.loc_host[0] = ip->daddr;
  738. EFX_BUG_ON_PARANOID(skb_headlen(skb) < nhoff + 4 * ip->ihl + 4);
  739. ports = (const __be16 *)(skb->data + nhoff + 4 * ip->ihl);
  740. } else {
  741. const struct ipv6hdr *ip6 =
  742. (const struct ipv6hdr *)(skb->data + nhoff);
  743. EFX_BUG_ON_PARANOID(skb_headlen(skb) <
  744. nhoff + sizeof(*ip6) + 4);
  745. spec.ip_proto = ip6->nexthdr;
  746. memcpy(spec.rem_host, &ip6->saddr, sizeof(ip6->saddr));
  747. memcpy(spec.loc_host, &ip6->daddr, sizeof(ip6->daddr));
  748. ports = (const __be16 *)(ip6 + 1);
  749. }
  750. spec.rem_port = ports[0];
  751. spec.loc_port = ports[1];
  752. rc = efx->type->filter_rfs_insert(efx, &spec);
  753. if (rc < 0)
  754. return rc;
  755. /* Remember this so we can check whether to expire the filter later */
  756. efx->rps_flow_id[rc] = flow_id;
  757. channel = efx_get_channel(efx, skb_get_rx_queue(skb));
  758. ++channel->rfs_filters_added;
  759. if (ether_type == htons(ETH_P_IP))
  760. netif_info(efx, rx_status, efx->net_dev,
  761. "steering %s %pI4:%u:%pI4:%u to queue %u [flow %u filter %d]\n",
  762. (spec.ip_proto == IPPROTO_TCP) ? "TCP" : "UDP",
  763. spec.rem_host, ntohs(ports[0]), spec.loc_host,
  764. ntohs(ports[1]), rxq_index, flow_id, rc);
  765. else
  766. netif_info(efx, rx_status, efx->net_dev,
  767. "steering %s [%pI6]:%u:[%pI6]:%u to queue %u [flow %u filter %d]\n",
  768. (spec.ip_proto == IPPROTO_TCP) ? "TCP" : "UDP",
  769. spec.rem_host, ntohs(ports[0]), spec.loc_host,
  770. ntohs(ports[1]), rxq_index, flow_id, rc);
  771. return rc;
  772. }
  773. bool __efx_filter_rfs_expire(struct efx_nic *efx, unsigned int quota)
  774. {
  775. bool (*expire_one)(struct efx_nic *efx, u32 flow_id, unsigned int index);
  776. unsigned int index, size;
  777. u32 flow_id;
  778. if (!spin_trylock_bh(&efx->filter_lock))
  779. return false;
  780. expire_one = efx->type->filter_rfs_expire_one;
  781. index = efx->rps_expire_index;
  782. size = efx->type->max_rx_ip_filters;
  783. while (quota--) {
  784. flow_id = efx->rps_flow_id[index];
  785. if (expire_one(efx, flow_id, index))
  786. netif_info(efx, rx_status, efx->net_dev,
  787. "expired filter %d [flow %u]\n",
  788. index, flow_id);
  789. if (++index == size)
  790. index = 0;
  791. }
  792. efx->rps_expire_index = index;
  793. spin_unlock_bh(&efx->filter_lock);
  794. return true;
  795. }
  796. #endif /* CONFIG_RFS_ACCEL */
  797. /**
  798. * efx_filter_is_mc_recipient - test whether spec is a multicast recipient
  799. * @spec: Specification to test
  800. *
  801. * Return: %true if the specification is a non-drop RX filter that
  802. * matches a local MAC address I/G bit value of 1 or matches a local
  803. * IPv4 or IPv6 address value in the respective multicast address
  804. * range. Otherwise %false.
  805. */
  806. bool efx_filter_is_mc_recipient(const struct efx_filter_spec *spec)
  807. {
  808. if (!(spec->flags & EFX_FILTER_FLAG_RX) ||
  809. spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP)
  810. return false;
  811. if (spec->match_flags &
  812. (EFX_FILTER_MATCH_LOC_MAC | EFX_FILTER_MATCH_LOC_MAC_IG) &&
  813. is_multicast_ether_addr(spec->loc_mac))
  814. return true;
  815. if ((spec->match_flags &
  816. (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) ==
  817. (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) {
  818. if (spec->ether_type == htons(ETH_P_IP) &&
  819. ipv4_is_multicast(spec->loc_host[0]))
  820. return true;
  821. if (spec->ether_type == htons(ETH_P_IPV6) &&
  822. ((const u8 *)spec->loc_host)[0] == 0xff)
  823. return true;
  824. }
  825. return false;
  826. }