gianfar.c 89 KB

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  1. /* drivers/net/ethernet/freescale/gianfar.c
  2. *
  3. * Gianfar Ethernet Driver
  4. * This driver is designed for the non-CPM ethernet controllers
  5. * on the 85xx and 83xx family of integrated processors
  6. * Based on 8260_io/fcc_enet.c
  7. *
  8. * Author: Andy Fleming
  9. * Maintainer: Kumar Gala
  10. * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
  11. *
  12. * Copyright 2002-2009, 2011 Freescale Semiconductor, Inc.
  13. * Copyright 2007 MontaVista Software, Inc.
  14. *
  15. * This program is free software; you can redistribute it and/or modify it
  16. * under the terms of the GNU General Public License as published by the
  17. * Free Software Foundation; either version 2 of the License, or (at your
  18. * option) any later version.
  19. *
  20. * Gianfar: AKA Lambda Draconis, "Dragon"
  21. * RA 11 31 24.2
  22. * Dec +69 19 52
  23. * V 3.84
  24. * B-V +1.62
  25. *
  26. * Theory of operation
  27. *
  28. * The driver is initialized through of_device. Configuration information
  29. * is therefore conveyed through an OF-style device tree.
  30. *
  31. * The Gianfar Ethernet Controller uses a ring of buffer
  32. * descriptors. The beginning is indicated by a register
  33. * pointing to the physical address of the start of the ring.
  34. * The end is determined by a "wrap" bit being set in the
  35. * last descriptor of the ring.
  36. *
  37. * When a packet is received, the RXF bit in the
  38. * IEVENT register is set, triggering an interrupt when the
  39. * corresponding bit in the IMASK register is also set (if
  40. * interrupt coalescing is active, then the interrupt may not
  41. * happen immediately, but will wait until either a set number
  42. * of frames or amount of time have passed). In NAPI, the
  43. * interrupt handler will signal there is work to be done, and
  44. * exit. This method will start at the last known empty
  45. * descriptor, and process every subsequent descriptor until there
  46. * are none left with data (NAPI will stop after a set number of
  47. * packets to give time to other tasks, but will eventually
  48. * process all the packets). The data arrives inside a
  49. * pre-allocated skb, and so after the skb is passed up to the
  50. * stack, a new skb must be allocated, and the address field in
  51. * the buffer descriptor must be updated to indicate this new
  52. * skb.
  53. *
  54. * When the kernel requests that a packet be transmitted, the
  55. * driver starts where it left off last time, and points the
  56. * descriptor at the buffer which was passed in. The driver
  57. * then informs the DMA engine that there are packets ready to
  58. * be transmitted. Once the controller is finished transmitting
  59. * the packet, an interrupt may be triggered (under the same
  60. * conditions as for reception, but depending on the TXF bit).
  61. * The driver then cleans up the buffer.
  62. */
  63. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  64. #define DEBUG
  65. #include <linux/kernel.h>
  66. #include <linux/string.h>
  67. #include <linux/errno.h>
  68. #include <linux/unistd.h>
  69. #include <linux/slab.h>
  70. #include <linux/interrupt.h>
  71. #include <linux/init.h>
  72. #include <linux/delay.h>
  73. #include <linux/netdevice.h>
  74. #include <linux/etherdevice.h>
  75. #include <linux/skbuff.h>
  76. #include <linux/if_vlan.h>
  77. #include <linux/spinlock.h>
  78. #include <linux/mm.h>
  79. #include <linux/of_mdio.h>
  80. #include <linux/of_platform.h>
  81. #include <linux/ip.h>
  82. #include <linux/tcp.h>
  83. #include <linux/udp.h>
  84. #include <linux/in.h>
  85. #include <linux/net_tstamp.h>
  86. #include <asm/io.h>
  87. #include <asm/reg.h>
  88. #include <asm/mpc85xx.h>
  89. #include <asm/irq.h>
  90. #include <asm/uaccess.h>
  91. #include <linux/module.h>
  92. #include <linux/dma-mapping.h>
  93. #include <linux/crc32.h>
  94. #include <linux/mii.h>
  95. #include <linux/phy.h>
  96. #include <linux/phy_fixed.h>
  97. #include <linux/of.h>
  98. #include <linux/of_net.h>
  99. #include "gianfar.h"
  100. #define TX_TIMEOUT (1*HZ)
  101. const char gfar_driver_version[] = "1.3";
  102. static int gfar_enet_open(struct net_device *dev);
  103. static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
  104. static void gfar_reset_task(struct work_struct *work);
  105. static void gfar_timeout(struct net_device *dev);
  106. static int gfar_close(struct net_device *dev);
  107. struct sk_buff *gfar_new_skb(struct net_device *dev);
  108. static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
  109. struct sk_buff *skb);
  110. static int gfar_set_mac_address(struct net_device *dev);
  111. static int gfar_change_mtu(struct net_device *dev, int new_mtu);
  112. static irqreturn_t gfar_error(int irq, void *dev_id);
  113. static irqreturn_t gfar_transmit(int irq, void *dev_id);
  114. static irqreturn_t gfar_interrupt(int irq, void *dev_id);
  115. static void adjust_link(struct net_device *dev);
  116. static void init_registers(struct net_device *dev);
  117. static int init_phy(struct net_device *dev);
  118. static int gfar_probe(struct platform_device *ofdev);
  119. static int gfar_remove(struct platform_device *ofdev);
  120. static void free_skb_resources(struct gfar_private *priv);
  121. static void gfar_set_multi(struct net_device *dev);
  122. static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
  123. static void gfar_configure_serdes(struct net_device *dev);
  124. static int gfar_poll(struct napi_struct *napi, int budget);
  125. static int gfar_poll_sq(struct napi_struct *napi, int budget);
  126. #ifdef CONFIG_NET_POLL_CONTROLLER
  127. static void gfar_netpoll(struct net_device *dev);
  128. #endif
  129. int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);
  130. static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);
  131. static void gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
  132. int amount_pull, struct napi_struct *napi);
  133. void gfar_halt(struct net_device *dev);
  134. static void gfar_halt_nodisable(struct net_device *dev);
  135. void gfar_start(struct net_device *dev);
  136. static void gfar_clear_exact_match(struct net_device *dev);
  137. static void gfar_set_mac_for_addr(struct net_device *dev, int num,
  138. const u8 *addr);
  139. static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
  140. MODULE_AUTHOR("Freescale Semiconductor, Inc");
  141. MODULE_DESCRIPTION("Gianfar Ethernet Driver");
  142. MODULE_LICENSE("GPL");
  143. static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
  144. dma_addr_t buf)
  145. {
  146. u32 lstatus;
  147. bdp->bufPtr = buf;
  148. lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
  149. if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
  150. lstatus |= BD_LFLAG(RXBD_WRAP);
  151. eieio();
  152. bdp->lstatus = lstatus;
  153. }
  154. static int gfar_init_bds(struct net_device *ndev)
  155. {
  156. struct gfar_private *priv = netdev_priv(ndev);
  157. struct gfar_priv_tx_q *tx_queue = NULL;
  158. struct gfar_priv_rx_q *rx_queue = NULL;
  159. struct txbd8 *txbdp;
  160. struct rxbd8 *rxbdp;
  161. int i, j;
  162. for (i = 0; i < priv->num_tx_queues; i++) {
  163. tx_queue = priv->tx_queue[i];
  164. /* Initialize some variables in our dev structure */
  165. tx_queue->num_txbdfree = tx_queue->tx_ring_size;
  166. tx_queue->dirty_tx = tx_queue->tx_bd_base;
  167. tx_queue->cur_tx = tx_queue->tx_bd_base;
  168. tx_queue->skb_curtx = 0;
  169. tx_queue->skb_dirtytx = 0;
  170. /* Initialize Transmit Descriptor Ring */
  171. txbdp = tx_queue->tx_bd_base;
  172. for (j = 0; j < tx_queue->tx_ring_size; j++) {
  173. txbdp->lstatus = 0;
  174. txbdp->bufPtr = 0;
  175. txbdp++;
  176. }
  177. /* Set the last descriptor in the ring to indicate wrap */
  178. txbdp--;
  179. txbdp->status |= TXBD_WRAP;
  180. }
  181. for (i = 0; i < priv->num_rx_queues; i++) {
  182. rx_queue = priv->rx_queue[i];
  183. rx_queue->cur_rx = rx_queue->rx_bd_base;
  184. rx_queue->skb_currx = 0;
  185. rxbdp = rx_queue->rx_bd_base;
  186. for (j = 0; j < rx_queue->rx_ring_size; j++) {
  187. struct sk_buff *skb = rx_queue->rx_skbuff[j];
  188. if (skb) {
  189. gfar_init_rxbdp(rx_queue, rxbdp,
  190. rxbdp->bufPtr);
  191. } else {
  192. skb = gfar_new_skb(ndev);
  193. if (!skb) {
  194. netdev_err(ndev, "Can't allocate RX buffers\n");
  195. return -ENOMEM;
  196. }
  197. rx_queue->rx_skbuff[j] = skb;
  198. gfar_new_rxbdp(rx_queue, rxbdp, skb);
  199. }
  200. rxbdp++;
  201. }
  202. }
  203. return 0;
  204. }
  205. static int gfar_alloc_skb_resources(struct net_device *ndev)
  206. {
  207. void *vaddr;
  208. dma_addr_t addr;
  209. int i, j, k;
  210. struct gfar_private *priv = netdev_priv(ndev);
  211. struct device *dev = priv->dev;
  212. struct gfar_priv_tx_q *tx_queue = NULL;
  213. struct gfar_priv_rx_q *rx_queue = NULL;
  214. priv->total_tx_ring_size = 0;
  215. for (i = 0; i < priv->num_tx_queues; i++)
  216. priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
  217. priv->total_rx_ring_size = 0;
  218. for (i = 0; i < priv->num_rx_queues; i++)
  219. priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
  220. /* Allocate memory for the buffer descriptors */
  221. vaddr = dma_alloc_coherent(dev,
  222. (priv->total_tx_ring_size *
  223. sizeof(struct txbd8)) +
  224. (priv->total_rx_ring_size *
  225. sizeof(struct rxbd8)),
  226. &addr, GFP_KERNEL);
  227. if (!vaddr)
  228. return -ENOMEM;
  229. for (i = 0; i < priv->num_tx_queues; i++) {
  230. tx_queue = priv->tx_queue[i];
  231. tx_queue->tx_bd_base = vaddr;
  232. tx_queue->tx_bd_dma_base = addr;
  233. tx_queue->dev = ndev;
  234. /* enet DMA only understands physical addresses */
  235. addr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
  236. vaddr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
  237. }
  238. /* Start the rx descriptor ring where the tx ring leaves off */
  239. for (i = 0; i < priv->num_rx_queues; i++) {
  240. rx_queue = priv->rx_queue[i];
  241. rx_queue->rx_bd_base = vaddr;
  242. rx_queue->rx_bd_dma_base = addr;
  243. rx_queue->dev = ndev;
  244. addr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
  245. vaddr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
  246. }
  247. /* Setup the skbuff rings */
  248. for (i = 0; i < priv->num_tx_queues; i++) {
  249. tx_queue = priv->tx_queue[i];
  250. tx_queue->tx_skbuff =
  251. kmalloc_array(tx_queue->tx_ring_size,
  252. sizeof(*tx_queue->tx_skbuff),
  253. GFP_KERNEL);
  254. if (!tx_queue->tx_skbuff)
  255. goto cleanup;
  256. for (k = 0; k < tx_queue->tx_ring_size; k++)
  257. tx_queue->tx_skbuff[k] = NULL;
  258. }
  259. for (i = 0; i < priv->num_rx_queues; i++) {
  260. rx_queue = priv->rx_queue[i];
  261. rx_queue->rx_skbuff =
  262. kmalloc_array(rx_queue->rx_ring_size,
  263. sizeof(*rx_queue->rx_skbuff),
  264. GFP_KERNEL);
  265. if (!rx_queue->rx_skbuff)
  266. goto cleanup;
  267. for (j = 0; j < rx_queue->rx_ring_size; j++)
  268. rx_queue->rx_skbuff[j] = NULL;
  269. }
  270. if (gfar_init_bds(ndev))
  271. goto cleanup;
  272. return 0;
  273. cleanup:
  274. free_skb_resources(priv);
  275. return -ENOMEM;
  276. }
  277. static void gfar_init_tx_rx_base(struct gfar_private *priv)
  278. {
  279. struct gfar __iomem *regs = priv->gfargrp[0].regs;
  280. u32 __iomem *baddr;
  281. int i;
  282. baddr = &regs->tbase0;
  283. for (i = 0; i < priv->num_tx_queues; i++) {
  284. gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
  285. baddr += 2;
  286. }
  287. baddr = &regs->rbase0;
  288. for (i = 0; i < priv->num_rx_queues; i++) {
  289. gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
  290. baddr += 2;
  291. }
  292. }
  293. static void gfar_init_mac(struct net_device *ndev)
  294. {
  295. struct gfar_private *priv = netdev_priv(ndev);
  296. struct gfar __iomem *regs = priv->gfargrp[0].regs;
  297. u32 rctrl = 0;
  298. u32 tctrl = 0;
  299. u32 attrs = 0;
  300. /* write the tx/rx base registers */
  301. gfar_init_tx_rx_base(priv);
  302. /* Configure the coalescing support */
  303. gfar_configure_coalescing_all(priv);
  304. /* set this when rx hw offload (TOE) functions are being used */
  305. priv->uses_rxfcb = 0;
  306. if (priv->rx_filer_enable) {
  307. rctrl |= RCTRL_FILREN;
  308. /* Program the RIR0 reg with the required distribution */
  309. gfar_write(&regs->rir0, DEFAULT_RIR0);
  310. }
  311. /* Restore PROMISC mode */
  312. if (ndev->flags & IFF_PROMISC)
  313. rctrl |= RCTRL_PROM;
  314. if (ndev->features & NETIF_F_RXCSUM) {
  315. rctrl |= RCTRL_CHECKSUMMING;
  316. priv->uses_rxfcb = 1;
  317. }
  318. if (priv->extended_hash) {
  319. rctrl |= RCTRL_EXTHASH;
  320. gfar_clear_exact_match(ndev);
  321. rctrl |= RCTRL_EMEN;
  322. }
  323. if (priv->padding) {
  324. rctrl &= ~RCTRL_PAL_MASK;
  325. rctrl |= RCTRL_PADDING(priv->padding);
  326. }
  327. /* Insert receive time stamps into padding alignment bytes */
  328. if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) {
  329. rctrl &= ~RCTRL_PAL_MASK;
  330. rctrl |= RCTRL_PADDING(8);
  331. priv->padding = 8;
  332. }
  333. /* Enable HW time stamping if requested from user space */
  334. if (priv->hwts_rx_en) {
  335. rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE;
  336. priv->uses_rxfcb = 1;
  337. }
  338. if (ndev->features & NETIF_F_HW_VLAN_CTAG_RX) {
  339. rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
  340. priv->uses_rxfcb = 1;
  341. }
  342. /* Init rctrl based on our settings */
  343. gfar_write(&regs->rctrl, rctrl);
  344. if (ndev->features & NETIF_F_IP_CSUM)
  345. tctrl |= TCTRL_INIT_CSUM;
  346. if (priv->prio_sched_en)
  347. tctrl |= TCTRL_TXSCHED_PRIO;
  348. else {
  349. tctrl |= TCTRL_TXSCHED_WRRS;
  350. gfar_write(&regs->tr03wt, DEFAULT_WRRS_WEIGHT);
  351. gfar_write(&regs->tr47wt, DEFAULT_WRRS_WEIGHT);
  352. }
  353. gfar_write(&regs->tctrl, tctrl);
  354. /* Set the extraction length and index */
  355. attrs = ATTRELI_EL(priv->rx_stash_size) |
  356. ATTRELI_EI(priv->rx_stash_index);
  357. gfar_write(&regs->attreli, attrs);
  358. /* Start with defaults, and add stashing or locking
  359. * depending on the approprate variables
  360. */
  361. attrs = ATTR_INIT_SETTINGS;
  362. if (priv->bd_stash_en)
  363. attrs |= ATTR_BDSTASH;
  364. if (priv->rx_stash_size != 0)
  365. attrs |= ATTR_BUFSTASH;
  366. gfar_write(&regs->attr, attrs);
  367. gfar_write(&regs->fifo_tx_thr, priv->fifo_threshold);
  368. gfar_write(&regs->fifo_tx_starve, priv->fifo_starve);
  369. gfar_write(&regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
  370. }
  371. static struct net_device_stats *gfar_get_stats(struct net_device *dev)
  372. {
  373. struct gfar_private *priv = netdev_priv(dev);
  374. unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0;
  375. unsigned long tx_packets = 0, tx_bytes = 0;
  376. int i;
  377. for (i = 0; i < priv->num_rx_queues; i++) {
  378. rx_packets += priv->rx_queue[i]->stats.rx_packets;
  379. rx_bytes += priv->rx_queue[i]->stats.rx_bytes;
  380. rx_dropped += priv->rx_queue[i]->stats.rx_dropped;
  381. }
  382. dev->stats.rx_packets = rx_packets;
  383. dev->stats.rx_bytes = rx_bytes;
  384. dev->stats.rx_dropped = rx_dropped;
  385. for (i = 0; i < priv->num_tx_queues; i++) {
  386. tx_bytes += priv->tx_queue[i]->stats.tx_bytes;
  387. tx_packets += priv->tx_queue[i]->stats.tx_packets;
  388. }
  389. dev->stats.tx_bytes = tx_bytes;
  390. dev->stats.tx_packets = tx_packets;
  391. return &dev->stats;
  392. }
  393. static const struct net_device_ops gfar_netdev_ops = {
  394. .ndo_open = gfar_enet_open,
  395. .ndo_start_xmit = gfar_start_xmit,
  396. .ndo_stop = gfar_close,
  397. .ndo_change_mtu = gfar_change_mtu,
  398. .ndo_set_features = gfar_set_features,
  399. .ndo_set_rx_mode = gfar_set_multi,
  400. .ndo_tx_timeout = gfar_timeout,
  401. .ndo_do_ioctl = gfar_ioctl,
  402. .ndo_get_stats = gfar_get_stats,
  403. .ndo_set_mac_address = eth_mac_addr,
  404. .ndo_validate_addr = eth_validate_addr,
  405. #ifdef CONFIG_NET_POLL_CONTROLLER
  406. .ndo_poll_controller = gfar_netpoll,
  407. #endif
  408. };
  409. void lock_rx_qs(struct gfar_private *priv)
  410. {
  411. int i;
  412. for (i = 0; i < priv->num_rx_queues; i++)
  413. spin_lock(&priv->rx_queue[i]->rxlock);
  414. }
  415. void lock_tx_qs(struct gfar_private *priv)
  416. {
  417. int i;
  418. for (i = 0; i < priv->num_tx_queues; i++)
  419. spin_lock(&priv->tx_queue[i]->txlock);
  420. }
  421. void unlock_rx_qs(struct gfar_private *priv)
  422. {
  423. int i;
  424. for (i = 0; i < priv->num_rx_queues; i++)
  425. spin_unlock(&priv->rx_queue[i]->rxlock);
  426. }
  427. void unlock_tx_qs(struct gfar_private *priv)
  428. {
  429. int i;
  430. for (i = 0; i < priv->num_tx_queues; i++)
  431. spin_unlock(&priv->tx_queue[i]->txlock);
  432. }
  433. static void free_tx_pointers(struct gfar_private *priv)
  434. {
  435. int i;
  436. for (i = 0; i < priv->num_tx_queues; i++)
  437. kfree(priv->tx_queue[i]);
  438. }
  439. static void free_rx_pointers(struct gfar_private *priv)
  440. {
  441. int i;
  442. for (i = 0; i < priv->num_rx_queues; i++)
  443. kfree(priv->rx_queue[i]);
  444. }
  445. static void unmap_group_regs(struct gfar_private *priv)
  446. {
  447. int i;
  448. for (i = 0; i < MAXGROUPS; i++)
  449. if (priv->gfargrp[i].regs)
  450. iounmap(priv->gfargrp[i].regs);
  451. }
  452. static void free_gfar_dev(struct gfar_private *priv)
  453. {
  454. int i, j;
  455. for (i = 0; i < priv->num_grps; i++)
  456. for (j = 0; j < GFAR_NUM_IRQS; j++) {
  457. kfree(priv->gfargrp[i].irqinfo[j]);
  458. priv->gfargrp[i].irqinfo[j] = NULL;
  459. }
  460. free_netdev(priv->ndev);
  461. }
  462. static void disable_napi(struct gfar_private *priv)
  463. {
  464. int i;
  465. for (i = 0; i < priv->num_grps; i++)
  466. napi_disable(&priv->gfargrp[i].napi);
  467. }
  468. static void enable_napi(struct gfar_private *priv)
  469. {
  470. int i;
  471. for (i = 0; i < priv->num_grps; i++)
  472. napi_enable(&priv->gfargrp[i].napi);
  473. }
  474. static int gfar_parse_group(struct device_node *np,
  475. struct gfar_private *priv, const char *model)
  476. {
  477. struct gfar_priv_grp *grp = &priv->gfargrp[priv->num_grps];
  478. u32 *queue_mask;
  479. int i;
  480. for (i = 0; i < GFAR_NUM_IRQS; i++) {
  481. grp->irqinfo[i] = kzalloc(sizeof(struct gfar_irqinfo),
  482. GFP_KERNEL);
  483. if (!grp->irqinfo[i])
  484. return -ENOMEM;
  485. }
  486. grp->regs = of_iomap(np, 0);
  487. if (!grp->regs)
  488. return -ENOMEM;
  489. gfar_irq(grp, TX)->irq = irq_of_parse_and_map(np, 0);
  490. /* If we aren't the FEC we have multiple interrupts */
  491. if (model && strcasecmp(model, "FEC")) {
  492. gfar_irq(grp, RX)->irq = irq_of_parse_and_map(np, 1);
  493. gfar_irq(grp, ER)->irq = irq_of_parse_and_map(np, 2);
  494. if (gfar_irq(grp, TX)->irq == NO_IRQ ||
  495. gfar_irq(grp, RX)->irq == NO_IRQ ||
  496. gfar_irq(grp, ER)->irq == NO_IRQ)
  497. return -EINVAL;
  498. }
  499. grp->priv = priv;
  500. spin_lock_init(&grp->grplock);
  501. if (priv->mode == MQ_MG_MODE) {
  502. queue_mask = (u32 *)of_get_property(np, "fsl,rx-bit-map", NULL);
  503. grp->rx_bit_map = queue_mask ?
  504. *queue_mask : (DEFAULT_MAPPING >> priv->num_grps);
  505. queue_mask = (u32 *)of_get_property(np, "fsl,tx-bit-map", NULL);
  506. grp->tx_bit_map = queue_mask ?
  507. *queue_mask : (DEFAULT_MAPPING >> priv->num_grps);
  508. } else {
  509. grp->rx_bit_map = 0xFF;
  510. grp->tx_bit_map = 0xFF;
  511. }
  512. priv->num_grps++;
  513. return 0;
  514. }
  515. static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
  516. {
  517. const char *model;
  518. const char *ctype;
  519. const void *mac_addr;
  520. int err = 0, i;
  521. struct net_device *dev = NULL;
  522. struct gfar_private *priv = NULL;
  523. struct device_node *np = ofdev->dev.of_node;
  524. struct device_node *child = NULL;
  525. const u32 *stash;
  526. const u32 *stash_len;
  527. const u32 *stash_idx;
  528. unsigned int num_tx_qs, num_rx_qs;
  529. u32 *tx_queues, *rx_queues;
  530. if (!np || !of_device_is_available(np))
  531. return -ENODEV;
  532. /* parse the num of tx and rx queues */
  533. tx_queues = (u32 *)of_get_property(np, "fsl,num_tx_queues", NULL);
  534. num_tx_qs = tx_queues ? *tx_queues : 1;
  535. if (num_tx_qs > MAX_TX_QS) {
  536. pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
  537. num_tx_qs, MAX_TX_QS);
  538. pr_err("Cannot do alloc_etherdev, aborting\n");
  539. return -EINVAL;
  540. }
  541. rx_queues = (u32 *)of_get_property(np, "fsl,num_rx_queues", NULL);
  542. num_rx_qs = rx_queues ? *rx_queues : 1;
  543. if (num_rx_qs > MAX_RX_QS) {
  544. pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
  545. num_rx_qs, MAX_RX_QS);
  546. pr_err("Cannot do alloc_etherdev, aborting\n");
  547. return -EINVAL;
  548. }
  549. *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
  550. dev = *pdev;
  551. if (NULL == dev)
  552. return -ENOMEM;
  553. priv = netdev_priv(dev);
  554. priv->ndev = dev;
  555. priv->num_tx_queues = num_tx_qs;
  556. netif_set_real_num_rx_queues(dev, num_rx_qs);
  557. priv->num_rx_queues = num_rx_qs;
  558. priv->num_grps = 0x0;
  559. /* Init Rx queue filer rule set linked list */
  560. INIT_LIST_HEAD(&priv->rx_list.list);
  561. priv->rx_list.count = 0;
  562. mutex_init(&priv->rx_queue_access);
  563. model = of_get_property(np, "model", NULL);
  564. for (i = 0; i < MAXGROUPS; i++)
  565. priv->gfargrp[i].regs = NULL;
  566. /* Parse and initialize group specific information */
  567. if (of_device_is_compatible(np, "fsl,etsec2")) {
  568. priv->mode = MQ_MG_MODE;
  569. for_each_child_of_node(np, child) {
  570. err = gfar_parse_group(child, priv, model);
  571. if (err)
  572. goto err_grp_init;
  573. }
  574. } else {
  575. priv->mode = SQ_SG_MODE;
  576. err = gfar_parse_group(np, priv, model);
  577. if (err)
  578. goto err_grp_init;
  579. }
  580. for (i = 0; i < priv->num_tx_queues; i++)
  581. priv->tx_queue[i] = NULL;
  582. for (i = 0; i < priv->num_rx_queues; i++)
  583. priv->rx_queue[i] = NULL;
  584. for (i = 0; i < priv->num_tx_queues; i++) {
  585. priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q),
  586. GFP_KERNEL);
  587. if (!priv->tx_queue[i]) {
  588. err = -ENOMEM;
  589. goto tx_alloc_failed;
  590. }
  591. priv->tx_queue[i]->tx_skbuff = NULL;
  592. priv->tx_queue[i]->qindex = i;
  593. priv->tx_queue[i]->dev = dev;
  594. spin_lock_init(&(priv->tx_queue[i]->txlock));
  595. }
  596. for (i = 0; i < priv->num_rx_queues; i++) {
  597. priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q),
  598. GFP_KERNEL);
  599. if (!priv->rx_queue[i]) {
  600. err = -ENOMEM;
  601. goto rx_alloc_failed;
  602. }
  603. priv->rx_queue[i]->rx_skbuff = NULL;
  604. priv->rx_queue[i]->qindex = i;
  605. priv->rx_queue[i]->dev = dev;
  606. spin_lock_init(&(priv->rx_queue[i]->rxlock));
  607. }
  608. stash = of_get_property(np, "bd-stash", NULL);
  609. if (stash) {
  610. priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
  611. priv->bd_stash_en = 1;
  612. }
  613. stash_len = of_get_property(np, "rx-stash-len", NULL);
  614. if (stash_len)
  615. priv->rx_stash_size = *stash_len;
  616. stash_idx = of_get_property(np, "rx-stash-idx", NULL);
  617. if (stash_idx)
  618. priv->rx_stash_index = *stash_idx;
  619. if (stash_len || stash_idx)
  620. priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
  621. mac_addr = of_get_mac_address(np);
  622. if (mac_addr)
  623. memcpy(dev->dev_addr, mac_addr, ETH_ALEN);
  624. if (model && !strcasecmp(model, "TSEC"))
  625. priv->device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
  626. FSL_GIANFAR_DEV_HAS_COALESCE |
  627. FSL_GIANFAR_DEV_HAS_RMON |
  628. FSL_GIANFAR_DEV_HAS_MULTI_INTR;
  629. if (model && !strcasecmp(model, "eTSEC"))
  630. priv->device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
  631. FSL_GIANFAR_DEV_HAS_COALESCE |
  632. FSL_GIANFAR_DEV_HAS_RMON |
  633. FSL_GIANFAR_DEV_HAS_MULTI_INTR |
  634. FSL_GIANFAR_DEV_HAS_PADDING |
  635. FSL_GIANFAR_DEV_HAS_CSUM |
  636. FSL_GIANFAR_DEV_HAS_VLAN |
  637. FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
  638. FSL_GIANFAR_DEV_HAS_EXTENDED_HASH |
  639. FSL_GIANFAR_DEV_HAS_TIMER;
  640. ctype = of_get_property(np, "phy-connection-type", NULL);
  641. /* We only care about rgmii-id. The rest are autodetected */
  642. if (ctype && !strcmp(ctype, "rgmii-id"))
  643. priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
  644. else
  645. priv->interface = PHY_INTERFACE_MODE_MII;
  646. if (of_get_property(np, "fsl,magic-packet", NULL))
  647. priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
  648. priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
  649. /* Find the TBI PHY. If it's not there, we don't support SGMII */
  650. priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
  651. return 0;
  652. rx_alloc_failed:
  653. free_rx_pointers(priv);
  654. tx_alloc_failed:
  655. free_tx_pointers(priv);
  656. err_grp_init:
  657. unmap_group_regs(priv);
  658. free_gfar_dev(priv);
  659. return err;
  660. }
  661. static int gfar_hwtstamp_ioctl(struct net_device *netdev,
  662. struct ifreq *ifr, int cmd)
  663. {
  664. struct hwtstamp_config config;
  665. struct gfar_private *priv = netdev_priv(netdev);
  666. if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
  667. return -EFAULT;
  668. /* reserved for future extensions */
  669. if (config.flags)
  670. return -EINVAL;
  671. switch (config.tx_type) {
  672. case HWTSTAMP_TX_OFF:
  673. priv->hwts_tx_en = 0;
  674. break;
  675. case HWTSTAMP_TX_ON:
  676. if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
  677. return -ERANGE;
  678. priv->hwts_tx_en = 1;
  679. break;
  680. default:
  681. return -ERANGE;
  682. }
  683. switch (config.rx_filter) {
  684. case HWTSTAMP_FILTER_NONE:
  685. if (priv->hwts_rx_en) {
  686. stop_gfar(netdev);
  687. priv->hwts_rx_en = 0;
  688. startup_gfar(netdev);
  689. }
  690. break;
  691. default:
  692. if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
  693. return -ERANGE;
  694. if (!priv->hwts_rx_en) {
  695. stop_gfar(netdev);
  696. priv->hwts_rx_en = 1;
  697. startup_gfar(netdev);
  698. }
  699. config.rx_filter = HWTSTAMP_FILTER_ALL;
  700. break;
  701. }
  702. return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
  703. -EFAULT : 0;
  704. }
  705. /* Ioctl MII Interface */
  706. static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
  707. {
  708. struct gfar_private *priv = netdev_priv(dev);
  709. if (!netif_running(dev))
  710. return -EINVAL;
  711. if (cmd == SIOCSHWTSTAMP)
  712. return gfar_hwtstamp_ioctl(dev, rq, cmd);
  713. if (!priv->phydev)
  714. return -ENODEV;
  715. return phy_mii_ioctl(priv->phydev, rq, cmd);
  716. }
  717. static unsigned int reverse_bitmap(unsigned int bit_map, unsigned int max_qs)
  718. {
  719. unsigned int new_bit_map = 0x0;
  720. int mask = 0x1 << (max_qs - 1), i;
  721. for (i = 0; i < max_qs; i++) {
  722. if (bit_map & mask)
  723. new_bit_map = new_bit_map + (1 << i);
  724. mask = mask >> 0x1;
  725. }
  726. return new_bit_map;
  727. }
  728. static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
  729. u32 class)
  730. {
  731. u32 rqfpr = FPR_FILER_MASK;
  732. u32 rqfcr = 0x0;
  733. rqfar--;
  734. rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
  735. priv->ftp_rqfpr[rqfar] = rqfpr;
  736. priv->ftp_rqfcr[rqfar] = rqfcr;
  737. gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
  738. rqfar--;
  739. rqfcr = RQFCR_CMP_NOMATCH;
  740. priv->ftp_rqfpr[rqfar] = rqfpr;
  741. priv->ftp_rqfcr[rqfar] = rqfcr;
  742. gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
  743. rqfar--;
  744. rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
  745. rqfpr = class;
  746. priv->ftp_rqfcr[rqfar] = rqfcr;
  747. priv->ftp_rqfpr[rqfar] = rqfpr;
  748. gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
  749. rqfar--;
  750. rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
  751. rqfpr = class;
  752. priv->ftp_rqfcr[rqfar] = rqfcr;
  753. priv->ftp_rqfpr[rqfar] = rqfpr;
  754. gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
  755. return rqfar;
  756. }
  757. static void gfar_init_filer_table(struct gfar_private *priv)
  758. {
  759. int i = 0x0;
  760. u32 rqfar = MAX_FILER_IDX;
  761. u32 rqfcr = 0x0;
  762. u32 rqfpr = FPR_FILER_MASK;
  763. /* Default rule */
  764. rqfcr = RQFCR_CMP_MATCH;
  765. priv->ftp_rqfcr[rqfar] = rqfcr;
  766. priv->ftp_rqfpr[rqfar] = rqfpr;
  767. gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
  768. rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
  769. rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
  770. rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
  771. rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
  772. rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
  773. rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
  774. /* cur_filer_idx indicated the first non-masked rule */
  775. priv->cur_filer_idx = rqfar;
  776. /* Rest are masked rules */
  777. rqfcr = RQFCR_CMP_NOMATCH;
  778. for (i = 0; i < rqfar; i++) {
  779. priv->ftp_rqfcr[i] = rqfcr;
  780. priv->ftp_rqfpr[i] = rqfpr;
  781. gfar_write_filer(priv, i, rqfcr, rqfpr);
  782. }
  783. }
  784. static void __gfar_detect_errata_83xx(struct gfar_private *priv)
  785. {
  786. unsigned int pvr = mfspr(SPRN_PVR);
  787. unsigned int svr = mfspr(SPRN_SVR);
  788. unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */
  789. unsigned int rev = svr & 0xffff;
  790. /* MPC8313 Rev 2.0 and higher; All MPC837x */
  791. if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) ||
  792. (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
  793. priv->errata |= GFAR_ERRATA_74;
  794. /* MPC8313 and MPC837x all rev */
  795. if ((pvr == 0x80850010 && mod == 0x80b0) ||
  796. (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
  797. priv->errata |= GFAR_ERRATA_76;
  798. /* MPC8313 Rev < 2.0 */
  799. if (pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020)
  800. priv->errata |= GFAR_ERRATA_12;
  801. }
  802. static void __gfar_detect_errata_85xx(struct gfar_private *priv)
  803. {
  804. unsigned int svr = mfspr(SPRN_SVR);
  805. if ((SVR_SOC_VER(svr) == SVR_8548) && (SVR_REV(svr) == 0x20))
  806. priv->errata |= GFAR_ERRATA_12;
  807. if (((SVR_SOC_VER(svr) == SVR_P2020) && (SVR_REV(svr) < 0x20)) ||
  808. ((SVR_SOC_VER(svr) == SVR_P2010) && (SVR_REV(svr) < 0x20)))
  809. priv->errata |= GFAR_ERRATA_76; /* aka eTSEC 20 */
  810. }
  811. static void gfar_detect_errata(struct gfar_private *priv)
  812. {
  813. struct device *dev = &priv->ofdev->dev;
  814. /* no plans to fix */
  815. priv->errata |= GFAR_ERRATA_A002;
  816. if (pvr_version_is(PVR_VER_E500V1) || pvr_version_is(PVR_VER_E500V2))
  817. __gfar_detect_errata_85xx(priv);
  818. else /* non-mpc85xx parts, i.e. e300 core based */
  819. __gfar_detect_errata_83xx(priv);
  820. if (priv->errata)
  821. dev_info(dev, "enabled errata workarounds, flags: 0x%x\n",
  822. priv->errata);
  823. }
  824. /* Set up the ethernet device structure, private data,
  825. * and anything else we need before we start
  826. */
  827. static int gfar_probe(struct platform_device *ofdev)
  828. {
  829. u32 tempval;
  830. struct net_device *dev = NULL;
  831. struct gfar_private *priv = NULL;
  832. struct gfar __iomem *regs = NULL;
  833. int err = 0, i, grp_idx = 0;
  834. u32 rstat = 0, tstat = 0, rqueue = 0, tqueue = 0;
  835. u32 isrg = 0;
  836. u32 __iomem *baddr;
  837. err = gfar_of_init(ofdev, &dev);
  838. if (err)
  839. return err;
  840. priv = netdev_priv(dev);
  841. priv->ndev = dev;
  842. priv->ofdev = ofdev;
  843. priv->dev = &ofdev->dev;
  844. SET_NETDEV_DEV(dev, &ofdev->dev);
  845. spin_lock_init(&priv->bflock);
  846. INIT_WORK(&priv->reset_task, gfar_reset_task);
  847. platform_set_drvdata(ofdev, priv);
  848. regs = priv->gfargrp[0].regs;
  849. gfar_detect_errata(priv);
  850. /* Stop the DMA engine now, in case it was running before
  851. * (The firmware could have used it, and left it running).
  852. */
  853. gfar_halt(dev);
  854. /* Reset MAC layer */
  855. gfar_write(&regs->maccfg1, MACCFG1_SOFT_RESET);
  856. /* We need to delay at least 3 TX clocks */
  857. udelay(2);
  858. tempval = 0;
  859. if (!priv->pause_aneg_en && priv->tx_pause_en)
  860. tempval |= MACCFG1_TX_FLOW;
  861. if (!priv->pause_aneg_en && priv->rx_pause_en)
  862. tempval |= MACCFG1_RX_FLOW;
  863. /* the soft reset bit is not self-resetting, so we need to
  864. * clear it before resuming normal operation
  865. */
  866. gfar_write(&regs->maccfg1, tempval);
  867. /* Initialize MACCFG2. */
  868. tempval = MACCFG2_INIT_SETTINGS;
  869. if (gfar_has_errata(priv, GFAR_ERRATA_74))
  870. tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK;
  871. gfar_write(&regs->maccfg2, tempval);
  872. /* Initialize ECNTRL */
  873. gfar_write(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
  874. /* Set the dev->base_addr to the gfar reg region */
  875. dev->base_addr = (unsigned long) regs;
  876. /* Fill in the dev structure */
  877. dev->watchdog_timeo = TX_TIMEOUT;
  878. dev->mtu = 1500;
  879. dev->netdev_ops = &gfar_netdev_ops;
  880. dev->ethtool_ops = &gfar_ethtool_ops;
  881. /* Register for napi ...We are registering NAPI for each grp */
  882. if (priv->mode == SQ_SG_MODE)
  883. netif_napi_add(dev, &priv->gfargrp[0].napi, gfar_poll_sq,
  884. GFAR_DEV_WEIGHT);
  885. else
  886. for (i = 0; i < priv->num_grps; i++)
  887. netif_napi_add(dev, &priv->gfargrp[i].napi, gfar_poll,
  888. GFAR_DEV_WEIGHT);
  889. if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
  890. dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
  891. NETIF_F_RXCSUM;
  892. dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG |
  893. NETIF_F_RXCSUM | NETIF_F_HIGHDMA;
  894. }
  895. if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
  896. dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX |
  897. NETIF_F_HW_VLAN_CTAG_RX;
  898. dev->features |= NETIF_F_HW_VLAN_CTAG_RX;
  899. }
  900. if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
  901. priv->extended_hash = 1;
  902. priv->hash_width = 9;
  903. priv->hash_regs[0] = &regs->igaddr0;
  904. priv->hash_regs[1] = &regs->igaddr1;
  905. priv->hash_regs[2] = &regs->igaddr2;
  906. priv->hash_regs[3] = &regs->igaddr3;
  907. priv->hash_regs[4] = &regs->igaddr4;
  908. priv->hash_regs[5] = &regs->igaddr5;
  909. priv->hash_regs[6] = &regs->igaddr6;
  910. priv->hash_regs[7] = &regs->igaddr7;
  911. priv->hash_regs[8] = &regs->gaddr0;
  912. priv->hash_regs[9] = &regs->gaddr1;
  913. priv->hash_regs[10] = &regs->gaddr2;
  914. priv->hash_regs[11] = &regs->gaddr3;
  915. priv->hash_regs[12] = &regs->gaddr4;
  916. priv->hash_regs[13] = &regs->gaddr5;
  917. priv->hash_regs[14] = &regs->gaddr6;
  918. priv->hash_regs[15] = &regs->gaddr7;
  919. } else {
  920. priv->extended_hash = 0;
  921. priv->hash_width = 8;
  922. priv->hash_regs[0] = &regs->gaddr0;
  923. priv->hash_regs[1] = &regs->gaddr1;
  924. priv->hash_regs[2] = &regs->gaddr2;
  925. priv->hash_regs[3] = &regs->gaddr3;
  926. priv->hash_regs[4] = &regs->gaddr4;
  927. priv->hash_regs[5] = &regs->gaddr5;
  928. priv->hash_regs[6] = &regs->gaddr6;
  929. priv->hash_regs[7] = &regs->gaddr7;
  930. }
  931. if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
  932. priv->padding = DEFAULT_PADDING;
  933. else
  934. priv->padding = 0;
  935. if (dev->features & NETIF_F_IP_CSUM ||
  936. priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
  937. dev->needed_headroom = GMAC_FCB_LEN;
  938. /* Program the isrg regs only if number of grps > 1 */
  939. if (priv->num_grps > 1) {
  940. baddr = &regs->isrg0;
  941. for (i = 0; i < priv->num_grps; i++) {
  942. isrg |= (priv->gfargrp[i].rx_bit_map << ISRG_SHIFT_RX);
  943. isrg |= (priv->gfargrp[i].tx_bit_map << ISRG_SHIFT_TX);
  944. gfar_write(baddr, isrg);
  945. baddr++;
  946. isrg = 0x0;
  947. }
  948. }
  949. /* Need to reverse the bit maps as bit_map's MSB is q0
  950. * but, for_each_set_bit parses from right to left, which
  951. * basically reverses the queue numbers
  952. */
  953. for (i = 0; i< priv->num_grps; i++) {
  954. priv->gfargrp[i].tx_bit_map =
  955. reverse_bitmap(priv->gfargrp[i].tx_bit_map, MAX_TX_QS);
  956. priv->gfargrp[i].rx_bit_map =
  957. reverse_bitmap(priv->gfargrp[i].rx_bit_map, MAX_RX_QS);
  958. }
  959. /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
  960. * also assign queues to groups
  961. */
  962. for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) {
  963. priv->gfargrp[grp_idx].num_rx_queues = 0x0;
  964. for_each_set_bit(i, &priv->gfargrp[grp_idx].rx_bit_map,
  965. priv->num_rx_queues) {
  966. priv->gfargrp[grp_idx].num_rx_queues++;
  967. priv->rx_queue[i]->grp = &priv->gfargrp[grp_idx];
  968. rstat = rstat | (RSTAT_CLEAR_RHALT >> i);
  969. rqueue = rqueue | ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
  970. }
  971. priv->gfargrp[grp_idx].num_tx_queues = 0x0;
  972. for_each_set_bit(i, &priv->gfargrp[grp_idx].tx_bit_map,
  973. priv->num_tx_queues) {
  974. priv->gfargrp[grp_idx].num_tx_queues++;
  975. priv->tx_queue[i]->grp = &priv->gfargrp[grp_idx];
  976. tstat = tstat | (TSTAT_CLEAR_THALT >> i);
  977. tqueue = tqueue | (TQUEUE_EN0 >> i);
  978. }
  979. priv->gfargrp[grp_idx].rstat = rstat;
  980. priv->gfargrp[grp_idx].tstat = tstat;
  981. rstat = tstat =0;
  982. }
  983. gfar_write(&regs->rqueue, rqueue);
  984. gfar_write(&regs->tqueue, tqueue);
  985. priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
  986. /* Initializing some of the rx/tx queue level parameters */
  987. for (i = 0; i < priv->num_tx_queues; i++) {
  988. priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
  989. priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
  990. priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
  991. priv->tx_queue[i]->txic = DEFAULT_TXIC;
  992. }
  993. for (i = 0; i < priv->num_rx_queues; i++) {
  994. priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
  995. priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
  996. priv->rx_queue[i]->rxic = DEFAULT_RXIC;
  997. }
  998. /* always enable rx filer */
  999. priv->rx_filer_enable = 1;
  1000. /* Enable most messages by default */
  1001. priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
  1002. /* use pritority h/w tx queue scheduling for single queue devices */
  1003. if (priv->num_tx_queues == 1)
  1004. priv->prio_sched_en = 1;
  1005. /* Carrier starts down, phylib will bring it up */
  1006. netif_carrier_off(dev);
  1007. err = register_netdev(dev);
  1008. if (err) {
  1009. pr_err("%s: Cannot register net device, aborting\n", dev->name);
  1010. goto register_fail;
  1011. }
  1012. device_init_wakeup(&dev->dev,
  1013. priv->device_flags &
  1014. FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
  1015. /* fill out IRQ number and name fields */
  1016. for (i = 0; i < priv->num_grps; i++) {
  1017. struct gfar_priv_grp *grp = &priv->gfargrp[i];
  1018. if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
  1019. sprintf(gfar_irq(grp, TX)->name, "%s%s%c%s",
  1020. dev->name, "_g", '0' + i, "_tx");
  1021. sprintf(gfar_irq(grp, RX)->name, "%s%s%c%s",
  1022. dev->name, "_g", '0' + i, "_rx");
  1023. sprintf(gfar_irq(grp, ER)->name, "%s%s%c%s",
  1024. dev->name, "_g", '0' + i, "_er");
  1025. } else
  1026. strcpy(gfar_irq(grp, TX)->name, dev->name);
  1027. }
  1028. /* Initialize the filer table */
  1029. gfar_init_filer_table(priv);
  1030. /* Create all the sysfs files */
  1031. gfar_init_sysfs(dev);
  1032. /* Print out the device info */
  1033. netdev_info(dev, "mac: %pM\n", dev->dev_addr);
  1034. /* Even more device info helps when determining which kernel
  1035. * provided which set of benchmarks.
  1036. */
  1037. netdev_info(dev, "Running with NAPI enabled\n");
  1038. for (i = 0; i < priv->num_rx_queues; i++)
  1039. netdev_info(dev, "RX BD ring size for Q[%d]: %d\n",
  1040. i, priv->rx_queue[i]->rx_ring_size);
  1041. for (i = 0; i < priv->num_tx_queues; i++)
  1042. netdev_info(dev, "TX BD ring size for Q[%d]: %d\n",
  1043. i, priv->tx_queue[i]->tx_ring_size);
  1044. return 0;
  1045. register_fail:
  1046. unmap_group_regs(priv);
  1047. free_tx_pointers(priv);
  1048. free_rx_pointers(priv);
  1049. if (priv->phy_node)
  1050. of_node_put(priv->phy_node);
  1051. if (priv->tbi_node)
  1052. of_node_put(priv->tbi_node);
  1053. free_gfar_dev(priv);
  1054. return err;
  1055. }
  1056. static int gfar_remove(struct platform_device *ofdev)
  1057. {
  1058. struct gfar_private *priv = platform_get_drvdata(ofdev);
  1059. if (priv->phy_node)
  1060. of_node_put(priv->phy_node);
  1061. if (priv->tbi_node)
  1062. of_node_put(priv->tbi_node);
  1063. unregister_netdev(priv->ndev);
  1064. unmap_group_regs(priv);
  1065. free_gfar_dev(priv);
  1066. return 0;
  1067. }
  1068. #ifdef CONFIG_PM
  1069. static int gfar_suspend(struct device *dev)
  1070. {
  1071. struct gfar_private *priv = dev_get_drvdata(dev);
  1072. struct net_device *ndev = priv->ndev;
  1073. struct gfar __iomem *regs = priv->gfargrp[0].regs;
  1074. unsigned long flags;
  1075. u32 tempval;
  1076. int magic_packet = priv->wol_en &&
  1077. (priv->device_flags &
  1078. FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
  1079. netif_device_detach(ndev);
  1080. if (netif_running(ndev)) {
  1081. local_irq_save(flags);
  1082. lock_tx_qs(priv);
  1083. lock_rx_qs(priv);
  1084. gfar_halt_nodisable(ndev);
  1085. /* Disable Tx, and Rx if wake-on-LAN is disabled. */
  1086. tempval = gfar_read(&regs->maccfg1);
  1087. tempval &= ~MACCFG1_TX_EN;
  1088. if (!magic_packet)
  1089. tempval &= ~MACCFG1_RX_EN;
  1090. gfar_write(&regs->maccfg1, tempval);
  1091. unlock_rx_qs(priv);
  1092. unlock_tx_qs(priv);
  1093. local_irq_restore(flags);
  1094. disable_napi(priv);
  1095. if (magic_packet) {
  1096. /* Enable interrupt on Magic Packet */
  1097. gfar_write(&regs->imask, IMASK_MAG);
  1098. /* Enable Magic Packet mode */
  1099. tempval = gfar_read(&regs->maccfg2);
  1100. tempval |= MACCFG2_MPEN;
  1101. gfar_write(&regs->maccfg2, tempval);
  1102. } else {
  1103. phy_stop(priv->phydev);
  1104. }
  1105. }
  1106. return 0;
  1107. }
  1108. static int gfar_resume(struct device *dev)
  1109. {
  1110. struct gfar_private *priv = dev_get_drvdata(dev);
  1111. struct net_device *ndev = priv->ndev;
  1112. struct gfar __iomem *regs = priv->gfargrp[0].regs;
  1113. unsigned long flags;
  1114. u32 tempval;
  1115. int magic_packet = priv->wol_en &&
  1116. (priv->device_flags &
  1117. FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
  1118. if (!netif_running(ndev)) {
  1119. netif_device_attach(ndev);
  1120. return 0;
  1121. }
  1122. if (!magic_packet && priv->phydev)
  1123. phy_start(priv->phydev);
  1124. /* Disable Magic Packet mode, in case something
  1125. * else woke us up.
  1126. */
  1127. local_irq_save(flags);
  1128. lock_tx_qs(priv);
  1129. lock_rx_qs(priv);
  1130. tempval = gfar_read(&regs->maccfg2);
  1131. tempval &= ~MACCFG2_MPEN;
  1132. gfar_write(&regs->maccfg2, tempval);
  1133. gfar_start(ndev);
  1134. unlock_rx_qs(priv);
  1135. unlock_tx_qs(priv);
  1136. local_irq_restore(flags);
  1137. netif_device_attach(ndev);
  1138. enable_napi(priv);
  1139. return 0;
  1140. }
  1141. static int gfar_restore(struct device *dev)
  1142. {
  1143. struct gfar_private *priv = dev_get_drvdata(dev);
  1144. struct net_device *ndev = priv->ndev;
  1145. if (!netif_running(ndev)) {
  1146. netif_device_attach(ndev);
  1147. return 0;
  1148. }
  1149. if (gfar_init_bds(ndev)) {
  1150. free_skb_resources(priv);
  1151. return -ENOMEM;
  1152. }
  1153. init_registers(ndev);
  1154. gfar_set_mac_address(ndev);
  1155. gfar_init_mac(ndev);
  1156. gfar_start(ndev);
  1157. priv->oldlink = 0;
  1158. priv->oldspeed = 0;
  1159. priv->oldduplex = -1;
  1160. if (priv->phydev)
  1161. phy_start(priv->phydev);
  1162. netif_device_attach(ndev);
  1163. enable_napi(priv);
  1164. return 0;
  1165. }
  1166. static struct dev_pm_ops gfar_pm_ops = {
  1167. .suspend = gfar_suspend,
  1168. .resume = gfar_resume,
  1169. .freeze = gfar_suspend,
  1170. .thaw = gfar_resume,
  1171. .restore = gfar_restore,
  1172. };
  1173. #define GFAR_PM_OPS (&gfar_pm_ops)
  1174. #else
  1175. #define GFAR_PM_OPS NULL
  1176. #endif
  1177. /* Reads the controller's registers to determine what interface
  1178. * connects it to the PHY.
  1179. */
  1180. static phy_interface_t gfar_get_interface(struct net_device *dev)
  1181. {
  1182. struct gfar_private *priv = netdev_priv(dev);
  1183. struct gfar __iomem *regs = priv->gfargrp[0].regs;
  1184. u32 ecntrl;
  1185. ecntrl = gfar_read(&regs->ecntrl);
  1186. if (ecntrl & ECNTRL_SGMII_MODE)
  1187. return PHY_INTERFACE_MODE_SGMII;
  1188. if (ecntrl & ECNTRL_TBI_MODE) {
  1189. if (ecntrl & ECNTRL_REDUCED_MODE)
  1190. return PHY_INTERFACE_MODE_RTBI;
  1191. else
  1192. return PHY_INTERFACE_MODE_TBI;
  1193. }
  1194. if (ecntrl & ECNTRL_REDUCED_MODE) {
  1195. if (ecntrl & ECNTRL_REDUCED_MII_MODE) {
  1196. return PHY_INTERFACE_MODE_RMII;
  1197. }
  1198. else {
  1199. phy_interface_t interface = priv->interface;
  1200. /* This isn't autodetected right now, so it must
  1201. * be set by the device tree or platform code.
  1202. */
  1203. if (interface == PHY_INTERFACE_MODE_RGMII_ID)
  1204. return PHY_INTERFACE_MODE_RGMII_ID;
  1205. return PHY_INTERFACE_MODE_RGMII;
  1206. }
  1207. }
  1208. if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
  1209. return PHY_INTERFACE_MODE_GMII;
  1210. return PHY_INTERFACE_MODE_MII;
  1211. }
  1212. /* Initializes driver's PHY state, and attaches to the PHY.
  1213. * Returns 0 on success.
  1214. */
  1215. static int init_phy(struct net_device *dev)
  1216. {
  1217. struct gfar_private *priv = netdev_priv(dev);
  1218. uint gigabit_support =
  1219. priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
  1220. GFAR_SUPPORTED_GBIT : 0;
  1221. phy_interface_t interface;
  1222. priv->oldlink = 0;
  1223. priv->oldspeed = 0;
  1224. priv->oldduplex = -1;
  1225. interface = gfar_get_interface(dev);
  1226. priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
  1227. interface);
  1228. if (!priv->phydev)
  1229. priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link,
  1230. interface);
  1231. if (!priv->phydev) {
  1232. dev_err(&dev->dev, "could not attach to PHY\n");
  1233. return -ENODEV;
  1234. }
  1235. if (interface == PHY_INTERFACE_MODE_SGMII)
  1236. gfar_configure_serdes(dev);
  1237. /* Remove any features not supported by the controller */
  1238. priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
  1239. priv->phydev->advertising = priv->phydev->supported;
  1240. return 0;
  1241. }
  1242. /* Initialize TBI PHY interface for communicating with the
  1243. * SERDES lynx PHY on the chip. We communicate with this PHY
  1244. * through the MDIO bus on each controller, treating it as a
  1245. * "normal" PHY at the address found in the TBIPA register. We assume
  1246. * that the TBIPA register is valid. Either the MDIO bus code will set
  1247. * it to a value that doesn't conflict with other PHYs on the bus, or the
  1248. * value doesn't matter, as there are no other PHYs on the bus.
  1249. */
  1250. static void gfar_configure_serdes(struct net_device *dev)
  1251. {
  1252. struct gfar_private *priv = netdev_priv(dev);
  1253. struct phy_device *tbiphy;
  1254. if (!priv->tbi_node) {
  1255. dev_warn(&dev->dev, "error: SGMII mode requires that the "
  1256. "device tree specify a tbi-handle\n");
  1257. return;
  1258. }
  1259. tbiphy = of_phy_find_device(priv->tbi_node);
  1260. if (!tbiphy) {
  1261. dev_err(&dev->dev, "error: Could not get TBI device\n");
  1262. return;
  1263. }
  1264. /* If the link is already up, we must already be ok, and don't need to
  1265. * configure and reset the TBI<->SerDes link. Maybe U-Boot configured
  1266. * everything for us? Resetting it takes the link down and requires
  1267. * several seconds for it to come back.
  1268. */
  1269. if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS)
  1270. return;
  1271. /* Single clk mode, mii mode off(for serdes communication) */
  1272. phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
  1273. phy_write(tbiphy, MII_ADVERTISE,
  1274. ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
  1275. ADVERTISE_1000XPSE_ASYM);
  1276. phy_write(tbiphy, MII_BMCR,
  1277. BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX |
  1278. BMCR_SPEED1000);
  1279. }
  1280. static void init_registers(struct net_device *dev)
  1281. {
  1282. struct gfar_private *priv = netdev_priv(dev);
  1283. struct gfar __iomem *regs = NULL;
  1284. int i;
  1285. for (i = 0; i < priv->num_grps; i++) {
  1286. regs = priv->gfargrp[i].regs;
  1287. /* Clear IEVENT */
  1288. gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
  1289. /* Initialize IMASK */
  1290. gfar_write(&regs->imask, IMASK_INIT_CLEAR);
  1291. }
  1292. regs = priv->gfargrp[0].regs;
  1293. /* Init hash registers to zero */
  1294. gfar_write(&regs->igaddr0, 0);
  1295. gfar_write(&regs->igaddr1, 0);
  1296. gfar_write(&regs->igaddr2, 0);
  1297. gfar_write(&regs->igaddr3, 0);
  1298. gfar_write(&regs->igaddr4, 0);
  1299. gfar_write(&regs->igaddr5, 0);
  1300. gfar_write(&regs->igaddr6, 0);
  1301. gfar_write(&regs->igaddr7, 0);
  1302. gfar_write(&regs->gaddr0, 0);
  1303. gfar_write(&regs->gaddr1, 0);
  1304. gfar_write(&regs->gaddr2, 0);
  1305. gfar_write(&regs->gaddr3, 0);
  1306. gfar_write(&regs->gaddr4, 0);
  1307. gfar_write(&regs->gaddr5, 0);
  1308. gfar_write(&regs->gaddr6, 0);
  1309. gfar_write(&regs->gaddr7, 0);
  1310. /* Zero out the rmon mib registers if it has them */
  1311. if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
  1312. memset_io(&(regs->rmon), 0, sizeof (struct rmon_mib));
  1313. /* Mask off the CAM interrupts */
  1314. gfar_write(&regs->rmon.cam1, 0xffffffff);
  1315. gfar_write(&regs->rmon.cam2, 0xffffffff);
  1316. }
  1317. /* Initialize the max receive buffer length */
  1318. gfar_write(&regs->mrblr, priv->rx_buffer_size);
  1319. /* Initialize the Minimum Frame Length Register */
  1320. gfar_write(&regs->minflr, MINFLR_INIT_SETTINGS);
  1321. }
  1322. static int __gfar_is_rx_idle(struct gfar_private *priv)
  1323. {
  1324. u32 res;
  1325. /* Normaly TSEC should not hang on GRS commands, so we should
  1326. * actually wait for IEVENT_GRSC flag.
  1327. */
  1328. if (!gfar_has_errata(priv, GFAR_ERRATA_A002))
  1329. return 0;
  1330. /* Read the eTSEC register at offset 0xD1C. If bits 7-14 are
  1331. * the same as bits 23-30, the eTSEC Rx is assumed to be idle
  1332. * and the Rx can be safely reset.
  1333. */
  1334. res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c);
  1335. res &= 0x7f807f80;
  1336. if ((res & 0xffff) == (res >> 16))
  1337. return 1;
  1338. return 0;
  1339. }
  1340. /* Halt the receive and transmit queues */
  1341. static void gfar_halt_nodisable(struct net_device *dev)
  1342. {
  1343. struct gfar_private *priv = netdev_priv(dev);
  1344. struct gfar __iomem *regs = NULL;
  1345. u32 tempval;
  1346. int i;
  1347. for (i = 0; i < priv->num_grps; i++) {
  1348. regs = priv->gfargrp[i].regs;
  1349. /* Mask all interrupts */
  1350. gfar_write(&regs->imask, IMASK_INIT_CLEAR);
  1351. /* Clear all interrupts */
  1352. gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
  1353. }
  1354. regs = priv->gfargrp[0].regs;
  1355. /* Stop the DMA, and wait for it to stop */
  1356. tempval = gfar_read(&regs->dmactrl);
  1357. if ((tempval & (DMACTRL_GRS | DMACTRL_GTS)) !=
  1358. (DMACTRL_GRS | DMACTRL_GTS)) {
  1359. int ret;
  1360. tempval |= (DMACTRL_GRS | DMACTRL_GTS);
  1361. gfar_write(&regs->dmactrl, tempval);
  1362. do {
  1363. ret = spin_event_timeout(((gfar_read(&regs->ievent) &
  1364. (IEVENT_GRSC | IEVENT_GTSC)) ==
  1365. (IEVENT_GRSC | IEVENT_GTSC)), 1000000, 0);
  1366. if (!ret && !(gfar_read(&regs->ievent) & IEVENT_GRSC))
  1367. ret = __gfar_is_rx_idle(priv);
  1368. } while (!ret);
  1369. }
  1370. }
  1371. /* Halt the receive and transmit queues */
  1372. void gfar_halt(struct net_device *dev)
  1373. {
  1374. struct gfar_private *priv = netdev_priv(dev);
  1375. struct gfar __iomem *regs = priv->gfargrp[0].regs;
  1376. u32 tempval;
  1377. gfar_halt_nodisable(dev);
  1378. /* Disable Rx and Tx */
  1379. tempval = gfar_read(&regs->maccfg1);
  1380. tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
  1381. gfar_write(&regs->maccfg1, tempval);
  1382. }
  1383. static void free_grp_irqs(struct gfar_priv_grp *grp)
  1384. {
  1385. free_irq(gfar_irq(grp, TX)->irq, grp);
  1386. free_irq(gfar_irq(grp, RX)->irq, grp);
  1387. free_irq(gfar_irq(grp, ER)->irq, grp);
  1388. }
  1389. void stop_gfar(struct net_device *dev)
  1390. {
  1391. struct gfar_private *priv = netdev_priv(dev);
  1392. unsigned long flags;
  1393. int i;
  1394. phy_stop(priv->phydev);
  1395. /* Lock it down */
  1396. local_irq_save(flags);
  1397. lock_tx_qs(priv);
  1398. lock_rx_qs(priv);
  1399. gfar_halt(dev);
  1400. unlock_rx_qs(priv);
  1401. unlock_tx_qs(priv);
  1402. local_irq_restore(flags);
  1403. /* Free the IRQs */
  1404. if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
  1405. for (i = 0; i < priv->num_grps; i++)
  1406. free_grp_irqs(&priv->gfargrp[i]);
  1407. } else {
  1408. for (i = 0; i < priv->num_grps; i++)
  1409. free_irq(gfar_irq(&priv->gfargrp[i], TX)->irq,
  1410. &priv->gfargrp[i]);
  1411. }
  1412. free_skb_resources(priv);
  1413. }
  1414. static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
  1415. {
  1416. struct txbd8 *txbdp;
  1417. struct gfar_private *priv = netdev_priv(tx_queue->dev);
  1418. int i, j;
  1419. txbdp = tx_queue->tx_bd_base;
  1420. for (i = 0; i < tx_queue->tx_ring_size; i++) {
  1421. if (!tx_queue->tx_skbuff[i])
  1422. continue;
  1423. dma_unmap_single(priv->dev, txbdp->bufPtr,
  1424. txbdp->length, DMA_TO_DEVICE);
  1425. txbdp->lstatus = 0;
  1426. for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
  1427. j++) {
  1428. txbdp++;
  1429. dma_unmap_page(priv->dev, txbdp->bufPtr,
  1430. txbdp->length, DMA_TO_DEVICE);
  1431. }
  1432. txbdp++;
  1433. dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
  1434. tx_queue->tx_skbuff[i] = NULL;
  1435. }
  1436. kfree(tx_queue->tx_skbuff);
  1437. tx_queue->tx_skbuff = NULL;
  1438. }
  1439. static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
  1440. {
  1441. struct rxbd8 *rxbdp;
  1442. struct gfar_private *priv = netdev_priv(rx_queue->dev);
  1443. int i;
  1444. rxbdp = rx_queue->rx_bd_base;
  1445. for (i = 0; i < rx_queue->rx_ring_size; i++) {
  1446. if (rx_queue->rx_skbuff[i]) {
  1447. dma_unmap_single(priv->dev, rxbdp->bufPtr,
  1448. priv->rx_buffer_size,
  1449. DMA_FROM_DEVICE);
  1450. dev_kfree_skb_any(rx_queue->rx_skbuff[i]);
  1451. rx_queue->rx_skbuff[i] = NULL;
  1452. }
  1453. rxbdp->lstatus = 0;
  1454. rxbdp->bufPtr = 0;
  1455. rxbdp++;
  1456. }
  1457. kfree(rx_queue->rx_skbuff);
  1458. rx_queue->rx_skbuff = NULL;
  1459. }
  1460. /* If there are any tx skbs or rx skbs still around, free them.
  1461. * Then free tx_skbuff and rx_skbuff
  1462. */
  1463. static void free_skb_resources(struct gfar_private *priv)
  1464. {
  1465. struct gfar_priv_tx_q *tx_queue = NULL;
  1466. struct gfar_priv_rx_q *rx_queue = NULL;
  1467. int i;
  1468. /* Go through all the buffer descriptors and free their data buffers */
  1469. for (i = 0; i < priv->num_tx_queues; i++) {
  1470. struct netdev_queue *txq;
  1471. tx_queue = priv->tx_queue[i];
  1472. txq = netdev_get_tx_queue(tx_queue->dev, tx_queue->qindex);
  1473. if (tx_queue->tx_skbuff)
  1474. free_skb_tx_queue(tx_queue);
  1475. netdev_tx_reset_queue(txq);
  1476. }
  1477. for (i = 0; i < priv->num_rx_queues; i++) {
  1478. rx_queue = priv->rx_queue[i];
  1479. if (rx_queue->rx_skbuff)
  1480. free_skb_rx_queue(rx_queue);
  1481. }
  1482. dma_free_coherent(priv->dev,
  1483. sizeof(struct txbd8) * priv->total_tx_ring_size +
  1484. sizeof(struct rxbd8) * priv->total_rx_ring_size,
  1485. priv->tx_queue[0]->tx_bd_base,
  1486. priv->tx_queue[0]->tx_bd_dma_base);
  1487. }
  1488. void gfar_start(struct net_device *dev)
  1489. {
  1490. struct gfar_private *priv = netdev_priv(dev);
  1491. struct gfar __iomem *regs = priv->gfargrp[0].regs;
  1492. u32 tempval;
  1493. int i = 0;
  1494. /* Enable Rx and Tx in MACCFG1 */
  1495. tempval = gfar_read(&regs->maccfg1);
  1496. tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
  1497. gfar_write(&regs->maccfg1, tempval);
  1498. /* Initialize DMACTRL to have WWR and WOP */
  1499. tempval = gfar_read(&regs->dmactrl);
  1500. tempval |= DMACTRL_INIT_SETTINGS;
  1501. gfar_write(&regs->dmactrl, tempval);
  1502. /* Make sure we aren't stopped */
  1503. tempval = gfar_read(&regs->dmactrl);
  1504. tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
  1505. gfar_write(&regs->dmactrl, tempval);
  1506. for (i = 0; i < priv->num_grps; i++) {
  1507. regs = priv->gfargrp[i].regs;
  1508. /* Clear THLT/RHLT, so that the DMA starts polling now */
  1509. gfar_write(&regs->tstat, priv->gfargrp[i].tstat);
  1510. gfar_write(&regs->rstat, priv->gfargrp[i].rstat);
  1511. /* Unmask the interrupts we look for */
  1512. gfar_write(&regs->imask, IMASK_DEFAULT);
  1513. }
  1514. dev->trans_start = jiffies; /* prevent tx timeout */
  1515. }
  1516. static void gfar_configure_coalescing(struct gfar_private *priv,
  1517. unsigned long tx_mask, unsigned long rx_mask)
  1518. {
  1519. struct gfar __iomem *regs = priv->gfargrp[0].regs;
  1520. u32 __iomem *baddr;
  1521. if (priv->mode == MQ_MG_MODE) {
  1522. int i = 0;
  1523. baddr = &regs->txic0;
  1524. for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
  1525. gfar_write(baddr + i, 0);
  1526. if (likely(priv->tx_queue[i]->txcoalescing))
  1527. gfar_write(baddr + i, priv->tx_queue[i]->txic);
  1528. }
  1529. baddr = &regs->rxic0;
  1530. for_each_set_bit(i, &rx_mask, priv->num_rx_queues) {
  1531. gfar_write(baddr + i, 0);
  1532. if (likely(priv->rx_queue[i]->rxcoalescing))
  1533. gfar_write(baddr + i, priv->rx_queue[i]->rxic);
  1534. }
  1535. } else {
  1536. /* Backward compatible case -- even if we enable
  1537. * multiple queues, there's only single reg to program
  1538. */
  1539. gfar_write(&regs->txic, 0);
  1540. if (likely(priv->tx_queue[0]->txcoalescing))
  1541. gfar_write(&regs->txic, priv->tx_queue[0]->txic);
  1542. gfar_write(&regs->rxic, 0);
  1543. if (unlikely(priv->rx_queue[0]->rxcoalescing))
  1544. gfar_write(&regs->rxic, priv->rx_queue[0]->rxic);
  1545. }
  1546. }
  1547. void gfar_configure_coalescing_all(struct gfar_private *priv)
  1548. {
  1549. gfar_configure_coalescing(priv, 0xFF, 0xFF);
  1550. }
  1551. static int register_grp_irqs(struct gfar_priv_grp *grp)
  1552. {
  1553. struct gfar_private *priv = grp->priv;
  1554. struct net_device *dev = priv->ndev;
  1555. int err;
  1556. /* If the device has multiple interrupts, register for
  1557. * them. Otherwise, only register for the one
  1558. */
  1559. if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
  1560. /* Install our interrupt handlers for Error,
  1561. * Transmit, and Receive
  1562. */
  1563. err = request_irq(gfar_irq(grp, ER)->irq, gfar_error, 0,
  1564. gfar_irq(grp, ER)->name, grp);
  1565. if (err < 0) {
  1566. netif_err(priv, intr, dev, "Can't get IRQ %d\n",
  1567. gfar_irq(grp, ER)->irq);
  1568. goto err_irq_fail;
  1569. }
  1570. err = request_irq(gfar_irq(grp, TX)->irq, gfar_transmit, 0,
  1571. gfar_irq(grp, TX)->name, grp);
  1572. if (err < 0) {
  1573. netif_err(priv, intr, dev, "Can't get IRQ %d\n",
  1574. gfar_irq(grp, TX)->irq);
  1575. goto tx_irq_fail;
  1576. }
  1577. err = request_irq(gfar_irq(grp, RX)->irq, gfar_receive, 0,
  1578. gfar_irq(grp, RX)->name, grp);
  1579. if (err < 0) {
  1580. netif_err(priv, intr, dev, "Can't get IRQ %d\n",
  1581. gfar_irq(grp, RX)->irq);
  1582. goto rx_irq_fail;
  1583. }
  1584. } else {
  1585. err = request_irq(gfar_irq(grp, TX)->irq, gfar_interrupt, 0,
  1586. gfar_irq(grp, TX)->name, grp);
  1587. if (err < 0) {
  1588. netif_err(priv, intr, dev, "Can't get IRQ %d\n",
  1589. gfar_irq(grp, TX)->irq);
  1590. goto err_irq_fail;
  1591. }
  1592. }
  1593. return 0;
  1594. rx_irq_fail:
  1595. free_irq(gfar_irq(grp, TX)->irq, grp);
  1596. tx_irq_fail:
  1597. free_irq(gfar_irq(grp, ER)->irq, grp);
  1598. err_irq_fail:
  1599. return err;
  1600. }
  1601. /* Bring the controller up and running */
  1602. int startup_gfar(struct net_device *ndev)
  1603. {
  1604. struct gfar_private *priv = netdev_priv(ndev);
  1605. struct gfar __iomem *regs = NULL;
  1606. int err, i, j;
  1607. for (i = 0; i < priv->num_grps; i++) {
  1608. regs= priv->gfargrp[i].regs;
  1609. gfar_write(&regs->imask, IMASK_INIT_CLEAR);
  1610. }
  1611. regs= priv->gfargrp[0].regs;
  1612. err = gfar_alloc_skb_resources(ndev);
  1613. if (err)
  1614. return err;
  1615. gfar_init_mac(ndev);
  1616. for (i = 0; i < priv->num_grps; i++) {
  1617. err = register_grp_irqs(&priv->gfargrp[i]);
  1618. if (err) {
  1619. for (j = 0; j < i; j++)
  1620. free_grp_irqs(&priv->gfargrp[j]);
  1621. goto irq_fail;
  1622. }
  1623. }
  1624. /* Start the controller */
  1625. gfar_start(ndev);
  1626. phy_start(priv->phydev);
  1627. gfar_configure_coalescing_all(priv);
  1628. return 0;
  1629. irq_fail:
  1630. free_skb_resources(priv);
  1631. return err;
  1632. }
  1633. /* Called when something needs to use the ethernet device
  1634. * Returns 0 for success.
  1635. */
  1636. static int gfar_enet_open(struct net_device *dev)
  1637. {
  1638. struct gfar_private *priv = netdev_priv(dev);
  1639. int err;
  1640. enable_napi(priv);
  1641. /* Initialize a bunch of registers */
  1642. init_registers(dev);
  1643. gfar_set_mac_address(dev);
  1644. err = init_phy(dev);
  1645. if (err) {
  1646. disable_napi(priv);
  1647. return err;
  1648. }
  1649. err = startup_gfar(dev);
  1650. if (err) {
  1651. disable_napi(priv);
  1652. return err;
  1653. }
  1654. netif_tx_start_all_queues(dev);
  1655. device_set_wakeup_enable(&dev->dev, priv->wol_en);
  1656. return err;
  1657. }
  1658. static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
  1659. {
  1660. struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
  1661. memset(fcb, 0, GMAC_FCB_LEN);
  1662. return fcb;
  1663. }
  1664. static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb,
  1665. int fcb_length)
  1666. {
  1667. /* If we're here, it's a IP packet with a TCP or UDP
  1668. * payload. We set it to checksum, using a pseudo-header
  1669. * we provide
  1670. */
  1671. u8 flags = TXFCB_DEFAULT;
  1672. /* Tell the controller what the protocol is
  1673. * And provide the already calculated phcs
  1674. */
  1675. if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
  1676. flags |= TXFCB_UDP;
  1677. fcb->phcs = udp_hdr(skb)->check;
  1678. } else
  1679. fcb->phcs = tcp_hdr(skb)->check;
  1680. /* l3os is the distance between the start of the
  1681. * frame (skb->data) and the start of the IP hdr.
  1682. * l4os is the distance between the start of the
  1683. * l3 hdr and the l4 hdr
  1684. */
  1685. fcb->l3os = (u16)(skb_network_offset(skb) - fcb_length);
  1686. fcb->l4os = skb_network_header_len(skb);
  1687. fcb->flags = flags;
  1688. }
  1689. void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
  1690. {
  1691. fcb->flags |= TXFCB_VLN;
  1692. fcb->vlctl = vlan_tx_tag_get(skb);
  1693. }
  1694. static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
  1695. struct txbd8 *base, int ring_size)
  1696. {
  1697. struct txbd8 *new_bd = bdp + stride;
  1698. return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
  1699. }
  1700. static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
  1701. int ring_size)
  1702. {
  1703. return skip_txbd(bdp, 1, base, ring_size);
  1704. }
  1705. /* eTSEC12: csum generation not supported for some fcb offsets */
  1706. static inline bool gfar_csum_errata_12(struct gfar_private *priv,
  1707. unsigned long fcb_addr)
  1708. {
  1709. return (gfar_has_errata(priv, GFAR_ERRATA_12) &&
  1710. (fcb_addr % 0x20) > 0x18);
  1711. }
  1712. /* eTSEC76: csum generation for frames larger than 2500 may
  1713. * cause excess delays before start of transmission
  1714. */
  1715. static inline bool gfar_csum_errata_76(struct gfar_private *priv,
  1716. unsigned int len)
  1717. {
  1718. return (gfar_has_errata(priv, GFAR_ERRATA_76) &&
  1719. (len > 2500));
  1720. }
  1721. /* This is called by the kernel when a frame is ready for transmission.
  1722. * It is pointed to by the dev->hard_start_xmit function pointer
  1723. */
  1724. static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
  1725. {
  1726. struct gfar_private *priv = netdev_priv(dev);
  1727. struct gfar_priv_tx_q *tx_queue = NULL;
  1728. struct netdev_queue *txq;
  1729. struct gfar __iomem *regs = NULL;
  1730. struct txfcb *fcb = NULL;
  1731. struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL;
  1732. u32 lstatus;
  1733. int i, rq = 0;
  1734. int do_tstamp, do_csum, do_vlan;
  1735. u32 bufaddr;
  1736. unsigned long flags;
  1737. unsigned int nr_frags, nr_txbds, bytes_sent, fcb_len = 0;
  1738. rq = skb->queue_mapping;
  1739. tx_queue = priv->tx_queue[rq];
  1740. txq = netdev_get_tx_queue(dev, rq);
  1741. base = tx_queue->tx_bd_base;
  1742. regs = tx_queue->grp->regs;
  1743. do_csum = (CHECKSUM_PARTIAL == skb->ip_summed);
  1744. do_vlan = vlan_tx_tag_present(skb);
  1745. do_tstamp = (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
  1746. priv->hwts_tx_en;
  1747. if (do_csum || do_vlan)
  1748. fcb_len = GMAC_FCB_LEN;
  1749. /* check if time stamp should be generated */
  1750. if (unlikely(do_tstamp))
  1751. fcb_len = GMAC_FCB_LEN + GMAC_TXPAL_LEN;
  1752. /* make space for additional header when fcb is needed */
  1753. if (fcb_len && unlikely(skb_headroom(skb) < fcb_len)) {
  1754. struct sk_buff *skb_new;
  1755. skb_new = skb_realloc_headroom(skb, fcb_len);
  1756. if (!skb_new) {
  1757. dev->stats.tx_errors++;
  1758. kfree_skb(skb);
  1759. return NETDEV_TX_OK;
  1760. }
  1761. if (skb->sk)
  1762. skb_set_owner_w(skb_new, skb->sk);
  1763. consume_skb(skb);
  1764. skb = skb_new;
  1765. }
  1766. /* total number of fragments in the SKB */
  1767. nr_frags = skb_shinfo(skb)->nr_frags;
  1768. /* calculate the required number of TxBDs for this skb */
  1769. if (unlikely(do_tstamp))
  1770. nr_txbds = nr_frags + 2;
  1771. else
  1772. nr_txbds = nr_frags + 1;
  1773. /* check if there is space to queue this packet */
  1774. if (nr_txbds > tx_queue->num_txbdfree) {
  1775. /* no space, stop the queue */
  1776. netif_tx_stop_queue(txq);
  1777. dev->stats.tx_fifo_errors++;
  1778. return NETDEV_TX_BUSY;
  1779. }
  1780. /* Update transmit stats */
  1781. bytes_sent = skb->len;
  1782. tx_queue->stats.tx_bytes += bytes_sent;
  1783. /* keep Tx bytes on wire for BQL accounting */
  1784. GFAR_CB(skb)->bytes_sent = bytes_sent;
  1785. tx_queue->stats.tx_packets++;
  1786. txbdp = txbdp_start = tx_queue->cur_tx;
  1787. lstatus = txbdp->lstatus;
  1788. /* Time stamp insertion requires one additional TxBD */
  1789. if (unlikely(do_tstamp))
  1790. txbdp_tstamp = txbdp = next_txbd(txbdp, base,
  1791. tx_queue->tx_ring_size);
  1792. if (nr_frags == 0) {
  1793. if (unlikely(do_tstamp))
  1794. txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_LAST |
  1795. TXBD_INTERRUPT);
  1796. else
  1797. lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
  1798. } else {
  1799. /* Place the fragment addresses and lengths into the TxBDs */
  1800. for (i = 0; i < nr_frags; i++) {
  1801. unsigned int frag_len;
  1802. /* Point at the next BD, wrapping as needed */
  1803. txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
  1804. frag_len = skb_shinfo(skb)->frags[i].size;
  1805. lstatus = txbdp->lstatus | frag_len |
  1806. BD_LFLAG(TXBD_READY);
  1807. /* Handle the last BD specially */
  1808. if (i == nr_frags - 1)
  1809. lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
  1810. bufaddr = skb_frag_dma_map(priv->dev,
  1811. &skb_shinfo(skb)->frags[i],
  1812. 0,
  1813. frag_len,
  1814. DMA_TO_DEVICE);
  1815. /* set the TxBD length and buffer pointer */
  1816. txbdp->bufPtr = bufaddr;
  1817. txbdp->lstatus = lstatus;
  1818. }
  1819. lstatus = txbdp_start->lstatus;
  1820. }
  1821. /* Add TxPAL between FCB and frame if required */
  1822. if (unlikely(do_tstamp)) {
  1823. skb_push(skb, GMAC_TXPAL_LEN);
  1824. memset(skb->data, 0, GMAC_TXPAL_LEN);
  1825. }
  1826. /* Add TxFCB if required */
  1827. if (fcb_len) {
  1828. fcb = gfar_add_fcb(skb);
  1829. lstatus |= BD_LFLAG(TXBD_TOE);
  1830. }
  1831. /* Set up checksumming */
  1832. if (do_csum) {
  1833. gfar_tx_checksum(skb, fcb, fcb_len);
  1834. if (unlikely(gfar_csum_errata_12(priv, (unsigned long)fcb)) ||
  1835. unlikely(gfar_csum_errata_76(priv, skb->len))) {
  1836. __skb_pull(skb, GMAC_FCB_LEN);
  1837. skb_checksum_help(skb);
  1838. if (do_vlan || do_tstamp) {
  1839. /* put back a new fcb for vlan/tstamp TOE */
  1840. fcb = gfar_add_fcb(skb);
  1841. } else {
  1842. /* Tx TOE not used */
  1843. lstatus &= ~(BD_LFLAG(TXBD_TOE));
  1844. fcb = NULL;
  1845. }
  1846. }
  1847. }
  1848. if (do_vlan)
  1849. gfar_tx_vlan(skb, fcb);
  1850. /* Setup tx hardware time stamping if requested */
  1851. if (unlikely(do_tstamp)) {
  1852. skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
  1853. fcb->ptp = 1;
  1854. }
  1855. txbdp_start->bufPtr = dma_map_single(priv->dev, skb->data,
  1856. skb_headlen(skb), DMA_TO_DEVICE);
  1857. /* If time stamping is requested one additional TxBD must be set up. The
  1858. * first TxBD points to the FCB and must have a data length of
  1859. * GMAC_FCB_LEN. The second TxBD points to the actual frame data with
  1860. * the full frame length.
  1861. */
  1862. if (unlikely(do_tstamp)) {
  1863. txbdp_tstamp->bufPtr = txbdp_start->bufPtr + fcb_len;
  1864. txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_READY) |
  1865. (skb_headlen(skb) - fcb_len);
  1866. lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN;
  1867. } else {
  1868. lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
  1869. }
  1870. netdev_tx_sent_queue(txq, bytes_sent);
  1871. /* We can work in parallel with gfar_clean_tx_ring(), except
  1872. * when modifying num_txbdfree. Note that we didn't grab the lock
  1873. * when we were reading the num_txbdfree and checking for available
  1874. * space, that's because outside of this function it can only grow,
  1875. * and once we've got needed space, it cannot suddenly disappear.
  1876. *
  1877. * The lock also protects us from gfar_error(), which can modify
  1878. * regs->tstat and thus retrigger the transfers, which is why we
  1879. * also must grab the lock before setting ready bit for the first
  1880. * to be transmitted BD.
  1881. */
  1882. spin_lock_irqsave(&tx_queue->txlock, flags);
  1883. /* The powerpc-specific eieio() is used, as wmb() has too strong
  1884. * semantics (it requires synchronization between cacheable and
  1885. * uncacheable mappings, which eieio doesn't provide and which we
  1886. * don't need), thus requiring a more expensive sync instruction. At
  1887. * some point, the set of architecture-independent barrier functions
  1888. * should be expanded to include weaker barriers.
  1889. */
  1890. eieio();
  1891. txbdp_start->lstatus = lstatus;
  1892. eieio(); /* force lstatus write before tx_skbuff */
  1893. tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
  1894. /* Update the current skb pointer to the next entry we will use
  1895. * (wrapping if necessary)
  1896. */
  1897. tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
  1898. TX_RING_MOD_MASK(tx_queue->tx_ring_size);
  1899. tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
  1900. /* reduce TxBD free count */
  1901. tx_queue->num_txbdfree -= (nr_txbds);
  1902. /* If the next BD still needs to be cleaned up, then the bds
  1903. * are full. We need to tell the kernel to stop sending us stuff.
  1904. */
  1905. if (!tx_queue->num_txbdfree) {
  1906. netif_tx_stop_queue(txq);
  1907. dev->stats.tx_fifo_errors++;
  1908. }
  1909. /* Tell the DMA to go go go */
  1910. gfar_write(&regs->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
  1911. /* Unlock priv */
  1912. spin_unlock_irqrestore(&tx_queue->txlock, flags);
  1913. return NETDEV_TX_OK;
  1914. }
  1915. /* Stops the kernel queue, and halts the controller */
  1916. static int gfar_close(struct net_device *dev)
  1917. {
  1918. struct gfar_private *priv = netdev_priv(dev);
  1919. disable_napi(priv);
  1920. cancel_work_sync(&priv->reset_task);
  1921. stop_gfar(dev);
  1922. /* Disconnect from the PHY */
  1923. phy_disconnect(priv->phydev);
  1924. priv->phydev = NULL;
  1925. netif_tx_stop_all_queues(dev);
  1926. return 0;
  1927. }
  1928. /* Changes the mac address if the controller is not running. */
  1929. static int gfar_set_mac_address(struct net_device *dev)
  1930. {
  1931. gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
  1932. return 0;
  1933. }
  1934. /* Check if rx parser should be activated */
  1935. void gfar_check_rx_parser_mode(struct gfar_private *priv)
  1936. {
  1937. struct gfar __iomem *regs;
  1938. u32 tempval;
  1939. regs = priv->gfargrp[0].regs;
  1940. tempval = gfar_read(&regs->rctrl);
  1941. /* If parse is no longer required, then disable parser */
  1942. if (tempval & RCTRL_REQ_PARSER) {
  1943. tempval |= RCTRL_PRSDEP_INIT;
  1944. priv->uses_rxfcb = 1;
  1945. } else {
  1946. tempval &= ~RCTRL_PRSDEP_INIT;
  1947. priv->uses_rxfcb = 0;
  1948. }
  1949. gfar_write(&regs->rctrl, tempval);
  1950. }
  1951. /* Enables and disables VLAN insertion/extraction */
  1952. void gfar_vlan_mode(struct net_device *dev, netdev_features_t features)
  1953. {
  1954. struct gfar_private *priv = netdev_priv(dev);
  1955. struct gfar __iomem *regs = NULL;
  1956. unsigned long flags;
  1957. u32 tempval;
  1958. regs = priv->gfargrp[0].regs;
  1959. local_irq_save(flags);
  1960. lock_rx_qs(priv);
  1961. if (features & NETIF_F_HW_VLAN_CTAG_TX) {
  1962. /* Enable VLAN tag insertion */
  1963. tempval = gfar_read(&regs->tctrl);
  1964. tempval |= TCTRL_VLINS;
  1965. gfar_write(&regs->tctrl, tempval);
  1966. } else {
  1967. /* Disable VLAN tag insertion */
  1968. tempval = gfar_read(&regs->tctrl);
  1969. tempval &= ~TCTRL_VLINS;
  1970. gfar_write(&regs->tctrl, tempval);
  1971. }
  1972. if (features & NETIF_F_HW_VLAN_CTAG_RX) {
  1973. /* Enable VLAN tag extraction */
  1974. tempval = gfar_read(&regs->rctrl);
  1975. tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT);
  1976. gfar_write(&regs->rctrl, tempval);
  1977. priv->uses_rxfcb = 1;
  1978. } else {
  1979. /* Disable VLAN tag extraction */
  1980. tempval = gfar_read(&regs->rctrl);
  1981. tempval &= ~RCTRL_VLEX;
  1982. gfar_write(&regs->rctrl, tempval);
  1983. gfar_check_rx_parser_mode(priv);
  1984. }
  1985. gfar_change_mtu(dev, dev->mtu);
  1986. unlock_rx_qs(priv);
  1987. local_irq_restore(flags);
  1988. }
  1989. static int gfar_change_mtu(struct net_device *dev, int new_mtu)
  1990. {
  1991. int tempsize, tempval;
  1992. struct gfar_private *priv = netdev_priv(dev);
  1993. struct gfar __iomem *regs = priv->gfargrp[0].regs;
  1994. int oldsize = priv->rx_buffer_size;
  1995. int frame_size = new_mtu + ETH_HLEN;
  1996. if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
  1997. netif_err(priv, drv, dev, "Invalid MTU setting\n");
  1998. return -EINVAL;
  1999. }
  2000. if (priv->uses_rxfcb)
  2001. frame_size += GMAC_FCB_LEN;
  2002. frame_size += priv->padding;
  2003. tempsize = (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
  2004. INCREMENTAL_BUFFER_SIZE;
  2005. /* Only stop and start the controller if it isn't already
  2006. * stopped, and we changed something
  2007. */
  2008. if ((oldsize != tempsize) && (dev->flags & IFF_UP))
  2009. stop_gfar(dev);
  2010. priv->rx_buffer_size = tempsize;
  2011. dev->mtu = new_mtu;
  2012. gfar_write(&regs->mrblr, priv->rx_buffer_size);
  2013. gfar_write(&regs->maxfrm, priv->rx_buffer_size);
  2014. /* If the mtu is larger than the max size for standard
  2015. * ethernet frames (ie, a jumbo frame), then set maccfg2
  2016. * to allow huge frames, and to check the length
  2017. */
  2018. tempval = gfar_read(&regs->maccfg2);
  2019. if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE ||
  2020. gfar_has_errata(priv, GFAR_ERRATA_74))
  2021. tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
  2022. else
  2023. tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
  2024. gfar_write(&regs->maccfg2, tempval);
  2025. if ((oldsize != tempsize) && (dev->flags & IFF_UP))
  2026. startup_gfar(dev);
  2027. return 0;
  2028. }
  2029. /* gfar_reset_task gets scheduled when a packet has not been
  2030. * transmitted after a set amount of time.
  2031. * For now, assume that clearing out all the structures, and
  2032. * starting over will fix the problem.
  2033. */
  2034. static void gfar_reset_task(struct work_struct *work)
  2035. {
  2036. struct gfar_private *priv = container_of(work, struct gfar_private,
  2037. reset_task);
  2038. struct net_device *dev = priv->ndev;
  2039. if (dev->flags & IFF_UP) {
  2040. netif_tx_stop_all_queues(dev);
  2041. stop_gfar(dev);
  2042. startup_gfar(dev);
  2043. netif_tx_start_all_queues(dev);
  2044. }
  2045. netif_tx_schedule_all(dev);
  2046. }
  2047. static void gfar_timeout(struct net_device *dev)
  2048. {
  2049. struct gfar_private *priv = netdev_priv(dev);
  2050. dev->stats.tx_errors++;
  2051. schedule_work(&priv->reset_task);
  2052. }
  2053. static void gfar_align_skb(struct sk_buff *skb)
  2054. {
  2055. /* We need the data buffer to be aligned properly. We will reserve
  2056. * as many bytes as needed to align the data properly
  2057. */
  2058. skb_reserve(skb, RXBUF_ALIGNMENT -
  2059. (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1)));
  2060. }
  2061. /* Interrupt Handler for Transmit complete */
  2062. static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
  2063. {
  2064. struct net_device *dev = tx_queue->dev;
  2065. struct netdev_queue *txq;
  2066. struct gfar_private *priv = netdev_priv(dev);
  2067. struct txbd8 *bdp, *next = NULL;
  2068. struct txbd8 *lbdp = NULL;
  2069. struct txbd8 *base = tx_queue->tx_bd_base;
  2070. struct sk_buff *skb;
  2071. int skb_dirtytx;
  2072. int tx_ring_size = tx_queue->tx_ring_size;
  2073. int frags = 0, nr_txbds = 0;
  2074. int i;
  2075. int howmany = 0;
  2076. int tqi = tx_queue->qindex;
  2077. unsigned int bytes_sent = 0;
  2078. u32 lstatus;
  2079. size_t buflen;
  2080. txq = netdev_get_tx_queue(dev, tqi);
  2081. bdp = tx_queue->dirty_tx;
  2082. skb_dirtytx = tx_queue->skb_dirtytx;
  2083. while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
  2084. unsigned long flags;
  2085. frags = skb_shinfo(skb)->nr_frags;
  2086. /* When time stamping, one additional TxBD must be freed.
  2087. * Also, we need to dma_unmap_single() the TxPAL.
  2088. */
  2089. if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))
  2090. nr_txbds = frags + 2;
  2091. else
  2092. nr_txbds = frags + 1;
  2093. lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size);
  2094. lstatus = lbdp->lstatus;
  2095. /* Only clean completed frames */
  2096. if ((lstatus & BD_LFLAG(TXBD_READY)) &&
  2097. (lstatus & BD_LENGTH_MASK))
  2098. break;
  2099. if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
  2100. next = next_txbd(bdp, base, tx_ring_size);
  2101. buflen = next->length + GMAC_FCB_LEN + GMAC_TXPAL_LEN;
  2102. } else
  2103. buflen = bdp->length;
  2104. dma_unmap_single(priv->dev, bdp->bufPtr,
  2105. buflen, DMA_TO_DEVICE);
  2106. if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
  2107. struct skb_shared_hwtstamps shhwtstamps;
  2108. u64 *ns = (u64*) (((u32)skb->data + 0x10) & ~0x7);
  2109. memset(&shhwtstamps, 0, sizeof(shhwtstamps));
  2110. shhwtstamps.hwtstamp = ns_to_ktime(*ns);
  2111. skb_pull(skb, GMAC_FCB_LEN + GMAC_TXPAL_LEN);
  2112. skb_tstamp_tx(skb, &shhwtstamps);
  2113. bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
  2114. bdp = next;
  2115. }
  2116. bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
  2117. bdp = next_txbd(bdp, base, tx_ring_size);
  2118. for (i = 0; i < frags; i++) {
  2119. dma_unmap_page(priv->dev, bdp->bufPtr,
  2120. bdp->length, DMA_TO_DEVICE);
  2121. bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
  2122. bdp = next_txbd(bdp, base, tx_ring_size);
  2123. }
  2124. bytes_sent += GFAR_CB(skb)->bytes_sent;
  2125. dev_kfree_skb_any(skb);
  2126. tx_queue->tx_skbuff[skb_dirtytx] = NULL;
  2127. skb_dirtytx = (skb_dirtytx + 1) &
  2128. TX_RING_MOD_MASK(tx_ring_size);
  2129. howmany++;
  2130. spin_lock_irqsave(&tx_queue->txlock, flags);
  2131. tx_queue->num_txbdfree += nr_txbds;
  2132. spin_unlock_irqrestore(&tx_queue->txlock, flags);
  2133. }
  2134. /* If we freed a buffer, we can restart transmission, if necessary */
  2135. if (netif_tx_queue_stopped(txq) && tx_queue->num_txbdfree)
  2136. netif_wake_subqueue(dev, tqi);
  2137. /* Update dirty indicators */
  2138. tx_queue->skb_dirtytx = skb_dirtytx;
  2139. tx_queue->dirty_tx = bdp;
  2140. netdev_tx_completed_queue(txq, howmany, bytes_sent);
  2141. }
  2142. static void gfar_schedule_cleanup(struct gfar_priv_grp *gfargrp)
  2143. {
  2144. unsigned long flags;
  2145. spin_lock_irqsave(&gfargrp->grplock, flags);
  2146. if (napi_schedule_prep(&gfargrp->napi)) {
  2147. gfar_write(&gfargrp->regs->imask, IMASK_RTX_DISABLED);
  2148. __napi_schedule(&gfargrp->napi);
  2149. } else {
  2150. /* Clear IEVENT, so interrupts aren't called again
  2151. * because of the packets that have already arrived.
  2152. */
  2153. gfar_write(&gfargrp->regs->ievent, IEVENT_RTX_MASK);
  2154. }
  2155. spin_unlock_irqrestore(&gfargrp->grplock, flags);
  2156. }
  2157. /* Interrupt Handler for Transmit complete */
  2158. static irqreturn_t gfar_transmit(int irq, void *grp_id)
  2159. {
  2160. gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
  2161. return IRQ_HANDLED;
  2162. }
  2163. static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
  2164. struct sk_buff *skb)
  2165. {
  2166. struct net_device *dev = rx_queue->dev;
  2167. struct gfar_private *priv = netdev_priv(dev);
  2168. dma_addr_t buf;
  2169. buf = dma_map_single(priv->dev, skb->data,
  2170. priv->rx_buffer_size, DMA_FROM_DEVICE);
  2171. gfar_init_rxbdp(rx_queue, bdp, buf);
  2172. }
  2173. static struct sk_buff *gfar_alloc_skb(struct net_device *dev)
  2174. {
  2175. struct gfar_private *priv = netdev_priv(dev);
  2176. struct sk_buff *skb;
  2177. skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT);
  2178. if (!skb)
  2179. return NULL;
  2180. gfar_align_skb(skb);
  2181. return skb;
  2182. }
  2183. struct sk_buff *gfar_new_skb(struct net_device *dev)
  2184. {
  2185. return gfar_alloc_skb(dev);
  2186. }
  2187. static inline void count_errors(unsigned short status, struct net_device *dev)
  2188. {
  2189. struct gfar_private *priv = netdev_priv(dev);
  2190. struct net_device_stats *stats = &dev->stats;
  2191. struct gfar_extra_stats *estats = &priv->extra_stats;
  2192. /* If the packet was truncated, none of the other errors matter */
  2193. if (status & RXBD_TRUNCATED) {
  2194. stats->rx_length_errors++;
  2195. atomic64_inc(&estats->rx_trunc);
  2196. return;
  2197. }
  2198. /* Count the errors, if there were any */
  2199. if (status & (RXBD_LARGE | RXBD_SHORT)) {
  2200. stats->rx_length_errors++;
  2201. if (status & RXBD_LARGE)
  2202. atomic64_inc(&estats->rx_large);
  2203. else
  2204. atomic64_inc(&estats->rx_short);
  2205. }
  2206. if (status & RXBD_NONOCTET) {
  2207. stats->rx_frame_errors++;
  2208. atomic64_inc(&estats->rx_nonoctet);
  2209. }
  2210. if (status & RXBD_CRCERR) {
  2211. atomic64_inc(&estats->rx_crcerr);
  2212. stats->rx_crc_errors++;
  2213. }
  2214. if (status & RXBD_OVERRUN) {
  2215. atomic64_inc(&estats->rx_overrun);
  2216. stats->rx_crc_errors++;
  2217. }
  2218. }
  2219. irqreturn_t gfar_receive(int irq, void *grp_id)
  2220. {
  2221. gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
  2222. return IRQ_HANDLED;
  2223. }
  2224. static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
  2225. {
  2226. /* If valid headers were found, and valid sums
  2227. * were verified, then we tell the kernel that no
  2228. * checksumming is necessary. Otherwise, it is [FIXME]
  2229. */
  2230. if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
  2231. skb->ip_summed = CHECKSUM_UNNECESSARY;
  2232. else
  2233. skb_checksum_none_assert(skb);
  2234. }
  2235. /* gfar_process_frame() -- handle one incoming packet if skb isn't NULL. */
  2236. static void gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
  2237. int amount_pull, struct napi_struct *napi)
  2238. {
  2239. struct gfar_private *priv = netdev_priv(dev);
  2240. struct rxfcb *fcb = NULL;
  2241. /* fcb is at the beginning if exists */
  2242. fcb = (struct rxfcb *)skb->data;
  2243. /* Remove the FCB from the skb
  2244. * Remove the padded bytes, if there are any
  2245. */
  2246. if (amount_pull) {
  2247. skb_record_rx_queue(skb, fcb->rq);
  2248. skb_pull(skb, amount_pull);
  2249. }
  2250. /* Get receive timestamp from the skb */
  2251. if (priv->hwts_rx_en) {
  2252. struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
  2253. u64 *ns = (u64 *) skb->data;
  2254. memset(shhwtstamps, 0, sizeof(*shhwtstamps));
  2255. shhwtstamps->hwtstamp = ns_to_ktime(*ns);
  2256. }
  2257. if (priv->padding)
  2258. skb_pull(skb, priv->padding);
  2259. if (dev->features & NETIF_F_RXCSUM)
  2260. gfar_rx_checksum(skb, fcb);
  2261. /* Tell the skb what kind of packet this is */
  2262. skb->protocol = eth_type_trans(skb, dev);
  2263. /* There's need to check for NETIF_F_HW_VLAN_CTAG_RX here.
  2264. * Even if vlan rx accel is disabled, on some chips
  2265. * RXFCB_VLN is pseudo randomly set.
  2266. */
  2267. if (dev->features & NETIF_F_HW_VLAN_CTAG_RX &&
  2268. fcb->flags & RXFCB_VLN)
  2269. __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), fcb->vlctl);
  2270. /* Send the packet up the stack */
  2271. napi_gro_receive(napi, skb);
  2272. }
  2273. /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
  2274. * until the budget/quota has been reached. Returns the number
  2275. * of frames handled
  2276. */
  2277. int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit)
  2278. {
  2279. struct net_device *dev = rx_queue->dev;
  2280. struct rxbd8 *bdp, *base;
  2281. struct sk_buff *skb;
  2282. int pkt_len;
  2283. int amount_pull;
  2284. int howmany = 0;
  2285. struct gfar_private *priv = netdev_priv(dev);
  2286. /* Get the first full descriptor */
  2287. bdp = rx_queue->cur_rx;
  2288. base = rx_queue->rx_bd_base;
  2289. amount_pull = priv->uses_rxfcb ? GMAC_FCB_LEN : 0;
  2290. while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
  2291. struct sk_buff *newskb;
  2292. rmb();
  2293. /* Add another skb for the future */
  2294. newskb = gfar_new_skb(dev);
  2295. skb = rx_queue->rx_skbuff[rx_queue->skb_currx];
  2296. dma_unmap_single(priv->dev, bdp->bufPtr,
  2297. priv->rx_buffer_size, DMA_FROM_DEVICE);
  2298. if (unlikely(!(bdp->status & RXBD_ERR) &&
  2299. bdp->length > priv->rx_buffer_size))
  2300. bdp->status = RXBD_LARGE;
  2301. /* We drop the frame if we failed to allocate a new buffer */
  2302. if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
  2303. bdp->status & RXBD_ERR)) {
  2304. count_errors(bdp->status, dev);
  2305. if (unlikely(!newskb))
  2306. newskb = skb;
  2307. else if (skb)
  2308. dev_kfree_skb(skb);
  2309. } else {
  2310. /* Increment the number of packets */
  2311. rx_queue->stats.rx_packets++;
  2312. howmany++;
  2313. if (likely(skb)) {
  2314. pkt_len = bdp->length - ETH_FCS_LEN;
  2315. /* Remove the FCS from the packet length */
  2316. skb_put(skb, pkt_len);
  2317. rx_queue->stats.rx_bytes += pkt_len;
  2318. skb_record_rx_queue(skb, rx_queue->qindex);
  2319. gfar_process_frame(dev, skb, amount_pull,
  2320. &rx_queue->grp->napi);
  2321. } else {
  2322. netif_warn(priv, rx_err, dev, "Missing skb!\n");
  2323. rx_queue->stats.rx_dropped++;
  2324. atomic64_inc(&priv->extra_stats.rx_skbmissing);
  2325. }
  2326. }
  2327. rx_queue->rx_skbuff[rx_queue->skb_currx] = newskb;
  2328. /* Setup the new bdp */
  2329. gfar_new_rxbdp(rx_queue, bdp, newskb);
  2330. /* Update to the next pointer */
  2331. bdp = next_bd(bdp, base, rx_queue->rx_ring_size);
  2332. /* update to point at the next skb */
  2333. rx_queue->skb_currx = (rx_queue->skb_currx + 1) &
  2334. RX_RING_MOD_MASK(rx_queue->rx_ring_size);
  2335. }
  2336. /* Update the current rxbd pointer to be the next one */
  2337. rx_queue->cur_rx = bdp;
  2338. return howmany;
  2339. }
  2340. static int gfar_poll_sq(struct napi_struct *napi, int budget)
  2341. {
  2342. struct gfar_priv_grp *gfargrp =
  2343. container_of(napi, struct gfar_priv_grp, napi);
  2344. struct gfar __iomem *regs = gfargrp->regs;
  2345. struct gfar_priv_tx_q *tx_queue = gfargrp->priv->tx_queue[0];
  2346. struct gfar_priv_rx_q *rx_queue = gfargrp->priv->rx_queue[0];
  2347. int work_done = 0;
  2348. /* Clear IEVENT, so interrupts aren't called again
  2349. * because of the packets that have already arrived
  2350. */
  2351. gfar_write(&regs->ievent, IEVENT_RTX_MASK);
  2352. /* run Tx cleanup to completion */
  2353. if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx])
  2354. gfar_clean_tx_ring(tx_queue);
  2355. work_done = gfar_clean_rx_ring(rx_queue, budget);
  2356. if (work_done < budget) {
  2357. napi_complete(napi);
  2358. /* Clear the halt bit in RSTAT */
  2359. gfar_write(&regs->rstat, gfargrp->rstat);
  2360. gfar_write(&regs->imask, IMASK_DEFAULT);
  2361. /* If we are coalescing interrupts, update the timer
  2362. * Otherwise, clear it
  2363. */
  2364. gfar_write(&regs->txic, 0);
  2365. if (likely(tx_queue->txcoalescing))
  2366. gfar_write(&regs->txic, tx_queue->txic);
  2367. gfar_write(&regs->rxic, 0);
  2368. if (unlikely(rx_queue->rxcoalescing))
  2369. gfar_write(&regs->rxic, rx_queue->rxic);
  2370. }
  2371. return work_done;
  2372. }
  2373. static int gfar_poll(struct napi_struct *napi, int budget)
  2374. {
  2375. struct gfar_priv_grp *gfargrp =
  2376. container_of(napi, struct gfar_priv_grp, napi);
  2377. struct gfar_private *priv = gfargrp->priv;
  2378. struct gfar __iomem *regs = gfargrp->regs;
  2379. struct gfar_priv_tx_q *tx_queue = NULL;
  2380. struct gfar_priv_rx_q *rx_queue = NULL;
  2381. int work_done = 0, work_done_per_q = 0;
  2382. int i, budget_per_q = 0;
  2383. int has_tx_work = 0;
  2384. unsigned long rstat_rxf;
  2385. int num_act_queues;
  2386. /* Clear IEVENT, so interrupts aren't called again
  2387. * because of the packets that have already arrived
  2388. */
  2389. gfar_write(&regs->ievent, IEVENT_RTX_MASK);
  2390. rstat_rxf = gfar_read(&regs->rstat) & RSTAT_RXF_MASK;
  2391. num_act_queues = bitmap_weight(&rstat_rxf, MAX_RX_QS);
  2392. if (num_act_queues)
  2393. budget_per_q = budget/num_act_queues;
  2394. for_each_set_bit(i, &gfargrp->tx_bit_map, priv->num_tx_queues) {
  2395. tx_queue = priv->tx_queue[i];
  2396. /* run Tx cleanup to completion */
  2397. if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx]) {
  2398. gfar_clean_tx_ring(tx_queue);
  2399. has_tx_work = 1;
  2400. }
  2401. }
  2402. for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
  2403. /* skip queue if not active */
  2404. if (!(rstat_rxf & (RSTAT_CLEAR_RXF0 >> i)))
  2405. continue;
  2406. rx_queue = priv->rx_queue[i];
  2407. work_done_per_q =
  2408. gfar_clean_rx_ring(rx_queue, budget_per_q);
  2409. work_done += work_done_per_q;
  2410. /* finished processing this queue */
  2411. if (work_done_per_q < budget_per_q) {
  2412. /* clear active queue hw indication */
  2413. gfar_write(&regs->rstat,
  2414. RSTAT_CLEAR_RXF0 >> i);
  2415. num_act_queues--;
  2416. if (!num_act_queues)
  2417. break;
  2418. }
  2419. }
  2420. if (!num_act_queues && !has_tx_work) {
  2421. napi_complete(napi);
  2422. /* Clear the halt bit in RSTAT */
  2423. gfar_write(&regs->rstat, gfargrp->rstat);
  2424. gfar_write(&regs->imask, IMASK_DEFAULT);
  2425. /* If we are coalescing interrupts, update the timer
  2426. * Otherwise, clear it
  2427. */
  2428. gfar_configure_coalescing(priv, gfargrp->rx_bit_map,
  2429. gfargrp->tx_bit_map);
  2430. }
  2431. return work_done;
  2432. }
  2433. #ifdef CONFIG_NET_POLL_CONTROLLER
  2434. /* Polling 'interrupt' - used by things like netconsole to send skbs
  2435. * without having to re-enable interrupts. It's not called while
  2436. * the interrupt routine is executing.
  2437. */
  2438. static void gfar_netpoll(struct net_device *dev)
  2439. {
  2440. struct gfar_private *priv = netdev_priv(dev);
  2441. int i;
  2442. /* If the device has multiple interrupts, run tx/rx */
  2443. if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
  2444. for (i = 0; i < priv->num_grps; i++) {
  2445. struct gfar_priv_grp *grp = &priv->gfargrp[i];
  2446. disable_irq(gfar_irq(grp, TX)->irq);
  2447. disable_irq(gfar_irq(grp, RX)->irq);
  2448. disable_irq(gfar_irq(grp, ER)->irq);
  2449. gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
  2450. enable_irq(gfar_irq(grp, ER)->irq);
  2451. enable_irq(gfar_irq(grp, RX)->irq);
  2452. enable_irq(gfar_irq(grp, TX)->irq);
  2453. }
  2454. } else {
  2455. for (i = 0; i < priv->num_grps; i++) {
  2456. struct gfar_priv_grp *grp = &priv->gfargrp[i];
  2457. disable_irq(gfar_irq(grp, TX)->irq);
  2458. gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
  2459. enable_irq(gfar_irq(grp, TX)->irq);
  2460. }
  2461. }
  2462. }
  2463. #endif
  2464. /* The interrupt handler for devices with one interrupt */
  2465. static irqreturn_t gfar_interrupt(int irq, void *grp_id)
  2466. {
  2467. struct gfar_priv_grp *gfargrp = grp_id;
  2468. /* Save ievent for future reference */
  2469. u32 events = gfar_read(&gfargrp->regs->ievent);
  2470. /* Check for reception */
  2471. if (events & IEVENT_RX_MASK)
  2472. gfar_receive(irq, grp_id);
  2473. /* Check for transmit completion */
  2474. if (events & IEVENT_TX_MASK)
  2475. gfar_transmit(irq, grp_id);
  2476. /* Check for errors */
  2477. if (events & IEVENT_ERR_MASK)
  2478. gfar_error(irq, grp_id);
  2479. return IRQ_HANDLED;
  2480. }
  2481. static u32 gfar_get_flowctrl_cfg(struct gfar_private *priv)
  2482. {
  2483. struct phy_device *phydev = priv->phydev;
  2484. u32 val = 0;
  2485. if (!phydev->duplex)
  2486. return val;
  2487. if (!priv->pause_aneg_en) {
  2488. if (priv->tx_pause_en)
  2489. val |= MACCFG1_TX_FLOW;
  2490. if (priv->rx_pause_en)
  2491. val |= MACCFG1_RX_FLOW;
  2492. } else {
  2493. u16 lcl_adv, rmt_adv;
  2494. u8 flowctrl;
  2495. /* get link partner capabilities */
  2496. rmt_adv = 0;
  2497. if (phydev->pause)
  2498. rmt_adv = LPA_PAUSE_CAP;
  2499. if (phydev->asym_pause)
  2500. rmt_adv |= LPA_PAUSE_ASYM;
  2501. lcl_adv = mii_advertise_flowctrl(phydev->advertising);
  2502. flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
  2503. if (flowctrl & FLOW_CTRL_TX)
  2504. val |= MACCFG1_TX_FLOW;
  2505. if (flowctrl & FLOW_CTRL_RX)
  2506. val |= MACCFG1_RX_FLOW;
  2507. }
  2508. return val;
  2509. }
  2510. /* Called every time the controller might need to be made
  2511. * aware of new link state. The PHY code conveys this
  2512. * information through variables in the phydev structure, and this
  2513. * function converts those variables into the appropriate
  2514. * register values, and can bring down the device if needed.
  2515. */
  2516. static void adjust_link(struct net_device *dev)
  2517. {
  2518. struct gfar_private *priv = netdev_priv(dev);
  2519. struct gfar __iomem *regs = priv->gfargrp[0].regs;
  2520. unsigned long flags;
  2521. struct phy_device *phydev = priv->phydev;
  2522. int new_state = 0;
  2523. local_irq_save(flags);
  2524. lock_tx_qs(priv);
  2525. if (phydev->link) {
  2526. u32 tempval1 = gfar_read(&regs->maccfg1);
  2527. u32 tempval = gfar_read(&regs->maccfg2);
  2528. u32 ecntrl = gfar_read(&regs->ecntrl);
  2529. /* Now we make sure that we can be in full duplex mode.
  2530. * If not, we operate in half-duplex mode.
  2531. */
  2532. if (phydev->duplex != priv->oldduplex) {
  2533. new_state = 1;
  2534. if (!(phydev->duplex))
  2535. tempval &= ~(MACCFG2_FULL_DUPLEX);
  2536. else
  2537. tempval |= MACCFG2_FULL_DUPLEX;
  2538. priv->oldduplex = phydev->duplex;
  2539. }
  2540. if (phydev->speed != priv->oldspeed) {
  2541. new_state = 1;
  2542. switch (phydev->speed) {
  2543. case 1000:
  2544. tempval =
  2545. ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
  2546. ecntrl &= ~(ECNTRL_R100);
  2547. break;
  2548. case 100:
  2549. case 10:
  2550. tempval =
  2551. ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
  2552. /* Reduced mode distinguishes
  2553. * between 10 and 100
  2554. */
  2555. if (phydev->speed == SPEED_100)
  2556. ecntrl |= ECNTRL_R100;
  2557. else
  2558. ecntrl &= ~(ECNTRL_R100);
  2559. break;
  2560. default:
  2561. netif_warn(priv, link, dev,
  2562. "Ack! Speed (%d) is not 10/100/1000!\n",
  2563. phydev->speed);
  2564. break;
  2565. }
  2566. priv->oldspeed = phydev->speed;
  2567. }
  2568. tempval1 &= ~(MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
  2569. tempval1 |= gfar_get_flowctrl_cfg(priv);
  2570. gfar_write(&regs->maccfg1, tempval1);
  2571. gfar_write(&regs->maccfg2, tempval);
  2572. gfar_write(&regs->ecntrl, ecntrl);
  2573. if (!priv->oldlink) {
  2574. new_state = 1;
  2575. priv->oldlink = 1;
  2576. }
  2577. } else if (priv->oldlink) {
  2578. new_state = 1;
  2579. priv->oldlink = 0;
  2580. priv->oldspeed = 0;
  2581. priv->oldduplex = -1;
  2582. }
  2583. if (new_state && netif_msg_link(priv))
  2584. phy_print_status(phydev);
  2585. unlock_tx_qs(priv);
  2586. local_irq_restore(flags);
  2587. }
  2588. /* Update the hash table based on the current list of multicast
  2589. * addresses we subscribe to. Also, change the promiscuity of
  2590. * the device based on the flags (this function is called
  2591. * whenever dev->flags is changed
  2592. */
  2593. static void gfar_set_multi(struct net_device *dev)
  2594. {
  2595. struct netdev_hw_addr *ha;
  2596. struct gfar_private *priv = netdev_priv(dev);
  2597. struct gfar __iomem *regs = priv->gfargrp[0].regs;
  2598. u32 tempval;
  2599. if (dev->flags & IFF_PROMISC) {
  2600. /* Set RCTRL to PROM */
  2601. tempval = gfar_read(&regs->rctrl);
  2602. tempval |= RCTRL_PROM;
  2603. gfar_write(&regs->rctrl, tempval);
  2604. } else {
  2605. /* Set RCTRL to not PROM */
  2606. tempval = gfar_read(&regs->rctrl);
  2607. tempval &= ~(RCTRL_PROM);
  2608. gfar_write(&regs->rctrl, tempval);
  2609. }
  2610. if (dev->flags & IFF_ALLMULTI) {
  2611. /* Set the hash to rx all multicast frames */
  2612. gfar_write(&regs->igaddr0, 0xffffffff);
  2613. gfar_write(&regs->igaddr1, 0xffffffff);
  2614. gfar_write(&regs->igaddr2, 0xffffffff);
  2615. gfar_write(&regs->igaddr3, 0xffffffff);
  2616. gfar_write(&regs->igaddr4, 0xffffffff);
  2617. gfar_write(&regs->igaddr5, 0xffffffff);
  2618. gfar_write(&regs->igaddr6, 0xffffffff);
  2619. gfar_write(&regs->igaddr7, 0xffffffff);
  2620. gfar_write(&regs->gaddr0, 0xffffffff);
  2621. gfar_write(&regs->gaddr1, 0xffffffff);
  2622. gfar_write(&regs->gaddr2, 0xffffffff);
  2623. gfar_write(&regs->gaddr3, 0xffffffff);
  2624. gfar_write(&regs->gaddr4, 0xffffffff);
  2625. gfar_write(&regs->gaddr5, 0xffffffff);
  2626. gfar_write(&regs->gaddr6, 0xffffffff);
  2627. gfar_write(&regs->gaddr7, 0xffffffff);
  2628. } else {
  2629. int em_num;
  2630. int idx;
  2631. /* zero out the hash */
  2632. gfar_write(&regs->igaddr0, 0x0);
  2633. gfar_write(&regs->igaddr1, 0x0);
  2634. gfar_write(&regs->igaddr2, 0x0);
  2635. gfar_write(&regs->igaddr3, 0x0);
  2636. gfar_write(&regs->igaddr4, 0x0);
  2637. gfar_write(&regs->igaddr5, 0x0);
  2638. gfar_write(&regs->igaddr6, 0x0);
  2639. gfar_write(&regs->igaddr7, 0x0);
  2640. gfar_write(&regs->gaddr0, 0x0);
  2641. gfar_write(&regs->gaddr1, 0x0);
  2642. gfar_write(&regs->gaddr2, 0x0);
  2643. gfar_write(&regs->gaddr3, 0x0);
  2644. gfar_write(&regs->gaddr4, 0x0);
  2645. gfar_write(&regs->gaddr5, 0x0);
  2646. gfar_write(&regs->gaddr6, 0x0);
  2647. gfar_write(&regs->gaddr7, 0x0);
  2648. /* If we have extended hash tables, we need to
  2649. * clear the exact match registers to prepare for
  2650. * setting them
  2651. */
  2652. if (priv->extended_hash) {
  2653. em_num = GFAR_EM_NUM + 1;
  2654. gfar_clear_exact_match(dev);
  2655. idx = 1;
  2656. } else {
  2657. idx = 0;
  2658. em_num = 0;
  2659. }
  2660. if (netdev_mc_empty(dev))
  2661. return;
  2662. /* Parse the list, and set the appropriate bits */
  2663. netdev_for_each_mc_addr(ha, dev) {
  2664. if (idx < em_num) {
  2665. gfar_set_mac_for_addr(dev, idx, ha->addr);
  2666. idx++;
  2667. } else
  2668. gfar_set_hash_for_addr(dev, ha->addr);
  2669. }
  2670. }
  2671. }
  2672. /* Clears each of the exact match registers to zero, so they
  2673. * don't interfere with normal reception
  2674. */
  2675. static void gfar_clear_exact_match(struct net_device *dev)
  2676. {
  2677. int idx;
  2678. static const u8 zero_arr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
  2679. for (idx = 1; idx < GFAR_EM_NUM + 1; idx++)
  2680. gfar_set_mac_for_addr(dev, idx, zero_arr);
  2681. }
  2682. /* Set the appropriate hash bit for the given addr */
  2683. /* The algorithm works like so:
  2684. * 1) Take the Destination Address (ie the multicast address), and
  2685. * do a CRC on it (little endian), and reverse the bits of the
  2686. * result.
  2687. * 2) Use the 8 most significant bits as a hash into a 256-entry
  2688. * table. The table is controlled through 8 32-bit registers:
  2689. * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
  2690. * gaddr7. This means that the 3 most significant bits in the
  2691. * hash index which gaddr register to use, and the 5 other bits
  2692. * indicate which bit (assuming an IBM numbering scheme, which
  2693. * for PowerPC (tm) is usually the case) in the register holds
  2694. * the entry.
  2695. */
  2696. static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
  2697. {
  2698. u32 tempval;
  2699. struct gfar_private *priv = netdev_priv(dev);
  2700. u32 result = ether_crc(ETH_ALEN, addr);
  2701. int width = priv->hash_width;
  2702. u8 whichbit = (result >> (32 - width)) & 0x1f;
  2703. u8 whichreg = result >> (32 - width + 5);
  2704. u32 value = (1 << (31-whichbit));
  2705. tempval = gfar_read(priv->hash_regs[whichreg]);
  2706. tempval |= value;
  2707. gfar_write(priv->hash_regs[whichreg], tempval);
  2708. }
  2709. /* There are multiple MAC Address register pairs on some controllers
  2710. * This function sets the numth pair to a given address
  2711. */
  2712. static void gfar_set_mac_for_addr(struct net_device *dev, int num,
  2713. const u8 *addr)
  2714. {
  2715. struct gfar_private *priv = netdev_priv(dev);
  2716. struct gfar __iomem *regs = priv->gfargrp[0].regs;
  2717. int idx;
  2718. char tmpbuf[ETH_ALEN];
  2719. u32 tempval;
  2720. u32 __iomem *macptr = &regs->macstnaddr1;
  2721. macptr += num*2;
  2722. /* Now copy it into the mac registers backwards, cuz
  2723. * little endian is silly
  2724. */
  2725. for (idx = 0; idx < ETH_ALEN; idx++)
  2726. tmpbuf[ETH_ALEN - 1 - idx] = addr[idx];
  2727. gfar_write(macptr, *((u32 *) (tmpbuf)));
  2728. tempval = *((u32 *) (tmpbuf + 4));
  2729. gfar_write(macptr+1, tempval);
  2730. }
  2731. /* GFAR error interrupt handler */
  2732. static irqreturn_t gfar_error(int irq, void *grp_id)
  2733. {
  2734. struct gfar_priv_grp *gfargrp = grp_id;
  2735. struct gfar __iomem *regs = gfargrp->regs;
  2736. struct gfar_private *priv= gfargrp->priv;
  2737. struct net_device *dev = priv->ndev;
  2738. /* Save ievent for future reference */
  2739. u32 events = gfar_read(&regs->ievent);
  2740. /* Clear IEVENT */
  2741. gfar_write(&regs->ievent, events & IEVENT_ERR_MASK);
  2742. /* Magic Packet is not an error. */
  2743. if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
  2744. (events & IEVENT_MAG))
  2745. events &= ~IEVENT_MAG;
  2746. /* Hmm... */
  2747. if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
  2748. netdev_dbg(dev,
  2749. "error interrupt (ievent=0x%08x imask=0x%08x)\n",
  2750. events, gfar_read(&regs->imask));
  2751. /* Update the error counters */
  2752. if (events & IEVENT_TXE) {
  2753. dev->stats.tx_errors++;
  2754. if (events & IEVENT_LC)
  2755. dev->stats.tx_window_errors++;
  2756. if (events & IEVENT_CRL)
  2757. dev->stats.tx_aborted_errors++;
  2758. if (events & IEVENT_XFUN) {
  2759. unsigned long flags;
  2760. netif_dbg(priv, tx_err, dev,
  2761. "TX FIFO underrun, packet dropped\n");
  2762. dev->stats.tx_dropped++;
  2763. atomic64_inc(&priv->extra_stats.tx_underrun);
  2764. local_irq_save(flags);
  2765. lock_tx_qs(priv);
  2766. /* Reactivate the Tx Queues */
  2767. gfar_write(&regs->tstat, gfargrp->tstat);
  2768. unlock_tx_qs(priv);
  2769. local_irq_restore(flags);
  2770. }
  2771. netif_dbg(priv, tx_err, dev, "Transmit Error\n");
  2772. }
  2773. if (events & IEVENT_BSY) {
  2774. dev->stats.rx_errors++;
  2775. atomic64_inc(&priv->extra_stats.rx_bsy);
  2776. gfar_receive(irq, grp_id);
  2777. netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n",
  2778. gfar_read(&regs->rstat));
  2779. }
  2780. if (events & IEVENT_BABR) {
  2781. dev->stats.rx_errors++;
  2782. atomic64_inc(&priv->extra_stats.rx_babr);
  2783. netif_dbg(priv, rx_err, dev, "babbling RX error\n");
  2784. }
  2785. if (events & IEVENT_EBERR) {
  2786. atomic64_inc(&priv->extra_stats.eberr);
  2787. netif_dbg(priv, rx_err, dev, "bus error\n");
  2788. }
  2789. if (events & IEVENT_RXC)
  2790. netif_dbg(priv, rx_status, dev, "control frame\n");
  2791. if (events & IEVENT_BABT) {
  2792. atomic64_inc(&priv->extra_stats.tx_babt);
  2793. netif_dbg(priv, tx_err, dev, "babbling TX error\n");
  2794. }
  2795. return IRQ_HANDLED;
  2796. }
  2797. static struct of_device_id gfar_match[] =
  2798. {
  2799. {
  2800. .type = "network",
  2801. .compatible = "gianfar",
  2802. },
  2803. {
  2804. .compatible = "fsl,etsec2",
  2805. },
  2806. {},
  2807. };
  2808. MODULE_DEVICE_TABLE(of, gfar_match);
  2809. /* Structure for a device driver */
  2810. static struct platform_driver gfar_driver = {
  2811. .driver = {
  2812. .name = "fsl-gianfar",
  2813. .owner = THIS_MODULE,
  2814. .pm = GFAR_PM_OPS,
  2815. .of_match_table = gfar_match,
  2816. },
  2817. .probe = gfar_probe,
  2818. .remove = gfar_remove,
  2819. };
  2820. module_platform_driver(gfar_driver);