fec_main.c 60 KB

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  1. /*
  2. * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
  3. * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
  4. *
  5. * Right now, I am very wasteful with the buffers. I allocate memory
  6. * pages and then divide them into 2K frame buffers. This way I know I
  7. * have buffers large enough to hold one frame within one buffer descriptor.
  8. * Once I get this working, I will use 64 or 128 byte CPM buffers, which
  9. * will be much more memory efficient and will easily handle lots of
  10. * small packets.
  11. *
  12. * Much better multiple PHY support by Magnus Damm.
  13. * Copyright (c) 2000 Ericsson Radio Systems AB.
  14. *
  15. * Support for FEC controller of ColdFire processors.
  16. * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
  17. *
  18. * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
  19. * Copyright (c) 2004-2006 Macq Electronique SA.
  20. *
  21. * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
  22. */
  23. #include <linux/module.h>
  24. #include <linux/kernel.h>
  25. #include <linux/string.h>
  26. #include <linux/ptrace.h>
  27. #include <linux/errno.h>
  28. #include <linux/ioport.h>
  29. #include <linux/slab.h>
  30. #include <linux/interrupt.h>
  31. #include <linux/init.h>
  32. #include <linux/delay.h>
  33. #include <linux/netdevice.h>
  34. #include <linux/etherdevice.h>
  35. #include <linux/skbuff.h>
  36. #include <linux/in.h>
  37. #include <linux/ip.h>
  38. #include <net/ip.h>
  39. #include <linux/tcp.h>
  40. #include <linux/udp.h>
  41. #include <linux/icmp.h>
  42. #include <linux/spinlock.h>
  43. #include <linux/workqueue.h>
  44. #include <linux/bitops.h>
  45. #include <linux/io.h>
  46. #include <linux/irq.h>
  47. #include <linux/clk.h>
  48. #include <linux/platform_device.h>
  49. #include <linux/phy.h>
  50. #include <linux/fec.h>
  51. #include <linux/of.h>
  52. #include <linux/of_device.h>
  53. #include <linux/of_gpio.h>
  54. #include <linux/of_net.h>
  55. #include <linux/regulator/consumer.h>
  56. #include <linux/if_vlan.h>
  57. #include <asm/cacheflush.h>
  58. #include "fec.h"
  59. static void set_multicast_list(struct net_device *ndev);
  60. #if defined(CONFIG_ARM)
  61. #define FEC_ALIGNMENT 0xf
  62. #else
  63. #define FEC_ALIGNMENT 0x3
  64. #endif
  65. #define DRIVER_NAME "fec"
  66. /* Pause frame feild and FIFO threshold */
  67. #define FEC_ENET_FCE (1 << 5)
  68. #define FEC_ENET_RSEM_V 0x84
  69. #define FEC_ENET_RSFL_V 16
  70. #define FEC_ENET_RAEM_V 0x8
  71. #define FEC_ENET_RAFL_V 0x8
  72. #define FEC_ENET_OPD_V 0xFFF0
  73. /* Controller is ENET-MAC */
  74. #define FEC_QUIRK_ENET_MAC (1 << 0)
  75. /* Controller needs driver to swap frame */
  76. #define FEC_QUIRK_SWAP_FRAME (1 << 1)
  77. /* Controller uses gasket */
  78. #define FEC_QUIRK_USE_GASKET (1 << 2)
  79. /* Controller has GBIT support */
  80. #define FEC_QUIRK_HAS_GBIT (1 << 3)
  81. /* Controller has extend desc buffer */
  82. #define FEC_QUIRK_HAS_BUFDESC_EX (1 << 4)
  83. /* Controller has hardware checksum support */
  84. #define FEC_QUIRK_HAS_CSUM (1 << 5)
  85. /* Controller has hardware vlan support */
  86. #define FEC_QUIRK_HAS_VLAN (1 << 6)
  87. /* ENET IP errata ERR006358
  88. *
  89. * If the ready bit in the transmit buffer descriptor (TxBD[R]) is previously
  90. * detected as not set during a prior frame transmission, then the
  91. * ENET_TDAR[TDAR] bit is cleared at a later time, even if additional TxBDs
  92. * were added to the ring and the ENET_TDAR[TDAR] bit is set. This results in
  93. * If the ready bit in the transmit buffer descriptor (TxBD[R]) is previously
  94. * detected as not set during a prior frame transmission, then the
  95. * ENET_TDAR[TDAR] bit is cleared at a later time, even if additional TxBDs
  96. * were added to the ring and the ENET_TDAR[TDAR] bit is set. This results in
  97. * frames not being transmitted until there is a 0-to-1 transition on
  98. * ENET_TDAR[TDAR].
  99. */
  100. #define FEC_QUIRK_ERR006358 (1 << 7)
  101. static struct platform_device_id fec_devtype[] = {
  102. {
  103. /* keep it for coldfire */
  104. .name = DRIVER_NAME,
  105. .driver_data = 0,
  106. }, {
  107. .name = "imx25-fec",
  108. .driver_data = FEC_QUIRK_USE_GASKET,
  109. }, {
  110. .name = "imx27-fec",
  111. .driver_data = 0,
  112. }, {
  113. .name = "imx28-fec",
  114. .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME,
  115. }, {
  116. .name = "imx6q-fec",
  117. .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
  118. FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
  119. FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358,
  120. }, {
  121. .name = "mvf600-fec",
  122. .driver_data = FEC_QUIRK_ENET_MAC,
  123. }, {
  124. /* sentinel */
  125. }
  126. };
  127. MODULE_DEVICE_TABLE(platform, fec_devtype);
  128. enum imx_fec_type {
  129. IMX25_FEC = 1, /* runs on i.mx25/50/53 */
  130. IMX27_FEC, /* runs on i.mx27/35/51 */
  131. IMX28_FEC,
  132. IMX6Q_FEC,
  133. MVF600_FEC,
  134. };
  135. static const struct of_device_id fec_dt_ids[] = {
  136. { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
  137. { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
  138. { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
  139. { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
  140. { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], },
  141. { /* sentinel */ }
  142. };
  143. MODULE_DEVICE_TABLE(of, fec_dt_ids);
  144. static unsigned char macaddr[ETH_ALEN];
  145. module_param_array(macaddr, byte, NULL, 0);
  146. MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
  147. #if defined(CONFIG_M5272)
  148. /*
  149. * Some hardware gets it MAC address out of local flash memory.
  150. * if this is non-zero then assume it is the address to get MAC from.
  151. */
  152. #if defined(CONFIG_NETtel)
  153. #define FEC_FLASHMAC 0xf0006006
  154. #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
  155. #define FEC_FLASHMAC 0xf0006000
  156. #elif defined(CONFIG_CANCam)
  157. #define FEC_FLASHMAC 0xf0020000
  158. #elif defined (CONFIG_M5272C3)
  159. #define FEC_FLASHMAC (0xffe04000 + 4)
  160. #elif defined(CONFIG_MOD5272)
  161. #define FEC_FLASHMAC 0xffc0406b
  162. #else
  163. #define FEC_FLASHMAC 0
  164. #endif
  165. #endif /* CONFIG_M5272 */
  166. #if (((RX_RING_SIZE + TX_RING_SIZE) * 32) > PAGE_SIZE)
  167. #error "FEC: descriptor ring size constants too large"
  168. #endif
  169. /* Interrupt events/masks. */
  170. #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
  171. #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
  172. #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
  173. #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
  174. #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
  175. #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
  176. #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
  177. #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
  178. #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
  179. #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
  180. #define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII)
  181. #define FEC_RX_DISABLED_IMASK (FEC_DEFAULT_IMASK & (~FEC_ENET_RXF))
  182. /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets.
  183. */
  184. #define PKT_MAXBUF_SIZE 1522
  185. #define PKT_MINBUF_SIZE 64
  186. #define PKT_MAXBLR_SIZE 1536
  187. /* FEC receive acceleration */
  188. #define FEC_RACC_IPDIS (1 << 1)
  189. #define FEC_RACC_PRODIS (1 << 2)
  190. #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS)
  191. /*
  192. * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
  193. * size bits. Other FEC hardware does not, so we need to take that into
  194. * account when setting it.
  195. */
  196. #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
  197. defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
  198. #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
  199. #else
  200. #define OPT_FRAME_SIZE 0
  201. #endif
  202. /* FEC MII MMFR bits definition */
  203. #define FEC_MMFR_ST (1 << 30)
  204. #define FEC_MMFR_OP_READ (2 << 28)
  205. #define FEC_MMFR_OP_WRITE (1 << 28)
  206. #define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
  207. #define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
  208. #define FEC_MMFR_TA (2 << 16)
  209. #define FEC_MMFR_DATA(v) (v & 0xffff)
  210. #define FEC_MII_TIMEOUT 30000 /* us */
  211. /* Transmitter timeout */
  212. #define TX_TIMEOUT (2 * HZ)
  213. #define FEC_PAUSE_FLAG_AUTONEG 0x1
  214. #define FEC_PAUSE_FLAG_ENABLE 0x2
  215. static int mii_cnt;
  216. static inline
  217. struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, struct fec_enet_private *fep)
  218. {
  219. struct bufdesc *new_bd = bdp + 1;
  220. struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp + 1;
  221. struct bufdesc_ex *ex_base;
  222. struct bufdesc *base;
  223. int ring_size;
  224. if (bdp >= fep->tx_bd_base) {
  225. base = fep->tx_bd_base;
  226. ring_size = fep->tx_ring_size;
  227. ex_base = (struct bufdesc_ex *)fep->tx_bd_base;
  228. } else {
  229. base = fep->rx_bd_base;
  230. ring_size = fep->rx_ring_size;
  231. ex_base = (struct bufdesc_ex *)fep->rx_bd_base;
  232. }
  233. if (fep->bufdesc_ex)
  234. return (struct bufdesc *)((ex_new_bd >= (ex_base + ring_size)) ?
  235. ex_base : ex_new_bd);
  236. else
  237. return (new_bd >= (base + ring_size)) ?
  238. base : new_bd;
  239. }
  240. static inline
  241. struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, struct fec_enet_private *fep)
  242. {
  243. struct bufdesc *new_bd = bdp - 1;
  244. struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp - 1;
  245. struct bufdesc_ex *ex_base;
  246. struct bufdesc *base;
  247. int ring_size;
  248. if (bdp >= fep->tx_bd_base) {
  249. base = fep->tx_bd_base;
  250. ring_size = fep->tx_ring_size;
  251. ex_base = (struct bufdesc_ex *)fep->tx_bd_base;
  252. } else {
  253. base = fep->rx_bd_base;
  254. ring_size = fep->rx_ring_size;
  255. ex_base = (struct bufdesc_ex *)fep->rx_bd_base;
  256. }
  257. if (fep->bufdesc_ex)
  258. return (struct bufdesc *)((ex_new_bd < ex_base) ?
  259. (ex_new_bd + ring_size) : ex_new_bd);
  260. else
  261. return (new_bd < base) ? (new_bd + ring_size) : new_bd;
  262. }
  263. static void *swap_buffer(void *bufaddr, int len)
  264. {
  265. int i;
  266. unsigned int *buf = bufaddr;
  267. for (i = 0; i < DIV_ROUND_UP(len, 4); i++, buf++)
  268. *buf = cpu_to_be32(*buf);
  269. return bufaddr;
  270. }
  271. static int
  272. fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev)
  273. {
  274. /* Only run for packets requiring a checksum. */
  275. if (skb->ip_summed != CHECKSUM_PARTIAL)
  276. return 0;
  277. if (unlikely(skb_cow_head(skb, 0)))
  278. return -1;
  279. *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0;
  280. return 0;
  281. }
  282. static netdev_tx_t
  283. fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
  284. {
  285. struct fec_enet_private *fep = netdev_priv(ndev);
  286. const struct platform_device_id *id_entry =
  287. platform_get_device_id(fep->pdev);
  288. struct bufdesc *bdp, *bdp_pre;
  289. void *bufaddr;
  290. unsigned short status;
  291. unsigned int index;
  292. /* Fill in a Tx ring entry */
  293. bdp = fep->cur_tx;
  294. status = bdp->cbd_sc;
  295. if (status & BD_ENET_TX_READY) {
  296. /* Ooops. All transmit buffers are full. Bail out.
  297. * This should not happen, since ndev->tbusy should be set.
  298. */
  299. netdev_err(ndev, "tx queue full!\n");
  300. return NETDEV_TX_BUSY;
  301. }
  302. /* Protocol checksum off-load for TCP and UDP. */
  303. if (fec_enet_clear_csum(skb, ndev)) {
  304. kfree_skb(skb);
  305. return NETDEV_TX_OK;
  306. }
  307. /* Clear all of the status flags */
  308. status &= ~BD_ENET_TX_STATS;
  309. /* Set buffer length and buffer pointer */
  310. bufaddr = skb->data;
  311. bdp->cbd_datlen = skb->len;
  312. /*
  313. * On some FEC implementations data must be aligned on
  314. * 4-byte boundaries. Use bounce buffers to copy data
  315. * and get it aligned. Ugh.
  316. */
  317. if (fep->bufdesc_ex)
  318. index = (struct bufdesc_ex *)bdp -
  319. (struct bufdesc_ex *)fep->tx_bd_base;
  320. else
  321. index = bdp - fep->tx_bd_base;
  322. if (((unsigned long) bufaddr) & FEC_ALIGNMENT) {
  323. memcpy(fep->tx_bounce[index], skb->data, skb->len);
  324. bufaddr = fep->tx_bounce[index];
  325. }
  326. /*
  327. * Some design made an incorrect assumption on endian mode of
  328. * the system that it's running on. As the result, driver has to
  329. * swap every frame going to and coming from the controller.
  330. */
  331. if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
  332. swap_buffer(bufaddr, skb->len);
  333. /* Save skb pointer */
  334. fep->tx_skbuff[index] = skb;
  335. /* Push the data cache so the CPM does not get stale memory
  336. * data.
  337. */
  338. bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, bufaddr,
  339. FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE);
  340. /* Send it on its way. Tell FEC it's ready, interrupt when done,
  341. * it's the last BD of the frame, and to put the CRC on the end.
  342. */
  343. status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR
  344. | BD_ENET_TX_LAST | BD_ENET_TX_TC);
  345. bdp->cbd_sc = status;
  346. if (fep->bufdesc_ex) {
  347. struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
  348. ebdp->cbd_bdu = 0;
  349. if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
  350. fep->hwts_tx_en)) {
  351. ebdp->cbd_esc = (BD_ENET_TX_TS | BD_ENET_TX_INT);
  352. skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
  353. } else {
  354. ebdp->cbd_esc = BD_ENET_TX_INT;
  355. /* Enable protocol checksum flags
  356. * We do not bother with the IP Checksum bits as they
  357. * are done by the kernel
  358. */
  359. if (skb->ip_summed == CHECKSUM_PARTIAL)
  360. ebdp->cbd_esc |= BD_ENET_TX_PINS;
  361. }
  362. }
  363. bdp_pre = fec_enet_get_prevdesc(bdp, fep);
  364. if ((id_entry->driver_data & FEC_QUIRK_ERR006358) &&
  365. !(bdp_pre->cbd_sc & BD_ENET_TX_READY)) {
  366. fep->delay_work.trig_tx = true;
  367. schedule_delayed_work(&(fep->delay_work.delay_work),
  368. msecs_to_jiffies(1));
  369. }
  370. /* If this was the last BD in the ring, start at the beginning again. */
  371. bdp = fec_enet_get_nextdesc(bdp, fep);
  372. fep->cur_tx = bdp;
  373. if (fep->cur_tx == fep->dirty_tx)
  374. netif_stop_queue(ndev);
  375. /* Trigger transmission start */
  376. writel(0, fep->hwp + FEC_X_DES_ACTIVE);
  377. skb_tx_timestamp(skb);
  378. return NETDEV_TX_OK;
  379. }
  380. /* Init RX & TX buffer descriptors
  381. */
  382. static void fec_enet_bd_init(struct net_device *dev)
  383. {
  384. struct fec_enet_private *fep = netdev_priv(dev);
  385. struct bufdesc *bdp;
  386. unsigned int i;
  387. /* Initialize the receive buffer descriptors. */
  388. bdp = fep->rx_bd_base;
  389. for (i = 0; i < fep->rx_ring_size; i++) {
  390. /* Initialize the BD for every fragment in the page. */
  391. if (bdp->cbd_bufaddr)
  392. bdp->cbd_sc = BD_ENET_RX_EMPTY;
  393. else
  394. bdp->cbd_sc = 0;
  395. bdp = fec_enet_get_nextdesc(bdp, fep);
  396. }
  397. /* Set the last buffer to wrap */
  398. bdp = fec_enet_get_prevdesc(bdp, fep);
  399. bdp->cbd_sc |= BD_SC_WRAP;
  400. fep->cur_rx = fep->rx_bd_base;
  401. /* ...and the same for transmit */
  402. bdp = fep->tx_bd_base;
  403. fep->cur_tx = bdp;
  404. for (i = 0; i < fep->tx_ring_size; i++) {
  405. /* Initialize the BD for every fragment in the page. */
  406. bdp->cbd_sc = 0;
  407. if (bdp->cbd_bufaddr && fep->tx_skbuff[i]) {
  408. dev_kfree_skb_any(fep->tx_skbuff[i]);
  409. fep->tx_skbuff[i] = NULL;
  410. }
  411. bdp->cbd_bufaddr = 0;
  412. bdp = fec_enet_get_nextdesc(bdp, fep);
  413. }
  414. /* Set the last buffer to wrap */
  415. bdp = fec_enet_get_prevdesc(bdp, fep);
  416. bdp->cbd_sc |= BD_SC_WRAP;
  417. fep->dirty_tx = bdp;
  418. }
  419. /* This function is called to start or restart the FEC during a link
  420. * change. This only happens when switching between half and full
  421. * duplex.
  422. */
  423. static void
  424. fec_restart(struct net_device *ndev, int duplex)
  425. {
  426. struct fec_enet_private *fep = netdev_priv(ndev);
  427. const struct platform_device_id *id_entry =
  428. platform_get_device_id(fep->pdev);
  429. int i;
  430. u32 val;
  431. u32 temp_mac[2];
  432. u32 rcntl = OPT_FRAME_SIZE | 0x04;
  433. u32 ecntl = 0x2; /* ETHEREN */
  434. if (netif_running(ndev)) {
  435. netif_device_detach(ndev);
  436. napi_disable(&fep->napi);
  437. netif_stop_queue(ndev);
  438. netif_tx_lock_bh(ndev);
  439. }
  440. /* Whack a reset. We should wait for this. */
  441. writel(1, fep->hwp + FEC_ECNTRL);
  442. udelay(10);
  443. /*
  444. * enet-mac reset will reset mac address registers too,
  445. * so need to reconfigure it.
  446. */
  447. if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
  448. memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
  449. writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW);
  450. writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH);
  451. }
  452. /* Clear any outstanding interrupt. */
  453. writel(0xffc00000, fep->hwp + FEC_IEVENT);
  454. /* Setup multicast filter. */
  455. set_multicast_list(ndev);
  456. #ifndef CONFIG_M5272
  457. writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
  458. writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
  459. #endif
  460. /* Set maximum receive buffer size. */
  461. writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE);
  462. fec_enet_bd_init(ndev);
  463. /* Set receive and transmit descriptor base. */
  464. writel(fep->bd_dma, fep->hwp + FEC_R_DES_START);
  465. if (fep->bufdesc_ex)
  466. writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc_ex)
  467. * fep->rx_ring_size, fep->hwp + FEC_X_DES_START);
  468. else
  469. writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc)
  470. * fep->rx_ring_size, fep->hwp + FEC_X_DES_START);
  471. for (i = 0; i <= TX_RING_MOD_MASK; i++) {
  472. if (fep->tx_skbuff[i]) {
  473. dev_kfree_skb_any(fep->tx_skbuff[i]);
  474. fep->tx_skbuff[i] = NULL;
  475. }
  476. }
  477. /* Enable MII mode */
  478. if (duplex) {
  479. /* FD enable */
  480. writel(0x04, fep->hwp + FEC_X_CNTRL);
  481. } else {
  482. /* No Rcv on Xmit */
  483. rcntl |= 0x02;
  484. writel(0x0, fep->hwp + FEC_X_CNTRL);
  485. }
  486. fep->full_duplex = duplex;
  487. /* Set MII speed */
  488. writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
  489. #if !defined(CONFIG_M5272)
  490. /* set RX checksum */
  491. val = readl(fep->hwp + FEC_RACC);
  492. if (fep->csum_flags & FLAG_RX_CSUM_ENABLED)
  493. val |= FEC_RACC_OPTIONS;
  494. else
  495. val &= ~FEC_RACC_OPTIONS;
  496. writel(val, fep->hwp + FEC_RACC);
  497. #endif
  498. /*
  499. * The phy interface and speed need to get configured
  500. * differently on enet-mac.
  501. */
  502. if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
  503. /* Enable flow control and length check */
  504. rcntl |= 0x40000000 | 0x00000020;
  505. /* RGMII, RMII or MII */
  506. if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII)
  507. rcntl |= (1 << 6);
  508. else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
  509. rcntl |= (1 << 8);
  510. else
  511. rcntl &= ~(1 << 8);
  512. /* 1G, 100M or 10M */
  513. if (fep->phy_dev) {
  514. if (fep->phy_dev->speed == SPEED_1000)
  515. ecntl |= (1 << 5);
  516. else if (fep->phy_dev->speed == SPEED_100)
  517. rcntl &= ~(1 << 9);
  518. else
  519. rcntl |= (1 << 9);
  520. }
  521. } else {
  522. #ifdef FEC_MIIGSK_ENR
  523. if (id_entry->driver_data & FEC_QUIRK_USE_GASKET) {
  524. u32 cfgr;
  525. /* disable the gasket and wait */
  526. writel(0, fep->hwp + FEC_MIIGSK_ENR);
  527. while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
  528. udelay(1);
  529. /*
  530. * configure the gasket:
  531. * RMII, 50 MHz, no loopback, no echo
  532. * MII, 25 MHz, no loopback, no echo
  533. */
  534. cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
  535. ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;
  536. if (fep->phy_dev && fep->phy_dev->speed == SPEED_10)
  537. cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;
  538. writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
  539. /* re-enable the gasket */
  540. writel(2, fep->hwp + FEC_MIIGSK_ENR);
  541. }
  542. #endif
  543. }
  544. #if !defined(CONFIG_M5272)
  545. /* enable pause frame*/
  546. if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) ||
  547. ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) &&
  548. fep->phy_dev && fep->phy_dev->pause)) {
  549. rcntl |= FEC_ENET_FCE;
  550. /* set FIFO threshold parameter to reduce overrun */
  551. writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM);
  552. writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL);
  553. writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM);
  554. writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL);
  555. /* OPD */
  556. writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD);
  557. } else {
  558. rcntl &= ~FEC_ENET_FCE;
  559. }
  560. #endif /* !defined(CONFIG_M5272) */
  561. writel(rcntl, fep->hwp + FEC_R_CNTRL);
  562. if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
  563. /* enable ENET endian swap */
  564. ecntl |= (1 << 8);
  565. /* enable ENET store and forward mode */
  566. writel(1 << 8, fep->hwp + FEC_X_WMRK);
  567. }
  568. if (fep->bufdesc_ex)
  569. ecntl |= (1 << 4);
  570. #ifndef CONFIG_M5272
  571. /* Enable the MIB statistic event counters */
  572. writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT);
  573. #endif
  574. /* And last, enable the transmit and receive processing */
  575. writel(ecntl, fep->hwp + FEC_ECNTRL);
  576. writel(0, fep->hwp + FEC_R_DES_ACTIVE);
  577. if (fep->bufdesc_ex)
  578. fec_ptp_start_cyclecounter(ndev);
  579. /* Enable interrupts we wish to service */
  580. writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
  581. if (netif_running(ndev)) {
  582. netif_tx_unlock_bh(ndev);
  583. netif_wake_queue(ndev);
  584. napi_enable(&fep->napi);
  585. netif_device_attach(ndev);
  586. }
  587. }
  588. static void
  589. fec_stop(struct net_device *ndev)
  590. {
  591. struct fec_enet_private *fep = netdev_priv(ndev);
  592. const struct platform_device_id *id_entry =
  593. platform_get_device_id(fep->pdev);
  594. u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8);
  595. /* We cannot expect a graceful transmit stop without link !!! */
  596. if (fep->link) {
  597. writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
  598. udelay(10);
  599. if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
  600. netdev_err(ndev, "Graceful transmit stop did not complete!\n");
  601. }
  602. /* Whack a reset. We should wait for this. */
  603. writel(1, fep->hwp + FEC_ECNTRL);
  604. udelay(10);
  605. writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
  606. writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
  607. /* We have to keep ENET enabled to have MII interrupt stay working */
  608. if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
  609. writel(2, fep->hwp + FEC_ECNTRL);
  610. writel(rmii_mode, fep->hwp + FEC_R_CNTRL);
  611. }
  612. }
  613. static void
  614. fec_timeout(struct net_device *ndev)
  615. {
  616. struct fec_enet_private *fep = netdev_priv(ndev);
  617. ndev->stats.tx_errors++;
  618. fep->delay_work.timeout = true;
  619. schedule_delayed_work(&(fep->delay_work.delay_work), 0);
  620. }
  621. static void fec_enet_work(struct work_struct *work)
  622. {
  623. struct fec_enet_private *fep =
  624. container_of(work,
  625. struct fec_enet_private,
  626. delay_work.delay_work.work);
  627. if (fep->delay_work.timeout) {
  628. fep->delay_work.timeout = false;
  629. fec_restart(fep->netdev, fep->full_duplex);
  630. netif_wake_queue(fep->netdev);
  631. }
  632. if (fep->delay_work.trig_tx) {
  633. fep->delay_work.trig_tx = false;
  634. writel(0, fep->hwp + FEC_X_DES_ACTIVE);
  635. }
  636. }
  637. static void
  638. fec_enet_tx(struct net_device *ndev)
  639. {
  640. struct fec_enet_private *fep;
  641. struct bufdesc *bdp;
  642. unsigned short status;
  643. struct sk_buff *skb;
  644. int index = 0;
  645. fep = netdev_priv(ndev);
  646. bdp = fep->dirty_tx;
  647. /* get next bdp of dirty_tx */
  648. bdp = fec_enet_get_nextdesc(bdp, fep);
  649. while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) {
  650. /* current queue is empty */
  651. if (bdp == fep->cur_tx)
  652. break;
  653. if (fep->bufdesc_ex)
  654. index = (struct bufdesc_ex *)bdp -
  655. (struct bufdesc_ex *)fep->tx_bd_base;
  656. else
  657. index = bdp - fep->tx_bd_base;
  658. dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
  659. FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE);
  660. bdp->cbd_bufaddr = 0;
  661. skb = fep->tx_skbuff[index];
  662. /* Check for errors. */
  663. if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
  664. BD_ENET_TX_RL | BD_ENET_TX_UN |
  665. BD_ENET_TX_CSL)) {
  666. ndev->stats.tx_errors++;
  667. if (status & BD_ENET_TX_HB) /* No heartbeat */
  668. ndev->stats.tx_heartbeat_errors++;
  669. if (status & BD_ENET_TX_LC) /* Late collision */
  670. ndev->stats.tx_window_errors++;
  671. if (status & BD_ENET_TX_RL) /* Retrans limit */
  672. ndev->stats.tx_aborted_errors++;
  673. if (status & BD_ENET_TX_UN) /* Underrun */
  674. ndev->stats.tx_fifo_errors++;
  675. if (status & BD_ENET_TX_CSL) /* Carrier lost */
  676. ndev->stats.tx_carrier_errors++;
  677. } else {
  678. ndev->stats.tx_packets++;
  679. ndev->stats.tx_bytes += bdp->cbd_datlen;
  680. }
  681. if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) &&
  682. fep->bufdesc_ex) {
  683. struct skb_shared_hwtstamps shhwtstamps;
  684. unsigned long flags;
  685. struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
  686. memset(&shhwtstamps, 0, sizeof(shhwtstamps));
  687. spin_lock_irqsave(&fep->tmreg_lock, flags);
  688. shhwtstamps.hwtstamp = ns_to_ktime(
  689. timecounter_cyc2time(&fep->tc, ebdp->ts));
  690. spin_unlock_irqrestore(&fep->tmreg_lock, flags);
  691. skb_tstamp_tx(skb, &shhwtstamps);
  692. }
  693. if (status & BD_ENET_TX_READY)
  694. netdev_err(ndev, "HEY! Enet xmit interrupt and TX_READY\n");
  695. /* Deferred means some collisions occurred during transmit,
  696. * but we eventually sent the packet OK.
  697. */
  698. if (status & BD_ENET_TX_DEF)
  699. ndev->stats.collisions++;
  700. /* Free the sk buffer associated with this last transmit */
  701. dev_kfree_skb_any(skb);
  702. fep->tx_skbuff[index] = NULL;
  703. fep->dirty_tx = bdp;
  704. /* Update pointer to next buffer descriptor to be transmitted */
  705. bdp = fec_enet_get_nextdesc(bdp, fep);
  706. /* Since we have freed up a buffer, the ring is no longer full
  707. */
  708. if (fep->dirty_tx != fep->cur_tx) {
  709. if (netif_queue_stopped(ndev))
  710. netif_wake_queue(ndev);
  711. }
  712. }
  713. return;
  714. }
  715. /* During a receive, the cur_rx points to the current incoming buffer.
  716. * When we update through the ring, if the next incoming buffer has
  717. * not been given to the system, we just set the empty indicator,
  718. * effectively tossing the packet.
  719. */
  720. static int
  721. fec_enet_rx(struct net_device *ndev, int budget)
  722. {
  723. struct fec_enet_private *fep = netdev_priv(ndev);
  724. const struct platform_device_id *id_entry =
  725. platform_get_device_id(fep->pdev);
  726. struct bufdesc *bdp;
  727. unsigned short status;
  728. struct sk_buff *skb;
  729. ushort pkt_len;
  730. __u8 *data;
  731. int pkt_received = 0;
  732. struct bufdesc_ex *ebdp = NULL;
  733. bool vlan_packet_rcvd = false;
  734. u16 vlan_tag;
  735. #ifdef CONFIG_M532x
  736. flush_cache_all();
  737. #endif
  738. /* First, grab all of the stats for the incoming packet.
  739. * These get messed up if we get called due to a busy condition.
  740. */
  741. bdp = fep->cur_rx;
  742. while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
  743. if (pkt_received >= budget)
  744. break;
  745. pkt_received++;
  746. /* Since we have allocated space to hold a complete frame,
  747. * the last indicator should be set.
  748. */
  749. if ((status & BD_ENET_RX_LAST) == 0)
  750. netdev_err(ndev, "rcv is not +last\n");
  751. if (!fep->opened)
  752. goto rx_processing_done;
  753. /* Check for errors. */
  754. if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
  755. BD_ENET_RX_CR | BD_ENET_RX_OV)) {
  756. ndev->stats.rx_errors++;
  757. if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
  758. /* Frame too long or too short. */
  759. ndev->stats.rx_length_errors++;
  760. }
  761. if (status & BD_ENET_RX_NO) /* Frame alignment */
  762. ndev->stats.rx_frame_errors++;
  763. if (status & BD_ENET_RX_CR) /* CRC Error */
  764. ndev->stats.rx_crc_errors++;
  765. if (status & BD_ENET_RX_OV) /* FIFO overrun */
  766. ndev->stats.rx_fifo_errors++;
  767. }
  768. /* Report late collisions as a frame error.
  769. * On this error, the BD is closed, but we don't know what we
  770. * have in the buffer. So, just drop this frame on the floor.
  771. */
  772. if (status & BD_ENET_RX_CL) {
  773. ndev->stats.rx_errors++;
  774. ndev->stats.rx_frame_errors++;
  775. goto rx_processing_done;
  776. }
  777. /* Process the incoming frame. */
  778. ndev->stats.rx_packets++;
  779. pkt_len = bdp->cbd_datlen;
  780. ndev->stats.rx_bytes += pkt_len;
  781. data = (__u8*)__va(bdp->cbd_bufaddr);
  782. dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
  783. FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE);
  784. if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
  785. swap_buffer(data, pkt_len);
  786. /* Extract the enhanced buffer descriptor */
  787. ebdp = NULL;
  788. if (fep->bufdesc_ex)
  789. ebdp = (struct bufdesc_ex *)bdp;
  790. /* If this is a VLAN packet remove the VLAN Tag */
  791. vlan_packet_rcvd = false;
  792. if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
  793. fep->bufdesc_ex && (ebdp->cbd_esc & BD_ENET_RX_VLAN)) {
  794. /* Push and remove the vlan tag */
  795. struct vlan_hdr *vlan_header =
  796. (struct vlan_hdr *) (data + ETH_HLEN);
  797. vlan_tag = ntohs(vlan_header->h_vlan_TCI);
  798. pkt_len -= VLAN_HLEN;
  799. vlan_packet_rcvd = true;
  800. }
  801. /* This does 16 byte alignment, exactly what we need.
  802. * The packet length includes FCS, but we don't want to
  803. * include that when passing upstream as it messes up
  804. * bridging applications.
  805. */
  806. skb = netdev_alloc_skb(ndev, pkt_len - 4 + NET_IP_ALIGN);
  807. if (unlikely(!skb)) {
  808. ndev->stats.rx_dropped++;
  809. } else {
  810. int payload_offset = (2 * ETH_ALEN);
  811. skb_reserve(skb, NET_IP_ALIGN);
  812. skb_put(skb, pkt_len - 4); /* Make room */
  813. /* Extract the frame data without the VLAN header. */
  814. skb_copy_to_linear_data(skb, data, (2 * ETH_ALEN));
  815. if (vlan_packet_rcvd)
  816. payload_offset = (2 * ETH_ALEN) + VLAN_HLEN;
  817. skb_copy_to_linear_data_offset(skb, (2 * ETH_ALEN),
  818. data + payload_offset,
  819. pkt_len - 4 - (2 * ETH_ALEN));
  820. skb->protocol = eth_type_trans(skb, ndev);
  821. /* Get receive timestamp from the skb */
  822. if (fep->hwts_rx_en && fep->bufdesc_ex) {
  823. struct skb_shared_hwtstamps *shhwtstamps =
  824. skb_hwtstamps(skb);
  825. unsigned long flags;
  826. memset(shhwtstamps, 0, sizeof(*shhwtstamps));
  827. spin_lock_irqsave(&fep->tmreg_lock, flags);
  828. shhwtstamps->hwtstamp = ns_to_ktime(
  829. timecounter_cyc2time(&fep->tc, ebdp->ts));
  830. spin_unlock_irqrestore(&fep->tmreg_lock, flags);
  831. }
  832. if (fep->bufdesc_ex &&
  833. (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) {
  834. if (!(ebdp->cbd_esc & FLAG_RX_CSUM_ERROR)) {
  835. /* don't check it */
  836. skb->ip_summed = CHECKSUM_UNNECESSARY;
  837. } else {
  838. skb_checksum_none_assert(skb);
  839. }
  840. }
  841. /* Handle received VLAN packets */
  842. if (vlan_packet_rcvd)
  843. __vlan_hwaccel_put_tag(skb,
  844. htons(ETH_P_8021Q),
  845. vlan_tag);
  846. napi_gro_receive(&fep->napi, skb);
  847. }
  848. bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, data,
  849. FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE);
  850. rx_processing_done:
  851. /* Clear the status flags for this buffer */
  852. status &= ~BD_ENET_RX_STATS;
  853. /* Mark the buffer empty */
  854. status |= BD_ENET_RX_EMPTY;
  855. bdp->cbd_sc = status;
  856. if (fep->bufdesc_ex) {
  857. struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
  858. ebdp->cbd_esc = BD_ENET_RX_INT;
  859. ebdp->cbd_prot = 0;
  860. ebdp->cbd_bdu = 0;
  861. }
  862. /* Update BD pointer to next entry */
  863. bdp = fec_enet_get_nextdesc(bdp, fep);
  864. /* Doing this here will keep the FEC running while we process
  865. * incoming frames. On a heavily loaded network, we should be
  866. * able to keep up at the expense of system resources.
  867. */
  868. writel(0, fep->hwp + FEC_R_DES_ACTIVE);
  869. }
  870. fep->cur_rx = bdp;
  871. return pkt_received;
  872. }
  873. static irqreturn_t
  874. fec_enet_interrupt(int irq, void *dev_id)
  875. {
  876. struct net_device *ndev = dev_id;
  877. struct fec_enet_private *fep = netdev_priv(ndev);
  878. uint int_events;
  879. irqreturn_t ret = IRQ_NONE;
  880. do {
  881. int_events = readl(fep->hwp + FEC_IEVENT);
  882. writel(int_events, fep->hwp + FEC_IEVENT);
  883. if (int_events & (FEC_ENET_RXF | FEC_ENET_TXF)) {
  884. ret = IRQ_HANDLED;
  885. /* Disable the RX interrupt */
  886. if (napi_schedule_prep(&fep->napi)) {
  887. writel(FEC_RX_DISABLED_IMASK,
  888. fep->hwp + FEC_IMASK);
  889. __napi_schedule(&fep->napi);
  890. }
  891. }
  892. if (int_events & FEC_ENET_MII) {
  893. ret = IRQ_HANDLED;
  894. complete(&fep->mdio_done);
  895. }
  896. } while (int_events);
  897. return ret;
  898. }
  899. static int fec_enet_rx_napi(struct napi_struct *napi, int budget)
  900. {
  901. struct net_device *ndev = napi->dev;
  902. int pkts = fec_enet_rx(ndev, budget);
  903. struct fec_enet_private *fep = netdev_priv(ndev);
  904. fec_enet_tx(ndev);
  905. if (pkts < budget) {
  906. napi_complete(napi);
  907. writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
  908. }
  909. return pkts;
  910. }
  911. /* ------------------------------------------------------------------------- */
  912. static void fec_get_mac(struct net_device *ndev)
  913. {
  914. struct fec_enet_private *fep = netdev_priv(ndev);
  915. struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev);
  916. unsigned char *iap, tmpaddr[ETH_ALEN];
  917. /*
  918. * try to get mac address in following order:
  919. *
  920. * 1) module parameter via kernel command line in form
  921. * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
  922. */
  923. iap = macaddr;
  924. /*
  925. * 2) from device tree data
  926. */
  927. if (!is_valid_ether_addr(iap)) {
  928. struct device_node *np = fep->pdev->dev.of_node;
  929. if (np) {
  930. const char *mac = of_get_mac_address(np);
  931. if (mac)
  932. iap = (unsigned char *) mac;
  933. }
  934. }
  935. /*
  936. * 3) from flash or fuse (via platform data)
  937. */
  938. if (!is_valid_ether_addr(iap)) {
  939. #ifdef CONFIG_M5272
  940. if (FEC_FLASHMAC)
  941. iap = (unsigned char *)FEC_FLASHMAC;
  942. #else
  943. if (pdata)
  944. iap = (unsigned char *)&pdata->mac;
  945. #endif
  946. }
  947. /*
  948. * 4) FEC mac registers set by bootloader
  949. */
  950. if (!is_valid_ether_addr(iap)) {
  951. *((__be32 *) &tmpaddr[0]) =
  952. cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW));
  953. *((__be16 *) &tmpaddr[4]) =
  954. cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
  955. iap = &tmpaddr[0];
  956. }
  957. /*
  958. * 5) random mac address
  959. */
  960. if (!is_valid_ether_addr(iap)) {
  961. /* Report it and use a random ethernet address instead */
  962. netdev_err(ndev, "Invalid MAC address: %pM\n", iap);
  963. eth_hw_addr_random(ndev);
  964. netdev_info(ndev, "Using random MAC address: %pM\n",
  965. ndev->dev_addr);
  966. return;
  967. }
  968. memcpy(ndev->dev_addr, iap, ETH_ALEN);
  969. /* Adjust MAC if using macaddr */
  970. if (iap == macaddr)
  971. ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id;
  972. }
  973. /* ------------------------------------------------------------------------- */
  974. /*
  975. * Phy section
  976. */
  977. static void fec_enet_adjust_link(struct net_device *ndev)
  978. {
  979. struct fec_enet_private *fep = netdev_priv(ndev);
  980. struct phy_device *phy_dev = fep->phy_dev;
  981. int status_change = 0;
  982. /* Prevent a state halted on mii error */
  983. if (fep->mii_timeout && phy_dev->state == PHY_HALTED) {
  984. phy_dev->state = PHY_RESUMING;
  985. return;
  986. }
  987. if (phy_dev->link) {
  988. if (!fep->link) {
  989. fep->link = phy_dev->link;
  990. status_change = 1;
  991. }
  992. if (fep->full_duplex != phy_dev->duplex)
  993. status_change = 1;
  994. if (phy_dev->speed != fep->speed) {
  995. fep->speed = phy_dev->speed;
  996. status_change = 1;
  997. }
  998. /* if any of the above changed restart the FEC */
  999. if (status_change)
  1000. fec_restart(ndev, phy_dev->duplex);
  1001. } else {
  1002. if (fep->link) {
  1003. fec_stop(ndev);
  1004. fep->link = phy_dev->link;
  1005. status_change = 1;
  1006. }
  1007. }
  1008. if (status_change)
  1009. phy_print_status(phy_dev);
  1010. }
  1011. static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
  1012. {
  1013. struct fec_enet_private *fep = bus->priv;
  1014. unsigned long time_left;
  1015. fep->mii_timeout = 0;
  1016. init_completion(&fep->mdio_done);
  1017. /* start a read op */
  1018. writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
  1019. FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
  1020. FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
  1021. /* wait for end of transfer */
  1022. time_left = wait_for_completion_timeout(&fep->mdio_done,
  1023. usecs_to_jiffies(FEC_MII_TIMEOUT));
  1024. if (time_left == 0) {
  1025. fep->mii_timeout = 1;
  1026. netdev_err(fep->netdev, "MDIO read timeout\n");
  1027. return -ETIMEDOUT;
  1028. }
  1029. /* return value */
  1030. return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
  1031. }
  1032. static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
  1033. u16 value)
  1034. {
  1035. struct fec_enet_private *fep = bus->priv;
  1036. unsigned long time_left;
  1037. fep->mii_timeout = 0;
  1038. init_completion(&fep->mdio_done);
  1039. /* start a write op */
  1040. writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
  1041. FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
  1042. FEC_MMFR_TA | FEC_MMFR_DATA(value),
  1043. fep->hwp + FEC_MII_DATA);
  1044. /* wait for end of transfer */
  1045. time_left = wait_for_completion_timeout(&fep->mdio_done,
  1046. usecs_to_jiffies(FEC_MII_TIMEOUT));
  1047. if (time_left == 0) {
  1048. fep->mii_timeout = 1;
  1049. netdev_err(fep->netdev, "MDIO write timeout\n");
  1050. return -ETIMEDOUT;
  1051. }
  1052. return 0;
  1053. }
  1054. static int fec_enet_mdio_reset(struct mii_bus *bus)
  1055. {
  1056. return 0;
  1057. }
  1058. static int fec_enet_mii_probe(struct net_device *ndev)
  1059. {
  1060. struct fec_enet_private *fep = netdev_priv(ndev);
  1061. const struct platform_device_id *id_entry =
  1062. platform_get_device_id(fep->pdev);
  1063. struct phy_device *phy_dev = NULL;
  1064. char mdio_bus_id[MII_BUS_ID_SIZE];
  1065. char phy_name[MII_BUS_ID_SIZE + 3];
  1066. int phy_id;
  1067. int dev_id = fep->dev_id;
  1068. fep->phy_dev = NULL;
  1069. /* check for attached phy */
  1070. for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
  1071. if ((fep->mii_bus->phy_mask & (1 << phy_id)))
  1072. continue;
  1073. if (fep->mii_bus->phy_map[phy_id] == NULL)
  1074. continue;
  1075. if (fep->mii_bus->phy_map[phy_id]->phy_id == 0)
  1076. continue;
  1077. if (dev_id--)
  1078. continue;
  1079. strncpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
  1080. break;
  1081. }
  1082. if (phy_id >= PHY_MAX_ADDR) {
  1083. netdev_info(ndev, "no PHY, assuming direct connection to switch\n");
  1084. strncpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
  1085. phy_id = 0;
  1086. }
  1087. snprintf(phy_name, sizeof(phy_name), PHY_ID_FMT, mdio_bus_id, phy_id);
  1088. phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link,
  1089. fep->phy_interface);
  1090. if (IS_ERR(phy_dev)) {
  1091. netdev_err(ndev, "could not attach to PHY\n");
  1092. return PTR_ERR(phy_dev);
  1093. }
  1094. /* mask with MAC supported features */
  1095. if (id_entry->driver_data & FEC_QUIRK_HAS_GBIT) {
  1096. phy_dev->supported &= PHY_GBIT_FEATURES;
  1097. #if !defined(CONFIG_M5272)
  1098. phy_dev->supported |= SUPPORTED_Pause;
  1099. #endif
  1100. }
  1101. else
  1102. phy_dev->supported &= PHY_BASIC_FEATURES;
  1103. phy_dev->advertising = phy_dev->supported;
  1104. fep->phy_dev = phy_dev;
  1105. fep->link = 0;
  1106. fep->full_duplex = 0;
  1107. netdev_info(ndev, "Freescale FEC PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
  1108. fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev),
  1109. fep->phy_dev->irq);
  1110. return 0;
  1111. }
  1112. static int fec_enet_mii_init(struct platform_device *pdev)
  1113. {
  1114. static struct mii_bus *fec0_mii_bus;
  1115. struct net_device *ndev = platform_get_drvdata(pdev);
  1116. struct fec_enet_private *fep = netdev_priv(ndev);
  1117. const struct platform_device_id *id_entry =
  1118. platform_get_device_id(fep->pdev);
  1119. int err = -ENXIO, i;
  1120. /*
  1121. * The dual fec interfaces are not equivalent with enet-mac.
  1122. * Here are the differences:
  1123. *
  1124. * - fec0 supports MII & RMII modes while fec1 only supports RMII
  1125. * - fec0 acts as the 1588 time master while fec1 is slave
  1126. * - external phys can only be configured by fec0
  1127. *
  1128. * That is to say fec1 can not work independently. It only works
  1129. * when fec0 is working. The reason behind this design is that the
  1130. * second interface is added primarily for Switch mode.
  1131. *
  1132. * Because of the last point above, both phys are attached on fec0
  1133. * mdio interface in board design, and need to be configured by
  1134. * fec0 mii_bus.
  1135. */
  1136. if ((id_entry->driver_data & FEC_QUIRK_ENET_MAC) && fep->dev_id > 0) {
  1137. /* fec1 uses fec0 mii_bus */
  1138. if (mii_cnt && fec0_mii_bus) {
  1139. fep->mii_bus = fec0_mii_bus;
  1140. mii_cnt++;
  1141. return 0;
  1142. }
  1143. return -ENOENT;
  1144. }
  1145. fep->mii_timeout = 0;
  1146. /*
  1147. * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
  1148. *
  1149. * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
  1150. * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28
  1151. * Reference Manual has an error on this, and gets fixed on i.MX6Q
  1152. * document.
  1153. */
  1154. fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ahb), 5000000);
  1155. if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
  1156. fep->phy_speed--;
  1157. fep->phy_speed <<= 1;
  1158. writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
  1159. fep->mii_bus = mdiobus_alloc();
  1160. if (fep->mii_bus == NULL) {
  1161. err = -ENOMEM;
  1162. goto err_out;
  1163. }
  1164. fep->mii_bus->name = "fec_enet_mii_bus";
  1165. fep->mii_bus->read = fec_enet_mdio_read;
  1166. fep->mii_bus->write = fec_enet_mdio_write;
  1167. fep->mii_bus->reset = fec_enet_mdio_reset;
  1168. snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
  1169. pdev->name, fep->dev_id + 1);
  1170. fep->mii_bus->priv = fep;
  1171. fep->mii_bus->parent = &pdev->dev;
  1172. fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
  1173. if (!fep->mii_bus->irq) {
  1174. err = -ENOMEM;
  1175. goto err_out_free_mdiobus;
  1176. }
  1177. for (i = 0; i < PHY_MAX_ADDR; i++)
  1178. fep->mii_bus->irq[i] = PHY_POLL;
  1179. if (mdiobus_register(fep->mii_bus))
  1180. goto err_out_free_mdio_irq;
  1181. mii_cnt++;
  1182. /* save fec0 mii_bus */
  1183. if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
  1184. fec0_mii_bus = fep->mii_bus;
  1185. return 0;
  1186. err_out_free_mdio_irq:
  1187. kfree(fep->mii_bus->irq);
  1188. err_out_free_mdiobus:
  1189. mdiobus_free(fep->mii_bus);
  1190. err_out:
  1191. return err;
  1192. }
  1193. static void fec_enet_mii_remove(struct fec_enet_private *fep)
  1194. {
  1195. if (--mii_cnt == 0) {
  1196. mdiobus_unregister(fep->mii_bus);
  1197. kfree(fep->mii_bus->irq);
  1198. mdiobus_free(fep->mii_bus);
  1199. }
  1200. }
  1201. static int fec_enet_get_settings(struct net_device *ndev,
  1202. struct ethtool_cmd *cmd)
  1203. {
  1204. struct fec_enet_private *fep = netdev_priv(ndev);
  1205. struct phy_device *phydev = fep->phy_dev;
  1206. if (!phydev)
  1207. return -ENODEV;
  1208. return phy_ethtool_gset(phydev, cmd);
  1209. }
  1210. static int fec_enet_set_settings(struct net_device *ndev,
  1211. struct ethtool_cmd *cmd)
  1212. {
  1213. struct fec_enet_private *fep = netdev_priv(ndev);
  1214. struct phy_device *phydev = fep->phy_dev;
  1215. if (!phydev)
  1216. return -ENODEV;
  1217. return phy_ethtool_sset(phydev, cmd);
  1218. }
  1219. static void fec_enet_get_drvinfo(struct net_device *ndev,
  1220. struct ethtool_drvinfo *info)
  1221. {
  1222. struct fec_enet_private *fep = netdev_priv(ndev);
  1223. strlcpy(info->driver, fep->pdev->dev.driver->name,
  1224. sizeof(info->driver));
  1225. strlcpy(info->version, "Revision: 1.0", sizeof(info->version));
  1226. strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info));
  1227. }
  1228. static int fec_enet_get_ts_info(struct net_device *ndev,
  1229. struct ethtool_ts_info *info)
  1230. {
  1231. struct fec_enet_private *fep = netdev_priv(ndev);
  1232. if (fep->bufdesc_ex) {
  1233. info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
  1234. SOF_TIMESTAMPING_RX_SOFTWARE |
  1235. SOF_TIMESTAMPING_SOFTWARE |
  1236. SOF_TIMESTAMPING_TX_HARDWARE |
  1237. SOF_TIMESTAMPING_RX_HARDWARE |
  1238. SOF_TIMESTAMPING_RAW_HARDWARE;
  1239. if (fep->ptp_clock)
  1240. info->phc_index = ptp_clock_index(fep->ptp_clock);
  1241. else
  1242. info->phc_index = -1;
  1243. info->tx_types = (1 << HWTSTAMP_TX_OFF) |
  1244. (1 << HWTSTAMP_TX_ON);
  1245. info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
  1246. (1 << HWTSTAMP_FILTER_ALL);
  1247. return 0;
  1248. } else {
  1249. return ethtool_op_get_ts_info(ndev, info);
  1250. }
  1251. }
  1252. #if !defined(CONFIG_M5272)
  1253. static void fec_enet_get_pauseparam(struct net_device *ndev,
  1254. struct ethtool_pauseparam *pause)
  1255. {
  1256. struct fec_enet_private *fep = netdev_priv(ndev);
  1257. pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0;
  1258. pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0;
  1259. pause->rx_pause = pause->tx_pause;
  1260. }
  1261. static int fec_enet_set_pauseparam(struct net_device *ndev,
  1262. struct ethtool_pauseparam *pause)
  1263. {
  1264. struct fec_enet_private *fep = netdev_priv(ndev);
  1265. if (pause->tx_pause != pause->rx_pause) {
  1266. netdev_info(ndev,
  1267. "hardware only support enable/disable both tx and rx");
  1268. return -EINVAL;
  1269. }
  1270. fep->pause_flag = 0;
  1271. /* tx pause must be same as rx pause */
  1272. fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0;
  1273. fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0;
  1274. if (pause->rx_pause || pause->autoneg) {
  1275. fep->phy_dev->supported |= ADVERTISED_Pause;
  1276. fep->phy_dev->advertising |= ADVERTISED_Pause;
  1277. } else {
  1278. fep->phy_dev->supported &= ~ADVERTISED_Pause;
  1279. fep->phy_dev->advertising &= ~ADVERTISED_Pause;
  1280. }
  1281. if (pause->autoneg) {
  1282. if (netif_running(ndev))
  1283. fec_stop(ndev);
  1284. phy_start_aneg(fep->phy_dev);
  1285. }
  1286. if (netif_running(ndev))
  1287. fec_restart(ndev, 0);
  1288. return 0;
  1289. }
  1290. static const struct fec_stat {
  1291. char name[ETH_GSTRING_LEN];
  1292. u16 offset;
  1293. } fec_stats[] = {
  1294. /* RMON TX */
  1295. { "tx_dropped", RMON_T_DROP },
  1296. { "tx_packets", RMON_T_PACKETS },
  1297. { "tx_broadcast", RMON_T_BC_PKT },
  1298. { "tx_multicast", RMON_T_MC_PKT },
  1299. { "tx_crc_errors", RMON_T_CRC_ALIGN },
  1300. { "tx_undersize", RMON_T_UNDERSIZE },
  1301. { "tx_oversize", RMON_T_OVERSIZE },
  1302. { "tx_fragment", RMON_T_FRAG },
  1303. { "tx_jabber", RMON_T_JAB },
  1304. { "tx_collision", RMON_T_COL },
  1305. { "tx_64byte", RMON_T_P64 },
  1306. { "tx_65to127byte", RMON_T_P65TO127 },
  1307. { "tx_128to255byte", RMON_T_P128TO255 },
  1308. { "tx_256to511byte", RMON_T_P256TO511 },
  1309. { "tx_512to1023byte", RMON_T_P512TO1023 },
  1310. { "tx_1024to2047byte", RMON_T_P1024TO2047 },
  1311. { "tx_GTE2048byte", RMON_T_P_GTE2048 },
  1312. { "tx_octets", RMON_T_OCTETS },
  1313. /* IEEE TX */
  1314. { "IEEE_tx_drop", IEEE_T_DROP },
  1315. { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK },
  1316. { "IEEE_tx_1col", IEEE_T_1COL },
  1317. { "IEEE_tx_mcol", IEEE_T_MCOL },
  1318. { "IEEE_tx_def", IEEE_T_DEF },
  1319. { "IEEE_tx_lcol", IEEE_T_LCOL },
  1320. { "IEEE_tx_excol", IEEE_T_EXCOL },
  1321. { "IEEE_tx_macerr", IEEE_T_MACERR },
  1322. { "IEEE_tx_cserr", IEEE_T_CSERR },
  1323. { "IEEE_tx_sqe", IEEE_T_SQE },
  1324. { "IEEE_tx_fdxfc", IEEE_T_FDXFC },
  1325. { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK },
  1326. /* RMON RX */
  1327. { "rx_packets", RMON_R_PACKETS },
  1328. { "rx_broadcast", RMON_R_BC_PKT },
  1329. { "rx_multicast", RMON_R_MC_PKT },
  1330. { "rx_crc_errors", RMON_R_CRC_ALIGN },
  1331. { "rx_undersize", RMON_R_UNDERSIZE },
  1332. { "rx_oversize", RMON_R_OVERSIZE },
  1333. { "rx_fragment", RMON_R_FRAG },
  1334. { "rx_jabber", RMON_R_JAB },
  1335. { "rx_64byte", RMON_R_P64 },
  1336. { "rx_65to127byte", RMON_R_P65TO127 },
  1337. { "rx_128to255byte", RMON_R_P128TO255 },
  1338. { "rx_256to511byte", RMON_R_P256TO511 },
  1339. { "rx_512to1023byte", RMON_R_P512TO1023 },
  1340. { "rx_1024to2047byte", RMON_R_P1024TO2047 },
  1341. { "rx_GTE2048byte", RMON_R_P_GTE2048 },
  1342. { "rx_octets", RMON_R_OCTETS },
  1343. /* IEEE RX */
  1344. { "IEEE_rx_drop", IEEE_R_DROP },
  1345. { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK },
  1346. { "IEEE_rx_crc", IEEE_R_CRC },
  1347. { "IEEE_rx_align", IEEE_R_ALIGN },
  1348. { "IEEE_rx_macerr", IEEE_R_MACERR },
  1349. { "IEEE_rx_fdxfc", IEEE_R_FDXFC },
  1350. { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK },
  1351. };
  1352. static void fec_enet_get_ethtool_stats(struct net_device *dev,
  1353. struct ethtool_stats *stats, u64 *data)
  1354. {
  1355. struct fec_enet_private *fep = netdev_priv(dev);
  1356. int i;
  1357. for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
  1358. data[i] = readl(fep->hwp + fec_stats[i].offset);
  1359. }
  1360. static void fec_enet_get_strings(struct net_device *netdev,
  1361. u32 stringset, u8 *data)
  1362. {
  1363. int i;
  1364. switch (stringset) {
  1365. case ETH_SS_STATS:
  1366. for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
  1367. memcpy(data + i * ETH_GSTRING_LEN,
  1368. fec_stats[i].name, ETH_GSTRING_LEN);
  1369. break;
  1370. }
  1371. }
  1372. static int fec_enet_get_sset_count(struct net_device *dev, int sset)
  1373. {
  1374. switch (sset) {
  1375. case ETH_SS_STATS:
  1376. return ARRAY_SIZE(fec_stats);
  1377. default:
  1378. return -EOPNOTSUPP;
  1379. }
  1380. }
  1381. #endif /* !defined(CONFIG_M5272) */
  1382. static int fec_enet_nway_reset(struct net_device *dev)
  1383. {
  1384. struct fec_enet_private *fep = netdev_priv(dev);
  1385. struct phy_device *phydev = fep->phy_dev;
  1386. if (!phydev)
  1387. return -ENODEV;
  1388. return genphy_restart_aneg(phydev);
  1389. }
  1390. static const struct ethtool_ops fec_enet_ethtool_ops = {
  1391. #if !defined(CONFIG_M5272)
  1392. .get_pauseparam = fec_enet_get_pauseparam,
  1393. .set_pauseparam = fec_enet_set_pauseparam,
  1394. #endif
  1395. .get_settings = fec_enet_get_settings,
  1396. .set_settings = fec_enet_set_settings,
  1397. .get_drvinfo = fec_enet_get_drvinfo,
  1398. .get_link = ethtool_op_get_link,
  1399. .get_ts_info = fec_enet_get_ts_info,
  1400. .nway_reset = fec_enet_nway_reset,
  1401. #ifndef CONFIG_M5272
  1402. .get_ethtool_stats = fec_enet_get_ethtool_stats,
  1403. .get_strings = fec_enet_get_strings,
  1404. .get_sset_count = fec_enet_get_sset_count,
  1405. #endif
  1406. };
  1407. static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
  1408. {
  1409. struct fec_enet_private *fep = netdev_priv(ndev);
  1410. struct phy_device *phydev = fep->phy_dev;
  1411. if (!netif_running(ndev))
  1412. return -EINVAL;
  1413. if (!phydev)
  1414. return -ENODEV;
  1415. if (cmd == SIOCSHWTSTAMP && fep->bufdesc_ex)
  1416. return fec_ptp_ioctl(ndev, rq, cmd);
  1417. return phy_mii_ioctl(phydev, rq, cmd);
  1418. }
  1419. static void fec_enet_free_buffers(struct net_device *ndev)
  1420. {
  1421. struct fec_enet_private *fep = netdev_priv(ndev);
  1422. unsigned int i;
  1423. struct sk_buff *skb;
  1424. struct bufdesc *bdp;
  1425. bdp = fep->rx_bd_base;
  1426. for (i = 0; i < fep->rx_ring_size; i++) {
  1427. skb = fep->rx_skbuff[i];
  1428. if (bdp->cbd_bufaddr)
  1429. dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
  1430. FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
  1431. if (skb)
  1432. dev_kfree_skb(skb);
  1433. bdp = fec_enet_get_nextdesc(bdp, fep);
  1434. }
  1435. bdp = fep->tx_bd_base;
  1436. for (i = 0; i < fep->tx_ring_size; i++)
  1437. kfree(fep->tx_bounce[i]);
  1438. }
  1439. static int fec_enet_alloc_buffers(struct net_device *ndev)
  1440. {
  1441. struct fec_enet_private *fep = netdev_priv(ndev);
  1442. unsigned int i;
  1443. struct sk_buff *skb;
  1444. struct bufdesc *bdp;
  1445. bdp = fep->rx_bd_base;
  1446. for (i = 0; i < fep->rx_ring_size; i++) {
  1447. skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
  1448. if (!skb) {
  1449. fec_enet_free_buffers(ndev);
  1450. return -ENOMEM;
  1451. }
  1452. fep->rx_skbuff[i] = skb;
  1453. bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, skb->data,
  1454. FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
  1455. bdp->cbd_sc = BD_ENET_RX_EMPTY;
  1456. if (fep->bufdesc_ex) {
  1457. struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
  1458. ebdp->cbd_esc = BD_ENET_RX_INT;
  1459. }
  1460. bdp = fec_enet_get_nextdesc(bdp, fep);
  1461. }
  1462. /* Set the last buffer to wrap. */
  1463. bdp = fec_enet_get_prevdesc(bdp, fep);
  1464. bdp->cbd_sc |= BD_SC_WRAP;
  1465. bdp = fep->tx_bd_base;
  1466. for (i = 0; i < fep->tx_ring_size; i++) {
  1467. fep->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
  1468. bdp->cbd_sc = 0;
  1469. bdp->cbd_bufaddr = 0;
  1470. if (fep->bufdesc_ex) {
  1471. struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
  1472. ebdp->cbd_esc = BD_ENET_TX_INT;
  1473. }
  1474. bdp = fec_enet_get_nextdesc(bdp, fep);
  1475. }
  1476. /* Set the last buffer to wrap. */
  1477. bdp = fec_enet_get_prevdesc(bdp, fep);
  1478. bdp->cbd_sc |= BD_SC_WRAP;
  1479. return 0;
  1480. }
  1481. static int
  1482. fec_enet_open(struct net_device *ndev)
  1483. {
  1484. struct fec_enet_private *fep = netdev_priv(ndev);
  1485. int ret;
  1486. napi_enable(&fep->napi);
  1487. /* I should reset the ring buffers here, but I don't yet know
  1488. * a simple way to do that.
  1489. */
  1490. ret = fec_enet_alloc_buffers(ndev);
  1491. if (ret)
  1492. return ret;
  1493. /* Probe and connect to PHY when open the interface */
  1494. ret = fec_enet_mii_probe(ndev);
  1495. if (ret) {
  1496. fec_enet_free_buffers(ndev);
  1497. return ret;
  1498. }
  1499. phy_start(fep->phy_dev);
  1500. netif_start_queue(ndev);
  1501. fep->opened = 1;
  1502. return 0;
  1503. }
  1504. static int
  1505. fec_enet_close(struct net_device *ndev)
  1506. {
  1507. struct fec_enet_private *fep = netdev_priv(ndev);
  1508. /* Don't know what to do yet. */
  1509. napi_disable(&fep->napi);
  1510. fep->opened = 0;
  1511. netif_stop_queue(ndev);
  1512. fec_stop(ndev);
  1513. if (fep->phy_dev) {
  1514. phy_stop(fep->phy_dev);
  1515. phy_disconnect(fep->phy_dev);
  1516. }
  1517. fec_enet_free_buffers(ndev);
  1518. return 0;
  1519. }
  1520. /* Set or clear the multicast filter for this adaptor.
  1521. * Skeleton taken from sunlance driver.
  1522. * The CPM Ethernet implementation allows Multicast as well as individual
  1523. * MAC address filtering. Some of the drivers check to make sure it is
  1524. * a group multicast address, and discard those that are not. I guess I
  1525. * will do the same for now, but just remove the test if you want
  1526. * individual filtering as well (do the upper net layers want or support
  1527. * this kind of feature?).
  1528. */
  1529. #define HASH_BITS 6 /* #bits in hash */
  1530. #define CRC32_POLY 0xEDB88320
  1531. static void set_multicast_list(struct net_device *ndev)
  1532. {
  1533. struct fec_enet_private *fep = netdev_priv(ndev);
  1534. struct netdev_hw_addr *ha;
  1535. unsigned int i, bit, data, crc, tmp;
  1536. unsigned char hash;
  1537. if (ndev->flags & IFF_PROMISC) {
  1538. tmp = readl(fep->hwp + FEC_R_CNTRL);
  1539. tmp |= 0x8;
  1540. writel(tmp, fep->hwp + FEC_R_CNTRL);
  1541. return;
  1542. }
  1543. tmp = readl(fep->hwp + FEC_R_CNTRL);
  1544. tmp &= ~0x8;
  1545. writel(tmp, fep->hwp + FEC_R_CNTRL);
  1546. if (ndev->flags & IFF_ALLMULTI) {
  1547. /* Catch all multicast addresses, so set the
  1548. * filter to all 1's
  1549. */
  1550. writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
  1551. writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
  1552. return;
  1553. }
  1554. /* Clear filter and add the addresses in hash register
  1555. */
  1556. writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
  1557. writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
  1558. netdev_for_each_mc_addr(ha, ndev) {
  1559. /* calculate crc32 value of mac address */
  1560. crc = 0xffffffff;
  1561. for (i = 0; i < ndev->addr_len; i++) {
  1562. data = ha->addr[i];
  1563. for (bit = 0; bit < 8; bit++, data >>= 1) {
  1564. crc = (crc >> 1) ^
  1565. (((crc ^ data) & 1) ? CRC32_POLY : 0);
  1566. }
  1567. }
  1568. /* only upper 6 bits (HASH_BITS) are used
  1569. * which point to specific bit in he hash registers
  1570. */
  1571. hash = (crc >> (32 - HASH_BITS)) & 0x3f;
  1572. if (hash > 31) {
  1573. tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
  1574. tmp |= 1 << (hash - 32);
  1575. writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
  1576. } else {
  1577. tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW);
  1578. tmp |= 1 << hash;
  1579. writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
  1580. }
  1581. }
  1582. }
  1583. /* Set a MAC change in hardware. */
  1584. static int
  1585. fec_set_mac_address(struct net_device *ndev, void *p)
  1586. {
  1587. struct fec_enet_private *fep = netdev_priv(ndev);
  1588. struct sockaddr *addr = p;
  1589. if (!is_valid_ether_addr(addr->sa_data))
  1590. return -EADDRNOTAVAIL;
  1591. memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
  1592. writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
  1593. (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
  1594. fep->hwp + FEC_ADDR_LOW);
  1595. writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
  1596. fep->hwp + FEC_ADDR_HIGH);
  1597. return 0;
  1598. }
  1599. #ifdef CONFIG_NET_POLL_CONTROLLER
  1600. /**
  1601. * fec_poll_controller - FEC Poll controller function
  1602. * @dev: The FEC network adapter
  1603. *
  1604. * Polled functionality used by netconsole and others in non interrupt mode
  1605. *
  1606. */
  1607. static void fec_poll_controller(struct net_device *dev)
  1608. {
  1609. int i;
  1610. struct fec_enet_private *fep = netdev_priv(dev);
  1611. for (i = 0; i < FEC_IRQ_NUM; i++) {
  1612. if (fep->irq[i] > 0) {
  1613. disable_irq(fep->irq[i]);
  1614. fec_enet_interrupt(fep->irq[i], dev);
  1615. enable_irq(fep->irq[i]);
  1616. }
  1617. }
  1618. }
  1619. #endif
  1620. static int fec_set_features(struct net_device *netdev,
  1621. netdev_features_t features)
  1622. {
  1623. struct fec_enet_private *fep = netdev_priv(netdev);
  1624. netdev_features_t changed = features ^ netdev->features;
  1625. netdev->features = features;
  1626. /* Receive checksum has been changed */
  1627. if (changed & NETIF_F_RXCSUM) {
  1628. if (features & NETIF_F_RXCSUM)
  1629. fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
  1630. else
  1631. fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED;
  1632. if (netif_running(netdev)) {
  1633. fec_stop(netdev);
  1634. fec_restart(netdev, fep->phy_dev->duplex);
  1635. netif_wake_queue(netdev);
  1636. } else {
  1637. fec_restart(netdev, fep->phy_dev->duplex);
  1638. }
  1639. }
  1640. return 0;
  1641. }
  1642. static const struct net_device_ops fec_netdev_ops = {
  1643. .ndo_open = fec_enet_open,
  1644. .ndo_stop = fec_enet_close,
  1645. .ndo_start_xmit = fec_enet_start_xmit,
  1646. .ndo_set_rx_mode = set_multicast_list,
  1647. .ndo_change_mtu = eth_change_mtu,
  1648. .ndo_validate_addr = eth_validate_addr,
  1649. .ndo_tx_timeout = fec_timeout,
  1650. .ndo_set_mac_address = fec_set_mac_address,
  1651. .ndo_do_ioctl = fec_enet_ioctl,
  1652. #ifdef CONFIG_NET_POLL_CONTROLLER
  1653. .ndo_poll_controller = fec_poll_controller,
  1654. #endif
  1655. .ndo_set_features = fec_set_features,
  1656. };
  1657. /*
  1658. * XXX: We need to clean up on failure exits here.
  1659. *
  1660. */
  1661. static int fec_enet_init(struct net_device *ndev)
  1662. {
  1663. struct fec_enet_private *fep = netdev_priv(ndev);
  1664. const struct platform_device_id *id_entry =
  1665. platform_get_device_id(fep->pdev);
  1666. struct bufdesc *cbd_base;
  1667. /* Allocate memory for buffer descriptors. */
  1668. cbd_base = dma_alloc_coherent(NULL, PAGE_SIZE, &fep->bd_dma,
  1669. GFP_KERNEL);
  1670. if (!cbd_base)
  1671. return -ENOMEM;
  1672. memset(cbd_base, 0, PAGE_SIZE);
  1673. fep->netdev = ndev;
  1674. /* Get the Ethernet address */
  1675. fec_get_mac(ndev);
  1676. /* init the tx & rx ring size */
  1677. fep->tx_ring_size = TX_RING_SIZE;
  1678. fep->rx_ring_size = RX_RING_SIZE;
  1679. /* Set receive and transmit descriptor base. */
  1680. fep->rx_bd_base = cbd_base;
  1681. if (fep->bufdesc_ex)
  1682. fep->tx_bd_base = (struct bufdesc *)
  1683. (((struct bufdesc_ex *)cbd_base) + fep->rx_ring_size);
  1684. else
  1685. fep->tx_bd_base = cbd_base + fep->rx_ring_size;
  1686. /* The FEC Ethernet specific entries in the device structure */
  1687. ndev->watchdog_timeo = TX_TIMEOUT;
  1688. ndev->netdev_ops = &fec_netdev_ops;
  1689. ndev->ethtool_ops = &fec_enet_ethtool_ops;
  1690. writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK);
  1691. netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT);
  1692. if (id_entry->driver_data & FEC_QUIRK_HAS_VLAN) {
  1693. /* enable hw VLAN support */
  1694. ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
  1695. ndev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
  1696. }
  1697. if (id_entry->driver_data & FEC_QUIRK_HAS_CSUM) {
  1698. /* enable hw accelerator */
  1699. ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
  1700. | NETIF_F_RXCSUM);
  1701. ndev->hw_features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
  1702. | NETIF_F_RXCSUM);
  1703. fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
  1704. }
  1705. fec_restart(ndev, 0);
  1706. return 0;
  1707. }
  1708. #ifdef CONFIG_OF
  1709. static void fec_reset_phy(struct platform_device *pdev)
  1710. {
  1711. int err, phy_reset;
  1712. int msec = 1;
  1713. struct device_node *np = pdev->dev.of_node;
  1714. if (!np)
  1715. return;
  1716. of_property_read_u32(np, "phy-reset-duration", &msec);
  1717. /* A sane reset duration should not be longer than 1s */
  1718. if (msec > 1000)
  1719. msec = 1;
  1720. phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
  1721. if (!gpio_is_valid(phy_reset))
  1722. return;
  1723. err = devm_gpio_request_one(&pdev->dev, phy_reset,
  1724. GPIOF_OUT_INIT_LOW, "phy-reset");
  1725. if (err) {
  1726. dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err);
  1727. return;
  1728. }
  1729. msleep(msec);
  1730. gpio_set_value(phy_reset, 1);
  1731. }
  1732. #else /* CONFIG_OF */
  1733. static void fec_reset_phy(struct platform_device *pdev)
  1734. {
  1735. /*
  1736. * In case of platform probe, the reset has been done
  1737. * by machine code.
  1738. */
  1739. }
  1740. #endif /* CONFIG_OF */
  1741. static int
  1742. fec_probe(struct platform_device *pdev)
  1743. {
  1744. struct fec_enet_private *fep;
  1745. struct fec_platform_data *pdata;
  1746. struct net_device *ndev;
  1747. int i, irq, ret = 0;
  1748. struct resource *r;
  1749. const struct of_device_id *of_id;
  1750. static int dev_id;
  1751. of_id = of_match_device(fec_dt_ids, &pdev->dev);
  1752. if (of_id)
  1753. pdev->id_entry = of_id->data;
  1754. /* Init network device */
  1755. ndev = alloc_etherdev(sizeof(struct fec_enet_private));
  1756. if (!ndev)
  1757. return -ENOMEM;
  1758. SET_NETDEV_DEV(ndev, &pdev->dev);
  1759. /* setup board info structure */
  1760. fep = netdev_priv(ndev);
  1761. #if !defined(CONFIG_M5272)
  1762. /* default enable pause frame auto negotiation */
  1763. if (pdev->id_entry &&
  1764. (pdev->id_entry->driver_data & FEC_QUIRK_HAS_GBIT))
  1765. fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG;
  1766. #endif
  1767. r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1768. fep->hwp = devm_ioremap_resource(&pdev->dev, r);
  1769. if (IS_ERR(fep->hwp)) {
  1770. ret = PTR_ERR(fep->hwp);
  1771. goto failed_ioremap;
  1772. }
  1773. fep->pdev = pdev;
  1774. fep->dev_id = dev_id++;
  1775. fep->bufdesc_ex = 0;
  1776. platform_set_drvdata(pdev, ndev);
  1777. ret = of_get_phy_mode(pdev->dev.of_node);
  1778. if (ret < 0) {
  1779. pdata = dev_get_platdata(&pdev->dev);
  1780. if (pdata)
  1781. fep->phy_interface = pdata->phy;
  1782. else
  1783. fep->phy_interface = PHY_INTERFACE_MODE_MII;
  1784. } else {
  1785. fep->phy_interface = ret;
  1786. }
  1787. fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
  1788. if (IS_ERR(fep->clk_ipg)) {
  1789. ret = PTR_ERR(fep->clk_ipg);
  1790. goto failed_clk;
  1791. }
  1792. fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
  1793. if (IS_ERR(fep->clk_ahb)) {
  1794. ret = PTR_ERR(fep->clk_ahb);
  1795. goto failed_clk;
  1796. }
  1797. /* enet_out is optional, depends on board */
  1798. fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out");
  1799. if (IS_ERR(fep->clk_enet_out))
  1800. fep->clk_enet_out = NULL;
  1801. fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp");
  1802. fep->bufdesc_ex =
  1803. pdev->id_entry->driver_data & FEC_QUIRK_HAS_BUFDESC_EX;
  1804. if (IS_ERR(fep->clk_ptp)) {
  1805. fep->clk_ptp = NULL;
  1806. fep->bufdesc_ex = 0;
  1807. }
  1808. ret = clk_prepare_enable(fep->clk_ahb);
  1809. if (ret)
  1810. goto failed_clk;
  1811. ret = clk_prepare_enable(fep->clk_ipg);
  1812. if (ret)
  1813. goto failed_clk_ipg;
  1814. if (fep->clk_enet_out) {
  1815. ret = clk_prepare_enable(fep->clk_enet_out);
  1816. if (ret)
  1817. goto failed_clk_enet_out;
  1818. }
  1819. if (fep->clk_ptp) {
  1820. ret = clk_prepare_enable(fep->clk_ptp);
  1821. if (ret)
  1822. goto failed_clk_ptp;
  1823. }
  1824. fep->reg_phy = devm_regulator_get(&pdev->dev, "phy");
  1825. if (!IS_ERR(fep->reg_phy)) {
  1826. ret = regulator_enable(fep->reg_phy);
  1827. if (ret) {
  1828. dev_err(&pdev->dev,
  1829. "Failed to enable phy regulator: %d\n", ret);
  1830. goto failed_regulator;
  1831. }
  1832. } else {
  1833. fep->reg_phy = NULL;
  1834. }
  1835. fec_reset_phy(pdev);
  1836. if (fep->bufdesc_ex)
  1837. fec_ptp_init(pdev);
  1838. ret = fec_enet_init(ndev);
  1839. if (ret)
  1840. goto failed_init;
  1841. for (i = 0; i < FEC_IRQ_NUM; i++) {
  1842. irq = platform_get_irq(pdev, i);
  1843. if (irq < 0) {
  1844. if (i)
  1845. break;
  1846. ret = irq;
  1847. goto failed_irq;
  1848. }
  1849. ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt,
  1850. 0, pdev->name, ndev);
  1851. if (ret)
  1852. goto failed_irq;
  1853. }
  1854. ret = fec_enet_mii_init(pdev);
  1855. if (ret)
  1856. goto failed_mii_init;
  1857. /* Carrier starts down, phylib will bring it up */
  1858. netif_carrier_off(ndev);
  1859. ret = register_netdev(ndev);
  1860. if (ret)
  1861. goto failed_register;
  1862. if (fep->bufdesc_ex && fep->ptp_clock)
  1863. netdev_info(ndev, "registered PHC device %d\n", fep->dev_id);
  1864. INIT_DELAYED_WORK(&(fep->delay_work.delay_work), fec_enet_work);
  1865. return 0;
  1866. failed_register:
  1867. fec_enet_mii_remove(fep);
  1868. failed_mii_init:
  1869. failed_irq:
  1870. failed_init:
  1871. if (fep->reg_phy)
  1872. regulator_disable(fep->reg_phy);
  1873. failed_regulator:
  1874. if (fep->clk_ptp)
  1875. clk_disable_unprepare(fep->clk_ptp);
  1876. failed_clk_ptp:
  1877. if (fep->clk_enet_out)
  1878. clk_disable_unprepare(fep->clk_enet_out);
  1879. failed_clk_enet_out:
  1880. clk_disable_unprepare(fep->clk_ipg);
  1881. failed_clk_ipg:
  1882. clk_disable_unprepare(fep->clk_ahb);
  1883. failed_clk:
  1884. failed_ioremap:
  1885. free_netdev(ndev);
  1886. return ret;
  1887. }
  1888. static int
  1889. fec_drv_remove(struct platform_device *pdev)
  1890. {
  1891. struct net_device *ndev = platform_get_drvdata(pdev);
  1892. struct fec_enet_private *fep = netdev_priv(ndev);
  1893. cancel_delayed_work_sync(&(fep->delay_work.delay_work));
  1894. unregister_netdev(ndev);
  1895. fec_enet_mii_remove(fep);
  1896. del_timer_sync(&fep->time_keep);
  1897. if (fep->reg_phy)
  1898. regulator_disable(fep->reg_phy);
  1899. if (fep->clk_ptp)
  1900. clk_disable_unprepare(fep->clk_ptp);
  1901. if (fep->ptp_clock)
  1902. ptp_clock_unregister(fep->ptp_clock);
  1903. if (fep->clk_enet_out)
  1904. clk_disable_unprepare(fep->clk_enet_out);
  1905. clk_disable_unprepare(fep->clk_ipg);
  1906. clk_disable_unprepare(fep->clk_ahb);
  1907. free_netdev(ndev);
  1908. return 0;
  1909. }
  1910. #ifdef CONFIG_PM_SLEEP
  1911. static int
  1912. fec_suspend(struct device *dev)
  1913. {
  1914. struct net_device *ndev = dev_get_drvdata(dev);
  1915. struct fec_enet_private *fep = netdev_priv(ndev);
  1916. if (netif_running(ndev)) {
  1917. fec_stop(ndev);
  1918. netif_device_detach(ndev);
  1919. }
  1920. if (fep->clk_ptp)
  1921. clk_disable_unprepare(fep->clk_ptp);
  1922. if (fep->clk_enet_out)
  1923. clk_disable_unprepare(fep->clk_enet_out);
  1924. clk_disable_unprepare(fep->clk_ipg);
  1925. clk_disable_unprepare(fep->clk_ahb);
  1926. if (fep->reg_phy)
  1927. regulator_disable(fep->reg_phy);
  1928. return 0;
  1929. }
  1930. static int
  1931. fec_resume(struct device *dev)
  1932. {
  1933. struct net_device *ndev = dev_get_drvdata(dev);
  1934. struct fec_enet_private *fep = netdev_priv(ndev);
  1935. int ret;
  1936. if (fep->reg_phy) {
  1937. ret = regulator_enable(fep->reg_phy);
  1938. if (ret)
  1939. return ret;
  1940. }
  1941. ret = clk_prepare_enable(fep->clk_ahb);
  1942. if (ret)
  1943. goto failed_clk_ahb;
  1944. ret = clk_prepare_enable(fep->clk_ipg);
  1945. if (ret)
  1946. goto failed_clk_ipg;
  1947. if (fep->clk_enet_out) {
  1948. ret = clk_prepare_enable(fep->clk_enet_out);
  1949. if (ret)
  1950. goto failed_clk_enet_out;
  1951. }
  1952. if (fep->clk_ptp) {
  1953. ret = clk_prepare_enable(fep->clk_ptp);
  1954. if (ret)
  1955. goto failed_clk_ptp;
  1956. }
  1957. if (netif_running(ndev)) {
  1958. fec_restart(ndev, fep->full_duplex);
  1959. netif_device_attach(ndev);
  1960. }
  1961. return 0;
  1962. failed_clk_ptp:
  1963. if (fep->clk_enet_out)
  1964. clk_disable_unprepare(fep->clk_enet_out);
  1965. failed_clk_enet_out:
  1966. clk_disable_unprepare(fep->clk_ipg);
  1967. failed_clk_ipg:
  1968. clk_disable_unprepare(fep->clk_ahb);
  1969. failed_clk_ahb:
  1970. if (fep->reg_phy)
  1971. regulator_disable(fep->reg_phy);
  1972. return ret;
  1973. }
  1974. #endif /* CONFIG_PM_SLEEP */
  1975. static SIMPLE_DEV_PM_OPS(fec_pm_ops, fec_suspend, fec_resume);
  1976. static struct platform_driver fec_driver = {
  1977. .driver = {
  1978. .name = DRIVER_NAME,
  1979. .owner = THIS_MODULE,
  1980. .pm = &fec_pm_ops,
  1981. .of_match_table = fec_dt_ids,
  1982. },
  1983. .id_table = fec_devtype,
  1984. .probe = fec_probe,
  1985. .remove = fec_drv_remove,
  1986. };
  1987. module_platform_driver(fec_driver);
  1988. MODULE_ALIAS("platform:"DRIVER_NAME);
  1989. MODULE_LICENSE("GPL");