i915_gem.c 94 KB

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  1. /*
  2. * Copyright © 2008 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21. * IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Eric Anholt <eric@anholt.net>
  25. *
  26. */
  27. #include "drmP.h"
  28. #include "drm.h"
  29. #include "i915_drm.h"
  30. #include "i915_drv.h"
  31. #include <linux/swap.h>
  32. #include <linux/pci.h>
  33. #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
  34. static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
  35. static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
  36. static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
  37. static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
  38. int write);
  39. static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
  40. uint64_t offset,
  41. uint64_t size);
  42. static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj);
  43. static int i915_gem_object_get_page_list(struct drm_gem_object *obj);
  44. static void i915_gem_object_free_page_list(struct drm_gem_object *obj);
  45. static int i915_gem_object_wait_rendering(struct drm_gem_object *obj);
  46. static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
  47. unsigned alignment);
  48. static int i915_gem_object_get_fence_reg(struct drm_gem_object *obj, bool write);
  49. static void i915_gem_clear_fence_reg(struct drm_gem_object *obj);
  50. static int i915_gem_evict_something(struct drm_device *dev);
  51. static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
  52. struct drm_i915_gem_pwrite *args,
  53. struct drm_file *file_priv);
  54. int i915_gem_do_init(struct drm_device *dev, unsigned long start,
  55. unsigned long end)
  56. {
  57. drm_i915_private_t *dev_priv = dev->dev_private;
  58. if (start >= end ||
  59. (start & (PAGE_SIZE - 1)) != 0 ||
  60. (end & (PAGE_SIZE - 1)) != 0) {
  61. return -EINVAL;
  62. }
  63. drm_mm_init(&dev_priv->mm.gtt_space, start,
  64. end - start);
  65. dev->gtt_total = (uint32_t) (end - start);
  66. return 0;
  67. }
  68. int
  69. i915_gem_init_ioctl(struct drm_device *dev, void *data,
  70. struct drm_file *file_priv)
  71. {
  72. struct drm_i915_gem_init *args = data;
  73. int ret;
  74. mutex_lock(&dev->struct_mutex);
  75. ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end);
  76. mutex_unlock(&dev->struct_mutex);
  77. return ret;
  78. }
  79. int
  80. i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
  81. struct drm_file *file_priv)
  82. {
  83. struct drm_i915_gem_get_aperture *args = data;
  84. if (!(dev->driver->driver_features & DRIVER_GEM))
  85. return -ENODEV;
  86. args->aper_size = dev->gtt_total;
  87. args->aper_available_size = (args->aper_size -
  88. atomic_read(&dev->pin_memory));
  89. return 0;
  90. }
  91. /**
  92. * Creates a new mm object and returns a handle to it.
  93. */
  94. int
  95. i915_gem_create_ioctl(struct drm_device *dev, void *data,
  96. struct drm_file *file_priv)
  97. {
  98. struct drm_i915_gem_create *args = data;
  99. struct drm_gem_object *obj;
  100. int handle, ret;
  101. args->size = roundup(args->size, PAGE_SIZE);
  102. /* Allocate the new object */
  103. obj = drm_gem_object_alloc(dev, args->size);
  104. if (obj == NULL)
  105. return -ENOMEM;
  106. ret = drm_gem_handle_create(file_priv, obj, &handle);
  107. mutex_lock(&dev->struct_mutex);
  108. drm_gem_object_handle_unreference(obj);
  109. mutex_unlock(&dev->struct_mutex);
  110. if (ret)
  111. return ret;
  112. args->handle = handle;
  113. return 0;
  114. }
  115. /**
  116. * Reads data from the object referenced by handle.
  117. *
  118. * On error, the contents of *data are undefined.
  119. */
  120. int
  121. i915_gem_pread_ioctl(struct drm_device *dev, void *data,
  122. struct drm_file *file_priv)
  123. {
  124. struct drm_i915_gem_pread *args = data;
  125. struct drm_gem_object *obj;
  126. struct drm_i915_gem_object *obj_priv;
  127. ssize_t read;
  128. loff_t offset;
  129. int ret;
  130. obj = drm_gem_object_lookup(dev, file_priv, args->handle);
  131. if (obj == NULL)
  132. return -EBADF;
  133. obj_priv = obj->driver_private;
  134. /* Bounds check source.
  135. *
  136. * XXX: This could use review for overflow issues...
  137. */
  138. if (args->offset > obj->size || args->size > obj->size ||
  139. args->offset + args->size > obj->size) {
  140. drm_gem_object_unreference(obj);
  141. return -EINVAL;
  142. }
  143. mutex_lock(&dev->struct_mutex);
  144. ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
  145. args->size);
  146. if (ret != 0) {
  147. drm_gem_object_unreference(obj);
  148. mutex_unlock(&dev->struct_mutex);
  149. return ret;
  150. }
  151. offset = args->offset;
  152. read = vfs_read(obj->filp, (char __user *)(uintptr_t)args->data_ptr,
  153. args->size, &offset);
  154. if (read != args->size) {
  155. drm_gem_object_unreference(obj);
  156. mutex_unlock(&dev->struct_mutex);
  157. if (read < 0)
  158. return read;
  159. else
  160. return -EINVAL;
  161. }
  162. drm_gem_object_unreference(obj);
  163. mutex_unlock(&dev->struct_mutex);
  164. return 0;
  165. }
  166. /* This is the fast write path which cannot handle
  167. * page faults in the source data
  168. */
  169. static inline int
  170. fast_user_write(struct io_mapping *mapping,
  171. loff_t page_base, int page_offset,
  172. char __user *user_data,
  173. int length)
  174. {
  175. char *vaddr_atomic;
  176. unsigned long unwritten;
  177. vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
  178. unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
  179. user_data, length);
  180. io_mapping_unmap_atomic(vaddr_atomic);
  181. if (unwritten)
  182. return -EFAULT;
  183. return 0;
  184. }
  185. /* Here's the write path which can sleep for
  186. * page faults
  187. */
  188. static inline int
  189. slow_user_write(struct io_mapping *mapping,
  190. loff_t page_base, int page_offset,
  191. char __user *user_data,
  192. int length)
  193. {
  194. char __iomem *vaddr;
  195. unsigned long unwritten;
  196. vaddr = io_mapping_map_wc(mapping, page_base);
  197. if (vaddr == NULL)
  198. return -EFAULT;
  199. unwritten = __copy_from_user(vaddr + page_offset,
  200. user_data, length);
  201. io_mapping_unmap(vaddr);
  202. if (unwritten)
  203. return -EFAULT;
  204. return 0;
  205. }
  206. static int
  207. i915_gem_gtt_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
  208. struct drm_i915_gem_pwrite *args,
  209. struct drm_file *file_priv)
  210. {
  211. struct drm_i915_gem_object *obj_priv = obj->driver_private;
  212. drm_i915_private_t *dev_priv = dev->dev_private;
  213. ssize_t remain;
  214. loff_t offset, page_base;
  215. char __user *user_data;
  216. int page_offset, page_length;
  217. int ret;
  218. user_data = (char __user *) (uintptr_t) args->data_ptr;
  219. remain = args->size;
  220. if (!access_ok(VERIFY_READ, user_data, remain))
  221. return -EFAULT;
  222. mutex_lock(&dev->struct_mutex);
  223. ret = i915_gem_object_pin(obj, 0);
  224. if (ret) {
  225. mutex_unlock(&dev->struct_mutex);
  226. return ret;
  227. }
  228. ret = i915_gem_object_set_to_gtt_domain(obj, 1);
  229. if (ret)
  230. goto fail;
  231. obj_priv = obj->driver_private;
  232. offset = obj_priv->gtt_offset + args->offset;
  233. obj_priv->dirty = 1;
  234. while (remain > 0) {
  235. /* Operation in this page
  236. *
  237. * page_base = page offset within aperture
  238. * page_offset = offset within page
  239. * page_length = bytes to copy for this page
  240. */
  241. page_base = (offset & ~(PAGE_SIZE-1));
  242. page_offset = offset & (PAGE_SIZE-1);
  243. page_length = remain;
  244. if ((page_offset + remain) > PAGE_SIZE)
  245. page_length = PAGE_SIZE - page_offset;
  246. ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base,
  247. page_offset, user_data, page_length);
  248. /* If we get a fault while copying data, then (presumably) our
  249. * source page isn't available. In this case, use the
  250. * non-atomic function
  251. */
  252. if (ret) {
  253. ret = slow_user_write (dev_priv->mm.gtt_mapping,
  254. page_base, page_offset,
  255. user_data, page_length);
  256. if (ret)
  257. goto fail;
  258. }
  259. remain -= page_length;
  260. user_data += page_length;
  261. offset += page_length;
  262. }
  263. fail:
  264. i915_gem_object_unpin(obj);
  265. mutex_unlock(&dev->struct_mutex);
  266. return ret;
  267. }
  268. static int
  269. i915_gem_shmem_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
  270. struct drm_i915_gem_pwrite *args,
  271. struct drm_file *file_priv)
  272. {
  273. int ret;
  274. loff_t offset;
  275. ssize_t written;
  276. mutex_lock(&dev->struct_mutex);
  277. ret = i915_gem_object_set_to_cpu_domain(obj, 1);
  278. if (ret) {
  279. mutex_unlock(&dev->struct_mutex);
  280. return ret;
  281. }
  282. offset = args->offset;
  283. written = vfs_write(obj->filp,
  284. (char __user *)(uintptr_t) args->data_ptr,
  285. args->size, &offset);
  286. if (written != args->size) {
  287. mutex_unlock(&dev->struct_mutex);
  288. if (written < 0)
  289. return written;
  290. else
  291. return -EINVAL;
  292. }
  293. mutex_unlock(&dev->struct_mutex);
  294. return 0;
  295. }
  296. /**
  297. * Writes data to the object referenced by handle.
  298. *
  299. * On error, the contents of the buffer that were to be modified are undefined.
  300. */
  301. int
  302. i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
  303. struct drm_file *file_priv)
  304. {
  305. struct drm_i915_gem_pwrite *args = data;
  306. struct drm_gem_object *obj;
  307. struct drm_i915_gem_object *obj_priv;
  308. int ret = 0;
  309. obj = drm_gem_object_lookup(dev, file_priv, args->handle);
  310. if (obj == NULL)
  311. return -EBADF;
  312. obj_priv = obj->driver_private;
  313. /* Bounds check destination.
  314. *
  315. * XXX: This could use review for overflow issues...
  316. */
  317. if (args->offset > obj->size || args->size > obj->size ||
  318. args->offset + args->size > obj->size) {
  319. drm_gem_object_unreference(obj);
  320. return -EINVAL;
  321. }
  322. /* We can only do the GTT pwrite on untiled buffers, as otherwise
  323. * it would end up going through the fenced access, and we'll get
  324. * different detiling behavior between reading and writing.
  325. * pread/pwrite currently are reading and writing from the CPU
  326. * perspective, requiring manual detiling by the client.
  327. */
  328. if (obj_priv->phys_obj)
  329. ret = i915_gem_phys_pwrite(dev, obj, args, file_priv);
  330. else if (obj_priv->tiling_mode == I915_TILING_NONE &&
  331. dev->gtt_total != 0)
  332. ret = i915_gem_gtt_pwrite(dev, obj, args, file_priv);
  333. else
  334. ret = i915_gem_shmem_pwrite(dev, obj, args, file_priv);
  335. #if WATCH_PWRITE
  336. if (ret)
  337. DRM_INFO("pwrite failed %d\n", ret);
  338. #endif
  339. drm_gem_object_unreference(obj);
  340. return ret;
  341. }
  342. /**
  343. * Called when user space prepares to use an object with the CPU, either
  344. * through the mmap ioctl's mapping or a GTT mapping.
  345. */
  346. int
  347. i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
  348. struct drm_file *file_priv)
  349. {
  350. struct drm_i915_gem_set_domain *args = data;
  351. struct drm_gem_object *obj;
  352. uint32_t read_domains = args->read_domains;
  353. uint32_t write_domain = args->write_domain;
  354. int ret;
  355. if (!(dev->driver->driver_features & DRIVER_GEM))
  356. return -ENODEV;
  357. /* Only handle setting domains to types used by the CPU. */
  358. if (write_domain & ~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
  359. return -EINVAL;
  360. if (read_domains & ~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
  361. return -EINVAL;
  362. /* Having something in the write domain implies it's in the read
  363. * domain, and only that read domain. Enforce that in the request.
  364. */
  365. if (write_domain != 0 && read_domains != write_domain)
  366. return -EINVAL;
  367. obj = drm_gem_object_lookup(dev, file_priv, args->handle);
  368. if (obj == NULL)
  369. return -EBADF;
  370. mutex_lock(&dev->struct_mutex);
  371. #if WATCH_BUF
  372. DRM_INFO("set_domain_ioctl %p(%d), %08x %08x\n",
  373. obj, obj->size, read_domains, write_domain);
  374. #endif
  375. if (read_domains & I915_GEM_DOMAIN_GTT) {
  376. ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
  377. /* Silently promote "you're not bound, there was nothing to do"
  378. * to success, since the client was just asking us to
  379. * make sure everything was done.
  380. */
  381. if (ret == -EINVAL)
  382. ret = 0;
  383. } else {
  384. ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
  385. }
  386. drm_gem_object_unreference(obj);
  387. mutex_unlock(&dev->struct_mutex);
  388. return ret;
  389. }
  390. /**
  391. * Called when user space has done writes to this buffer
  392. */
  393. int
  394. i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
  395. struct drm_file *file_priv)
  396. {
  397. struct drm_i915_gem_sw_finish *args = data;
  398. struct drm_gem_object *obj;
  399. struct drm_i915_gem_object *obj_priv;
  400. int ret = 0;
  401. if (!(dev->driver->driver_features & DRIVER_GEM))
  402. return -ENODEV;
  403. mutex_lock(&dev->struct_mutex);
  404. obj = drm_gem_object_lookup(dev, file_priv, args->handle);
  405. if (obj == NULL) {
  406. mutex_unlock(&dev->struct_mutex);
  407. return -EBADF;
  408. }
  409. #if WATCH_BUF
  410. DRM_INFO("%s: sw_finish %d (%p %d)\n",
  411. __func__, args->handle, obj, obj->size);
  412. #endif
  413. obj_priv = obj->driver_private;
  414. /* Pinned buffers may be scanout, so flush the cache */
  415. if (obj_priv->pin_count)
  416. i915_gem_object_flush_cpu_write_domain(obj);
  417. drm_gem_object_unreference(obj);
  418. mutex_unlock(&dev->struct_mutex);
  419. return ret;
  420. }
  421. /**
  422. * Maps the contents of an object, returning the address it is mapped
  423. * into.
  424. *
  425. * While the mapping holds a reference on the contents of the object, it doesn't
  426. * imply a ref on the object itself.
  427. */
  428. int
  429. i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
  430. struct drm_file *file_priv)
  431. {
  432. struct drm_i915_gem_mmap *args = data;
  433. struct drm_gem_object *obj;
  434. loff_t offset;
  435. unsigned long addr;
  436. if (!(dev->driver->driver_features & DRIVER_GEM))
  437. return -ENODEV;
  438. obj = drm_gem_object_lookup(dev, file_priv, args->handle);
  439. if (obj == NULL)
  440. return -EBADF;
  441. offset = args->offset;
  442. down_write(&current->mm->mmap_sem);
  443. addr = do_mmap(obj->filp, 0, args->size,
  444. PROT_READ | PROT_WRITE, MAP_SHARED,
  445. args->offset);
  446. up_write(&current->mm->mmap_sem);
  447. mutex_lock(&dev->struct_mutex);
  448. drm_gem_object_unreference(obj);
  449. mutex_unlock(&dev->struct_mutex);
  450. if (IS_ERR((void *)addr))
  451. return addr;
  452. args->addr_ptr = (uint64_t) addr;
  453. return 0;
  454. }
  455. /**
  456. * i915_gem_fault - fault a page into the GTT
  457. * vma: VMA in question
  458. * vmf: fault info
  459. *
  460. * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
  461. * from userspace. The fault handler takes care of binding the object to
  462. * the GTT (if needed), allocating and programming a fence register (again,
  463. * only if needed based on whether the old reg is still valid or the object
  464. * is tiled) and inserting a new PTE into the faulting process.
  465. *
  466. * Note that the faulting process may involve evicting existing objects
  467. * from the GTT and/or fence registers to make room. So performance may
  468. * suffer if the GTT working set is large or there are few fence registers
  469. * left.
  470. */
  471. int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
  472. {
  473. struct drm_gem_object *obj = vma->vm_private_data;
  474. struct drm_device *dev = obj->dev;
  475. struct drm_i915_private *dev_priv = dev->dev_private;
  476. struct drm_i915_gem_object *obj_priv = obj->driver_private;
  477. pgoff_t page_offset;
  478. unsigned long pfn;
  479. int ret = 0;
  480. bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
  481. /* We don't use vmf->pgoff since that has the fake offset */
  482. page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
  483. PAGE_SHIFT;
  484. /* Now bind it into the GTT if needed */
  485. mutex_lock(&dev->struct_mutex);
  486. if (!obj_priv->gtt_space) {
  487. ret = i915_gem_object_bind_to_gtt(obj, obj_priv->gtt_alignment);
  488. if (ret) {
  489. mutex_unlock(&dev->struct_mutex);
  490. return VM_FAULT_SIGBUS;
  491. }
  492. list_add(&obj_priv->list, &dev_priv->mm.inactive_list);
  493. }
  494. /* Need a new fence register? */
  495. if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
  496. obj_priv->tiling_mode != I915_TILING_NONE) {
  497. ret = i915_gem_object_get_fence_reg(obj, write);
  498. if (ret) {
  499. mutex_unlock(&dev->struct_mutex);
  500. return VM_FAULT_SIGBUS;
  501. }
  502. }
  503. pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) +
  504. page_offset;
  505. /* Finally, remap it using the new GTT offset */
  506. ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
  507. mutex_unlock(&dev->struct_mutex);
  508. switch (ret) {
  509. case -ENOMEM:
  510. case -EAGAIN:
  511. return VM_FAULT_OOM;
  512. case -EFAULT:
  513. return VM_FAULT_SIGBUS;
  514. default:
  515. return VM_FAULT_NOPAGE;
  516. }
  517. }
  518. /**
  519. * i915_gem_create_mmap_offset - create a fake mmap offset for an object
  520. * @obj: obj in question
  521. *
  522. * GEM memory mapping works by handing back to userspace a fake mmap offset
  523. * it can use in a subsequent mmap(2) call. The DRM core code then looks
  524. * up the object based on the offset and sets up the various memory mapping
  525. * structures.
  526. *
  527. * This routine allocates and attaches a fake offset for @obj.
  528. */
  529. static int
  530. i915_gem_create_mmap_offset(struct drm_gem_object *obj)
  531. {
  532. struct drm_device *dev = obj->dev;
  533. struct drm_gem_mm *mm = dev->mm_private;
  534. struct drm_i915_gem_object *obj_priv = obj->driver_private;
  535. struct drm_map_list *list;
  536. struct drm_map *map;
  537. int ret = 0;
  538. /* Set the object up for mmap'ing */
  539. list = &obj->map_list;
  540. list->map = drm_calloc(1, sizeof(struct drm_map_list),
  541. DRM_MEM_DRIVER);
  542. if (!list->map)
  543. return -ENOMEM;
  544. map = list->map;
  545. map->type = _DRM_GEM;
  546. map->size = obj->size;
  547. map->handle = obj;
  548. /* Get a DRM GEM mmap offset allocated... */
  549. list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
  550. obj->size / PAGE_SIZE, 0, 0);
  551. if (!list->file_offset_node) {
  552. DRM_ERROR("failed to allocate offset for bo %d\n", obj->name);
  553. ret = -ENOMEM;
  554. goto out_free_list;
  555. }
  556. list->file_offset_node = drm_mm_get_block(list->file_offset_node,
  557. obj->size / PAGE_SIZE, 0);
  558. if (!list->file_offset_node) {
  559. ret = -ENOMEM;
  560. goto out_free_list;
  561. }
  562. list->hash.key = list->file_offset_node->start;
  563. if (drm_ht_insert_item(&mm->offset_hash, &list->hash)) {
  564. DRM_ERROR("failed to add to map hash\n");
  565. goto out_free_mm;
  566. }
  567. /* By now we should be all set, any drm_mmap request on the offset
  568. * below will get to our mmap & fault handler */
  569. obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT;
  570. return 0;
  571. out_free_mm:
  572. drm_mm_put_block(list->file_offset_node);
  573. out_free_list:
  574. drm_free(list->map, sizeof(struct drm_map_list), DRM_MEM_DRIVER);
  575. return ret;
  576. }
  577. static void
  578. i915_gem_free_mmap_offset(struct drm_gem_object *obj)
  579. {
  580. struct drm_device *dev = obj->dev;
  581. struct drm_i915_gem_object *obj_priv = obj->driver_private;
  582. struct drm_gem_mm *mm = dev->mm_private;
  583. struct drm_map_list *list;
  584. list = &obj->map_list;
  585. drm_ht_remove_item(&mm->offset_hash, &list->hash);
  586. if (list->file_offset_node) {
  587. drm_mm_put_block(list->file_offset_node);
  588. list->file_offset_node = NULL;
  589. }
  590. if (list->map) {
  591. drm_free(list->map, sizeof(struct drm_map), DRM_MEM_DRIVER);
  592. list->map = NULL;
  593. }
  594. obj_priv->mmap_offset = 0;
  595. }
  596. /**
  597. * i915_gem_get_gtt_alignment - return required GTT alignment for an object
  598. * @obj: object to check
  599. *
  600. * Return the required GTT alignment for an object, taking into account
  601. * potential fence register mapping if needed.
  602. */
  603. static uint32_t
  604. i915_gem_get_gtt_alignment(struct drm_gem_object *obj)
  605. {
  606. struct drm_device *dev = obj->dev;
  607. struct drm_i915_gem_object *obj_priv = obj->driver_private;
  608. int start, i;
  609. /*
  610. * Minimum alignment is 4k (GTT page size), but might be greater
  611. * if a fence register is needed for the object.
  612. */
  613. if (IS_I965G(dev) || obj_priv->tiling_mode == I915_TILING_NONE)
  614. return 4096;
  615. /*
  616. * Previous chips need to be aligned to the size of the smallest
  617. * fence register that can contain the object.
  618. */
  619. if (IS_I9XX(dev))
  620. start = 1024*1024;
  621. else
  622. start = 512*1024;
  623. for (i = start; i < obj->size; i <<= 1)
  624. ;
  625. return i;
  626. }
  627. /**
  628. * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
  629. * @dev: DRM device
  630. * @data: GTT mapping ioctl data
  631. * @file_priv: GEM object info
  632. *
  633. * Simply returns the fake offset to userspace so it can mmap it.
  634. * The mmap call will end up in drm_gem_mmap(), which will set things
  635. * up so we can get faults in the handler above.
  636. *
  637. * The fault handler will take care of binding the object into the GTT
  638. * (since it may have been evicted to make room for something), allocating
  639. * a fence register, and mapping the appropriate aperture address into
  640. * userspace.
  641. */
  642. int
  643. i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
  644. struct drm_file *file_priv)
  645. {
  646. struct drm_i915_gem_mmap_gtt *args = data;
  647. struct drm_i915_private *dev_priv = dev->dev_private;
  648. struct drm_gem_object *obj;
  649. struct drm_i915_gem_object *obj_priv;
  650. int ret;
  651. if (!(dev->driver->driver_features & DRIVER_GEM))
  652. return -ENODEV;
  653. obj = drm_gem_object_lookup(dev, file_priv, args->handle);
  654. if (obj == NULL)
  655. return -EBADF;
  656. mutex_lock(&dev->struct_mutex);
  657. obj_priv = obj->driver_private;
  658. if (!obj_priv->mmap_offset) {
  659. ret = i915_gem_create_mmap_offset(obj);
  660. if (ret) {
  661. drm_gem_object_unreference(obj);
  662. mutex_unlock(&dev->struct_mutex);
  663. return ret;
  664. }
  665. }
  666. args->offset = obj_priv->mmap_offset;
  667. obj_priv->gtt_alignment = i915_gem_get_gtt_alignment(obj);
  668. /* Make sure the alignment is correct for fence regs etc */
  669. if (obj_priv->agp_mem &&
  670. (obj_priv->gtt_offset & (obj_priv->gtt_alignment - 1))) {
  671. drm_gem_object_unreference(obj);
  672. mutex_unlock(&dev->struct_mutex);
  673. return -EINVAL;
  674. }
  675. /*
  676. * Pull it into the GTT so that we have a page list (makes the
  677. * initial fault faster and any subsequent flushing possible).
  678. */
  679. if (!obj_priv->agp_mem) {
  680. ret = i915_gem_object_bind_to_gtt(obj, obj_priv->gtt_alignment);
  681. if (ret) {
  682. drm_gem_object_unreference(obj);
  683. mutex_unlock(&dev->struct_mutex);
  684. return ret;
  685. }
  686. list_add(&obj_priv->list, &dev_priv->mm.inactive_list);
  687. }
  688. drm_gem_object_unreference(obj);
  689. mutex_unlock(&dev->struct_mutex);
  690. return 0;
  691. }
  692. static void
  693. i915_gem_object_free_page_list(struct drm_gem_object *obj)
  694. {
  695. struct drm_i915_gem_object *obj_priv = obj->driver_private;
  696. int page_count = obj->size / PAGE_SIZE;
  697. int i;
  698. if (obj_priv->page_list == NULL)
  699. return;
  700. for (i = 0; i < page_count; i++)
  701. if (obj_priv->page_list[i] != NULL) {
  702. if (obj_priv->dirty)
  703. set_page_dirty(obj_priv->page_list[i]);
  704. mark_page_accessed(obj_priv->page_list[i]);
  705. page_cache_release(obj_priv->page_list[i]);
  706. }
  707. obj_priv->dirty = 0;
  708. drm_free(obj_priv->page_list,
  709. page_count * sizeof(struct page *),
  710. DRM_MEM_DRIVER);
  711. obj_priv->page_list = NULL;
  712. }
  713. static void
  714. i915_gem_object_move_to_active(struct drm_gem_object *obj, uint32_t seqno)
  715. {
  716. struct drm_device *dev = obj->dev;
  717. drm_i915_private_t *dev_priv = dev->dev_private;
  718. struct drm_i915_gem_object *obj_priv = obj->driver_private;
  719. /* Add a reference if we're newly entering the active list. */
  720. if (!obj_priv->active) {
  721. drm_gem_object_reference(obj);
  722. obj_priv->active = 1;
  723. }
  724. /* Move from whatever list we were on to the tail of execution. */
  725. list_move_tail(&obj_priv->list,
  726. &dev_priv->mm.active_list);
  727. obj_priv->last_rendering_seqno = seqno;
  728. }
  729. static void
  730. i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
  731. {
  732. struct drm_device *dev = obj->dev;
  733. drm_i915_private_t *dev_priv = dev->dev_private;
  734. struct drm_i915_gem_object *obj_priv = obj->driver_private;
  735. BUG_ON(!obj_priv->active);
  736. list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list);
  737. obj_priv->last_rendering_seqno = 0;
  738. }
  739. static void
  740. i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
  741. {
  742. struct drm_device *dev = obj->dev;
  743. drm_i915_private_t *dev_priv = dev->dev_private;
  744. struct drm_i915_gem_object *obj_priv = obj->driver_private;
  745. i915_verify_inactive(dev, __FILE__, __LINE__);
  746. if (obj_priv->pin_count != 0)
  747. list_del_init(&obj_priv->list);
  748. else
  749. list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
  750. obj_priv->last_rendering_seqno = 0;
  751. if (obj_priv->active) {
  752. obj_priv->active = 0;
  753. drm_gem_object_unreference(obj);
  754. }
  755. i915_verify_inactive(dev, __FILE__, __LINE__);
  756. }
  757. /**
  758. * Creates a new sequence number, emitting a write of it to the status page
  759. * plus an interrupt, which will trigger i915_user_interrupt_handler.
  760. *
  761. * Must be called with struct_lock held.
  762. *
  763. * Returned sequence numbers are nonzero on success.
  764. */
  765. static uint32_t
  766. i915_add_request(struct drm_device *dev, uint32_t flush_domains)
  767. {
  768. drm_i915_private_t *dev_priv = dev->dev_private;
  769. struct drm_i915_gem_request *request;
  770. uint32_t seqno;
  771. int was_empty;
  772. RING_LOCALS;
  773. request = drm_calloc(1, sizeof(*request), DRM_MEM_DRIVER);
  774. if (request == NULL)
  775. return 0;
  776. /* Grab the seqno we're going to make this request be, and bump the
  777. * next (skipping 0 so it can be the reserved no-seqno value).
  778. */
  779. seqno = dev_priv->mm.next_gem_seqno;
  780. dev_priv->mm.next_gem_seqno++;
  781. if (dev_priv->mm.next_gem_seqno == 0)
  782. dev_priv->mm.next_gem_seqno++;
  783. BEGIN_LP_RING(4);
  784. OUT_RING(MI_STORE_DWORD_INDEX);
  785. OUT_RING(I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
  786. OUT_RING(seqno);
  787. OUT_RING(MI_USER_INTERRUPT);
  788. ADVANCE_LP_RING();
  789. DRM_DEBUG("%d\n", seqno);
  790. request->seqno = seqno;
  791. request->emitted_jiffies = jiffies;
  792. was_empty = list_empty(&dev_priv->mm.request_list);
  793. list_add_tail(&request->list, &dev_priv->mm.request_list);
  794. /* Associate any objects on the flushing list matching the write
  795. * domain we're flushing with our flush.
  796. */
  797. if (flush_domains != 0) {
  798. struct drm_i915_gem_object *obj_priv, *next;
  799. list_for_each_entry_safe(obj_priv, next,
  800. &dev_priv->mm.flushing_list, list) {
  801. struct drm_gem_object *obj = obj_priv->obj;
  802. if ((obj->write_domain & flush_domains) ==
  803. obj->write_domain) {
  804. obj->write_domain = 0;
  805. i915_gem_object_move_to_active(obj, seqno);
  806. }
  807. }
  808. }
  809. if (was_empty && !dev_priv->mm.suspended)
  810. schedule_delayed_work(&dev_priv->mm.retire_work, HZ);
  811. return seqno;
  812. }
  813. /**
  814. * Command execution barrier
  815. *
  816. * Ensures that all commands in the ring are finished
  817. * before signalling the CPU
  818. */
  819. static uint32_t
  820. i915_retire_commands(struct drm_device *dev)
  821. {
  822. drm_i915_private_t *dev_priv = dev->dev_private;
  823. uint32_t cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
  824. uint32_t flush_domains = 0;
  825. RING_LOCALS;
  826. /* The sampler always gets flushed on i965 (sigh) */
  827. if (IS_I965G(dev))
  828. flush_domains |= I915_GEM_DOMAIN_SAMPLER;
  829. BEGIN_LP_RING(2);
  830. OUT_RING(cmd);
  831. OUT_RING(0); /* noop */
  832. ADVANCE_LP_RING();
  833. return flush_domains;
  834. }
  835. /**
  836. * Moves buffers associated only with the given active seqno from the active
  837. * to inactive list, potentially freeing them.
  838. */
  839. static void
  840. i915_gem_retire_request(struct drm_device *dev,
  841. struct drm_i915_gem_request *request)
  842. {
  843. drm_i915_private_t *dev_priv = dev->dev_private;
  844. /* Move any buffers on the active list that are no longer referenced
  845. * by the ringbuffer to the flushing/inactive lists as appropriate.
  846. */
  847. while (!list_empty(&dev_priv->mm.active_list)) {
  848. struct drm_gem_object *obj;
  849. struct drm_i915_gem_object *obj_priv;
  850. obj_priv = list_first_entry(&dev_priv->mm.active_list,
  851. struct drm_i915_gem_object,
  852. list);
  853. obj = obj_priv->obj;
  854. /* If the seqno being retired doesn't match the oldest in the
  855. * list, then the oldest in the list must still be newer than
  856. * this seqno.
  857. */
  858. if (obj_priv->last_rendering_seqno != request->seqno)
  859. return;
  860. #if WATCH_LRU
  861. DRM_INFO("%s: retire %d moves to inactive list %p\n",
  862. __func__, request->seqno, obj);
  863. #endif
  864. if (obj->write_domain != 0)
  865. i915_gem_object_move_to_flushing(obj);
  866. else
  867. i915_gem_object_move_to_inactive(obj);
  868. }
  869. }
  870. /**
  871. * Returns true if seq1 is later than seq2.
  872. */
  873. static int
  874. i915_seqno_passed(uint32_t seq1, uint32_t seq2)
  875. {
  876. return (int32_t)(seq1 - seq2) >= 0;
  877. }
  878. uint32_t
  879. i915_get_gem_seqno(struct drm_device *dev)
  880. {
  881. drm_i915_private_t *dev_priv = dev->dev_private;
  882. return READ_HWSP(dev_priv, I915_GEM_HWS_INDEX);
  883. }
  884. /**
  885. * This function clears the request list as sequence numbers are passed.
  886. */
  887. void
  888. i915_gem_retire_requests(struct drm_device *dev)
  889. {
  890. drm_i915_private_t *dev_priv = dev->dev_private;
  891. uint32_t seqno;
  892. if (!dev_priv->hw_status_page)
  893. return;
  894. seqno = i915_get_gem_seqno(dev);
  895. while (!list_empty(&dev_priv->mm.request_list)) {
  896. struct drm_i915_gem_request *request;
  897. uint32_t retiring_seqno;
  898. request = list_first_entry(&dev_priv->mm.request_list,
  899. struct drm_i915_gem_request,
  900. list);
  901. retiring_seqno = request->seqno;
  902. if (i915_seqno_passed(seqno, retiring_seqno) ||
  903. dev_priv->mm.wedged) {
  904. i915_gem_retire_request(dev, request);
  905. list_del(&request->list);
  906. drm_free(request, sizeof(*request), DRM_MEM_DRIVER);
  907. } else
  908. break;
  909. }
  910. }
  911. void
  912. i915_gem_retire_work_handler(struct work_struct *work)
  913. {
  914. drm_i915_private_t *dev_priv;
  915. struct drm_device *dev;
  916. dev_priv = container_of(work, drm_i915_private_t,
  917. mm.retire_work.work);
  918. dev = dev_priv->dev;
  919. mutex_lock(&dev->struct_mutex);
  920. i915_gem_retire_requests(dev);
  921. if (!dev_priv->mm.suspended &&
  922. !list_empty(&dev_priv->mm.request_list))
  923. schedule_delayed_work(&dev_priv->mm.retire_work, HZ);
  924. mutex_unlock(&dev->struct_mutex);
  925. }
  926. /**
  927. * Waits for a sequence number to be signaled, and cleans up the
  928. * request and object lists appropriately for that event.
  929. */
  930. static int
  931. i915_wait_request(struct drm_device *dev, uint32_t seqno)
  932. {
  933. drm_i915_private_t *dev_priv = dev->dev_private;
  934. int ret = 0;
  935. BUG_ON(seqno == 0);
  936. if (!i915_seqno_passed(i915_get_gem_seqno(dev), seqno)) {
  937. dev_priv->mm.waiting_gem_seqno = seqno;
  938. i915_user_irq_get(dev);
  939. ret = wait_event_interruptible(dev_priv->irq_queue,
  940. i915_seqno_passed(i915_get_gem_seqno(dev),
  941. seqno) ||
  942. dev_priv->mm.wedged);
  943. i915_user_irq_put(dev);
  944. dev_priv->mm.waiting_gem_seqno = 0;
  945. }
  946. if (dev_priv->mm.wedged)
  947. ret = -EIO;
  948. if (ret && ret != -ERESTARTSYS)
  949. DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
  950. __func__, ret, seqno, i915_get_gem_seqno(dev));
  951. /* Directly dispatch request retiring. While we have the work queue
  952. * to handle this, the waiter on a request often wants an associated
  953. * buffer to have made it to the inactive list, and we would need
  954. * a separate wait queue to handle that.
  955. */
  956. if (ret == 0)
  957. i915_gem_retire_requests(dev);
  958. return ret;
  959. }
  960. static void
  961. i915_gem_flush(struct drm_device *dev,
  962. uint32_t invalidate_domains,
  963. uint32_t flush_domains)
  964. {
  965. drm_i915_private_t *dev_priv = dev->dev_private;
  966. uint32_t cmd;
  967. RING_LOCALS;
  968. #if WATCH_EXEC
  969. DRM_INFO("%s: invalidate %08x flush %08x\n", __func__,
  970. invalidate_domains, flush_domains);
  971. #endif
  972. if (flush_domains & I915_GEM_DOMAIN_CPU)
  973. drm_agp_chipset_flush(dev);
  974. if ((invalidate_domains | flush_domains) & ~(I915_GEM_DOMAIN_CPU |
  975. I915_GEM_DOMAIN_GTT)) {
  976. /*
  977. * read/write caches:
  978. *
  979. * I915_GEM_DOMAIN_RENDER is always invalidated, but is
  980. * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
  981. * also flushed at 2d versus 3d pipeline switches.
  982. *
  983. * read-only caches:
  984. *
  985. * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
  986. * MI_READ_FLUSH is set, and is always flushed on 965.
  987. *
  988. * I915_GEM_DOMAIN_COMMAND may not exist?
  989. *
  990. * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
  991. * invalidated when MI_EXE_FLUSH is set.
  992. *
  993. * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
  994. * invalidated with every MI_FLUSH.
  995. *
  996. * TLBs:
  997. *
  998. * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
  999. * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
  1000. * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
  1001. * are flushed at any MI_FLUSH.
  1002. */
  1003. cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
  1004. if ((invalidate_domains|flush_domains) &
  1005. I915_GEM_DOMAIN_RENDER)
  1006. cmd &= ~MI_NO_WRITE_FLUSH;
  1007. if (!IS_I965G(dev)) {
  1008. /*
  1009. * On the 965, the sampler cache always gets flushed
  1010. * and this bit is reserved.
  1011. */
  1012. if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
  1013. cmd |= MI_READ_FLUSH;
  1014. }
  1015. if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
  1016. cmd |= MI_EXE_FLUSH;
  1017. #if WATCH_EXEC
  1018. DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd);
  1019. #endif
  1020. BEGIN_LP_RING(2);
  1021. OUT_RING(cmd);
  1022. OUT_RING(0); /* noop */
  1023. ADVANCE_LP_RING();
  1024. }
  1025. }
  1026. /**
  1027. * Ensures that all rendering to the object has completed and the object is
  1028. * safe to unbind from the GTT or access from the CPU.
  1029. */
  1030. static int
  1031. i915_gem_object_wait_rendering(struct drm_gem_object *obj)
  1032. {
  1033. struct drm_device *dev = obj->dev;
  1034. struct drm_i915_gem_object *obj_priv = obj->driver_private;
  1035. int ret;
  1036. /* This function only exists to support waiting for existing rendering,
  1037. * not for emitting required flushes.
  1038. */
  1039. BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0);
  1040. /* If there is rendering queued on the buffer being evicted, wait for
  1041. * it.
  1042. */
  1043. if (obj_priv->active) {
  1044. #if WATCH_BUF
  1045. DRM_INFO("%s: object %p wait for seqno %08x\n",
  1046. __func__, obj, obj_priv->last_rendering_seqno);
  1047. #endif
  1048. ret = i915_wait_request(dev, obj_priv->last_rendering_seqno);
  1049. if (ret != 0)
  1050. return ret;
  1051. }
  1052. return 0;
  1053. }
  1054. /**
  1055. * Unbinds an object from the GTT aperture.
  1056. */
  1057. int
  1058. i915_gem_object_unbind(struct drm_gem_object *obj)
  1059. {
  1060. struct drm_device *dev = obj->dev;
  1061. struct drm_i915_gem_object *obj_priv = obj->driver_private;
  1062. loff_t offset;
  1063. int ret = 0;
  1064. #if WATCH_BUF
  1065. DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj);
  1066. DRM_INFO("gtt_space %p\n", obj_priv->gtt_space);
  1067. #endif
  1068. if (obj_priv->gtt_space == NULL)
  1069. return 0;
  1070. if (obj_priv->pin_count != 0) {
  1071. DRM_ERROR("Attempting to unbind pinned buffer\n");
  1072. return -EINVAL;
  1073. }
  1074. /* Move the object to the CPU domain to ensure that
  1075. * any possible CPU writes while it's not in the GTT
  1076. * are flushed when we go to remap it. This will
  1077. * also ensure that all pending GPU writes are finished
  1078. * before we unbind.
  1079. */
  1080. ret = i915_gem_object_set_to_cpu_domain(obj, 1);
  1081. if (ret) {
  1082. if (ret != -ERESTARTSYS)
  1083. DRM_ERROR("set_domain failed: %d\n", ret);
  1084. return ret;
  1085. }
  1086. if (obj_priv->agp_mem != NULL) {
  1087. drm_unbind_agp(obj_priv->agp_mem);
  1088. drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
  1089. obj_priv->agp_mem = NULL;
  1090. }
  1091. BUG_ON(obj_priv->active);
  1092. /* blow away mappings if mapped through GTT */
  1093. offset = ((loff_t) obj->map_list.hash.key) << PAGE_SHIFT;
  1094. if (dev->dev_mapping)
  1095. unmap_mapping_range(dev->dev_mapping, offset, obj->size, 1);
  1096. if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
  1097. i915_gem_clear_fence_reg(obj);
  1098. i915_gem_object_free_page_list(obj);
  1099. if (obj_priv->gtt_space) {
  1100. atomic_dec(&dev->gtt_count);
  1101. atomic_sub(obj->size, &dev->gtt_memory);
  1102. drm_mm_put_block(obj_priv->gtt_space);
  1103. obj_priv->gtt_space = NULL;
  1104. }
  1105. /* Remove ourselves from the LRU list if present. */
  1106. if (!list_empty(&obj_priv->list))
  1107. list_del_init(&obj_priv->list);
  1108. return 0;
  1109. }
  1110. static int
  1111. i915_gem_evict_something(struct drm_device *dev)
  1112. {
  1113. drm_i915_private_t *dev_priv = dev->dev_private;
  1114. struct drm_gem_object *obj;
  1115. struct drm_i915_gem_object *obj_priv;
  1116. int ret = 0;
  1117. for (;;) {
  1118. /* If there's an inactive buffer available now, grab it
  1119. * and be done.
  1120. */
  1121. if (!list_empty(&dev_priv->mm.inactive_list)) {
  1122. obj_priv = list_first_entry(&dev_priv->mm.inactive_list,
  1123. struct drm_i915_gem_object,
  1124. list);
  1125. obj = obj_priv->obj;
  1126. BUG_ON(obj_priv->pin_count != 0);
  1127. #if WATCH_LRU
  1128. DRM_INFO("%s: evicting %p\n", __func__, obj);
  1129. #endif
  1130. BUG_ON(obj_priv->active);
  1131. /* Wait on the rendering and unbind the buffer. */
  1132. ret = i915_gem_object_unbind(obj);
  1133. break;
  1134. }
  1135. /* If we didn't get anything, but the ring is still processing
  1136. * things, wait for one of those things to finish and hopefully
  1137. * leave us a buffer to evict.
  1138. */
  1139. if (!list_empty(&dev_priv->mm.request_list)) {
  1140. struct drm_i915_gem_request *request;
  1141. request = list_first_entry(&dev_priv->mm.request_list,
  1142. struct drm_i915_gem_request,
  1143. list);
  1144. ret = i915_wait_request(dev, request->seqno);
  1145. if (ret)
  1146. break;
  1147. /* if waiting caused an object to become inactive,
  1148. * then loop around and wait for it. Otherwise, we
  1149. * assume that waiting freed and unbound something,
  1150. * so there should now be some space in the GTT
  1151. */
  1152. if (!list_empty(&dev_priv->mm.inactive_list))
  1153. continue;
  1154. break;
  1155. }
  1156. /* If we didn't have anything on the request list but there
  1157. * are buffers awaiting a flush, emit one and try again.
  1158. * When we wait on it, those buffers waiting for that flush
  1159. * will get moved to inactive.
  1160. */
  1161. if (!list_empty(&dev_priv->mm.flushing_list)) {
  1162. obj_priv = list_first_entry(&dev_priv->mm.flushing_list,
  1163. struct drm_i915_gem_object,
  1164. list);
  1165. obj = obj_priv->obj;
  1166. i915_gem_flush(dev,
  1167. obj->write_domain,
  1168. obj->write_domain);
  1169. i915_add_request(dev, obj->write_domain);
  1170. obj = NULL;
  1171. continue;
  1172. }
  1173. DRM_ERROR("inactive empty %d request empty %d "
  1174. "flushing empty %d\n",
  1175. list_empty(&dev_priv->mm.inactive_list),
  1176. list_empty(&dev_priv->mm.request_list),
  1177. list_empty(&dev_priv->mm.flushing_list));
  1178. /* If we didn't do any of the above, there's nothing to be done
  1179. * and we just can't fit it in.
  1180. */
  1181. return -ENOMEM;
  1182. }
  1183. return ret;
  1184. }
  1185. static int
  1186. i915_gem_evict_everything(struct drm_device *dev)
  1187. {
  1188. int ret;
  1189. for (;;) {
  1190. ret = i915_gem_evict_something(dev);
  1191. if (ret != 0)
  1192. break;
  1193. }
  1194. if (ret == -ENOMEM)
  1195. return 0;
  1196. return ret;
  1197. }
  1198. static int
  1199. i915_gem_object_get_page_list(struct drm_gem_object *obj)
  1200. {
  1201. struct drm_i915_gem_object *obj_priv = obj->driver_private;
  1202. int page_count, i;
  1203. struct address_space *mapping;
  1204. struct inode *inode;
  1205. struct page *page;
  1206. int ret;
  1207. if (obj_priv->page_list)
  1208. return 0;
  1209. /* Get the list of pages out of our struct file. They'll be pinned
  1210. * at this point until we release them.
  1211. */
  1212. page_count = obj->size / PAGE_SIZE;
  1213. BUG_ON(obj_priv->page_list != NULL);
  1214. obj_priv->page_list = drm_calloc(page_count, sizeof(struct page *),
  1215. DRM_MEM_DRIVER);
  1216. if (obj_priv->page_list == NULL) {
  1217. DRM_ERROR("Faled to allocate page list\n");
  1218. return -ENOMEM;
  1219. }
  1220. inode = obj->filp->f_path.dentry->d_inode;
  1221. mapping = inode->i_mapping;
  1222. for (i = 0; i < page_count; i++) {
  1223. page = read_mapping_page(mapping, i, NULL);
  1224. if (IS_ERR(page)) {
  1225. ret = PTR_ERR(page);
  1226. DRM_ERROR("read_mapping_page failed: %d\n", ret);
  1227. i915_gem_object_free_page_list(obj);
  1228. return ret;
  1229. }
  1230. obj_priv->page_list[i] = page;
  1231. }
  1232. return 0;
  1233. }
  1234. static void i965_write_fence_reg(struct drm_i915_fence_reg *reg)
  1235. {
  1236. struct drm_gem_object *obj = reg->obj;
  1237. struct drm_device *dev = obj->dev;
  1238. drm_i915_private_t *dev_priv = dev->dev_private;
  1239. struct drm_i915_gem_object *obj_priv = obj->driver_private;
  1240. int regnum = obj_priv->fence_reg;
  1241. uint64_t val;
  1242. val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
  1243. 0xfffff000) << 32;
  1244. val |= obj_priv->gtt_offset & 0xfffff000;
  1245. val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
  1246. if (obj_priv->tiling_mode == I915_TILING_Y)
  1247. val |= 1 << I965_FENCE_TILING_Y_SHIFT;
  1248. val |= I965_FENCE_REG_VALID;
  1249. I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val);
  1250. }
  1251. static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
  1252. {
  1253. struct drm_gem_object *obj = reg->obj;
  1254. struct drm_device *dev = obj->dev;
  1255. drm_i915_private_t *dev_priv = dev->dev_private;
  1256. struct drm_i915_gem_object *obj_priv = obj->driver_private;
  1257. int regnum = obj_priv->fence_reg;
  1258. int tile_width;
  1259. uint32_t val;
  1260. uint32_t pitch_val;
  1261. if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
  1262. (obj_priv->gtt_offset & (obj->size - 1))) {
  1263. WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
  1264. __func__, obj_priv->gtt_offset, obj->size);
  1265. return;
  1266. }
  1267. if (obj_priv->tiling_mode == I915_TILING_Y &&
  1268. HAS_128_BYTE_Y_TILING(dev))
  1269. tile_width = 128;
  1270. else
  1271. tile_width = 512;
  1272. /* Note: pitch better be a power of two tile widths */
  1273. pitch_val = obj_priv->stride / tile_width;
  1274. pitch_val = ffs(pitch_val) - 1;
  1275. val = obj_priv->gtt_offset;
  1276. if (obj_priv->tiling_mode == I915_TILING_Y)
  1277. val |= 1 << I830_FENCE_TILING_Y_SHIFT;
  1278. val |= I915_FENCE_SIZE_BITS(obj->size);
  1279. val |= pitch_val << I830_FENCE_PITCH_SHIFT;
  1280. val |= I830_FENCE_REG_VALID;
  1281. I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
  1282. }
  1283. static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
  1284. {
  1285. struct drm_gem_object *obj = reg->obj;
  1286. struct drm_device *dev = obj->dev;
  1287. drm_i915_private_t *dev_priv = dev->dev_private;
  1288. struct drm_i915_gem_object *obj_priv = obj->driver_private;
  1289. int regnum = obj_priv->fence_reg;
  1290. uint32_t val;
  1291. uint32_t pitch_val;
  1292. if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
  1293. (obj_priv->gtt_offset & (obj->size - 1))) {
  1294. WARN(1, "%s: object 0x%08x not 1M or size aligned\n",
  1295. __func__, obj_priv->gtt_offset);
  1296. return;
  1297. }
  1298. pitch_val = (obj_priv->stride / 128) - 1;
  1299. val = obj_priv->gtt_offset;
  1300. if (obj_priv->tiling_mode == I915_TILING_Y)
  1301. val |= 1 << I830_FENCE_TILING_Y_SHIFT;
  1302. val |= I830_FENCE_SIZE_BITS(obj->size);
  1303. val |= pitch_val << I830_FENCE_PITCH_SHIFT;
  1304. val |= I830_FENCE_REG_VALID;
  1305. I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
  1306. }
  1307. /**
  1308. * i915_gem_object_get_fence_reg - set up a fence reg for an object
  1309. * @obj: object to map through a fence reg
  1310. * @write: object is about to be written
  1311. *
  1312. * When mapping objects through the GTT, userspace wants to be able to write
  1313. * to them without having to worry about swizzling if the object is tiled.
  1314. *
  1315. * This function walks the fence regs looking for a free one for @obj,
  1316. * stealing one if it can't find any.
  1317. *
  1318. * It then sets up the reg based on the object's properties: address, pitch
  1319. * and tiling format.
  1320. */
  1321. static int
  1322. i915_gem_object_get_fence_reg(struct drm_gem_object *obj, bool write)
  1323. {
  1324. struct drm_device *dev = obj->dev;
  1325. struct drm_i915_private *dev_priv = dev->dev_private;
  1326. struct drm_i915_gem_object *obj_priv = obj->driver_private;
  1327. struct drm_i915_fence_reg *reg = NULL;
  1328. int i, ret;
  1329. switch (obj_priv->tiling_mode) {
  1330. case I915_TILING_NONE:
  1331. WARN(1, "allocating a fence for non-tiled object?\n");
  1332. break;
  1333. case I915_TILING_X:
  1334. if (!obj_priv->stride)
  1335. return -EINVAL;
  1336. WARN((obj_priv->stride & (512 - 1)),
  1337. "object 0x%08x is X tiled but has non-512B pitch\n",
  1338. obj_priv->gtt_offset);
  1339. break;
  1340. case I915_TILING_Y:
  1341. if (!obj_priv->stride)
  1342. return -EINVAL;
  1343. WARN((obj_priv->stride & (128 - 1)),
  1344. "object 0x%08x is Y tiled but has non-128B pitch\n",
  1345. obj_priv->gtt_offset);
  1346. break;
  1347. }
  1348. /* First try to find a free reg */
  1349. for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
  1350. reg = &dev_priv->fence_regs[i];
  1351. if (!reg->obj)
  1352. break;
  1353. }
  1354. /* None available, try to steal one or wait for a user to finish */
  1355. if (i == dev_priv->num_fence_regs) {
  1356. struct drm_i915_gem_object *old_obj_priv = NULL;
  1357. loff_t offset;
  1358. try_again:
  1359. /* Could try to use LRU here instead... */
  1360. for (i = dev_priv->fence_reg_start;
  1361. i < dev_priv->num_fence_regs; i++) {
  1362. reg = &dev_priv->fence_regs[i];
  1363. old_obj_priv = reg->obj->driver_private;
  1364. if (!old_obj_priv->pin_count)
  1365. break;
  1366. }
  1367. /*
  1368. * Now things get ugly... we have to wait for one of the
  1369. * objects to finish before trying again.
  1370. */
  1371. if (i == dev_priv->num_fence_regs) {
  1372. ret = i915_gem_object_set_to_gtt_domain(reg->obj, 0);
  1373. if (ret) {
  1374. WARN(ret != -ERESTARTSYS,
  1375. "switch to GTT domain failed: %d\n", ret);
  1376. return ret;
  1377. }
  1378. goto try_again;
  1379. }
  1380. /*
  1381. * Zap this virtual mapping so we can set up a fence again
  1382. * for this object next time we need it.
  1383. */
  1384. offset = ((loff_t) reg->obj->map_list.hash.key) << PAGE_SHIFT;
  1385. if (dev->dev_mapping)
  1386. unmap_mapping_range(dev->dev_mapping, offset,
  1387. reg->obj->size, 1);
  1388. old_obj_priv->fence_reg = I915_FENCE_REG_NONE;
  1389. }
  1390. obj_priv->fence_reg = i;
  1391. reg->obj = obj;
  1392. if (IS_I965G(dev))
  1393. i965_write_fence_reg(reg);
  1394. else if (IS_I9XX(dev))
  1395. i915_write_fence_reg(reg);
  1396. else
  1397. i830_write_fence_reg(reg);
  1398. return 0;
  1399. }
  1400. /**
  1401. * i915_gem_clear_fence_reg - clear out fence register info
  1402. * @obj: object to clear
  1403. *
  1404. * Zeroes out the fence register itself and clears out the associated
  1405. * data structures in dev_priv and obj_priv.
  1406. */
  1407. static void
  1408. i915_gem_clear_fence_reg(struct drm_gem_object *obj)
  1409. {
  1410. struct drm_device *dev = obj->dev;
  1411. drm_i915_private_t *dev_priv = dev->dev_private;
  1412. struct drm_i915_gem_object *obj_priv = obj->driver_private;
  1413. if (IS_I965G(dev))
  1414. I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
  1415. else
  1416. I915_WRITE(FENCE_REG_830_0 + (obj_priv->fence_reg * 4), 0);
  1417. dev_priv->fence_regs[obj_priv->fence_reg].obj = NULL;
  1418. obj_priv->fence_reg = I915_FENCE_REG_NONE;
  1419. }
  1420. /**
  1421. * Finds free space in the GTT aperture and binds the object there.
  1422. */
  1423. static int
  1424. i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
  1425. {
  1426. struct drm_device *dev = obj->dev;
  1427. drm_i915_private_t *dev_priv = dev->dev_private;
  1428. struct drm_i915_gem_object *obj_priv = obj->driver_private;
  1429. struct drm_mm_node *free_space;
  1430. int page_count, ret;
  1431. if (dev_priv->mm.suspended)
  1432. return -EBUSY;
  1433. if (alignment == 0)
  1434. alignment = i915_gem_get_gtt_alignment(obj);
  1435. if (alignment & (PAGE_SIZE - 1)) {
  1436. DRM_ERROR("Invalid object alignment requested %u\n", alignment);
  1437. return -EINVAL;
  1438. }
  1439. search_free:
  1440. free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
  1441. obj->size, alignment, 0);
  1442. if (free_space != NULL) {
  1443. obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size,
  1444. alignment);
  1445. if (obj_priv->gtt_space != NULL) {
  1446. obj_priv->gtt_space->private = obj;
  1447. obj_priv->gtt_offset = obj_priv->gtt_space->start;
  1448. }
  1449. }
  1450. if (obj_priv->gtt_space == NULL) {
  1451. /* If the gtt is empty and we're still having trouble
  1452. * fitting our object in, we're out of memory.
  1453. */
  1454. #if WATCH_LRU
  1455. DRM_INFO("%s: GTT full, evicting something\n", __func__);
  1456. #endif
  1457. if (list_empty(&dev_priv->mm.inactive_list) &&
  1458. list_empty(&dev_priv->mm.flushing_list) &&
  1459. list_empty(&dev_priv->mm.active_list)) {
  1460. DRM_ERROR("GTT full, but LRU list empty\n");
  1461. return -ENOMEM;
  1462. }
  1463. ret = i915_gem_evict_something(dev);
  1464. if (ret != 0) {
  1465. if (ret != -ERESTARTSYS)
  1466. DRM_ERROR("Failed to evict a buffer %d\n", ret);
  1467. return ret;
  1468. }
  1469. goto search_free;
  1470. }
  1471. #if WATCH_BUF
  1472. DRM_INFO("Binding object of size %d at 0x%08x\n",
  1473. obj->size, obj_priv->gtt_offset);
  1474. #endif
  1475. ret = i915_gem_object_get_page_list(obj);
  1476. if (ret) {
  1477. drm_mm_put_block(obj_priv->gtt_space);
  1478. obj_priv->gtt_space = NULL;
  1479. return ret;
  1480. }
  1481. page_count = obj->size / PAGE_SIZE;
  1482. /* Create an AGP memory structure pointing at our pages, and bind it
  1483. * into the GTT.
  1484. */
  1485. obj_priv->agp_mem = drm_agp_bind_pages(dev,
  1486. obj_priv->page_list,
  1487. page_count,
  1488. obj_priv->gtt_offset,
  1489. obj_priv->agp_type);
  1490. if (obj_priv->agp_mem == NULL) {
  1491. i915_gem_object_free_page_list(obj);
  1492. drm_mm_put_block(obj_priv->gtt_space);
  1493. obj_priv->gtt_space = NULL;
  1494. return -ENOMEM;
  1495. }
  1496. atomic_inc(&dev->gtt_count);
  1497. atomic_add(obj->size, &dev->gtt_memory);
  1498. /* Assert that the object is not currently in any GPU domain. As it
  1499. * wasn't in the GTT, there shouldn't be any way it could have been in
  1500. * a GPU cache
  1501. */
  1502. BUG_ON(obj->read_domains & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT));
  1503. BUG_ON(obj->write_domain & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT));
  1504. return 0;
  1505. }
  1506. void
  1507. i915_gem_clflush_object(struct drm_gem_object *obj)
  1508. {
  1509. struct drm_i915_gem_object *obj_priv = obj->driver_private;
  1510. /* If we don't have a page list set up, then we're not pinned
  1511. * to GPU, and we can ignore the cache flush because it'll happen
  1512. * again at bind time.
  1513. */
  1514. if (obj_priv->page_list == NULL)
  1515. return;
  1516. drm_clflush_pages(obj_priv->page_list, obj->size / PAGE_SIZE);
  1517. }
  1518. /** Flushes any GPU write domain for the object if it's dirty. */
  1519. static void
  1520. i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj)
  1521. {
  1522. struct drm_device *dev = obj->dev;
  1523. uint32_t seqno;
  1524. if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
  1525. return;
  1526. /* Queue the GPU write cache flushing we need. */
  1527. i915_gem_flush(dev, 0, obj->write_domain);
  1528. seqno = i915_add_request(dev, obj->write_domain);
  1529. obj->write_domain = 0;
  1530. i915_gem_object_move_to_active(obj, seqno);
  1531. }
  1532. /** Flushes the GTT write domain for the object if it's dirty. */
  1533. static void
  1534. i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
  1535. {
  1536. if (obj->write_domain != I915_GEM_DOMAIN_GTT)
  1537. return;
  1538. /* No actual flushing is required for the GTT write domain. Writes
  1539. * to it immediately go to main memory as far as we know, so there's
  1540. * no chipset flush. It also doesn't land in render cache.
  1541. */
  1542. obj->write_domain = 0;
  1543. }
  1544. /** Flushes the CPU write domain for the object if it's dirty. */
  1545. static void
  1546. i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
  1547. {
  1548. struct drm_device *dev = obj->dev;
  1549. if (obj->write_domain != I915_GEM_DOMAIN_CPU)
  1550. return;
  1551. i915_gem_clflush_object(obj);
  1552. drm_agp_chipset_flush(dev);
  1553. obj->write_domain = 0;
  1554. }
  1555. /**
  1556. * Moves a single object to the GTT read, and possibly write domain.
  1557. *
  1558. * This function returns when the move is complete, including waiting on
  1559. * flushes to occur.
  1560. */
  1561. int
  1562. i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
  1563. {
  1564. struct drm_i915_gem_object *obj_priv = obj->driver_private;
  1565. int ret;
  1566. /* Not valid to be called on unbound objects. */
  1567. if (obj_priv->gtt_space == NULL)
  1568. return -EINVAL;
  1569. i915_gem_object_flush_gpu_write_domain(obj);
  1570. /* Wait on any GPU rendering and flushing to occur. */
  1571. ret = i915_gem_object_wait_rendering(obj);
  1572. if (ret != 0)
  1573. return ret;
  1574. /* If we're writing through the GTT domain, then CPU and GPU caches
  1575. * will need to be invalidated at next use.
  1576. */
  1577. if (write)
  1578. obj->read_domains &= I915_GEM_DOMAIN_GTT;
  1579. i915_gem_object_flush_cpu_write_domain(obj);
  1580. /* It should now be out of any other write domains, and we can update
  1581. * the domain values for our changes.
  1582. */
  1583. BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
  1584. obj->read_domains |= I915_GEM_DOMAIN_GTT;
  1585. if (write) {
  1586. obj->write_domain = I915_GEM_DOMAIN_GTT;
  1587. obj_priv->dirty = 1;
  1588. }
  1589. return 0;
  1590. }
  1591. /**
  1592. * Moves a single object to the CPU read, and possibly write domain.
  1593. *
  1594. * This function returns when the move is complete, including waiting on
  1595. * flushes to occur.
  1596. */
  1597. static int
  1598. i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
  1599. {
  1600. struct drm_device *dev = obj->dev;
  1601. int ret;
  1602. i915_gem_object_flush_gpu_write_domain(obj);
  1603. /* Wait on any GPU rendering and flushing to occur. */
  1604. ret = i915_gem_object_wait_rendering(obj);
  1605. if (ret != 0)
  1606. return ret;
  1607. i915_gem_object_flush_gtt_write_domain(obj);
  1608. /* If we have a partially-valid cache of the object in the CPU,
  1609. * finish invalidating it and free the per-page flags.
  1610. */
  1611. i915_gem_object_set_to_full_cpu_read_domain(obj);
  1612. /* Flush the CPU cache if it's still invalid. */
  1613. if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
  1614. i915_gem_clflush_object(obj);
  1615. drm_agp_chipset_flush(dev);
  1616. obj->read_domains |= I915_GEM_DOMAIN_CPU;
  1617. }
  1618. /* It should now be out of any other write domains, and we can update
  1619. * the domain values for our changes.
  1620. */
  1621. BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
  1622. /* If we're writing through the CPU, then the GPU read domains will
  1623. * need to be invalidated at next use.
  1624. */
  1625. if (write) {
  1626. obj->read_domains &= I915_GEM_DOMAIN_CPU;
  1627. obj->write_domain = I915_GEM_DOMAIN_CPU;
  1628. }
  1629. return 0;
  1630. }
  1631. /*
  1632. * Set the next domain for the specified object. This
  1633. * may not actually perform the necessary flushing/invaliding though,
  1634. * as that may want to be batched with other set_domain operations
  1635. *
  1636. * This is (we hope) the only really tricky part of gem. The goal
  1637. * is fairly simple -- track which caches hold bits of the object
  1638. * and make sure they remain coherent. A few concrete examples may
  1639. * help to explain how it works. For shorthand, we use the notation
  1640. * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
  1641. * a pair of read and write domain masks.
  1642. *
  1643. * Case 1: the batch buffer
  1644. *
  1645. * 1. Allocated
  1646. * 2. Written by CPU
  1647. * 3. Mapped to GTT
  1648. * 4. Read by GPU
  1649. * 5. Unmapped from GTT
  1650. * 6. Freed
  1651. *
  1652. * Let's take these a step at a time
  1653. *
  1654. * 1. Allocated
  1655. * Pages allocated from the kernel may still have
  1656. * cache contents, so we set them to (CPU, CPU) always.
  1657. * 2. Written by CPU (using pwrite)
  1658. * The pwrite function calls set_domain (CPU, CPU) and
  1659. * this function does nothing (as nothing changes)
  1660. * 3. Mapped by GTT
  1661. * This function asserts that the object is not
  1662. * currently in any GPU-based read or write domains
  1663. * 4. Read by GPU
  1664. * i915_gem_execbuffer calls set_domain (COMMAND, 0).
  1665. * As write_domain is zero, this function adds in the
  1666. * current read domains (CPU+COMMAND, 0).
  1667. * flush_domains is set to CPU.
  1668. * invalidate_domains is set to COMMAND
  1669. * clflush is run to get data out of the CPU caches
  1670. * then i915_dev_set_domain calls i915_gem_flush to
  1671. * emit an MI_FLUSH and drm_agp_chipset_flush
  1672. * 5. Unmapped from GTT
  1673. * i915_gem_object_unbind calls set_domain (CPU, CPU)
  1674. * flush_domains and invalidate_domains end up both zero
  1675. * so no flushing/invalidating happens
  1676. * 6. Freed
  1677. * yay, done
  1678. *
  1679. * Case 2: The shared render buffer
  1680. *
  1681. * 1. Allocated
  1682. * 2. Mapped to GTT
  1683. * 3. Read/written by GPU
  1684. * 4. set_domain to (CPU,CPU)
  1685. * 5. Read/written by CPU
  1686. * 6. Read/written by GPU
  1687. *
  1688. * 1. Allocated
  1689. * Same as last example, (CPU, CPU)
  1690. * 2. Mapped to GTT
  1691. * Nothing changes (assertions find that it is not in the GPU)
  1692. * 3. Read/written by GPU
  1693. * execbuffer calls set_domain (RENDER, RENDER)
  1694. * flush_domains gets CPU
  1695. * invalidate_domains gets GPU
  1696. * clflush (obj)
  1697. * MI_FLUSH and drm_agp_chipset_flush
  1698. * 4. set_domain (CPU, CPU)
  1699. * flush_domains gets GPU
  1700. * invalidate_domains gets CPU
  1701. * wait_rendering (obj) to make sure all drawing is complete.
  1702. * This will include an MI_FLUSH to get the data from GPU
  1703. * to memory
  1704. * clflush (obj) to invalidate the CPU cache
  1705. * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
  1706. * 5. Read/written by CPU
  1707. * cache lines are loaded and dirtied
  1708. * 6. Read written by GPU
  1709. * Same as last GPU access
  1710. *
  1711. * Case 3: The constant buffer
  1712. *
  1713. * 1. Allocated
  1714. * 2. Written by CPU
  1715. * 3. Read by GPU
  1716. * 4. Updated (written) by CPU again
  1717. * 5. Read by GPU
  1718. *
  1719. * 1. Allocated
  1720. * (CPU, CPU)
  1721. * 2. Written by CPU
  1722. * (CPU, CPU)
  1723. * 3. Read by GPU
  1724. * (CPU+RENDER, 0)
  1725. * flush_domains = CPU
  1726. * invalidate_domains = RENDER
  1727. * clflush (obj)
  1728. * MI_FLUSH
  1729. * drm_agp_chipset_flush
  1730. * 4. Updated (written) by CPU again
  1731. * (CPU, CPU)
  1732. * flush_domains = 0 (no previous write domain)
  1733. * invalidate_domains = 0 (no new read domains)
  1734. * 5. Read by GPU
  1735. * (CPU+RENDER, 0)
  1736. * flush_domains = CPU
  1737. * invalidate_domains = RENDER
  1738. * clflush (obj)
  1739. * MI_FLUSH
  1740. * drm_agp_chipset_flush
  1741. */
  1742. static void
  1743. i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj)
  1744. {
  1745. struct drm_device *dev = obj->dev;
  1746. struct drm_i915_gem_object *obj_priv = obj->driver_private;
  1747. uint32_t invalidate_domains = 0;
  1748. uint32_t flush_domains = 0;
  1749. BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU);
  1750. BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU);
  1751. #if WATCH_BUF
  1752. DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
  1753. __func__, obj,
  1754. obj->read_domains, obj->pending_read_domains,
  1755. obj->write_domain, obj->pending_write_domain);
  1756. #endif
  1757. /*
  1758. * If the object isn't moving to a new write domain,
  1759. * let the object stay in multiple read domains
  1760. */
  1761. if (obj->pending_write_domain == 0)
  1762. obj->pending_read_domains |= obj->read_domains;
  1763. else
  1764. obj_priv->dirty = 1;
  1765. /*
  1766. * Flush the current write domain if
  1767. * the new read domains don't match. Invalidate
  1768. * any read domains which differ from the old
  1769. * write domain
  1770. */
  1771. if (obj->write_domain &&
  1772. obj->write_domain != obj->pending_read_domains) {
  1773. flush_domains |= obj->write_domain;
  1774. invalidate_domains |=
  1775. obj->pending_read_domains & ~obj->write_domain;
  1776. }
  1777. /*
  1778. * Invalidate any read caches which may have
  1779. * stale data. That is, any new read domains.
  1780. */
  1781. invalidate_domains |= obj->pending_read_domains & ~obj->read_domains;
  1782. if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) {
  1783. #if WATCH_BUF
  1784. DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
  1785. __func__, flush_domains, invalidate_domains);
  1786. #endif
  1787. i915_gem_clflush_object(obj);
  1788. }
  1789. /* The actual obj->write_domain will be updated with
  1790. * pending_write_domain after we emit the accumulated flush for all
  1791. * of our domain changes in execbuffers (which clears objects'
  1792. * write_domains). So if we have a current write domain that we
  1793. * aren't changing, set pending_write_domain to that.
  1794. */
  1795. if (flush_domains == 0 && obj->pending_write_domain == 0)
  1796. obj->pending_write_domain = obj->write_domain;
  1797. obj->read_domains = obj->pending_read_domains;
  1798. dev->invalidate_domains |= invalidate_domains;
  1799. dev->flush_domains |= flush_domains;
  1800. #if WATCH_BUF
  1801. DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
  1802. __func__,
  1803. obj->read_domains, obj->write_domain,
  1804. dev->invalidate_domains, dev->flush_domains);
  1805. #endif
  1806. }
  1807. /**
  1808. * Moves the object from a partially CPU read to a full one.
  1809. *
  1810. * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
  1811. * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
  1812. */
  1813. static void
  1814. i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj)
  1815. {
  1816. struct drm_device *dev = obj->dev;
  1817. struct drm_i915_gem_object *obj_priv = obj->driver_private;
  1818. if (!obj_priv->page_cpu_valid)
  1819. return;
  1820. /* If we're partially in the CPU read domain, finish moving it in.
  1821. */
  1822. if (obj->read_domains & I915_GEM_DOMAIN_CPU) {
  1823. int i;
  1824. for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) {
  1825. if (obj_priv->page_cpu_valid[i])
  1826. continue;
  1827. drm_clflush_pages(obj_priv->page_list + i, 1);
  1828. }
  1829. drm_agp_chipset_flush(dev);
  1830. }
  1831. /* Free the page_cpu_valid mappings which are now stale, whether
  1832. * or not we've got I915_GEM_DOMAIN_CPU.
  1833. */
  1834. drm_free(obj_priv->page_cpu_valid, obj->size / PAGE_SIZE,
  1835. DRM_MEM_DRIVER);
  1836. obj_priv->page_cpu_valid = NULL;
  1837. }
  1838. /**
  1839. * Set the CPU read domain on a range of the object.
  1840. *
  1841. * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
  1842. * not entirely valid. The page_cpu_valid member of the object flags which
  1843. * pages have been flushed, and will be respected by
  1844. * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
  1845. * of the whole object.
  1846. *
  1847. * This function returns when the move is complete, including waiting on
  1848. * flushes to occur.
  1849. */
  1850. static int
  1851. i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
  1852. uint64_t offset, uint64_t size)
  1853. {
  1854. struct drm_i915_gem_object *obj_priv = obj->driver_private;
  1855. int i, ret;
  1856. if (offset == 0 && size == obj->size)
  1857. return i915_gem_object_set_to_cpu_domain(obj, 0);
  1858. i915_gem_object_flush_gpu_write_domain(obj);
  1859. /* Wait on any GPU rendering and flushing to occur. */
  1860. ret = i915_gem_object_wait_rendering(obj);
  1861. if (ret != 0)
  1862. return ret;
  1863. i915_gem_object_flush_gtt_write_domain(obj);
  1864. /* If we're already fully in the CPU read domain, we're done. */
  1865. if (obj_priv->page_cpu_valid == NULL &&
  1866. (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0)
  1867. return 0;
  1868. /* Otherwise, create/clear the per-page CPU read domain flag if we're
  1869. * newly adding I915_GEM_DOMAIN_CPU
  1870. */
  1871. if (obj_priv->page_cpu_valid == NULL) {
  1872. obj_priv->page_cpu_valid = drm_calloc(1, obj->size / PAGE_SIZE,
  1873. DRM_MEM_DRIVER);
  1874. if (obj_priv->page_cpu_valid == NULL)
  1875. return -ENOMEM;
  1876. } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0)
  1877. memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE);
  1878. /* Flush the cache on any pages that are still invalid from the CPU's
  1879. * perspective.
  1880. */
  1881. for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
  1882. i++) {
  1883. if (obj_priv->page_cpu_valid[i])
  1884. continue;
  1885. drm_clflush_pages(obj_priv->page_list + i, 1);
  1886. obj_priv->page_cpu_valid[i] = 1;
  1887. }
  1888. /* It should now be out of any other write domains, and we can update
  1889. * the domain values for our changes.
  1890. */
  1891. BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
  1892. obj->read_domains |= I915_GEM_DOMAIN_CPU;
  1893. return 0;
  1894. }
  1895. /**
  1896. * Pin an object to the GTT and evaluate the relocations landing in it.
  1897. */
  1898. static int
  1899. i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
  1900. struct drm_file *file_priv,
  1901. struct drm_i915_gem_exec_object *entry)
  1902. {
  1903. struct drm_device *dev = obj->dev;
  1904. drm_i915_private_t *dev_priv = dev->dev_private;
  1905. struct drm_i915_gem_relocation_entry reloc;
  1906. struct drm_i915_gem_relocation_entry __user *relocs;
  1907. struct drm_i915_gem_object *obj_priv = obj->driver_private;
  1908. int i, ret;
  1909. void __iomem *reloc_page;
  1910. /* Choose the GTT offset for our buffer and put it there. */
  1911. ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
  1912. if (ret)
  1913. return ret;
  1914. entry->offset = obj_priv->gtt_offset;
  1915. relocs = (struct drm_i915_gem_relocation_entry __user *)
  1916. (uintptr_t) entry->relocs_ptr;
  1917. /* Apply the relocations, using the GTT aperture to avoid cache
  1918. * flushing requirements.
  1919. */
  1920. for (i = 0; i < entry->relocation_count; i++) {
  1921. struct drm_gem_object *target_obj;
  1922. struct drm_i915_gem_object *target_obj_priv;
  1923. uint32_t reloc_val, reloc_offset;
  1924. uint32_t __iomem *reloc_entry;
  1925. ret = copy_from_user(&reloc, relocs + i, sizeof(reloc));
  1926. if (ret != 0) {
  1927. i915_gem_object_unpin(obj);
  1928. return ret;
  1929. }
  1930. target_obj = drm_gem_object_lookup(obj->dev, file_priv,
  1931. reloc.target_handle);
  1932. if (target_obj == NULL) {
  1933. i915_gem_object_unpin(obj);
  1934. return -EBADF;
  1935. }
  1936. target_obj_priv = target_obj->driver_private;
  1937. /* The target buffer should have appeared before us in the
  1938. * exec_object list, so it should have a GTT space bound by now.
  1939. */
  1940. if (target_obj_priv->gtt_space == NULL) {
  1941. DRM_ERROR("No GTT space found for object %d\n",
  1942. reloc.target_handle);
  1943. drm_gem_object_unreference(target_obj);
  1944. i915_gem_object_unpin(obj);
  1945. return -EINVAL;
  1946. }
  1947. if (reloc.offset > obj->size - 4) {
  1948. DRM_ERROR("Relocation beyond object bounds: "
  1949. "obj %p target %d offset %d size %d.\n",
  1950. obj, reloc.target_handle,
  1951. (int) reloc.offset, (int) obj->size);
  1952. drm_gem_object_unreference(target_obj);
  1953. i915_gem_object_unpin(obj);
  1954. return -EINVAL;
  1955. }
  1956. if (reloc.offset & 3) {
  1957. DRM_ERROR("Relocation not 4-byte aligned: "
  1958. "obj %p target %d offset %d.\n",
  1959. obj, reloc.target_handle,
  1960. (int) reloc.offset);
  1961. drm_gem_object_unreference(target_obj);
  1962. i915_gem_object_unpin(obj);
  1963. return -EINVAL;
  1964. }
  1965. if (reloc.write_domain & I915_GEM_DOMAIN_CPU ||
  1966. reloc.read_domains & I915_GEM_DOMAIN_CPU) {
  1967. DRM_ERROR("reloc with read/write CPU domains: "
  1968. "obj %p target %d offset %d "
  1969. "read %08x write %08x",
  1970. obj, reloc.target_handle,
  1971. (int) reloc.offset,
  1972. reloc.read_domains,
  1973. reloc.write_domain);
  1974. drm_gem_object_unreference(target_obj);
  1975. i915_gem_object_unpin(obj);
  1976. return -EINVAL;
  1977. }
  1978. if (reloc.write_domain && target_obj->pending_write_domain &&
  1979. reloc.write_domain != target_obj->pending_write_domain) {
  1980. DRM_ERROR("Write domain conflict: "
  1981. "obj %p target %d offset %d "
  1982. "new %08x old %08x\n",
  1983. obj, reloc.target_handle,
  1984. (int) reloc.offset,
  1985. reloc.write_domain,
  1986. target_obj->pending_write_domain);
  1987. drm_gem_object_unreference(target_obj);
  1988. i915_gem_object_unpin(obj);
  1989. return -EINVAL;
  1990. }
  1991. #if WATCH_RELOC
  1992. DRM_INFO("%s: obj %p offset %08x target %d "
  1993. "read %08x write %08x gtt %08x "
  1994. "presumed %08x delta %08x\n",
  1995. __func__,
  1996. obj,
  1997. (int) reloc.offset,
  1998. (int) reloc.target_handle,
  1999. (int) reloc.read_domains,
  2000. (int) reloc.write_domain,
  2001. (int) target_obj_priv->gtt_offset,
  2002. (int) reloc.presumed_offset,
  2003. reloc.delta);
  2004. #endif
  2005. target_obj->pending_read_domains |= reloc.read_domains;
  2006. target_obj->pending_write_domain |= reloc.write_domain;
  2007. /* If the relocation already has the right value in it, no
  2008. * more work needs to be done.
  2009. */
  2010. if (target_obj_priv->gtt_offset == reloc.presumed_offset) {
  2011. drm_gem_object_unreference(target_obj);
  2012. continue;
  2013. }
  2014. ret = i915_gem_object_set_to_gtt_domain(obj, 1);
  2015. if (ret != 0) {
  2016. drm_gem_object_unreference(target_obj);
  2017. i915_gem_object_unpin(obj);
  2018. return -EINVAL;
  2019. }
  2020. /* Map the page containing the relocation we're going to
  2021. * perform.
  2022. */
  2023. reloc_offset = obj_priv->gtt_offset + reloc.offset;
  2024. reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
  2025. (reloc_offset &
  2026. ~(PAGE_SIZE - 1)));
  2027. reloc_entry = (uint32_t __iomem *)(reloc_page +
  2028. (reloc_offset & (PAGE_SIZE - 1)));
  2029. reloc_val = target_obj_priv->gtt_offset + reloc.delta;
  2030. #if WATCH_BUF
  2031. DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
  2032. obj, (unsigned int) reloc.offset,
  2033. readl(reloc_entry), reloc_val);
  2034. #endif
  2035. writel(reloc_val, reloc_entry);
  2036. io_mapping_unmap_atomic(reloc_page);
  2037. /* Write the updated presumed offset for this entry back out
  2038. * to the user.
  2039. */
  2040. reloc.presumed_offset = target_obj_priv->gtt_offset;
  2041. ret = copy_to_user(relocs + i, &reloc, sizeof(reloc));
  2042. if (ret != 0) {
  2043. drm_gem_object_unreference(target_obj);
  2044. i915_gem_object_unpin(obj);
  2045. return ret;
  2046. }
  2047. drm_gem_object_unreference(target_obj);
  2048. }
  2049. #if WATCH_BUF
  2050. if (0)
  2051. i915_gem_dump_object(obj, 128, __func__, ~0);
  2052. #endif
  2053. return 0;
  2054. }
  2055. /** Dispatch a batchbuffer to the ring
  2056. */
  2057. static int
  2058. i915_dispatch_gem_execbuffer(struct drm_device *dev,
  2059. struct drm_i915_gem_execbuffer *exec,
  2060. uint64_t exec_offset)
  2061. {
  2062. drm_i915_private_t *dev_priv = dev->dev_private;
  2063. struct drm_clip_rect __user *boxes = (struct drm_clip_rect __user *)
  2064. (uintptr_t) exec->cliprects_ptr;
  2065. int nbox = exec->num_cliprects;
  2066. int i = 0, count;
  2067. uint32_t exec_start, exec_len;
  2068. RING_LOCALS;
  2069. exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
  2070. exec_len = (uint32_t) exec->batch_len;
  2071. if ((exec_start | exec_len) & 0x7) {
  2072. DRM_ERROR("alignment\n");
  2073. return -EINVAL;
  2074. }
  2075. if (!exec_start)
  2076. return -EINVAL;
  2077. count = nbox ? nbox : 1;
  2078. for (i = 0; i < count; i++) {
  2079. if (i < nbox) {
  2080. int ret = i915_emit_box(dev, boxes, i,
  2081. exec->DR1, exec->DR4);
  2082. if (ret)
  2083. return ret;
  2084. }
  2085. if (IS_I830(dev) || IS_845G(dev)) {
  2086. BEGIN_LP_RING(4);
  2087. OUT_RING(MI_BATCH_BUFFER);
  2088. OUT_RING(exec_start | MI_BATCH_NON_SECURE);
  2089. OUT_RING(exec_start + exec_len - 4);
  2090. OUT_RING(0);
  2091. ADVANCE_LP_RING();
  2092. } else {
  2093. BEGIN_LP_RING(2);
  2094. if (IS_I965G(dev)) {
  2095. OUT_RING(MI_BATCH_BUFFER_START |
  2096. (2 << 6) |
  2097. MI_BATCH_NON_SECURE_I965);
  2098. OUT_RING(exec_start);
  2099. } else {
  2100. OUT_RING(MI_BATCH_BUFFER_START |
  2101. (2 << 6));
  2102. OUT_RING(exec_start | MI_BATCH_NON_SECURE);
  2103. }
  2104. ADVANCE_LP_RING();
  2105. }
  2106. }
  2107. /* XXX breadcrumb */
  2108. return 0;
  2109. }
  2110. /* Throttle our rendering by waiting until the ring has completed our requests
  2111. * emitted over 20 msec ago.
  2112. *
  2113. * This should get us reasonable parallelism between CPU and GPU but also
  2114. * relatively low latency when blocking on a particular request to finish.
  2115. */
  2116. static int
  2117. i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv)
  2118. {
  2119. struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
  2120. int ret = 0;
  2121. uint32_t seqno;
  2122. mutex_lock(&dev->struct_mutex);
  2123. seqno = i915_file_priv->mm.last_gem_throttle_seqno;
  2124. i915_file_priv->mm.last_gem_throttle_seqno =
  2125. i915_file_priv->mm.last_gem_seqno;
  2126. if (seqno)
  2127. ret = i915_wait_request(dev, seqno);
  2128. mutex_unlock(&dev->struct_mutex);
  2129. return ret;
  2130. }
  2131. int
  2132. i915_gem_execbuffer(struct drm_device *dev, void *data,
  2133. struct drm_file *file_priv)
  2134. {
  2135. drm_i915_private_t *dev_priv = dev->dev_private;
  2136. struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
  2137. struct drm_i915_gem_execbuffer *args = data;
  2138. struct drm_i915_gem_exec_object *exec_list = NULL;
  2139. struct drm_gem_object **object_list = NULL;
  2140. struct drm_gem_object *batch_obj;
  2141. int ret, i, pinned = 0;
  2142. uint64_t exec_offset;
  2143. uint32_t seqno, flush_domains;
  2144. int pin_tries;
  2145. #if WATCH_EXEC
  2146. DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
  2147. (int) args->buffers_ptr, args->buffer_count, args->batch_len);
  2148. #endif
  2149. if (args->buffer_count < 1) {
  2150. DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
  2151. return -EINVAL;
  2152. }
  2153. /* Copy in the exec list from userland */
  2154. exec_list = drm_calloc(sizeof(*exec_list), args->buffer_count,
  2155. DRM_MEM_DRIVER);
  2156. object_list = drm_calloc(sizeof(*object_list), args->buffer_count,
  2157. DRM_MEM_DRIVER);
  2158. if (exec_list == NULL || object_list == NULL) {
  2159. DRM_ERROR("Failed to allocate exec or object list "
  2160. "for %d buffers\n",
  2161. args->buffer_count);
  2162. ret = -ENOMEM;
  2163. goto pre_mutex_err;
  2164. }
  2165. ret = copy_from_user(exec_list,
  2166. (struct drm_i915_relocation_entry __user *)
  2167. (uintptr_t) args->buffers_ptr,
  2168. sizeof(*exec_list) * args->buffer_count);
  2169. if (ret != 0) {
  2170. DRM_ERROR("copy %d exec entries failed %d\n",
  2171. args->buffer_count, ret);
  2172. goto pre_mutex_err;
  2173. }
  2174. mutex_lock(&dev->struct_mutex);
  2175. i915_verify_inactive(dev, __FILE__, __LINE__);
  2176. if (dev_priv->mm.wedged) {
  2177. DRM_ERROR("Execbuf while wedged\n");
  2178. mutex_unlock(&dev->struct_mutex);
  2179. ret = -EIO;
  2180. goto pre_mutex_err;
  2181. }
  2182. if (dev_priv->mm.suspended) {
  2183. DRM_ERROR("Execbuf while VT-switched.\n");
  2184. mutex_unlock(&dev->struct_mutex);
  2185. ret = -EBUSY;
  2186. goto pre_mutex_err;
  2187. }
  2188. /* Look up object handles */
  2189. for (i = 0; i < args->buffer_count; i++) {
  2190. object_list[i] = drm_gem_object_lookup(dev, file_priv,
  2191. exec_list[i].handle);
  2192. if (object_list[i] == NULL) {
  2193. DRM_ERROR("Invalid object handle %d at index %d\n",
  2194. exec_list[i].handle, i);
  2195. ret = -EBADF;
  2196. goto err;
  2197. }
  2198. }
  2199. /* Pin and relocate */
  2200. for (pin_tries = 0; ; pin_tries++) {
  2201. ret = 0;
  2202. for (i = 0; i < args->buffer_count; i++) {
  2203. object_list[i]->pending_read_domains = 0;
  2204. object_list[i]->pending_write_domain = 0;
  2205. ret = i915_gem_object_pin_and_relocate(object_list[i],
  2206. file_priv,
  2207. &exec_list[i]);
  2208. if (ret)
  2209. break;
  2210. pinned = i + 1;
  2211. }
  2212. /* success */
  2213. if (ret == 0)
  2214. break;
  2215. /* error other than GTT full, or we've already tried again */
  2216. if (ret != -ENOMEM || pin_tries >= 1) {
  2217. if (ret != -ERESTARTSYS)
  2218. DRM_ERROR("Failed to pin buffers %d\n", ret);
  2219. goto err;
  2220. }
  2221. /* unpin all of our buffers */
  2222. for (i = 0; i < pinned; i++)
  2223. i915_gem_object_unpin(object_list[i]);
  2224. pinned = 0;
  2225. /* evict everyone we can from the aperture */
  2226. ret = i915_gem_evict_everything(dev);
  2227. if (ret)
  2228. goto err;
  2229. }
  2230. /* Set the pending read domains for the batch buffer to COMMAND */
  2231. batch_obj = object_list[args->buffer_count-1];
  2232. batch_obj->pending_read_domains = I915_GEM_DOMAIN_COMMAND;
  2233. batch_obj->pending_write_domain = 0;
  2234. i915_verify_inactive(dev, __FILE__, __LINE__);
  2235. /* Zero the global flush/invalidate flags. These
  2236. * will be modified as new domains are computed
  2237. * for each object
  2238. */
  2239. dev->invalidate_domains = 0;
  2240. dev->flush_domains = 0;
  2241. for (i = 0; i < args->buffer_count; i++) {
  2242. struct drm_gem_object *obj = object_list[i];
  2243. /* Compute new gpu domains and update invalidate/flush */
  2244. i915_gem_object_set_to_gpu_domain(obj);
  2245. }
  2246. i915_verify_inactive(dev, __FILE__, __LINE__);
  2247. if (dev->invalidate_domains | dev->flush_domains) {
  2248. #if WATCH_EXEC
  2249. DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
  2250. __func__,
  2251. dev->invalidate_domains,
  2252. dev->flush_domains);
  2253. #endif
  2254. i915_gem_flush(dev,
  2255. dev->invalidate_domains,
  2256. dev->flush_domains);
  2257. if (dev->flush_domains)
  2258. (void)i915_add_request(dev, dev->flush_domains);
  2259. }
  2260. for (i = 0; i < args->buffer_count; i++) {
  2261. struct drm_gem_object *obj = object_list[i];
  2262. obj->write_domain = obj->pending_write_domain;
  2263. }
  2264. i915_verify_inactive(dev, __FILE__, __LINE__);
  2265. #if WATCH_COHERENCY
  2266. for (i = 0; i < args->buffer_count; i++) {
  2267. i915_gem_object_check_coherency(object_list[i],
  2268. exec_list[i].handle);
  2269. }
  2270. #endif
  2271. exec_offset = exec_list[args->buffer_count - 1].offset;
  2272. #if WATCH_EXEC
  2273. i915_gem_dump_object(object_list[args->buffer_count - 1],
  2274. args->batch_len,
  2275. __func__,
  2276. ~0);
  2277. #endif
  2278. /* Exec the batchbuffer */
  2279. ret = i915_dispatch_gem_execbuffer(dev, args, exec_offset);
  2280. if (ret) {
  2281. DRM_ERROR("dispatch failed %d\n", ret);
  2282. goto err;
  2283. }
  2284. /*
  2285. * Ensure that the commands in the batch buffer are
  2286. * finished before the interrupt fires
  2287. */
  2288. flush_domains = i915_retire_commands(dev);
  2289. i915_verify_inactive(dev, __FILE__, __LINE__);
  2290. /*
  2291. * Get a seqno representing the execution of the current buffer,
  2292. * which we can wait on. We would like to mitigate these interrupts,
  2293. * likely by only creating seqnos occasionally (so that we have
  2294. * *some* interrupts representing completion of buffers that we can
  2295. * wait on when trying to clear up gtt space).
  2296. */
  2297. seqno = i915_add_request(dev, flush_domains);
  2298. BUG_ON(seqno == 0);
  2299. i915_file_priv->mm.last_gem_seqno = seqno;
  2300. for (i = 0; i < args->buffer_count; i++) {
  2301. struct drm_gem_object *obj = object_list[i];
  2302. i915_gem_object_move_to_active(obj, seqno);
  2303. #if WATCH_LRU
  2304. DRM_INFO("%s: move to exec list %p\n", __func__, obj);
  2305. #endif
  2306. }
  2307. #if WATCH_LRU
  2308. i915_dump_lru(dev, __func__);
  2309. #endif
  2310. i915_verify_inactive(dev, __FILE__, __LINE__);
  2311. err:
  2312. for (i = 0; i < pinned; i++)
  2313. i915_gem_object_unpin(object_list[i]);
  2314. for (i = 0; i < args->buffer_count; i++)
  2315. drm_gem_object_unreference(object_list[i]);
  2316. mutex_unlock(&dev->struct_mutex);
  2317. if (!ret) {
  2318. /* Copy the new buffer offsets back to the user's exec list. */
  2319. ret = copy_to_user((struct drm_i915_relocation_entry __user *)
  2320. (uintptr_t) args->buffers_ptr,
  2321. exec_list,
  2322. sizeof(*exec_list) * args->buffer_count);
  2323. if (ret)
  2324. DRM_ERROR("failed to copy %d exec entries "
  2325. "back to user (%d)\n",
  2326. args->buffer_count, ret);
  2327. }
  2328. pre_mutex_err:
  2329. drm_free(object_list, sizeof(*object_list) * args->buffer_count,
  2330. DRM_MEM_DRIVER);
  2331. drm_free(exec_list, sizeof(*exec_list) * args->buffer_count,
  2332. DRM_MEM_DRIVER);
  2333. return ret;
  2334. }
  2335. int
  2336. i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
  2337. {
  2338. struct drm_device *dev = obj->dev;
  2339. struct drm_i915_gem_object *obj_priv = obj->driver_private;
  2340. int ret;
  2341. i915_verify_inactive(dev, __FILE__, __LINE__);
  2342. if (obj_priv->gtt_space == NULL) {
  2343. ret = i915_gem_object_bind_to_gtt(obj, alignment);
  2344. if (ret != 0) {
  2345. if (ret != -EBUSY && ret != -ERESTARTSYS)
  2346. DRM_ERROR("Failure to bind: %d", ret);
  2347. return ret;
  2348. }
  2349. /*
  2350. * Pre-965 chips need a fence register set up in order to
  2351. * properly handle tiled surfaces.
  2352. */
  2353. if (!IS_I965G(dev) &&
  2354. obj_priv->fence_reg == I915_FENCE_REG_NONE &&
  2355. obj_priv->tiling_mode != I915_TILING_NONE)
  2356. i915_gem_object_get_fence_reg(obj, true);
  2357. }
  2358. obj_priv->pin_count++;
  2359. /* If the object is not active and not pending a flush,
  2360. * remove it from the inactive list
  2361. */
  2362. if (obj_priv->pin_count == 1) {
  2363. atomic_inc(&dev->pin_count);
  2364. atomic_add(obj->size, &dev->pin_memory);
  2365. if (!obj_priv->active &&
  2366. (obj->write_domain & ~(I915_GEM_DOMAIN_CPU |
  2367. I915_GEM_DOMAIN_GTT)) == 0 &&
  2368. !list_empty(&obj_priv->list))
  2369. list_del_init(&obj_priv->list);
  2370. }
  2371. i915_verify_inactive(dev, __FILE__, __LINE__);
  2372. return 0;
  2373. }
  2374. void
  2375. i915_gem_object_unpin(struct drm_gem_object *obj)
  2376. {
  2377. struct drm_device *dev = obj->dev;
  2378. drm_i915_private_t *dev_priv = dev->dev_private;
  2379. struct drm_i915_gem_object *obj_priv = obj->driver_private;
  2380. i915_verify_inactive(dev, __FILE__, __LINE__);
  2381. obj_priv->pin_count--;
  2382. BUG_ON(obj_priv->pin_count < 0);
  2383. BUG_ON(obj_priv->gtt_space == NULL);
  2384. /* If the object is no longer pinned, and is
  2385. * neither active nor being flushed, then stick it on
  2386. * the inactive list
  2387. */
  2388. if (obj_priv->pin_count == 0) {
  2389. if (!obj_priv->active &&
  2390. (obj->write_domain & ~(I915_GEM_DOMAIN_CPU |
  2391. I915_GEM_DOMAIN_GTT)) == 0)
  2392. list_move_tail(&obj_priv->list,
  2393. &dev_priv->mm.inactive_list);
  2394. atomic_dec(&dev->pin_count);
  2395. atomic_sub(obj->size, &dev->pin_memory);
  2396. }
  2397. i915_verify_inactive(dev, __FILE__, __LINE__);
  2398. }
  2399. int
  2400. i915_gem_pin_ioctl(struct drm_device *dev, void *data,
  2401. struct drm_file *file_priv)
  2402. {
  2403. struct drm_i915_gem_pin *args = data;
  2404. struct drm_gem_object *obj;
  2405. struct drm_i915_gem_object *obj_priv;
  2406. int ret;
  2407. mutex_lock(&dev->struct_mutex);
  2408. obj = drm_gem_object_lookup(dev, file_priv, args->handle);
  2409. if (obj == NULL) {
  2410. DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
  2411. args->handle);
  2412. mutex_unlock(&dev->struct_mutex);
  2413. return -EBADF;
  2414. }
  2415. obj_priv = obj->driver_private;
  2416. if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) {
  2417. DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
  2418. args->handle);
  2419. drm_gem_object_unreference(obj);
  2420. mutex_unlock(&dev->struct_mutex);
  2421. return -EINVAL;
  2422. }
  2423. obj_priv->user_pin_count++;
  2424. obj_priv->pin_filp = file_priv;
  2425. if (obj_priv->user_pin_count == 1) {
  2426. ret = i915_gem_object_pin(obj, args->alignment);
  2427. if (ret != 0) {
  2428. drm_gem_object_unreference(obj);
  2429. mutex_unlock(&dev->struct_mutex);
  2430. return ret;
  2431. }
  2432. }
  2433. /* XXX - flush the CPU caches for pinned objects
  2434. * as the X server doesn't manage domains yet
  2435. */
  2436. i915_gem_object_flush_cpu_write_domain(obj);
  2437. args->offset = obj_priv->gtt_offset;
  2438. drm_gem_object_unreference(obj);
  2439. mutex_unlock(&dev->struct_mutex);
  2440. return 0;
  2441. }
  2442. int
  2443. i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
  2444. struct drm_file *file_priv)
  2445. {
  2446. struct drm_i915_gem_pin *args = data;
  2447. struct drm_gem_object *obj;
  2448. struct drm_i915_gem_object *obj_priv;
  2449. mutex_lock(&dev->struct_mutex);
  2450. obj = drm_gem_object_lookup(dev, file_priv, args->handle);
  2451. if (obj == NULL) {
  2452. DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
  2453. args->handle);
  2454. mutex_unlock(&dev->struct_mutex);
  2455. return -EBADF;
  2456. }
  2457. obj_priv = obj->driver_private;
  2458. if (obj_priv->pin_filp != file_priv) {
  2459. DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
  2460. args->handle);
  2461. drm_gem_object_unreference(obj);
  2462. mutex_unlock(&dev->struct_mutex);
  2463. return -EINVAL;
  2464. }
  2465. obj_priv->user_pin_count--;
  2466. if (obj_priv->user_pin_count == 0) {
  2467. obj_priv->pin_filp = NULL;
  2468. i915_gem_object_unpin(obj);
  2469. }
  2470. drm_gem_object_unreference(obj);
  2471. mutex_unlock(&dev->struct_mutex);
  2472. return 0;
  2473. }
  2474. int
  2475. i915_gem_busy_ioctl(struct drm_device *dev, void *data,
  2476. struct drm_file *file_priv)
  2477. {
  2478. struct drm_i915_gem_busy *args = data;
  2479. struct drm_gem_object *obj;
  2480. struct drm_i915_gem_object *obj_priv;
  2481. mutex_lock(&dev->struct_mutex);
  2482. obj = drm_gem_object_lookup(dev, file_priv, args->handle);
  2483. if (obj == NULL) {
  2484. DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
  2485. args->handle);
  2486. mutex_unlock(&dev->struct_mutex);
  2487. return -EBADF;
  2488. }
  2489. /* Update the active list for the hardware's current position.
  2490. * Otherwise this only updates on a delayed timer or when irqs are
  2491. * actually unmasked, and our working set ends up being larger than
  2492. * required.
  2493. */
  2494. i915_gem_retire_requests(dev);
  2495. obj_priv = obj->driver_private;
  2496. /* Don't count being on the flushing list against the object being
  2497. * done. Otherwise, a buffer left on the flushing list but not getting
  2498. * flushed (because nobody's flushing that domain) won't ever return
  2499. * unbusy and get reused by libdrm's bo cache. The other expected
  2500. * consumer of this interface, OpenGL's occlusion queries, also specs
  2501. * that the objects get unbusy "eventually" without any interference.
  2502. */
  2503. args->busy = obj_priv->active && obj_priv->last_rendering_seqno != 0;
  2504. drm_gem_object_unreference(obj);
  2505. mutex_unlock(&dev->struct_mutex);
  2506. return 0;
  2507. }
  2508. int
  2509. i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
  2510. struct drm_file *file_priv)
  2511. {
  2512. return i915_gem_ring_throttle(dev, file_priv);
  2513. }
  2514. int i915_gem_init_object(struct drm_gem_object *obj)
  2515. {
  2516. struct drm_i915_gem_object *obj_priv;
  2517. obj_priv = drm_calloc(1, sizeof(*obj_priv), DRM_MEM_DRIVER);
  2518. if (obj_priv == NULL)
  2519. return -ENOMEM;
  2520. /*
  2521. * We've just allocated pages from the kernel,
  2522. * so they've just been written by the CPU with
  2523. * zeros. They'll need to be clflushed before we
  2524. * use them with the GPU.
  2525. */
  2526. obj->write_domain = I915_GEM_DOMAIN_CPU;
  2527. obj->read_domains = I915_GEM_DOMAIN_CPU;
  2528. obj_priv->agp_type = AGP_USER_MEMORY;
  2529. obj->driver_private = obj_priv;
  2530. obj_priv->obj = obj;
  2531. obj_priv->fence_reg = I915_FENCE_REG_NONE;
  2532. INIT_LIST_HEAD(&obj_priv->list);
  2533. return 0;
  2534. }
  2535. void i915_gem_free_object(struct drm_gem_object *obj)
  2536. {
  2537. struct drm_device *dev = obj->dev;
  2538. struct drm_i915_gem_object *obj_priv = obj->driver_private;
  2539. while (obj_priv->pin_count > 0)
  2540. i915_gem_object_unpin(obj);
  2541. if (obj_priv->phys_obj)
  2542. i915_gem_detach_phys_object(dev, obj);
  2543. i915_gem_object_unbind(obj);
  2544. i915_gem_free_mmap_offset(obj);
  2545. drm_free(obj_priv->page_cpu_valid, 1, DRM_MEM_DRIVER);
  2546. drm_free(obj->driver_private, 1, DRM_MEM_DRIVER);
  2547. }
  2548. /** Unbinds all objects that are on the given buffer list. */
  2549. static int
  2550. i915_gem_evict_from_list(struct drm_device *dev, struct list_head *head)
  2551. {
  2552. struct drm_gem_object *obj;
  2553. struct drm_i915_gem_object *obj_priv;
  2554. int ret;
  2555. while (!list_empty(head)) {
  2556. obj_priv = list_first_entry(head,
  2557. struct drm_i915_gem_object,
  2558. list);
  2559. obj = obj_priv->obj;
  2560. if (obj_priv->pin_count != 0) {
  2561. DRM_ERROR("Pinned object in unbind list\n");
  2562. mutex_unlock(&dev->struct_mutex);
  2563. return -EINVAL;
  2564. }
  2565. ret = i915_gem_object_unbind(obj);
  2566. if (ret != 0) {
  2567. DRM_ERROR("Error unbinding object in LeaveVT: %d\n",
  2568. ret);
  2569. mutex_unlock(&dev->struct_mutex);
  2570. return ret;
  2571. }
  2572. }
  2573. return 0;
  2574. }
  2575. int
  2576. i915_gem_idle(struct drm_device *dev)
  2577. {
  2578. drm_i915_private_t *dev_priv = dev->dev_private;
  2579. uint32_t seqno, cur_seqno, last_seqno;
  2580. int stuck, ret;
  2581. mutex_lock(&dev->struct_mutex);
  2582. if (dev_priv->mm.suspended || dev_priv->ring.ring_obj == NULL) {
  2583. mutex_unlock(&dev->struct_mutex);
  2584. return 0;
  2585. }
  2586. /* Hack! Don't let anybody do execbuf while we don't control the chip.
  2587. * We need to replace this with a semaphore, or something.
  2588. */
  2589. dev_priv->mm.suspended = 1;
  2590. /* Cancel the retire work handler, wait for it to finish if running
  2591. */
  2592. mutex_unlock(&dev->struct_mutex);
  2593. cancel_delayed_work_sync(&dev_priv->mm.retire_work);
  2594. mutex_lock(&dev->struct_mutex);
  2595. i915_kernel_lost_context(dev);
  2596. /* Flush the GPU along with all non-CPU write domains
  2597. */
  2598. i915_gem_flush(dev, ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT),
  2599. ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT));
  2600. seqno = i915_add_request(dev, ~I915_GEM_DOMAIN_CPU);
  2601. if (seqno == 0) {
  2602. mutex_unlock(&dev->struct_mutex);
  2603. return -ENOMEM;
  2604. }
  2605. dev_priv->mm.waiting_gem_seqno = seqno;
  2606. last_seqno = 0;
  2607. stuck = 0;
  2608. for (;;) {
  2609. cur_seqno = i915_get_gem_seqno(dev);
  2610. if (i915_seqno_passed(cur_seqno, seqno))
  2611. break;
  2612. if (last_seqno == cur_seqno) {
  2613. if (stuck++ > 100) {
  2614. DRM_ERROR("hardware wedged\n");
  2615. dev_priv->mm.wedged = 1;
  2616. DRM_WAKEUP(&dev_priv->irq_queue);
  2617. break;
  2618. }
  2619. }
  2620. msleep(10);
  2621. last_seqno = cur_seqno;
  2622. }
  2623. dev_priv->mm.waiting_gem_seqno = 0;
  2624. i915_gem_retire_requests(dev);
  2625. if (!dev_priv->mm.wedged) {
  2626. /* Active and flushing should now be empty as we've
  2627. * waited for a sequence higher than any pending execbuffer
  2628. */
  2629. WARN_ON(!list_empty(&dev_priv->mm.active_list));
  2630. WARN_ON(!list_empty(&dev_priv->mm.flushing_list));
  2631. /* Request should now be empty as we've also waited
  2632. * for the last request in the list
  2633. */
  2634. WARN_ON(!list_empty(&dev_priv->mm.request_list));
  2635. }
  2636. /* Empty the active and flushing lists to inactive. If there's
  2637. * anything left at this point, it means that we're wedged and
  2638. * nothing good's going to happen by leaving them there. So strip
  2639. * the GPU domains and just stuff them onto inactive.
  2640. */
  2641. while (!list_empty(&dev_priv->mm.active_list)) {
  2642. struct drm_i915_gem_object *obj_priv;
  2643. obj_priv = list_first_entry(&dev_priv->mm.active_list,
  2644. struct drm_i915_gem_object,
  2645. list);
  2646. obj_priv->obj->write_domain &= ~I915_GEM_GPU_DOMAINS;
  2647. i915_gem_object_move_to_inactive(obj_priv->obj);
  2648. }
  2649. while (!list_empty(&dev_priv->mm.flushing_list)) {
  2650. struct drm_i915_gem_object *obj_priv;
  2651. obj_priv = list_first_entry(&dev_priv->mm.flushing_list,
  2652. struct drm_i915_gem_object,
  2653. list);
  2654. obj_priv->obj->write_domain &= ~I915_GEM_GPU_DOMAINS;
  2655. i915_gem_object_move_to_inactive(obj_priv->obj);
  2656. }
  2657. /* Move all inactive buffers out of the GTT. */
  2658. ret = i915_gem_evict_from_list(dev, &dev_priv->mm.inactive_list);
  2659. WARN_ON(!list_empty(&dev_priv->mm.inactive_list));
  2660. if (ret) {
  2661. mutex_unlock(&dev->struct_mutex);
  2662. return ret;
  2663. }
  2664. i915_gem_cleanup_ringbuffer(dev);
  2665. mutex_unlock(&dev->struct_mutex);
  2666. return 0;
  2667. }
  2668. static int
  2669. i915_gem_init_hws(struct drm_device *dev)
  2670. {
  2671. drm_i915_private_t *dev_priv = dev->dev_private;
  2672. struct drm_gem_object *obj;
  2673. struct drm_i915_gem_object *obj_priv;
  2674. int ret;
  2675. /* If we need a physical address for the status page, it's already
  2676. * initialized at driver load time.
  2677. */
  2678. if (!I915_NEED_GFX_HWS(dev))
  2679. return 0;
  2680. obj = drm_gem_object_alloc(dev, 4096);
  2681. if (obj == NULL) {
  2682. DRM_ERROR("Failed to allocate status page\n");
  2683. return -ENOMEM;
  2684. }
  2685. obj_priv = obj->driver_private;
  2686. obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
  2687. ret = i915_gem_object_pin(obj, 4096);
  2688. if (ret != 0) {
  2689. drm_gem_object_unreference(obj);
  2690. return ret;
  2691. }
  2692. dev_priv->status_gfx_addr = obj_priv->gtt_offset;
  2693. dev_priv->hw_status_page = kmap(obj_priv->page_list[0]);
  2694. if (dev_priv->hw_status_page == NULL) {
  2695. DRM_ERROR("Failed to map status page.\n");
  2696. memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
  2697. i915_gem_object_unpin(obj);
  2698. drm_gem_object_unreference(obj);
  2699. return -EINVAL;
  2700. }
  2701. dev_priv->hws_obj = obj;
  2702. memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
  2703. I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
  2704. I915_READ(HWS_PGA); /* posting read */
  2705. DRM_DEBUG("hws offset: 0x%08x\n", dev_priv->status_gfx_addr);
  2706. return 0;
  2707. }
  2708. static void
  2709. i915_gem_cleanup_hws(struct drm_device *dev)
  2710. {
  2711. drm_i915_private_t *dev_priv = dev->dev_private;
  2712. struct drm_gem_object *obj;
  2713. struct drm_i915_gem_object *obj_priv;
  2714. if (dev_priv->hws_obj == NULL)
  2715. return;
  2716. obj = dev_priv->hws_obj;
  2717. obj_priv = obj->driver_private;
  2718. kunmap(obj_priv->page_list[0]);
  2719. i915_gem_object_unpin(obj);
  2720. drm_gem_object_unreference(obj);
  2721. dev_priv->hws_obj = NULL;
  2722. memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
  2723. dev_priv->hw_status_page = NULL;
  2724. /* Write high address into HWS_PGA when disabling. */
  2725. I915_WRITE(HWS_PGA, 0x1ffff000);
  2726. }
  2727. int
  2728. i915_gem_init_ringbuffer(struct drm_device *dev)
  2729. {
  2730. drm_i915_private_t *dev_priv = dev->dev_private;
  2731. struct drm_gem_object *obj;
  2732. struct drm_i915_gem_object *obj_priv;
  2733. drm_i915_ring_buffer_t *ring = &dev_priv->ring;
  2734. int ret;
  2735. u32 head;
  2736. ret = i915_gem_init_hws(dev);
  2737. if (ret != 0)
  2738. return ret;
  2739. obj = drm_gem_object_alloc(dev, 128 * 1024);
  2740. if (obj == NULL) {
  2741. DRM_ERROR("Failed to allocate ringbuffer\n");
  2742. i915_gem_cleanup_hws(dev);
  2743. return -ENOMEM;
  2744. }
  2745. obj_priv = obj->driver_private;
  2746. ret = i915_gem_object_pin(obj, 4096);
  2747. if (ret != 0) {
  2748. drm_gem_object_unreference(obj);
  2749. i915_gem_cleanup_hws(dev);
  2750. return ret;
  2751. }
  2752. /* Set up the kernel mapping for the ring. */
  2753. ring->Size = obj->size;
  2754. ring->tail_mask = obj->size - 1;
  2755. ring->map.offset = dev->agp->base + obj_priv->gtt_offset;
  2756. ring->map.size = obj->size;
  2757. ring->map.type = 0;
  2758. ring->map.flags = 0;
  2759. ring->map.mtrr = 0;
  2760. drm_core_ioremap_wc(&ring->map, dev);
  2761. if (ring->map.handle == NULL) {
  2762. DRM_ERROR("Failed to map ringbuffer.\n");
  2763. memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
  2764. i915_gem_object_unpin(obj);
  2765. drm_gem_object_unreference(obj);
  2766. i915_gem_cleanup_hws(dev);
  2767. return -EINVAL;
  2768. }
  2769. ring->ring_obj = obj;
  2770. ring->virtual_start = ring->map.handle;
  2771. /* Stop the ring if it's running. */
  2772. I915_WRITE(PRB0_CTL, 0);
  2773. I915_WRITE(PRB0_TAIL, 0);
  2774. I915_WRITE(PRB0_HEAD, 0);
  2775. /* Initialize the ring. */
  2776. I915_WRITE(PRB0_START, obj_priv->gtt_offset);
  2777. head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
  2778. /* G45 ring initialization fails to reset head to zero */
  2779. if (head != 0) {
  2780. DRM_ERROR("Ring head not reset to zero "
  2781. "ctl %08x head %08x tail %08x start %08x\n",
  2782. I915_READ(PRB0_CTL),
  2783. I915_READ(PRB0_HEAD),
  2784. I915_READ(PRB0_TAIL),
  2785. I915_READ(PRB0_START));
  2786. I915_WRITE(PRB0_HEAD, 0);
  2787. DRM_ERROR("Ring head forced to zero "
  2788. "ctl %08x head %08x tail %08x start %08x\n",
  2789. I915_READ(PRB0_CTL),
  2790. I915_READ(PRB0_HEAD),
  2791. I915_READ(PRB0_TAIL),
  2792. I915_READ(PRB0_START));
  2793. }
  2794. I915_WRITE(PRB0_CTL,
  2795. ((obj->size - 4096) & RING_NR_PAGES) |
  2796. RING_NO_REPORT |
  2797. RING_VALID);
  2798. head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
  2799. /* If the head is still not zero, the ring is dead */
  2800. if (head != 0) {
  2801. DRM_ERROR("Ring initialization failed "
  2802. "ctl %08x head %08x tail %08x start %08x\n",
  2803. I915_READ(PRB0_CTL),
  2804. I915_READ(PRB0_HEAD),
  2805. I915_READ(PRB0_TAIL),
  2806. I915_READ(PRB0_START));
  2807. return -EIO;
  2808. }
  2809. /* Update our cache of the ring state */
  2810. if (!drm_core_check_feature(dev, DRIVER_MODESET))
  2811. i915_kernel_lost_context(dev);
  2812. else {
  2813. ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
  2814. ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
  2815. ring->space = ring->head - (ring->tail + 8);
  2816. if (ring->space < 0)
  2817. ring->space += ring->Size;
  2818. }
  2819. return 0;
  2820. }
  2821. void
  2822. i915_gem_cleanup_ringbuffer(struct drm_device *dev)
  2823. {
  2824. drm_i915_private_t *dev_priv = dev->dev_private;
  2825. if (dev_priv->ring.ring_obj == NULL)
  2826. return;
  2827. drm_core_ioremapfree(&dev_priv->ring.map, dev);
  2828. i915_gem_object_unpin(dev_priv->ring.ring_obj);
  2829. drm_gem_object_unreference(dev_priv->ring.ring_obj);
  2830. dev_priv->ring.ring_obj = NULL;
  2831. memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
  2832. i915_gem_cleanup_hws(dev);
  2833. }
  2834. int
  2835. i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
  2836. struct drm_file *file_priv)
  2837. {
  2838. drm_i915_private_t *dev_priv = dev->dev_private;
  2839. int ret;
  2840. if (drm_core_check_feature(dev, DRIVER_MODESET))
  2841. return 0;
  2842. if (dev_priv->mm.wedged) {
  2843. DRM_ERROR("Reenabling wedged hardware, good luck\n");
  2844. dev_priv->mm.wedged = 0;
  2845. }
  2846. mutex_lock(&dev->struct_mutex);
  2847. dev_priv->mm.suspended = 0;
  2848. ret = i915_gem_init_ringbuffer(dev);
  2849. if (ret != 0)
  2850. return ret;
  2851. BUG_ON(!list_empty(&dev_priv->mm.active_list));
  2852. BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
  2853. BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
  2854. BUG_ON(!list_empty(&dev_priv->mm.request_list));
  2855. mutex_unlock(&dev->struct_mutex);
  2856. drm_irq_install(dev);
  2857. return 0;
  2858. }
  2859. int
  2860. i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
  2861. struct drm_file *file_priv)
  2862. {
  2863. int ret;
  2864. if (drm_core_check_feature(dev, DRIVER_MODESET))
  2865. return 0;
  2866. ret = i915_gem_idle(dev);
  2867. drm_irq_uninstall(dev);
  2868. return ret;
  2869. }
  2870. void
  2871. i915_gem_lastclose(struct drm_device *dev)
  2872. {
  2873. int ret;
  2874. if (drm_core_check_feature(dev, DRIVER_MODESET))
  2875. return;
  2876. ret = i915_gem_idle(dev);
  2877. if (ret)
  2878. DRM_ERROR("failed to idle hardware: %d\n", ret);
  2879. }
  2880. void
  2881. i915_gem_load(struct drm_device *dev)
  2882. {
  2883. drm_i915_private_t *dev_priv = dev->dev_private;
  2884. INIT_LIST_HEAD(&dev_priv->mm.active_list);
  2885. INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
  2886. INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
  2887. INIT_LIST_HEAD(&dev_priv->mm.request_list);
  2888. INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
  2889. i915_gem_retire_work_handler);
  2890. dev_priv->mm.next_gem_seqno = 1;
  2891. /* Old X drivers will take 0-2 for front, back, depth buffers */
  2892. dev_priv->fence_reg_start = 3;
  2893. if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
  2894. dev_priv->num_fence_regs = 16;
  2895. else
  2896. dev_priv->num_fence_regs = 8;
  2897. i915_gem_detect_bit_6_swizzle(dev);
  2898. }
  2899. /*
  2900. * Create a physically contiguous memory object for this object
  2901. * e.g. for cursor + overlay regs
  2902. */
  2903. int i915_gem_init_phys_object(struct drm_device *dev,
  2904. int id, int size)
  2905. {
  2906. drm_i915_private_t *dev_priv = dev->dev_private;
  2907. struct drm_i915_gem_phys_object *phys_obj;
  2908. int ret;
  2909. if (dev_priv->mm.phys_objs[id - 1] || !size)
  2910. return 0;
  2911. phys_obj = drm_calloc(1, sizeof(struct drm_i915_gem_phys_object), DRM_MEM_DRIVER);
  2912. if (!phys_obj)
  2913. return -ENOMEM;
  2914. phys_obj->id = id;
  2915. phys_obj->handle = drm_pci_alloc(dev, size, 0, 0xffffffff);
  2916. if (!phys_obj->handle) {
  2917. ret = -ENOMEM;
  2918. goto kfree_obj;
  2919. }
  2920. #ifdef CONFIG_X86
  2921. set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
  2922. #endif
  2923. dev_priv->mm.phys_objs[id - 1] = phys_obj;
  2924. return 0;
  2925. kfree_obj:
  2926. drm_free(phys_obj, sizeof(struct drm_i915_gem_phys_object), DRM_MEM_DRIVER);
  2927. return ret;
  2928. }
  2929. void i915_gem_free_phys_object(struct drm_device *dev, int id)
  2930. {
  2931. drm_i915_private_t *dev_priv = dev->dev_private;
  2932. struct drm_i915_gem_phys_object *phys_obj;
  2933. if (!dev_priv->mm.phys_objs[id - 1])
  2934. return;
  2935. phys_obj = dev_priv->mm.phys_objs[id - 1];
  2936. if (phys_obj->cur_obj) {
  2937. i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
  2938. }
  2939. #ifdef CONFIG_X86
  2940. set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
  2941. #endif
  2942. drm_pci_free(dev, phys_obj->handle);
  2943. kfree(phys_obj);
  2944. dev_priv->mm.phys_objs[id - 1] = NULL;
  2945. }
  2946. void i915_gem_free_all_phys_object(struct drm_device *dev)
  2947. {
  2948. int i;
  2949. for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
  2950. i915_gem_free_phys_object(dev, i);
  2951. }
  2952. void i915_gem_detach_phys_object(struct drm_device *dev,
  2953. struct drm_gem_object *obj)
  2954. {
  2955. struct drm_i915_gem_object *obj_priv;
  2956. int i;
  2957. int ret;
  2958. int page_count;
  2959. obj_priv = obj->driver_private;
  2960. if (!obj_priv->phys_obj)
  2961. return;
  2962. ret = i915_gem_object_get_page_list(obj);
  2963. if (ret)
  2964. goto out;
  2965. page_count = obj->size / PAGE_SIZE;
  2966. for (i = 0; i < page_count; i++) {
  2967. char *dst = kmap_atomic(obj_priv->page_list[i], KM_USER0);
  2968. char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
  2969. memcpy(dst, src, PAGE_SIZE);
  2970. kunmap_atomic(dst, KM_USER0);
  2971. }
  2972. drm_clflush_pages(obj_priv->page_list, page_count);
  2973. drm_agp_chipset_flush(dev);
  2974. out:
  2975. obj_priv->phys_obj->cur_obj = NULL;
  2976. obj_priv->phys_obj = NULL;
  2977. }
  2978. int
  2979. i915_gem_attach_phys_object(struct drm_device *dev,
  2980. struct drm_gem_object *obj, int id)
  2981. {
  2982. drm_i915_private_t *dev_priv = dev->dev_private;
  2983. struct drm_i915_gem_object *obj_priv;
  2984. int ret = 0;
  2985. int page_count;
  2986. int i;
  2987. if (id > I915_MAX_PHYS_OBJECT)
  2988. return -EINVAL;
  2989. obj_priv = obj->driver_private;
  2990. if (obj_priv->phys_obj) {
  2991. if (obj_priv->phys_obj->id == id)
  2992. return 0;
  2993. i915_gem_detach_phys_object(dev, obj);
  2994. }
  2995. /* create a new object */
  2996. if (!dev_priv->mm.phys_objs[id - 1]) {
  2997. ret = i915_gem_init_phys_object(dev, id,
  2998. obj->size);
  2999. if (ret) {
  3000. DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size);
  3001. goto out;
  3002. }
  3003. }
  3004. /* bind to the object */
  3005. obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1];
  3006. obj_priv->phys_obj->cur_obj = obj;
  3007. ret = i915_gem_object_get_page_list(obj);
  3008. if (ret) {
  3009. DRM_ERROR("failed to get page list\n");
  3010. goto out;
  3011. }
  3012. page_count = obj->size / PAGE_SIZE;
  3013. for (i = 0; i < page_count; i++) {
  3014. char *src = kmap_atomic(obj_priv->page_list[i], KM_USER0);
  3015. char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
  3016. memcpy(dst, src, PAGE_SIZE);
  3017. kunmap_atomic(src, KM_USER0);
  3018. }
  3019. return 0;
  3020. out:
  3021. return ret;
  3022. }
  3023. static int
  3024. i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
  3025. struct drm_i915_gem_pwrite *args,
  3026. struct drm_file *file_priv)
  3027. {
  3028. struct drm_i915_gem_object *obj_priv = obj->driver_private;
  3029. void *obj_addr;
  3030. int ret;
  3031. char __user *user_data;
  3032. user_data = (char __user *) (uintptr_t) args->data_ptr;
  3033. obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset;
  3034. DRM_DEBUG("obj_addr %p, %lld\n", obj_addr, args->size);
  3035. ret = copy_from_user(obj_addr, user_data, args->size);
  3036. if (ret)
  3037. return -EFAULT;
  3038. drm_agp_chipset_flush(dev);
  3039. return 0;
  3040. }