main.c 58 KB

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  1. /*
  2. * Copyright (c) 2008-2011 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include <linux/nl80211.h>
  17. #include <linux/delay.h>
  18. #include "ath9k.h"
  19. #include "btcoex.h"
  20. u8 ath9k_parse_mpdudensity(u8 mpdudensity)
  21. {
  22. /*
  23. * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
  24. * 0 for no restriction
  25. * 1 for 1/4 us
  26. * 2 for 1/2 us
  27. * 3 for 1 us
  28. * 4 for 2 us
  29. * 5 for 4 us
  30. * 6 for 8 us
  31. * 7 for 16 us
  32. */
  33. switch (mpdudensity) {
  34. case 0:
  35. return 0;
  36. case 1:
  37. case 2:
  38. case 3:
  39. /* Our lower layer calculations limit our precision to
  40. 1 microsecond */
  41. return 1;
  42. case 4:
  43. return 2;
  44. case 5:
  45. return 4;
  46. case 6:
  47. return 8;
  48. case 7:
  49. return 16;
  50. default:
  51. return 0;
  52. }
  53. }
  54. static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq)
  55. {
  56. bool pending = false;
  57. spin_lock_bh(&txq->axq_lock);
  58. if (txq->axq_depth || !list_empty(&txq->axq_acq))
  59. pending = true;
  60. spin_unlock_bh(&txq->axq_lock);
  61. return pending;
  62. }
  63. static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
  64. {
  65. unsigned long flags;
  66. bool ret;
  67. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  68. ret = ath9k_hw_setpower(sc->sc_ah, mode);
  69. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  70. return ret;
  71. }
  72. void ath9k_ps_wakeup(struct ath_softc *sc)
  73. {
  74. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  75. unsigned long flags;
  76. enum ath9k_power_mode power_mode;
  77. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  78. if (++sc->ps_usecount != 1)
  79. goto unlock;
  80. power_mode = sc->sc_ah->power_mode;
  81. ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
  82. /*
  83. * While the hardware is asleep, the cycle counters contain no
  84. * useful data. Better clear them now so that they don't mess up
  85. * survey data results.
  86. */
  87. if (power_mode != ATH9K_PM_AWAKE) {
  88. spin_lock(&common->cc_lock);
  89. ath_hw_cycle_counters_update(common);
  90. memset(&common->cc_survey, 0, sizeof(common->cc_survey));
  91. memset(&common->cc_ani, 0, sizeof(common->cc_ani));
  92. spin_unlock(&common->cc_lock);
  93. }
  94. unlock:
  95. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  96. }
  97. void ath9k_ps_restore(struct ath_softc *sc)
  98. {
  99. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  100. enum ath9k_power_mode mode;
  101. unsigned long flags;
  102. bool reset;
  103. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  104. if (--sc->ps_usecount != 0)
  105. goto unlock;
  106. if (sc->ps_idle) {
  107. ath9k_hw_setrxabort(sc->sc_ah, 1);
  108. ath9k_hw_stopdmarecv(sc->sc_ah, &reset);
  109. mode = ATH9K_PM_FULL_SLEEP;
  110. } else if (sc->ps_enabled &&
  111. !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
  112. PS_WAIT_FOR_CAB |
  113. PS_WAIT_FOR_PSPOLL_DATA |
  114. PS_WAIT_FOR_TX_ACK))) {
  115. mode = ATH9K_PM_NETWORK_SLEEP;
  116. if (ath9k_hw_btcoex_is_enabled(sc->sc_ah))
  117. ath9k_btcoex_stop_gen_timer(sc);
  118. } else {
  119. goto unlock;
  120. }
  121. spin_lock(&common->cc_lock);
  122. ath_hw_cycle_counters_update(common);
  123. spin_unlock(&common->cc_lock);
  124. ath9k_hw_setpower(sc->sc_ah, mode);
  125. unlock:
  126. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  127. }
  128. static void __ath_cancel_work(struct ath_softc *sc)
  129. {
  130. cancel_work_sync(&sc->paprd_work);
  131. cancel_work_sync(&sc->hw_check_work);
  132. cancel_delayed_work_sync(&sc->tx_complete_work);
  133. cancel_delayed_work_sync(&sc->hw_pll_work);
  134. #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
  135. if (ath9k_hw_mci_is_enabled(sc->sc_ah))
  136. cancel_work_sync(&sc->mci_work);
  137. #endif
  138. }
  139. static void ath_cancel_work(struct ath_softc *sc)
  140. {
  141. __ath_cancel_work(sc);
  142. cancel_work_sync(&sc->hw_reset_work);
  143. }
  144. static void ath_restart_work(struct ath_softc *sc)
  145. {
  146. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  147. ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
  148. if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9485(sc->sc_ah) ||
  149. AR_SREV_9550(sc->sc_ah))
  150. ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work,
  151. msecs_to_jiffies(ATH_PLL_WORK_INTERVAL));
  152. ath_start_rx_poll(sc, 3);
  153. if (!common->disable_ani)
  154. ath_start_ani(common);
  155. }
  156. static bool ath_prepare_reset(struct ath_softc *sc, bool retry_tx, bool flush)
  157. {
  158. struct ath_hw *ah = sc->sc_ah;
  159. struct ath_common *common = ath9k_hw_common(ah);
  160. bool ret = true;
  161. ieee80211_stop_queues(sc->hw);
  162. sc->hw_busy_count = 0;
  163. del_timer_sync(&common->ani.timer);
  164. del_timer_sync(&sc->rx_poll_timer);
  165. ath9k_debug_samp_bb_mac(sc);
  166. ath9k_hw_disable_interrupts(ah);
  167. if (!ath_stoprecv(sc))
  168. ret = false;
  169. if (!ath_drain_all_txq(sc, retry_tx))
  170. ret = false;
  171. if (!flush) {
  172. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  173. ath_rx_tasklet(sc, 1, true);
  174. ath_rx_tasklet(sc, 1, false);
  175. } else {
  176. ath_flushrecv(sc);
  177. }
  178. return ret;
  179. }
  180. static bool ath_complete_reset(struct ath_softc *sc, bool start)
  181. {
  182. struct ath_hw *ah = sc->sc_ah;
  183. struct ath_common *common = ath9k_hw_common(ah);
  184. unsigned long flags;
  185. if (ath_startrecv(sc) != 0) {
  186. ath_err(common, "Unable to restart recv logic\n");
  187. return false;
  188. }
  189. ath9k_cmn_update_txpow(ah, sc->curtxpow,
  190. sc->config.txpowlimit, &sc->curtxpow);
  191. clear_bit(SC_OP_HW_RESET, &sc->sc_flags);
  192. ath9k_hw_set_interrupts(ah);
  193. ath9k_hw_enable_interrupts(ah);
  194. if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) && start) {
  195. if (!test_bit(SC_OP_BEACONS, &sc->sc_flags))
  196. goto work;
  197. ath9k_set_beacon(sc);
  198. if (ah->opmode == NL80211_IFTYPE_STATION &&
  199. test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
  200. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  201. sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
  202. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  203. }
  204. work:
  205. ath_restart_work(sc);
  206. }
  207. if ((ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) && sc->ant_rx != 3)
  208. ath_ant_comb_update(sc);
  209. ieee80211_wake_queues(sc->hw);
  210. return true;
  211. }
  212. static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan,
  213. bool retry_tx)
  214. {
  215. struct ath_hw *ah = sc->sc_ah;
  216. struct ath_common *common = ath9k_hw_common(ah);
  217. struct ath9k_hw_cal_data *caldata = NULL;
  218. bool fastcc = true;
  219. bool flush = false;
  220. int r;
  221. __ath_cancel_work(sc);
  222. spin_lock_bh(&sc->sc_pcu_lock);
  223. if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)) {
  224. fastcc = false;
  225. caldata = &sc->caldata;
  226. }
  227. if (!hchan) {
  228. fastcc = false;
  229. flush = true;
  230. hchan = ah->curchan;
  231. }
  232. if (!ath_prepare_reset(sc, retry_tx, flush))
  233. fastcc = false;
  234. ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n",
  235. hchan->channel, IS_CHAN_HT40(hchan), fastcc);
  236. r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
  237. if (r) {
  238. ath_err(common,
  239. "Unable to reset channel, reset status %d\n", r);
  240. goto out;
  241. }
  242. if (!ath_complete_reset(sc, true))
  243. r = -EIO;
  244. out:
  245. spin_unlock_bh(&sc->sc_pcu_lock);
  246. return r;
  247. }
  248. /*
  249. * Set/change channels. If the channel is really being changed, it's done
  250. * by reseting the chip. To accomplish this we must first cleanup any pending
  251. * DMA, then restart stuff.
  252. */
  253. static int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
  254. struct ath9k_channel *hchan)
  255. {
  256. int r;
  257. if (test_bit(SC_OP_INVALID, &sc->sc_flags))
  258. return -EIO;
  259. r = ath_reset_internal(sc, hchan, false);
  260. return r;
  261. }
  262. static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta,
  263. struct ieee80211_vif *vif)
  264. {
  265. struct ath_node *an;
  266. u8 density;
  267. an = (struct ath_node *)sta->drv_priv;
  268. #ifdef CONFIG_ATH9K_DEBUGFS
  269. spin_lock(&sc->nodes_lock);
  270. list_add(&an->list, &sc->nodes);
  271. spin_unlock(&sc->nodes_lock);
  272. #endif
  273. an->sta = sta;
  274. an->vif = vif;
  275. if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
  276. ath_tx_node_init(sc, an);
  277. an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
  278. sta->ht_cap.ampdu_factor);
  279. density = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density);
  280. an->mpdudensity = density;
  281. }
  282. }
  283. static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
  284. {
  285. struct ath_node *an = (struct ath_node *)sta->drv_priv;
  286. #ifdef CONFIG_ATH9K_DEBUGFS
  287. spin_lock(&sc->nodes_lock);
  288. list_del(&an->list);
  289. spin_unlock(&sc->nodes_lock);
  290. an->sta = NULL;
  291. #endif
  292. if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
  293. ath_tx_node_cleanup(sc, an);
  294. }
  295. void ath9k_tasklet(unsigned long data)
  296. {
  297. struct ath_softc *sc = (struct ath_softc *)data;
  298. struct ath_hw *ah = sc->sc_ah;
  299. struct ath_common *common = ath9k_hw_common(ah);
  300. unsigned long flags;
  301. u32 status = sc->intrstatus;
  302. u32 rxmask;
  303. ath9k_ps_wakeup(sc);
  304. spin_lock(&sc->sc_pcu_lock);
  305. if ((status & ATH9K_INT_FATAL) ||
  306. (status & ATH9K_INT_BB_WATCHDOG)) {
  307. #ifdef CONFIG_ATH9K_DEBUGFS
  308. enum ath_reset_type type;
  309. if (status & ATH9K_INT_FATAL)
  310. type = RESET_TYPE_FATAL_INT;
  311. else
  312. type = RESET_TYPE_BB_WATCHDOG;
  313. RESET_STAT_INC(sc, type);
  314. #endif
  315. set_bit(SC_OP_HW_RESET, &sc->sc_flags);
  316. ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
  317. goto out;
  318. }
  319. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  320. if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
  321. /*
  322. * TSF sync does not look correct; remain awake to sync with
  323. * the next Beacon.
  324. */
  325. ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n");
  326. sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
  327. }
  328. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  329. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  330. rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
  331. ATH9K_INT_RXORN);
  332. else
  333. rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
  334. if (status & rxmask) {
  335. /* Check for high priority Rx first */
  336. if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
  337. (status & ATH9K_INT_RXHP))
  338. ath_rx_tasklet(sc, 0, true);
  339. ath_rx_tasklet(sc, 0, false);
  340. }
  341. if (status & ATH9K_INT_TX) {
  342. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  343. ath_tx_edma_tasklet(sc);
  344. else
  345. ath_tx_tasklet(sc);
  346. }
  347. ath9k_btcoex_handle_interrupt(sc, status);
  348. out:
  349. /* re-enable hardware interrupt */
  350. ath9k_hw_enable_interrupts(ah);
  351. spin_unlock(&sc->sc_pcu_lock);
  352. ath9k_ps_restore(sc);
  353. }
  354. irqreturn_t ath_isr(int irq, void *dev)
  355. {
  356. #define SCHED_INTR ( \
  357. ATH9K_INT_FATAL | \
  358. ATH9K_INT_BB_WATCHDOG | \
  359. ATH9K_INT_RXORN | \
  360. ATH9K_INT_RXEOL | \
  361. ATH9K_INT_RX | \
  362. ATH9K_INT_RXLP | \
  363. ATH9K_INT_RXHP | \
  364. ATH9K_INT_TX | \
  365. ATH9K_INT_BMISS | \
  366. ATH9K_INT_CST | \
  367. ATH9K_INT_TSFOOR | \
  368. ATH9K_INT_GENTIMER | \
  369. ATH9K_INT_MCI)
  370. struct ath_softc *sc = dev;
  371. struct ath_hw *ah = sc->sc_ah;
  372. struct ath_common *common = ath9k_hw_common(ah);
  373. enum ath9k_int status;
  374. bool sched = false;
  375. /*
  376. * The hardware is not ready/present, don't
  377. * touch anything. Note this can happen early
  378. * on if the IRQ is shared.
  379. */
  380. if (test_bit(SC_OP_INVALID, &sc->sc_flags))
  381. return IRQ_NONE;
  382. /* shared irq, not for us */
  383. if (!ath9k_hw_intrpend(ah))
  384. return IRQ_NONE;
  385. if(test_bit(SC_OP_HW_RESET, &sc->sc_flags))
  386. return IRQ_HANDLED;
  387. /*
  388. * Figure out the reason(s) for the interrupt. Note
  389. * that the hal returns a pseudo-ISR that may include
  390. * bits we haven't explicitly enabled so we mask the
  391. * value to insure we only process bits we requested.
  392. */
  393. ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
  394. status &= ah->imask; /* discard unasked-for bits */
  395. /*
  396. * If there are no status bits set, then this interrupt was not
  397. * for me (should have been caught above).
  398. */
  399. if (!status)
  400. return IRQ_NONE;
  401. /* Cache the status */
  402. sc->intrstatus = status;
  403. if (status & SCHED_INTR)
  404. sched = true;
  405. #ifdef CONFIG_PM_SLEEP
  406. if (status & ATH9K_INT_BMISS) {
  407. if (atomic_read(&sc->wow_sleep_proc_intr) == 0) {
  408. ath_dbg(common, ANY, "during WoW we got a BMISS\n");
  409. atomic_inc(&sc->wow_got_bmiss_intr);
  410. atomic_dec(&sc->wow_sleep_proc_intr);
  411. }
  412. ath_dbg(common, INTERRUPT, "beacon miss interrupt\n");
  413. }
  414. #endif
  415. /*
  416. * If a FATAL or RXORN interrupt is received, we have to reset the
  417. * chip immediately.
  418. */
  419. if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
  420. !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
  421. goto chip_reset;
  422. if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
  423. (status & ATH9K_INT_BB_WATCHDOG)) {
  424. spin_lock(&common->cc_lock);
  425. ath_hw_cycle_counters_update(common);
  426. ar9003_hw_bb_watchdog_dbg_info(ah);
  427. spin_unlock(&common->cc_lock);
  428. goto chip_reset;
  429. }
  430. if (status & ATH9K_INT_SWBA)
  431. tasklet_schedule(&sc->bcon_tasklet);
  432. if (status & ATH9K_INT_TXURN)
  433. ath9k_hw_updatetxtriglevel(ah, true);
  434. if (status & ATH9K_INT_RXEOL) {
  435. ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
  436. ath9k_hw_set_interrupts(ah);
  437. }
  438. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
  439. if (status & ATH9K_INT_TIM_TIMER) {
  440. if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
  441. goto chip_reset;
  442. /* Clear RxAbort bit so that we can
  443. * receive frames */
  444. ath9k_setpower(sc, ATH9K_PM_AWAKE);
  445. spin_lock(&sc->sc_pm_lock);
  446. ath9k_hw_setrxabort(sc->sc_ah, 0);
  447. sc->ps_flags |= PS_WAIT_FOR_BEACON;
  448. spin_unlock(&sc->sc_pm_lock);
  449. }
  450. chip_reset:
  451. ath_debug_stat_interrupt(sc, status);
  452. if (sched) {
  453. /* turn off every interrupt */
  454. ath9k_hw_disable_interrupts(ah);
  455. tasklet_schedule(&sc->intr_tq);
  456. }
  457. return IRQ_HANDLED;
  458. #undef SCHED_INTR
  459. }
  460. static int ath_reset(struct ath_softc *sc, bool retry_tx)
  461. {
  462. int r;
  463. ath9k_ps_wakeup(sc);
  464. r = ath_reset_internal(sc, NULL, retry_tx);
  465. if (retry_tx) {
  466. int i;
  467. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  468. if (ATH_TXQ_SETUP(sc, i)) {
  469. spin_lock_bh(&sc->tx.txq[i].axq_lock);
  470. ath_txq_schedule(sc, &sc->tx.txq[i]);
  471. spin_unlock_bh(&sc->tx.txq[i].axq_lock);
  472. }
  473. }
  474. }
  475. ath9k_ps_restore(sc);
  476. return r;
  477. }
  478. void ath_reset_work(struct work_struct *work)
  479. {
  480. struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work);
  481. ath_reset(sc, true);
  482. }
  483. /**********************/
  484. /* mac80211 callbacks */
  485. /**********************/
  486. static int ath9k_start(struct ieee80211_hw *hw)
  487. {
  488. struct ath_softc *sc = hw->priv;
  489. struct ath_hw *ah = sc->sc_ah;
  490. struct ath_common *common = ath9k_hw_common(ah);
  491. struct ieee80211_channel *curchan = hw->conf.channel;
  492. struct ath9k_channel *init_channel;
  493. int r;
  494. ath_dbg(common, CONFIG,
  495. "Starting driver with initial channel: %d MHz\n",
  496. curchan->center_freq);
  497. ath9k_ps_wakeup(sc);
  498. mutex_lock(&sc->mutex);
  499. init_channel = ath9k_cmn_get_curchannel(hw, ah);
  500. /* Reset SERDES registers */
  501. ath9k_hw_configpcipowersave(ah, false);
  502. /*
  503. * The basic interface to setting the hardware in a good
  504. * state is ``reset''. On return the hardware is known to
  505. * be powered up and with interrupts disabled. This must
  506. * be followed by initialization of the appropriate bits
  507. * and then setup of the interrupt mask.
  508. */
  509. spin_lock_bh(&sc->sc_pcu_lock);
  510. atomic_set(&ah->intr_ref_cnt, -1);
  511. r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
  512. if (r) {
  513. ath_err(common,
  514. "Unable to reset hardware; reset status %d (freq %u MHz)\n",
  515. r, curchan->center_freq);
  516. spin_unlock_bh(&sc->sc_pcu_lock);
  517. goto mutex_unlock;
  518. }
  519. /* Setup our intr mask. */
  520. ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
  521. ATH9K_INT_RXORN | ATH9K_INT_FATAL |
  522. ATH9K_INT_GLOBAL;
  523. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  524. ah->imask |= ATH9K_INT_RXHP |
  525. ATH9K_INT_RXLP |
  526. ATH9K_INT_BB_WATCHDOG;
  527. else
  528. ah->imask |= ATH9K_INT_RX;
  529. ah->imask |= ATH9K_INT_GTT;
  530. if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
  531. ah->imask |= ATH9K_INT_CST;
  532. ath_mci_enable(sc);
  533. clear_bit(SC_OP_INVALID, &sc->sc_flags);
  534. sc->sc_ah->is_monitoring = false;
  535. if (!ath_complete_reset(sc, false)) {
  536. r = -EIO;
  537. spin_unlock_bh(&sc->sc_pcu_lock);
  538. goto mutex_unlock;
  539. }
  540. if (ah->led_pin >= 0) {
  541. ath9k_hw_cfg_output(ah, ah->led_pin,
  542. AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
  543. ath9k_hw_set_gpio(ah, ah->led_pin, 0);
  544. }
  545. /*
  546. * Reset key cache to sane defaults (all entries cleared) instead of
  547. * semi-random values after suspend/resume.
  548. */
  549. ath9k_cmn_init_crypto(sc->sc_ah);
  550. spin_unlock_bh(&sc->sc_pcu_lock);
  551. if (ah->caps.pcie_lcr_extsync_en && common->bus_ops->extn_synch_en)
  552. common->bus_ops->extn_synch_en(common);
  553. mutex_unlock:
  554. mutex_unlock(&sc->mutex);
  555. ath9k_ps_restore(sc);
  556. return r;
  557. }
  558. static void ath9k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  559. {
  560. struct ath_softc *sc = hw->priv;
  561. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  562. struct ath_tx_control txctl;
  563. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
  564. unsigned long flags;
  565. if (sc->ps_enabled) {
  566. /*
  567. * mac80211 does not set PM field for normal data frames, so we
  568. * need to update that based on the current PS mode.
  569. */
  570. if (ieee80211_is_data(hdr->frame_control) &&
  571. !ieee80211_is_nullfunc(hdr->frame_control) &&
  572. !ieee80211_has_pm(hdr->frame_control)) {
  573. ath_dbg(common, PS,
  574. "Add PM=1 for a TX frame while in PS mode\n");
  575. hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
  576. }
  577. }
  578. if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) {
  579. /*
  580. * We are using PS-Poll and mac80211 can request TX while in
  581. * power save mode. Need to wake up hardware for the TX to be
  582. * completed and if needed, also for RX of buffered frames.
  583. */
  584. ath9k_ps_wakeup(sc);
  585. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  586. if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
  587. ath9k_hw_setrxabort(sc->sc_ah, 0);
  588. if (ieee80211_is_pspoll(hdr->frame_control)) {
  589. ath_dbg(common, PS,
  590. "Sending PS-Poll to pick a buffered frame\n");
  591. sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
  592. } else {
  593. ath_dbg(common, PS, "Wake up to complete TX\n");
  594. sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
  595. }
  596. /*
  597. * The actual restore operation will happen only after
  598. * the ps_flags bit is cleared. We are just dropping
  599. * the ps_usecount here.
  600. */
  601. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  602. ath9k_ps_restore(sc);
  603. }
  604. /*
  605. * Cannot tx while the hardware is in full sleep, it first needs a full
  606. * chip reset to recover from that
  607. */
  608. if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) {
  609. ath_err(common, "TX while HW is in FULL_SLEEP mode\n");
  610. goto exit;
  611. }
  612. memset(&txctl, 0, sizeof(struct ath_tx_control));
  613. txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
  614. ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb);
  615. if (ath_tx_start(hw, skb, &txctl) != 0) {
  616. ath_dbg(common, XMIT, "TX failed\n");
  617. TX_STAT_INC(txctl.txq->axq_qnum, txfailed);
  618. goto exit;
  619. }
  620. return;
  621. exit:
  622. dev_kfree_skb_any(skb);
  623. }
  624. static void ath9k_stop(struct ieee80211_hw *hw)
  625. {
  626. struct ath_softc *sc = hw->priv;
  627. struct ath_hw *ah = sc->sc_ah;
  628. struct ath_common *common = ath9k_hw_common(ah);
  629. bool prev_idle;
  630. mutex_lock(&sc->mutex);
  631. ath_cancel_work(sc);
  632. del_timer_sync(&sc->rx_poll_timer);
  633. if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
  634. ath_dbg(common, ANY, "Device not present\n");
  635. mutex_unlock(&sc->mutex);
  636. return;
  637. }
  638. /* Ensure HW is awake when we try to shut it down. */
  639. ath9k_ps_wakeup(sc);
  640. spin_lock_bh(&sc->sc_pcu_lock);
  641. /* prevent tasklets to enable interrupts once we disable them */
  642. ah->imask &= ~ATH9K_INT_GLOBAL;
  643. /* make sure h/w will not generate any interrupt
  644. * before setting the invalid flag. */
  645. ath9k_hw_disable_interrupts(ah);
  646. spin_unlock_bh(&sc->sc_pcu_lock);
  647. /* we can now sync irq and kill any running tasklets, since we already
  648. * disabled interrupts and not holding a spin lock */
  649. synchronize_irq(sc->irq);
  650. tasklet_kill(&sc->intr_tq);
  651. tasklet_kill(&sc->bcon_tasklet);
  652. prev_idle = sc->ps_idle;
  653. sc->ps_idle = true;
  654. spin_lock_bh(&sc->sc_pcu_lock);
  655. if (ah->led_pin >= 0) {
  656. ath9k_hw_set_gpio(ah, ah->led_pin, 1);
  657. ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
  658. }
  659. ath_prepare_reset(sc, false, true);
  660. if (sc->rx.frag) {
  661. dev_kfree_skb_any(sc->rx.frag);
  662. sc->rx.frag = NULL;
  663. }
  664. if (!ah->curchan)
  665. ah->curchan = ath9k_cmn_get_curchannel(hw, ah);
  666. ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
  667. ath9k_hw_phy_disable(ah);
  668. ath9k_hw_configpcipowersave(ah, true);
  669. spin_unlock_bh(&sc->sc_pcu_lock);
  670. ath9k_ps_restore(sc);
  671. set_bit(SC_OP_INVALID, &sc->sc_flags);
  672. sc->ps_idle = prev_idle;
  673. mutex_unlock(&sc->mutex);
  674. ath_dbg(common, CONFIG, "Driver halt\n");
  675. }
  676. bool ath9k_uses_beacons(int type)
  677. {
  678. switch (type) {
  679. case NL80211_IFTYPE_AP:
  680. case NL80211_IFTYPE_ADHOC:
  681. case NL80211_IFTYPE_MESH_POINT:
  682. return true;
  683. default:
  684. return false;
  685. }
  686. }
  687. static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
  688. {
  689. struct ath9k_vif_iter_data *iter_data = data;
  690. int i;
  691. if (iter_data->hw_macaddr)
  692. for (i = 0; i < ETH_ALEN; i++)
  693. iter_data->mask[i] &=
  694. ~(iter_data->hw_macaddr[i] ^ mac[i]);
  695. switch (vif->type) {
  696. case NL80211_IFTYPE_AP:
  697. iter_data->naps++;
  698. break;
  699. case NL80211_IFTYPE_STATION:
  700. iter_data->nstations++;
  701. break;
  702. case NL80211_IFTYPE_ADHOC:
  703. iter_data->nadhocs++;
  704. break;
  705. case NL80211_IFTYPE_MESH_POINT:
  706. iter_data->nmeshes++;
  707. break;
  708. case NL80211_IFTYPE_WDS:
  709. iter_data->nwds++;
  710. break;
  711. default:
  712. break;
  713. }
  714. }
  715. /* Called with sc->mutex held. */
  716. void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
  717. struct ieee80211_vif *vif,
  718. struct ath9k_vif_iter_data *iter_data)
  719. {
  720. struct ath_softc *sc = hw->priv;
  721. struct ath_hw *ah = sc->sc_ah;
  722. struct ath_common *common = ath9k_hw_common(ah);
  723. /*
  724. * Use the hardware MAC address as reference, the hardware uses it
  725. * together with the BSSID mask when matching addresses.
  726. */
  727. memset(iter_data, 0, sizeof(*iter_data));
  728. iter_data->hw_macaddr = common->macaddr;
  729. memset(&iter_data->mask, 0xff, ETH_ALEN);
  730. if (vif)
  731. ath9k_vif_iter(iter_data, vif->addr, vif);
  732. /* Get list of all active MAC addresses */
  733. ieee80211_iterate_active_interfaces_atomic(sc->hw, ath9k_vif_iter,
  734. iter_data);
  735. }
  736. /* Called with sc->mutex held. */
  737. static void ath9k_calculate_summary_state(struct ieee80211_hw *hw,
  738. struct ieee80211_vif *vif)
  739. {
  740. struct ath_softc *sc = hw->priv;
  741. struct ath_hw *ah = sc->sc_ah;
  742. struct ath_common *common = ath9k_hw_common(ah);
  743. struct ath9k_vif_iter_data iter_data;
  744. ath9k_calculate_iter_data(hw, vif, &iter_data);
  745. memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
  746. ath_hw_setbssidmask(common);
  747. if (iter_data.naps > 0) {
  748. ath9k_hw_set_tsfadjust(ah, true);
  749. ah->opmode = NL80211_IFTYPE_AP;
  750. } else {
  751. ath9k_hw_set_tsfadjust(ah, false);
  752. if (iter_data.nmeshes)
  753. ah->opmode = NL80211_IFTYPE_MESH_POINT;
  754. else if (iter_data.nwds)
  755. ah->opmode = NL80211_IFTYPE_AP;
  756. else if (iter_data.nadhocs)
  757. ah->opmode = NL80211_IFTYPE_ADHOC;
  758. else
  759. ah->opmode = NL80211_IFTYPE_STATION;
  760. }
  761. ath9k_hw_setopmode(ah);
  762. if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0)
  763. ah->imask |= ATH9K_INT_TSFOOR;
  764. else
  765. ah->imask &= ~ATH9K_INT_TSFOOR;
  766. ath9k_hw_set_interrupts(ah);
  767. }
  768. static int ath9k_add_interface(struct ieee80211_hw *hw,
  769. struct ieee80211_vif *vif)
  770. {
  771. struct ath_softc *sc = hw->priv;
  772. struct ath_hw *ah = sc->sc_ah;
  773. struct ath_common *common = ath9k_hw_common(ah);
  774. int ret = 0;
  775. ath9k_ps_wakeup(sc);
  776. mutex_lock(&sc->mutex);
  777. switch (vif->type) {
  778. case NL80211_IFTYPE_STATION:
  779. case NL80211_IFTYPE_WDS:
  780. case NL80211_IFTYPE_ADHOC:
  781. case NL80211_IFTYPE_AP:
  782. case NL80211_IFTYPE_MESH_POINT:
  783. break;
  784. default:
  785. ath_err(common, "Interface type %d not yet supported\n",
  786. vif->type);
  787. ret = -EOPNOTSUPP;
  788. goto out;
  789. }
  790. if (ath9k_uses_beacons(vif->type)) {
  791. if (sc->nbcnvifs >= ATH_BCBUF) {
  792. ath_err(common, "Not enough beacon buffers when adding"
  793. " new interface of type: %i\n",
  794. vif->type);
  795. ret = -ENOBUFS;
  796. goto out;
  797. }
  798. }
  799. ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type);
  800. sc->nvifs++;
  801. ath9k_calculate_summary_state(hw, vif);
  802. if (ath9k_uses_beacons(vif->type))
  803. ath9k_beacon_assign_slot(sc, vif);
  804. out:
  805. mutex_unlock(&sc->mutex);
  806. ath9k_ps_restore(sc);
  807. return ret;
  808. }
  809. static int ath9k_change_interface(struct ieee80211_hw *hw,
  810. struct ieee80211_vif *vif,
  811. enum nl80211_iftype new_type,
  812. bool p2p)
  813. {
  814. struct ath_softc *sc = hw->priv;
  815. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  816. int ret = 0;
  817. ath_dbg(common, CONFIG, "Change Interface\n");
  818. mutex_lock(&sc->mutex);
  819. ath9k_ps_wakeup(sc);
  820. if (ath9k_uses_beacons(new_type) &&
  821. !ath9k_uses_beacons(vif->type)) {
  822. if (sc->nbcnvifs >= ATH_BCBUF) {
  823. ath_err(common, "No beacon slot available\n");
  824. ret = -ENOBUFS;
  825. goto out;
  826. }
  827. }
  828. if (ath9k_uses_beacons(vif->type))
  829. ath9k_beacon_remove_slot(sc, vif);
  830. vif->type = new_type;
  831. vif->p2p = p2p;
  832. ath9k_calculate_summary_state(hw, vif);
  833. if (ath9k_uses_beacons(vif->type))
  834. ath9k_beacon_assign_slot(sc, vif);
  835. out:
  836. ath9k_ps_restore(sc);
  837. mutex_unlock(&sc->mutex);
  838. return ret;
  839. }
  840. static void ath9k_remove_interface(struct ieee80211_hw *hw,
  841. struct ieee80211_vif *vif)
  842. {
  843. struct ath_softc *sc = hw->priv;
  844. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  845. ath_dbg(common, CONFIG, "Detach Interface\n");
  846. ath9k_ps_wakeup(sc);
  847. mutex_lock(&sc->mutex);
  848. sc->nvifs--;
  849. if (ath9k_uses_beacons(vif->type))
  850. ath9k_beacon_remove_slot(sc, vif);
  851. ath9k_calculate_summary_state(hw, NULL);
  852. mutex_unlock(&sc->mutex);
  853. ath9k_ps_restore(sc);
  854. }
  855. static void ath9k_enable_ps(struct ath_softc *sc)
  856. {
  857. struct ath_hw *ah = sc->sc_ah;
  858. struct ath_common *common = ath9k_hw_common(ah);
  859. sc->ps_enabled = true;
  860. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
  861. if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
  862. ah->imask |= ATH9K_INT_TIM_TIMER;
  863. ath9k_hw_set_interrupts(ah);
  864. }
  865. ath9k_hw_setrxabort(ah, 1);
  866. }
  867. ath_dbg(common, PS, "PowerSave enabled\n");
  868. }
  869. static void ath9k_disable_ps(struct ath_softc *sc)
  870. {
  871. struct ath_hw *ah = sc->sc_ah;
  872. struct ath_common *common = ath9k_hw_common(ah);
  873. sc->ps_enabled = false;
  874. ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
  875. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
  876. ath9k_hw_setrxabort(ah, 0);
  877. sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
  878. PS_WAIT_FOR_CAB |
  879. PS_WAIT_FOR_PSPOLL_DATA |
  880. PS_WAIT_FOR_TX_ACK);
  881. if (ah->imask & ATH9K_INT_TIM_TIMER) {
  882. ah->imask &= ~ATH9K_INT_TIM_TIMER;
  883. ath9k_hw_set_interrupts(ah);
  884. }
  885. }
  886. ath_dbg(common, PS, "PowerSave disabled\n");
  887. }
  888. static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
  889. {
  890. struct ath_softc *sc = hw->priv;
  891. struct ath_hw *ah = sc->sc_ah;
  892. struct ath_common *common = ath9k_hw_common(ah);
  893. struct ieee80211_conf *conf = &hw->conf;
  894. bool reset_channel = false;
  895. ath9k_ps_wakeup(sc);
  896. mutex_lock(&sc->mutex);
  897. if (changed & IEEE80211_CONF_CHANGE_IDLE) {
  898. sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
  899. if (sc->ps_idle) {
  900. ath_cancel_work(sc);
  901. ath9k_stop_btcoex(sc);
  902. } else {
  903. ath9k_start_btcoex(sc);
  904. /*
  905. * The chip needs a reset to properly wake up from
  906. * full sleep
  907. */
  908. reset_channel = ah->chip_fullsleep;
  909. }
  910. }
  911. /*
  912. * We just prepare to enable PS. We have to wait until our AP has
  913. * ACK'd our null data frame to disable RX otherwise we'll ignore
  914. * those ACKs and end up retransmitting the same null data frames.
  915. * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
  916. */
  917. if (changed & IEEE80211_CONF_CHANGE_PS) {
  918. unsigned long flags;
  919. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  920. if (conf->flags & IEEE80211_CONF_PS)
  921. ath9k_enable_ps(sc);
  922. else
  923. ath9k_disable_ps(sc);
  924. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  925. }
  926. if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
  927. if (conf->flags & IEEE80211_CONF_MONITOR) {
  928. ath_dbg(common, CONFIG, "Monitor mode is enabled\n");
  929. sc->sc_ah->is_monitoring = true;
  930. } else {
  931. ath_dbg(common, CONFIG, "Monitor mode is disabled\n");
  932. sc->sc_ah->is_monitoring = false;
  933. }
  934. }
  935. if ((changed & IEEE80211_CONF_CHANGE_CHANNEL) || reset_channel) {
  936. struct ieee80211_channel *curchan = hw->conf.channel;
  937. int pos = curchan->hw_value;
  938. int old_pos = -1;
  939. unsigned long flags;
  940. if (ah->curchan)
  941. old_pos = ah->curchan - &ah->channels[0];
  942. ath_dbg(common, CONFIG, "Set channel: %d MHz type: %d\n",
  943. curchan->center_freq, conf->channel_type);
  944. /* update survey stats for the old channel before switching */
  945. spin_lock_irqsave(&common->cc_lock, flags);
  946. ath_update_survey_stats(sc);
  947. spin_unlock_irqrestore(&common->cc_lock, flags);
  948. /*
  949. * Preserve the current channel values, before updating
  950. * the same channel
  951. */
  952. if (ah->curchan && (old_pos == pos))
  953. ath9k_hw_getnf(ah, ah->curchan);
  954. ath9k_cmn_update_ichannel(&sc->sc_ah->channels[pos],
  955. curchan, conf->channel_type);
  956. /*
  957. * If the operating channel changes, change the survey in-use flags
  958. * along with it.
  959. * Reset the survey data for the new channel, unless we're switching
  960. * back to the operating channel from an off-channel operation.
  961. */
  962. if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) &&
  963. sc->cur_survey != &sc->survey[pos]) {
  964. if (sc->cur_survey)
  965. sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE;
  966. sc->cur_survey = &sc->survey[pos];
  967. memset(sc->cur_survey, 0, sizeof(struct survey_info));
  968. sc->cur_survey->filled |= SURVEY_INFO_IN_USE;
  969. } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) {
  970. memset(&sc->survey[pos], 0, sizeof(struct survey_info));
  971. }
  972. if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
  973. ath_err(common, "Unable to set channel\n");
  974. mutex_unlock(&sc->mutex);
  975. ath9k_ps_restore(sc);
  976. return -EINVAL;
  977. }
  978. /*
  979. * The most recent snapshot of channel->noisefloor for the old
  980. * channel is only available after the hardware reset. Copy it to
  981. * the survey stats now.
  982. */
  983. if (old_pos >= 0)
  984. ath_update_survey_nf(sc, old_pos);
  985. }
  986. if (changed & IEEE80211_CONF_CHANGE_POWER) {
  987. ath_dbg(common, CONFIG, "Set power: %d\n", conf->power_level);
  988. sc->config.txpowlimit = 2 * conf->power_level;
  989. ath9k_cmn_update_txpow(ah, sc->curtxpow,
  990. sc->config.txpowlimit, &sc->curtxpow);
  991. }
  992. mutex_unlock(&sc->mutex);
  993. ath9k_ps_restore(sc);
  994. return 0;
  995. }
  996. #define SUPPORTED_FILTERS \
  997. (FIF_PROMISC_IN_BSS | \
  998. FIF_ALLMULTI | \
  999. FIF_CONTROL | \
  1000. FIF_PSPOLL | \
  1001. FIF_OTHER_BSS | \
  1002. FIF_BCN_PRBRESP_PROMISC | \
  1003. FIF_PROBE_REQ | \
  1004. FIF_FCSFAIL)
  1005. /* FIXME: sc->sc_full_reset ? */
  1006. static void ath9k_configure_filter(struct ieee80211_hw *hw,
  1007. unsigned int changed_flags,
  1008. unsigned int *total_flags,
  1009. u64 multicast)
  1010. {
  1011. struct ath_softc *sc = hw->priv;
  1012. u32 rfilt;
  1013. changed_flags &= SUPPORTED_FILTERS;
  1014. *total_flags &= SUPPORTED_FILTERS;
  1015. sc->rx.rxfilter = *total_flags;
  1016. ath9k_ps_wakeup(sc);
  1017. rfilt = ath_calcrxfilter(sc);
  1018. ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
  1019. ath9k_ps_restore(sc);
  1020. ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n",
  1021. rfilt);
  1022. }
  1023. static int ath9k_sta_add(struct ieee80211_hw *hw,
  1024. struct ieee80211_vif *vif,
  1025. struct ieee80211_sta *sta)
  1026. {
  1027. struct ath_softc *sc = hw->priv;
  1028. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1029. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1030. struct ieee80211_key_conf ps_key = { };
  1031. ath_node_attach(sc, sta, vif);
  1032. if (vif->type != NL80211_IFTYPE_AP &&
  1033. vif->type != NL80211_IFTYPE_AP_VLAN)
  1034. return 0;
  1035. an->ps_key = ath_key_config(common, vif, sta, &ps_key);
  1036. return 0;
  1037. }
  1038. static void ath9k_del_ps_key(struct ath_softc *sc,
  1039. struct ieee80211_vif *vif,
  1040. struct ieee80211_sta *sta)
  1041. {
  1042. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1043. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1044. struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key };
  1045. if (!an->ps_key)
  1046. return;
  1047. ath_key_delete(common, &ps_key);
  1048. }
  1049. static int ath9k_sta_remove(struct ieee80211_hw *hw,
  1050. struct ieee80211_vif *vif,
  1051. struct ieee80211_sta *sta)
  1052. {
  1053. struct ath_softc *sc = hw->priv;
  1054. ath9k_del_ps_key(sc, vif, sta);
  1055. ath_node_detach(sc, sta);
  1056. return 0;
  1057. }
  1058. static void ath9k_sta_notify(struct ieee80211_hw *hw,
  1059. struct ieee80211_vif *vif,
  1060. enum sta_notify_cmd cmd,
  1061. struct ieee80211_sta *sta)
  1062. {
  1063. struct ath_softc *sc = hw->priv;
  1064. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1065. if (!sta->ht_cap.ht_supported)
  1066. return;
  1067. switch (cmd) {
  1068. case STA_NOTIFY_SLEEP:
  1069. an->sleeping = true;
  1070. ath_tx_aggr_sleep(sta, sc, an);
  1071. break;
  1072. case STA_NOTIFY_AWAKE:
  1073. an->sleeping = false;
  1074. ath_tx_aggr_wakeup(sc, an);
  1075. break;
  1076. }
  1077. }
  1078. static int ath9k_conf_tx(struct ieee80211_hw *hw,
  1079. struct ieee80211_vif *vif, u16 queue,
  1080. const struct ieee80211_tx_queue_params *params)
  1081. {
  1082. struct ath_softc *sc = hw->priv;
  1083. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1084. struct ath_txq *txq;
  1085. struct ath9k_tx_queue_info qi;
  1086. int ret = 0;
  1087. if (queue >= WME_NUM_AC)
  1088. return 0;
  1089. txq = sc->tx.txq_map[queue];
  1090. ath9k_ps_wakeup(sc);
  1091. mutex_lock(&sc->mutex);
  1092. memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
  1093. qi.tqi_aifs = params->aifs;
  1094. qi.tqi_cwmin = params->cw_min;
  1095. qi.tqi_cwmax = params->cw_max;
  1096. qi.tqi_burstTime = params->txop * 32;
  1097. ath_dbg(common, CONFIG,
  1098. "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
  1099. queue, txq->axq_qnum, params->aifs, params->cw_min,
  1100. params->cw_max, params->txop);
  1101. ath_update_max_aggr_framelen(sc, queue, qi.tqi_burstTime);
  1102. ret = ath_txq_update(sc, txq->axq_qnum, &qi);
  1103. if (ret)
  1104. ath_err(common, "TXQ Update failed\n");
  1105. if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC)
  1106. if (queue == WME_AC_BE && !ret)
  1107. ath_beaconq_config(sc);
  1108. mutex_unlock(&sc->mutex);
  1109. ath9k_ps_restore(sc);
  1110. return ret;
  1111. }
  1112. static int ath9k_set_key(struct ieee80211_hw *hw,
  1113. enum set_key_cmd cmd,
  1114. struct ieee80211_vif *vif,
  1115. struct ieee80211_sta *sta,
  1116. struct ieee80211_key_conf *key)
  1117. {
  1118. struct ath_softc *sc = hw->priv;
  1119. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1120. int ret = 0;
  1121. if (ath9k_modparam_nohwcrypt)
  1122. return -ENOSPC;
  1123. if ((vif->type == NL80211_IFTYPE_ADHOC ||
  1124. vif->type == NL80211_IFTYPE_MESH_POINT) &&
  1125. (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
  1126. key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
  1127. !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
  1128. /*
  1129. * For now, disable hw crypto for the RSN IBSS group keys. This
  1130. * could be optimized in the future to use a modified key cache
  1131. * design to support per-STA RX GTK, but until that gets
  1132. * implemented, use of software crypto for group addressed
  1133. * frames is a acceptable to allow RSN IBSS to be used.
  1134. */
  1135. return -EOPNOTSUPP;
  1136. }
  1137. mutex_lock(&sc->mutex);
  1138. ath9k_ps_wakeup(sc);
  1139. ath_dbg(common, CONFIG, "Set HW Key\n");
  1140. switch (cmd) {
  1141. case SET_KEY:
  1142. if (sta)
  1143. ath9k_del_ps_key(sc, vif, sta);
  1144. ret = ath_key_config(common, vif, sta, key);
  1145. if (ret >= 0) {
  1146. key->hw_key_idx = ret;
  1147. /* push IV and Michael MIC generation to stack */
  1148. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  1149. if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
  1150. key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
  1151. if (sc->sc_ah->sw_mgmt_crypto &&
  1152. key->cipher == WLAN_CIPHER_SUITE_CCMP)
  1153. key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
  1154. ret = 0;
  1155. }
  1156. break;
  1157. case DISABLE_KEY:
  1158. ath_key_delete(common, key);
  1159. break;
  1160. default:
  1161. ret = -EINVAL;
  1162. }
  1163. ath9k_ps_restore(sc);
  1164. mutex_unlock(&sc->mutex);
  1165. return ret;
  1166. }
  1167. static void ath9k_set_assoc_state(struct ath_softc *sc,
  1168. struct ieee80211_vif *vif)
  1169. {
  1170. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1171. struct ath_vif *avp = (void *)vif->drv_priv;
  1172. struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
  1173. unsigned long flags;
  1174. set_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags);
  1175. avp->primary_sta_vif = true;
  1176. /*
  1177. * Set the AID, BSSID and do beacon-sync only when
  1178. * the HW opmode is STATION.
  1179. *
  1180. * But the primary bit is set above in any case.
  1181. */
  1182. if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION)
  1183. return;
  1184. memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
  1185. common->curaid = bss_conf->aid;
  1186. ath9k_hw_write_associd(sc->sc_ah);
  1187. sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
  1188. sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
  1189. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  1190. sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
  1191. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  1192. ath_dbg(common, CONFIG,
  1193. "Primary Station interface: %pM, BSSID: %pM\n",
  1194. vif->addr, common->curbssid);
  1195. }
  1196. static void ath9k_bss_assoc_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
  1197. {
  1198. struct ath_softc *sc = data;
  1199. struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
  1200. if (test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags))
  1201. return;
  1202. if (bss_conf->assoc)
  1203. ath9k_set_assoc_state(sc, vif);
  1204. }
  1205. static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
  1206. struct ieee80211_vif *vif,
  1207. struct ieee80211_bss_conf *bss_conf,
  1208. u32 changed)
  1209. {
  1210. struct ath_softc *sc = hw->priv;
  1211. struct ath_hw *ah = sc->sc_ah;
  1212. struct ath_common *common = ath9k_hw_common(ah);
  1213. struct ath_vif *avp = (void *)vif->drv_priv;
  1214. int slottime;
  1215. ath9k_ps_wakeup(sc);
  1216. mutex_lock(&sc->mutex);
  1217. if (changed & BSS_CHANGED_ASSOC) {
  1218. ath_dbg(common, CONFIG, "BSSID %pM Changed ASSOC %d\n",
  1219. bss_conf->bssid, bss_conf->assoc);
  1220. if (avp->primary_sta_vif && !bss_conf->assoc) {
  1221. clear_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags);
  1222. avp->primary_sta_vif = false;
  1223. if (ah->opmode == NL80211_IFTYPE_STATION)
  1224. clear_bit(SC_OP_BEACONS, &sc->sc_flags);
  1225. }
  1226. ieee80211_iterate_active_interfaces_atomic(sc->hw,
  1227. ath9k_bss_assoc_iter, sc);
  1228. if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags) &&
  1229. ah->opmode == NL80211_IFTYPE_STATION) {
  1230. memset(common->curbssid, 0, ETH_ALEN);
  1231. common->curaid = 0;
  1232. ath9k_hw_write_associd(sc->sc_ah);
  1233. }
  1234. }
  1235. if (changed & BSS_CHANGED_IBSS) {
  1236. memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
  1237. common->curaid = bss_conf->aid;
  1238. ath9k_hw_write_associd(sc->sc_ah);
  1239. if (bss_conf->ibss_joined) {
  1240. if (!common->disable_ani) {
  1241. set_bit(SC_OP_ANI_RUN, &sc->sc_flags);
  1242. ath_start_ani(common);
  1243. }
  1244. } else {
  1245. clear_bit(SC_OP_ANI_RUN, &sc->sc_flags);
  1246. del_timer_sync(&common->ani.timer);
  1247. }
  1248. }
  1249. if ((changed & BSS_CHANGED_BEACON_ENABLED) ||
  1250. (changed & BSS_CHANGED_BEACON_INT)) {
  1251. if (ath9k_allow_beacon_config(sc, vif))
  1252. ath9k_beacon_config(sc, vif, changed);
  1253. }
  1254. if (changed & BSS_CHANGED_ERP_SLOT) {
  1255. if (bss_conf->use_short_slot)
  1256. slottime = 9;
  1257. else
  1258. slottime = 20;
  1259. if (vif->type == NL80211_IFTYPE_AP) {
  1260. /*
  1261. * Defer update, so that connected stations can adjust
  1262. * their settings at the same time.
  1263. * See beacon.c for more details
  1264. */
  1265. sc->beacon.slottime = slottime;
  1266. sc->beacon.updateslot = UPDATE;
  1267. } else {
  1268. ah->slottime = slottime;
  1269. ath9k_hw_init_global_settings(ah);
  1270. }
  1271. }
  1272. mutex_unlock(&sc->mutex);
  1273. ath9k_ps_restore(sc);
  1274. }
  1275. static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
  1276. {
  1277. struct ath_softc *sc = hw->priv;
  1278. u64 tsf;
  1279. mutex_lock(&sc->mutex);
  1280. ath9k_ps_wakeup(sc);
  1281. tsf = ath9k_hw_gettsf64(sc->sc_ah);
  1282. ath9k_ps_restore(sc);
  1283. mutex_unlock(&sc->mutex);
  1284. return tsf;
  1285. }
  1286. static void ath9k_set_tsf(struct ieee80211_hw *hw,
  1287. struct ieee80211_vif *vif,
  1288. u64 tsf)
  1289. {
  1290. struct ath_softc *sc = hw->priv;
  1291. mutex_lock(&sc->mutex);
  1292. ath9k_ps_wakeup(sc);
  1293. ath9k_hw_settsf64(sc->sc_ah, tsf);
  1294. ath9k_ps_restore(sc);
  1295. mutex_unlock(&sc->mutex);
  1296. }
  1297. static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
  1298. {
  1299. struct ath_softc *sc = hw->priv;
  1300. mutex_lock(&sc->mutex);
  1301. ath9k_ps_wakeup(sc);
  1302. ath9k_hw_reset_tsf(sc->sc_ah);
  1303. ath9k_ps_restore(sc);
  1304. mutex_unlock(&sc->mutex);
  1305. }
  1306. static int ath9k_ampdu_action(struct ieee80211_hw *hw,
  1307. struct ieee80211_vif *vif,
  1308. enum ieee80211_ampdu_mlme_action action,
  1309. struct ieee80211_sta *sta,
  1310. u16 tid, u16 *ssn, u8 buf_size)
  1311. {
  1312. struct ath_softc *sc = hw->priv;
  1313. int ret = 0;
  1314. local_bh_disable();
  1315. switch (action) {
  1316. case IEEE80211_AMPDU_RX_START:
  1317. break;
  1318. case IEEE80211_AMPDU_RX_STOP:
  1319. break;
  1320. case IEEE80211_AMPDU_TX_START:
  1321. ath9k_ps_wakeup(sc);
  1322. ret = ath_tx_aggr_start(sc, sta, tid, ssn);
  1323. if (!ret)
  1324. ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  1325. ath9k_ps_restore(sc);
  1326. break;
  1327. case IEEE80211_AMPDU_TX_STOP:
  1328. ath9k_ps_wakeup(sc);
  1329. ath_tx_aggr_stop(sc, sta, tid);
  1330. ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  1331. ath9k_ps_restore(sc);
  1332. break;
  1333. case IEEE80211_AMPDU_TX_OPERATIONAL:
  1334. ath9k_ps_wakeup(sc);
  1335. ath_tx_aggr_resume(sc, sta, tid);
  1336. ath9k_ps_restore(sc);
  1337. break;
  1338. default:
  1339. ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
  1340. }
  1341. local_bh_enable();
  1342. return ret;
  1343. }
  1344. static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
  1345. struct survey_info *survey)
  1346. {
  1347. struct ath_softc *sc = hw->priv;
  1348. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1349. struct ieee80211_supported_band *sband;
  1350. struct ieee80211_channel *chan;
  1351. unsigned long flags;
  1352. int pos;
  1353. spin_lock_irqsave(&common->cc_lock, flags);
  1354. if (idx == 0)
  1355. ath_update_survey_stats(sc);
  1356. sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ];
  1357. if (sband && idx >= sband->n_channels) {
  1358. idx -= sband->n_channels;
  1359. sband = NULL;
  1360. }
  1361. if (!sband)
  1362. sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ];
  1363. if (!sband || idx >= sband->n_channels) {
  1364. spin_unlock_irqrestore(&common->cc_lock, flags);
  1365. return -ENOENT;
  1366. }
  1367. chan = &sband->channels[idx];
  1368. pos = chan->hw_value;
  1369. memcpy(survey, &sc->survey[pos], sizeof(*survey));
  1370. survey->channel = chan;
  1371. spin_unlock_irqrestore(&common->cc_lock, flags);
  1372. return 0;
  1373. }
  1374. static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
  1375. {
  1376. struct ath_softc *sc = hw->priv;
  1377. struct ath_hw *ah = sc->sc_ah;
  1378. mutex_lock(&sc->mutex);
  1379. ah->coverage_class = coverage_class;
  1380. ath9k_ps_wakeup(sc);
  1381. ath9k_hw_init_global_settings(ah);
  1382. ath9k_ps_restore(sc);
  1383. mutex_unlock(&sc->mutex);
  1384. }
  1385. static void ath9k_flush(struct ieee80211_hw *hw, bool drop)
  1386. {
  1387. struct ath_softc *sc = hw->priv;
  1388. struct ath_hw *ah = sc->sc_ah;
  1389. struct ath_common *common = ath9k_hw_common(ah);
  1390. int timeout = 200; /* ms */
  1391. int i, j;
  1392. bool drain_txq;
  1393. mutex_lock(&sc->mutex);
  1394. cancel_delayed_work_sync(&sc->tx_complete_work);
  1395. if (ah->ah_flags & AH_UNPLUGGED) {
  1396. ath_dbg(common, ANY, "Device has been unplugged!\n");
  1397. mutex_unlock(&sc->mutex);
  1398. return;
  1399. }
  1400. if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
  1401. ath_dbg(common, ANY, "Device not present\n");
  1402. mutex_unlock(&sc->mutex);
  1403. return;
  1404. }
  1405. for (j = 0; j < timeout; j++) {
  1406. bool npend = false;
  1407. if (j)
  1408. usleep_range(1000, 2000);
  1409. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  1410. if (!ATH_TXQ_SETUP(sc, i))
  1411. continue;
  1412. npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]);
  1413. if (npend)
  1414. break;
  1415. }
  1416. if (!npend)
  1417. break;
  1418. }
  1419. if (drop) {
  1420. ath9k_ps_wakeup(sc);
  1421. spin_lock_bh(&sc->sc_pcu_lock);
  1422. drain_txq = ath_drain_all_txq(sc, false);
  1423. spin_unlock_bh(&sc->sc_pcu_lock);
  1424. if (!drain_txq)
  1425. ath_reset(sc, false);
  1426. ath9k_ps_restore(sc);
  1427. ieee80211_wake_queues(hw);
  1428. }
  1429. ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0);
  1430. mutex_unlock(&sc->mutex);
  1431. }
  1432. static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
  1433. {
  1434. struct ath_softc *sc = hw->priv;
  1435. int i;
  1436. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  1437. if (!ATH_TXQ_SETUP(sc, i))
  1438. continue;
  1439. if (ath9k_has_pending_frames(sc, &sc->tx.txq[i]))
  1440. return true;
  1441. }
  1442. return false;
  1443. }
  1444. static int ath9k_tx_last_beacon(struct ieee80211_hw *hw)
  1445. {
  1446. struct ath_softc *sc = hw->priv;
  1447. struct ath_hw *ah = sc->sc_ah;
  1448. struct ieee80211_vif *vif;
  1449. struct ath_vif *avp;
  1450. struct ath_buf *bf;
  1451. struct ath_tx_status ts;
  1452. bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
  1453. int status;
  1454. vif = sc->beacon.bslot[0];
  1455. if (!vif)
  1456. return 0;
  1457. if (!vif->bss_conf.enable_beacon)
  1458. return 0;
  1459. avp = (void *)vif->drv_priv;
  1460. if (!sc->beacon.tx_processed && !edma) {
  1461. tasklet_disable(&sc->bcon_tasklet);
  1462. bf = avp->av_bcbuf;
  1463. if (!bf || !bf->bf_mpdu)
  1464. goto skip;
  1465. status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts);
  1466. if (status == -EINPROGRESS)
  1467. goto skip;
  1468. sc->beacon.tx_processed = true;
  1469. sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
  1470. skip:
  1471. tasklet_enable(&sc->bcon_tasklet);
  1472. }
  1473. return sc->beacon.tx_last;
  1474. }
  1475. static int ath9k_get_stats(struct ieee80211_hw *hw,
  1476. struct ieee80211_low_level_stats *stats)
  1477. {
  1478. struct ath_softc *sc = hw->priv;
  1479. struct ath_hw *ah = sc->sc_ah;
  1480. struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats;
  1481. stats->dot11ACKFailureCount = mib_stats->ackrcv_bad;
  1482. stats->dot11RTSFailureCount = mib_stats->rts_bad;
  1483. stats->dot11FCSErrorCount = mib_stats->fcs_bad;
  1484. stats->dot11RTSSuccessCount = mib_stats->rts_good;
  1485. return 0;
  1486. }
  1487. static u32 fill_chainmask(u32 cap, u32 new)
  1488. {
  1489. u32 filled = 0;
  1490. int i;
  1491. for (i = 0; cap && new; i++, cap >>= 1) {
  1492. if (!(cap & BIT(0)))
  1493. continue;
  1494. if (new & BIT(0))
  1495. filled |= BIT(i);
  1496. new >>= 1;
  1497. }
  1498. return filled;
  1499. }
  1500. static bool validate_antenna_mask(struct ath_hw *ah, u32 val)
  1501. {
  1502. switch (val & 0x7) {
  1503. case 0x1:
  1504. case 0x3:
  1505. case 0x7:
  1506. return true;
  1507. case 0x2:
  1508. return (ah->caps.rx_chainmask == 1);
  1509. default:
  1510. return false;
  1511. }
  1512. }
  1513. static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
  1514. {
  1515. struct ath_softc *sc = hw->priv;
  1516. struct ath_hw *ah = sc->sc_ah;
  1517. if (ah->caps.rx_chainmask != 1)
  1518. rx_ant |= tx_ant;
  1519. if (!validate_antenna_mask(ah, rx_ant) || !tx_ant)
  1520. return -EINVAL;
  1521. sc->ant_rx = rx_ant;
  1522. sc->ant_tx = tx_ant;
  1523. if (ah->caps.rx_chainmask == 1)
  1524. return 0;
  1525. /* AR9100 runs into calibration issues if not all rx chains are enabled */
  1526. if (AR_SREV_9100(ah))
  1527. ah->rxchainmask = 0x7;
  1528. else
  1529. ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant);
  1530. ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant);
  1531. ath9k_reload_chainmask_settings(sc);
  1532. return 0;
  1533. }
  1534. static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
  1535. {
  1536. struct ath_softc *sc = hw->priv;
  1537. *tx_ant = sc->ant_tx;
  1538. *rx_ant = sc->ant_rx;
  1539. return 0;
  1540. }
  1541. #ifdef CONFIG_ATH9K_DEBUGFS
  1542. /* Ethtool support for get-stats */
  1543. #define AMKSTR(nm) #nm "_BE", #nm "_BK", #nm "_VI", #nm "_VO"
  1544. static const char ath9k_gstrings_stats[][ETH_GSTRING_LEN] = {
  1545. "tx_pkts_nic",
  1546. "tx_bytes_nic",
  1547. "rx_pkts_nic",
  1548. "rx_bytes_nic",
  1549. AMKSTR(d_tx_pkts),
  1550. AMKSTR(d_tx_bytes),
  1551. AMKSTR(d_tx_mpdus_queued),
  1552. AMKSTR(d_tx_mpdus_completed),
  1553. AMKSTR(d_tx_mpdu_xretries),
  1554. AMKSTR(d_tx_aggregates),
  1555. AMKSTR(d_tx_ampdus_queued_hw),
  1556. AMKSTR(d_tx_ampdus_queued_sw),
  1557. AMKSTR(d_tx_ampdus_completed),
  1558. AMKSTR(d_tx_ampdu_retries),
  1559. AMKSTR(d_tx_ampdu_xretries),
  1560. AMKSTR(d_tx_fifo_underrun),
  1561. AMKSTR(d_tx_op_exceeded),
  1562. AMKSTR(d_tx_timer_expiry),
  1563. AMKSTR(d_tx_desc_cfg_err),
  1564. AMKSTR(d_tx_data_underrun),
  1565. AMKSTR(d_tx_delim_underrun),
  1566. "d_rx_decrypt_crc_err",
  1567. "d_rx_phy_err",
  1568. "d_rx_mic_err",
  1569. "d_rx_pre_delim_crc_err",
  1570. "d_rx_post_delim_crc_err",
  1571. "d_rx_decrypt_busy_err",
  1572. "d_rx_phyerr_radar",
  1573. "d_rx_phyerr_ofdm_timing",
  1574. "d_rx_phyerr_cck_timing",
  1575. };
  1576. #define ATH9K_SSTATS_LEN ARRAY_SIZE(ath9k_gstrings_stats)
  1577. static void ath9k_get_et_strings(struct ieee80211_hw *hw,
  1578. struct ieee80211_vif *vif,
  1579. u32 sset, u8 *data)
  1580. {
  1581. if (sset == ETH_SS_STATS)
  1582. memcpy(data, *ath9k_gstrings_stats,
  1583. sizeof(ath9k_gstrings_stats));
  1584. }
  1585. static int ath9k_get_et_sset_count(struct ieee80211_hw *hw,
  1586. struct ieee80211_vif *vif, int sset)
  1587. {
  1588. if (sset == ETH_SS_STATS)
  1589. return ATH9K_SSTATS_LEN;
  1590. return 0;
  1591. }
  1592. #define PR_QNUM(_n) (sc->tx.txq_map[_n]->axq_qnum)
  1593. #define AWDATA(elem) \
  1594. do { \
  1595. data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_BE)].elem; \
  1596. data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_BK)].elem; \
  1597. data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_VI)].elem; \
  1598. data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_VO)].elem; \
  1599. } while (0)
  1600. #define AWDATA_RX(elem) \
  1601. do { \
  1602. data[i++] = sc->debug.stats.rxstats.elem; \
  1603. } while (0)
  1604. static void ath9k_get_et_stats(struct ieee80211_hw *hw,
  1605. struct ieee80211_vif *vif,
  1606. struct ethtool_stats *stats, u64 *data)
  1607. {
  1608. struct ath_softc *sc = hw->priv;
  1609. int i = 0;
  1610. data[i++] = (sc->debug.stats.txstats[PR_QNUM(WME_AC_BE)].tx_pkts_all +
  1611. sc->debug.stats.txstats[PR_QNUM(WME_AC_BK)].tx_pkts_all +
  1612. sc->debug.stats.txstats[PR_QNUM(WME_AC_VI)].tx_pkts_all +
  1613. sc->debug.stats.txstats[PR_QNUM(WME_AC_VO)].tx_pkts_all);
  1614. data[i++] = (sc->debug.stats.txstats[PR_QNUM(WME_AC_BE)].tx_bytes_all +
  1615. sc->debug.stats.txstats[PR_QNUM(WME_AC_BK)].tx_bytes_all +
  1616. sc->debug.stats.txstats[PR_QNUM(WME_AC_VI)].tx_bytes_all +
  1617. sc->debug.stats.txstats[PR_QNUM(WME_AC_VO)].tx_bytes_all);
  1618. AWDATA_RX(rx_pkts_all);
  1619. AWDATA_RX(rx_bytes_all);
  1620. AWDATA(tx_pkts_all);
  1621. AWDATA(tx_bytes_all);
  1622. AWDATA(queued);
  1623. AWDATA(completed);
  1624. AWDATA(xretries);
  1625. AWDATA(a_aggr);
  1626. AWDATA(a_queued_hw);
  1627. AWDATA(a_queued_sw);
  1628. AWDATA(a_completed);
  1629. AWDATA(a_retries);
  1630. AWDATA(a_xretries);
  1631. AWDATA(fifo_underrun);
  1632. AWDATA(xtxop);
  1633. AWDATA(timer_exp);
  1634. AWDATA(desc_cfg_err);
  1635. AWDATA(data_underrun);
  1636. AWDATA(delim_underrun);
  1637. AWDATA_RX(decrypt_crc_err);
  1638. AWDATA_RX(phy_err);
  1639. AWDATA_RX(mic_err);
  1640. AWDATA_RX(pre_delim_crc_err);
  1641. AWDATA_RX(post_delim_crc_err);
  1642. AWDATA_RX(decrypt_busy_err);
  1643. AWDATA_RX(phy_err_stats[ATH9K_PHYERR_RADAR]);
  1644. AWDATA_RX(phy_err_stats[ATH9K_PHYERR_OFDM_TIMING]);
  1645. AWDATA_RX(phy_err_stats[ATH9K_PHYERR_CCK_TIMING]);
  1646. WARN_ON(i != ATH9K_SSTATS_LEN);
  1647. }
  1648. /* End of ethtool get-stats functions */
  1649. #endif
  1650. #ifdef CONFIG_PM_SLEEP
  1651. static void ath9k_wow_map_triggers(struct ath_softc *sc,
  1652. struct cfg80211_wowlan *wowlan,
  1653. u32 *wow_triggers)
  1654. {
  1655. if (wowlan->disconnect)
  1656. *wow_triggers |= AH_WOW_LINK_CHANGE |
  1657. AH_WOW_BEACON_MISS;
  1658. if (wowlan->magic_pkt)
  1659. *wow_triggers |= AH_WOW_MAGIC_PATTERN_EN;
  1660. if (wowlan->n_patterns)
  1661. *wow_triggers |= AH_WOW_USER_PATTERN_EN;
  1662. sc->wow_enabled = *wow_triggers;
  1663. }
  1664. static void ath9k_wow_add_disassoc_deauth_pattern(struct ath_softc *sc)
  1665. {
  1666. struct ath_hw *ah = sc->sc_ah;
  1667. struct ath_common *common = ath9k_hw_common(ah);
  1668. struct ath9k_hw_capabilities *pcaps = &ah->caps;
  1669. int pattern_count = 0;
  1670. int i, byte_cnt;
  1671. u8 dis_deauth_pattern[MAX_PATTERN_SIZE];
  1672. u8 dis_deauth_mask[MAX_PATTERN_SIZE];
  1673. memset(dis_deauth_pattern, 0, MAX_PATTERN_SIZE);
  1674. memset(dis_deauth_mask, 0, MAX_PATTERN_SIZE);
  1675. /*
  1676. * Create Dissassociate / Deauthenticate packet filter
  1677. *
  1678. * 2 bytes 2 byte 6 bytes 6 bytes 6 bytes
  1679. * +--------------+----------+---------+--------+--------+----
  1680. * + Frame Control+ Duration + DA + SA + BSSID +
  1681. * +--------------+----------+---------+--------+--------+----
  1682. *
  1683. * The above is the management frame format for disassociate/
  1684. * deauthenticate pattern, from this we need to match the first byte
  1685. * of 'Frame Control' and DA, SA, and BSSID fields
  1686. * (skipping 2nd byte of FC and Duration feild.
  1687. *
  1688. * Disassociate pattern
  1689. * --------------------
  1690. * Frame control = 00 00 1010
  1691. * DA, SA, BSSID = x:x:x:x:x:x
  1692. * Pattern will be A0000000 | x:x:x:x:x:x | x:x:x:x:x:x
  1693. * | x:x:x:x:x:x -- 22 bytes
  1694. *
  1695. * Deauthenticate pattern
  1696. * ----------------------
  1697. * Frame control = 00 00 1100
  1698. * DA, SA, BSSID = x:x:x:x:x:x
  1699. * Pattern will be C0000000 | x:x:x:x:x:x | x:x:x:x:x:x
  1700. * | x:x:x:x:x:x -- 22 bytes
  1701. */
  1702. /* Create Disassociate Pattern first */
  1703. byte_cnt = 0;
  1704. /* Fill out the mask with all FF's */
  1705. for (i = 0; i < MAX_PATTERN_MASK_SIZE; i++)
  1706. dis_deauth_mask[i] = 0xff;
  1707. /* copy the first byte of frame control field */
  1708. dis_deauth_pattern[byte_cnt] = 0xa0;
  1709. byte_cnt++;
  1710. /* skip 2nd byte of frame control and Duration field */
  1711. byte_cnt += 3;
  1712. /*
  1713. * need not match the destination mac address, it can be a broadcast
  1714. * mac address or an unicast to this station
  1715. */
  1716. byte_cnt += 6;
  1717. /* copy the source mac address */
  1718. memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN);
  1719. byte_cnt += 6;
  1720. /* copy the bssid, its same as the source mac address */
  1721. memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN);
  1722. /* Create Disassociate pattern mask */
  1723. if (pcaps->hw_caps & ATH9K_HW_WOW_PATTERN_MATCH_EXACT) {
  1724. if (pcaps->hw_caps & ATH9K_HW_WOW_PATTERN_MATCH_DWORD) {
  1725. /*
  1726. * for AR9280, because of hardware limitation, the
  1727. * first 4 bytes have to be matched for all patterns.
  1728. * the mask for disassociation and de-auth pattern
  1729. * matching need to enable the first 4 bytes.
  1730. * also the duration field needs to be filled.
  1731. */
  1732. dis_deauth_mask[0] = 0xf0;
  1733. /*
  1734. * fill in duration field
  1735. FIXME: what is the exact value ?
  1736. */
  1737. dis_deauth_pattern[2] = 0xff;
  1738. dis_deauth_pattern[3] = 0xff;
  1739. } else {
  1740. dis_deauth_mask[0] = 0xfe;
  1741. }
  1742. dis_deauth_mask[1] = 0x03;
  1743. dis_deauth_mask[2] = 0xc0;
  1744. } else {
  1745. dis_deauth_mask[0] = 0xef;
  1746. dis_deauth_mask[1] = 0x3f;
  1747. dis_deauth_mask[2] = 0x00;
  1748. dis_deauth_mask[3] = 0xfc;
  1749. }
  1750. ath_dbg(common, WOW, "Adding disassoc/deauth patterns for WoW\n");
  1751. ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask,
  1752. pattern_count, byte_cnt);
  1753. pattern_count++;
  1754. /*
  1755. * for de-authenticate pattern, only the first byte of the frame
  1756. * control field gets changed from 0xA0 to 0xC0
  1757. */
  1758. dis_deauth_pattern[0] = 0xC0;
  1759. ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask,
  1760. pattern_count, byte_cnt);
  1761. }
  1762. static void ath9k_wow_add_pattern(struct ath_softc *sc,
  1763. struct cfg80211_wowlan *wowlan)
  1764. {
  1765. struct ath_hw *ah = sc->sc_ah;
  1766. struct ath9k_wow_pattern *wow_pattern = NULL;
  1767. struct cfg80211_wowlan_trig_pkt_pattern *patterns = wowlan->patterns;
  1768. int mask_len;
  1769. s8 i = 0;
  1770. if (!wowlan->n_patterns)
  1771. return;
  1772. /*
  1773. * Add the new user configured patterns
  1774. */
  1775. for (i = 0; i < wowlan->n_patterns; i++) {
  1776. wow_pattern = kzalloc(sizeof(*wow_pattern), GFP_KERNEL);
  1777. if (!wow_pattern)
  1778. return;
  1779. /*
  1780. * TODO: convert the generic user space pattern to
  1781. * appropriate chip specific/802.11 pattern.
  1782. */
  1783. mask_len = DIV_ROUND_UP(wowlan->patterns[i].pattern_len, 8);
  1784. memset(wow_pattern->pattern_bytes, 0, MAX_PATTERN_SIZE);
  1785. memset(wow_pattern->mask_bytes, 0, MAX_PATTERN_SIZE);
  1786. memcpy(wow_pattern->pattern_bytes, patterns[i].pattern,
  1787. patterns[i].pattern_len);
  1788. memcpy(wow_pattern->mask_bytes, patterns[i].mask, mask_len);
  1789. wow_pattern->pattern_len = patterns[i].pattern_len;
  1790. /*
  1791. * just need to take care of deauth and disssoc pattern,
  1792. * make sure we don't overwrite them.
  1793. */
  1794. ath9k_hw_wow_apply_pattern(ah, wow_pattern->pattern_bytes,
  1795. wow_pattern->mask_bytes,
  1796. i + 2,
  1797. wow_pattern->pattern_len);
  1798. kfree(wow_pattern);
  1799. }
  1800. }
  1801. static int ath9k_suspend(struct ieee80211_hw *hw,
  1802. struct cfg80211_wowlan *wowlan)
  1803. {
  1804. struct ath_softc *sc = hw->priv;
  1805. struct ath_hw *ah = sc->sc_ah;
  1806. struct ath_common *common = ath9k_hw_common(ah);
  1807. u32 wow_triggers_enabled = 0;
  1808. int ret = 0;
  1809. mutex_lock(&sc->mutex);
  1810. ath_cancel_work(sc);
  1811. del_timer_sync(&common->ani.timer);
  1812. del_timer_sync(&sc->rx_poll_timer);
  1813. if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
  1814. ath_dbg(common, ANY, "Device not present\n");
  1815. ret = -EINVAL;
  1816. goto fail_wow;
  1817. }
  1818. if (WARN_ON(!wowlan)) {
  1819. ath_dbg(common, WOW, "None of the WoW triggers enabled\n");
  1820. ret = -EINVAL;
  1821. goto fail_wow;
  1822. }
  1823. if (!device_can_wakeup(sc->dev)) {
  1824. ath_dbg(common, WOW, "device_can_wakeup failed, WoW is not enabled\n");
  1825. ret = 1;
  1826. goto fail_wow;
  1827. }
  1828. /*
  1829. * none of the sta vifs are associated
  1830. * and we are not currently handling multivif
  1831. * cases, for instance we have to seperately
  1832. * configure 'keep alive frame' for each
  1833. * STA.
  1834. */
  1835. if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
  1836. ath_dbg(common, WOW, "None of the STA vifs are associated\n");
  1837. ret = 1;
  1838. goto fail_wow;
  1839. }
  1840. if (sc->nvifs > 1) {
  1841. ath_dbg(common, WOW, "WoW for multivif is not yet supported\n");
  1842. ret = 1;
  1843. goto fail_wow;
  1844. }
  1845. ath9k_wow_map_triggers(sc, wowlan, &wow_triggers_enabled);
  1846. ath_dbg(common, WOW, "WoW triggers enabled 0x%x\n",
  1847. wow_triggers_enabled);
  1848. ath9k_ps_wakeup(sc);
  1849. ath9k_stop_btcoex(sc);
  1850. /*
  1851. * Enable wake up on recieving disassoc/deauth
  1852. * frame by default.
  1853. */
  1854. ath9k_wow_add_disassoc_deauth_pattern(sc);
  1855. if (wow_triggers_enabled & AH_WOW_USER_PATTERN_EN)
  1856. ath9k_wow_add_pattern(sc, wowlan);
  1857. spin_lock_bh(&sc->sc_pcu_lock);
  1858. /*
  1859. * To avoid false wake, we enable beacon miss interrupt only
  1860. * when we go to sleep. We save the current interrupt mask
  1861. * so we can restore it after the system wakes up
  1862. */
  1863. sc->wow_intr_before_sleep = ah->imask;
  1864. ah->imask &= ~ATH9K_INT_GLOBAL;
  1865. ath9k_hw_disable_interrupts(ah);
  1866. ah->imask = ATH9K_INT_BMISS | ATH9K_INT_GLOBAL;
  1867. ath9k_hw_set_interrupts(ah);
  1868. ath9k_hw_enable_interrupts(ah);
  1869. spin_unlock_bh(&sc->sc_pcu_lock);
  1870. /*
  1871. * we can now sync irq and kill any running tasklets, since we already
  1872. * disabled interrupts and not holding a spin lock
  1873. */
  1874. synchronize_irq(sc->irq);
  1875. tasklet_kill(&sc->intr_tq);
  1876. ath9k_hw_wow_enable(ah, wow_triggers_enabled);
  1877. ath9k_ps_restore(sc);
  1878. ath_dbg(common, ANY, "WoW enabled in ath9k\n");
  1879. atomic_inc(&sc->wow_sleep_proc_intr);
  1880. fail_wow:
  1881. mutex_unlock(&sc->mutex);
  1882. return ret;
  1883. }
  1884. static int ath9k_resume(struct ieee80211_hw *hw)
  1885. {
  1886. struct ath_softc *sc = hw->priv;
  1887. struct ath_hw *ah = sc->sc_ah;
  1888. struct ath_common *common = ath9k_hw_common(ah);
  1889. u32 wow_status;
  1890. mutex_lock(&sc->mutex);
  1891. ath9k_ps_wakeup(sc);
  1892. spin_lock_bh(&sc->sc_pcu_lock);
  1893. ath9k_hw_disable_interrupts(ah);
  1894. ah->imask = sc->wow_intr_before_sleep;
  1895. ath9k_hw_set_interrupts(ah);
  1896. ath9k_hw_enable_interrupts(ah);
  1897. spin_unlock_bh(&sc->sc_pcu_lock);
  1898. wow_status = ath9k_hw_wow_wakeup(ah);
  1899. if (atomic_read(&sc->wow_got_bmiss_intr) == 0) {
  1900. /*
  1901. * some devices may not pick beacon miss
  1902. * as the reason they woke up so we add
  1903. * that here for that shortcoming.
  1904. */
  1905. wow_status |= AH_WOW_BEACON_MISS;
  1906. atomic_dec(&sc->wow_got_bmiss_intr);
  1907. ath_dbg(common, ANY, "Beacon miss interrupt picked up during WoW sleep\n");
  1908. }
  1909. atomic_dec(&sc->wow_sleep_proc_intr);
  1910. if (wow_status) {
  1911. ath_dbg(common, ANY, "Waking up due to WoW triggers %s with WoW status = %x\n",
  1912. ath9k_hw_wow_event_to_string(wow_status), wow_status);
  1913. }
  1914. ath_restart_work(sc);
  1915. ath9k_start_btcoex(sc);
  1916. ath9k_ps_restore(sc);
  1917. mutex_unlock(&sc->mutex);
  1918. return 0;
  1919. }
  1920. static void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled)
  1921. {
  1922. struct ath_softc *sc = hw->priv;
  1923. mutex_lock(&sc->mutex);
  1924. device_init_wakeup(sc->dev, 1);
  1925. device_set_wakeup_enable(sc->dev, enabled);
  1926. mutex_unlock(&sc->mutex);
  1927. }
  1928. #endif
  1929. struct ieee80211_ops ath9k_ops = {
  1930. .tx = ath9k_tx,
  1931. .start = ath9k_start,
  1932. .stop = ath9k_stop,
  1933. .add_interface = ath9k_add_interface,
  1934. .change_interface = ath9k_change_interface,
  1935. .remove_interface = ath9k_remove_interface,
  1936. .config = ath9k_config,
  1937. .configure_filter = ath9k_configure_filter,
  1938. .sta_add = ath9k_sta_add,
  1939. .sta_remove = ath9k_sta_remove,
  1940. .sta_notify = ath9k_sta_notify,
  1941. .conf_tx = ath9k_conf_tx,
  1942. .bss_info_changed = ath9k_bss_info_changed,
  1943. .set_key = ath9k_set_key,
  1944. .get_tsf = ath9k_get_tsf,
  1945. .set_tsf = ath9k_set_tsf,
  1946. .reset_tsf = ath9k_reset_tsf,
  1947. .ampdu_action = ath9k_ampdu_action,
  1948. .get_survey = ath9k_get_survey,
  1949. .rfkill_poll = ath9k_rfkill_poll_state,
  1950. .set_coverage_class = ath9k_set_coverage_class,
  1951. .flush = ath9k_flush,
  1952. .tx_frames_pending = ath9k_tx_frames_pending,
  1953. .tx_last_beacon = ath9k_tx_last_beacon,
  1954. .get_stats = ath9k_get_stats,
  1955. .set_antenna = ath9k_set_antenna,
  1956. .get_antenna = ath9k_get_antenna,
  1957. #ifdef CONFIG_PM_SLEEP
  1958. .suspend = ath9k_suspend,
  1959. .resume = ath9k_resume,
  1960. .set_wakeup = ath9k_set_wakeup,
  1961. #endif
  1962. #ifdef CONFIG_ATH9K_DEBUGFS
  1963. .get_et_sset_count = ath9k_get_et_sset_count,
  1964. .get_et_stats = ath9k_get_et_stats,
  1965. .get_et_strings = ath9k_get_et_strings,
  1966. #endif
  1967. };