qla_isr.c 81 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873187418751876187718781879188018811882188318841885188618871888188918901891189218931894189518961897189818991900190119021903190419051906190719081909191019111912191319141915191619171918191919201921192219231924192519261927192819291930193119321933193419351936193719381939194019411942194319441945194619471948194919501951195219531954195519561957195819591960196119621963196419651966196719681969197019711972197319741975197619771978197919801981198219831984198519861987198819891990199119921993199419951996199719981999200020012002200320042005200620072008200920102011201220132014201520162017201820192020202120222023202420252026202720282029203020312032203320342035203620372038203920402041204220432044204520462047204820492050205120522053205420552056205720582059206020612062206320642065206620672068206920702071207220732074207520762077207820792080208120822083208420852086208720882089209020912092209320942095209620972098209921002101210221032104210521062107210821092110211121122113211421152116211721182119212021212122212321242125212621272128212921302131213221332134213521362137213821392140214121422143214421452146214721482149215021512152215321542155215621572158215921602161216221632164216521662167216821692170217121722173217421752176217721782179218021812182218321842185218621872188218921902191219221932194219521962197219821992200220122022203220422052206220722082209221022112212221322142215221622172218221922202221222222232224222522262227222822292230223122322233223422352236223722382239224022412242224322442245224622472248224922502251225222532254225522562257225822592260226122622263226422652266226722682269227022712272227322742275227622772278227922802281228222832284228522862287228822892290229122922293229422952296229722982299230023012302230323042305230623072308230923102311231223132314231523162317231823192320232123222323232423252326232723282329233023312332233323342335233623372338233923402341234223432344234523462347234823492350235123522353235423552356235723582359236023612362236323642365236623672368236923702371237223732374237523762377237823792380238123822383238423852386238723882389239023912392239323942395239623972398239924002401240224032404240524062407240824092410241124122413241424152416241724182419242024212422242324242425242624272428242924302431243224332434243524362437243824392440244124422443244424452446244724482449245024512452245324542455245624572458245924602461246224632464246524662467246824692470247124722473247424752476247724782479248024812482248324842485248624872488248924902491249224932494249524962497249824992500250125022503250425052506250725082509251025112512251325142515251625172518251925202521252225232524252525262527252825292530253125322533253425352536253725382539254025412542254325442545254625472548254925502551255225532554255525562557255825592560256125622563256425652566256725682569257025712572257325742575257625772578257925802581258225832584258525862587258825892590259125922593259425952596259725982599260026012602260326042605260626072608260926102611261226132614261526162617261826192620262126222623262426252626262726282629263026312632263326342635263626372638263926402641264226432644264526462647264826492650265126522653265426552656265726582659266026612662266326642665266626672668266926702671267226732674267526762677267826792680268126822683268426852686268726882689269026912692269326942695269626972698269927002701270227032704270527062707270827092710271127122713271427152716271727182719272027212722272327242725272627272728272927302731273227332734273527362737273827392740274127422743274427452746274727482749275027512752275327542755275627572758275927602761276227632764276527662767276827692770277127722773277427752776277727782779278027812782278327842785278627872788278927902791279227932794279527962797279827992800280128022803280428052806280728082809281028112812281328142815281628172818281928202821282228232824282528262827282828292830283128322833283428352836283728382839284028412842284328442845284628472848284928502851285228532854285528562857285828592860286128622863286428652866286728682869287028712872287328742875287628772878287928802881288228832884288528862887288828892890289128922893289428952896289728982899290029012902290329042905290629072908290929102911291229132914291529162917291829192920292129222923292429252926292729282929293029312932293329342935293629372938293929402941294229432944294529462947294829492950295129522953295429552956295729582959296029612962296329642965296629672968296929702971297229732974297529762977297829792980298129822983298429852986298729882989299029912992299329942995299629972998299930003001300230033004300530063007300830093010301130123013301430153016
  1. /*
  2. * QLogic Fibre Channel HBA Driver
  3. * Copyright (c) 2003-2012 QLogic Corporation
  4. *
  5. * See LICENSE.qla2xxx for copyright and licensing details.
  6. */
  7. #include "qla_def.h"
  8. #include "qla_target.h"
  9. #include <linux/delay.h>
  10. #include <linux/slab.h>
  11. #include <scsi/scsi_tcq.h>
  12. #include <scsi/scsi_bsg_fc.h>
  13. #include <scsi/scsi_eh.h>
  14. #include "qla_target.h"
  15. static void qla2x00_mbx_completion(scsi_qla_host_t *, uint16_t);
  16. static void qla2x00_process_completed_request(struct scsi_qla_host *,
  17. struct req_que *, uint32_t);
  18. static void qla2x00_status_entry(scsi_qla_host_t *, struct rsp_que *, void *);
  19. static void qla2x00_status_cont_entry(struct rsp_que *, sts_cont_entry_t *);
  20. static void qla2x00_error_entry(scsi_qla_host_t *, struct rsp_que *,
  21. sts_entry_t *);
  22. /**
  23. * qla2100_intr_handler() - Process interrupts for the ISP2100 and ISP2200.
  24. * @irq:
  25. * @dev_id: SCSI driver HA context
  26. *
  27. * Called by system whenever the host adapter generates an interrupt.
  28. *
  29. * Returns handled flag.
  30. */
  31. irqreturn_t
  32. qla2100_intr_handler(int irq, void *dev_id)
  33. {
  34. scsi_qla_host_t *vha;
  35. struct qla_hw_data *ha;
  36. struct device_reg_2xxx __iomem *reg;
  37. int status;
  38. unsigned long iter;
  39. uint16_t hccr;
  40. uint16_t mb[4];
  41. struct rsp_que *rsp;
  42. unsigned long flags;
  43. rsp = (struct rsp_que *) dev_id;
  44. if (!rsp) {
  45. ql_log(ql_log_info, NULL, 0x505d,
  46. "%s: NULL response queue pointer.\n", __func__);
  47. return (IRQ_NONE);
  48. }
  49. ha = rsp->hw;
  50. reg = &ha->iobase->isp;
  51. status = 0;
  52. spin_lock_irqsave(&ha->hardware_lock, flags);
  53. vha = pci_get_drvdata(ha->pdev);
  54. for (iter = 50; iter--; ) {
  55. hccr = RD_REG_WORD(&reg->hccr);
  56. if (hccr & HCCR_RISC_PAUSE) {
  57. if (pci_channel_offline(ha->pdev))
  58. break;
  59. /*
  60. * Issue a "HARD" reset in order for the RISC interrupt
  61. * bit to be cleared. Schedule a big hammer to get
  62. * out of the RISC PAUSED state.
  63. */
  64. WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
  65. RD_REG_WORD(&reg->hccr);
  66. ha->isp_ops->fw_dump(vha, 1);
  67. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  68. break;
  69. } else if ((RD_REG_WORD(&reg->istatus) & ISR_RISC_INT) == 0)
  70. break;
  71. if (RD_REG_WORD(&reg->semaphore) & BIT_0) {
  72. WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
  73. RD_REG_WORD(&reg->hccr);
  74. /* Get mailbox data. */
  75. mb[0] = RD_MAILBOX_REG(ha, reg, 0);
  76. if (mb[0] > 0x3fff && mb[0] < 0x8000) {
  77. qla2x00_mbx_completion(vha, mb[0]);
  78. status |= MBX_INTERRUPT;
  79. } else if (mb[0] > 0x7fff && mb[0] < 0xc000) {
  80. mb[1] = RD_MAILBOX_REG(ha, reg, 1);
  81. mb[2] = RD_MAILBOX_REG(ha, reg, 2);
  82. mb[3] = RD_MAILBOX_REG(ha, reg, 3);
  83. qla2x00_async_event(vha, rsp, mb);
  84. } else {
  85. /*EMPTY*/
  86. ql_dbg(ql_dbg_async, vha, 0x5025,
  87. "Unrecognized interrupt type (%d).\n",
  88. mb[0]);
  89. }
  90. /* Release mailbox registers. */
  91. WRT_REG_WORD(&reg->semaphore, 0);
  92. RD_REG_WORD(&reg->semaphore);
  93. } else {
  94. qla2x00_process_response_queue(rsp);
  95. WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
  96. RD_REG_WORD(&reg->hccr);
  97. }
  98. }
  99. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  100. if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) &&
  101. (status & MBX_INTERRUPT) && ha->flags.mbox_int) {
  102. set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
  103. complete(&ha->mbx_intr_comp);
  104. }
  105. return (IRQ_HANDLED);
  106. }
  107. /**
  108. * qla2300_intr_handler() - Process interrupts for the ISP23xx and ISP63xx.
  109. * @irq:
  110. * @dev_id: SCSI driver HA context
  111. *
  112. * Called by system whenever the host adapter generates an interrupt.
  113. *
  114. * Returns handled flag.
  115. */
  116. irqreturn_t
  117. qla2300_intr_handler(int irq, void *dev_id)
  118. {
  119. scsi_qla_host_t *vha;
  120. struct device_reg_2xxx __iomem *reg;
  121. int status;
  122. unsigned long iter;
  123. uint32_t stat;
  124. uint16_t hccr;
  125. uint16_t mb[4];
  126. struct rsp_que *rsp;
  127. struct qla_hw_data *ha;
  128. unsigned long flags;
  129. rsp = (struct rsp_que *) dev_id;
  130. if (!rsp) {
  131. ql_log(ql_log_info, NULL, 0x5058,
  132. "%s: NULL response queue pointer.\n", __func__);
  133. return (IRQ_NONE);
  134. }
  135. ha = rsp->hw;
  136. reg = &ha->iobase->isp;
  137. status = 0;
  138. spin_lock_irqsave(&ha->hardware_lock, flags);
  139. vha = pci_get_drvdata(ha->pdev);
  140. for (iter = 50; iter--; ) {
  141. stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
  142. if (stat & HSR_RISC_PAUSED) {
  143. if (unlikely(pci_channel_offline(ha->pdev)))
  144. break;
  145. hccr = RD_REG_WORD(&reg->hccr);
  146. if (hccr & (BIT_15 | BIT_13 | BIT_11 | BIT_8))
  147. ql_log(ql_log_warn, vha, 0x5026,
  148. "Parity error -- HCCR=%x, Dumping "
  149. "firmware.\n", hccr);
  150. else
  151. ql_log(ql_log_warn, vha, 0x5027,
  152. "RISC paused -- HCCR=%x, Dumping "
  153. "firmware.\n", hccr);
  154. /*
  155. * Issue a "HARD" reset in order for the RISC
  156. * interrupt bit to be cleared. Schedule a big
  157. * hammer to get out of the RISC PAUSED state.
  158. */
  159. WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
  160. RD_REG_WORD(&reg->hccr);
  161. ha->isp_ops->fw_dump(vha, 1);
  162. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  163. break;
  164. } else if ((stat & HSR_RISC_INT) == 0)
  165. break;
  166. switch (stat & 0xff) {
  167. case 0x1:
  168. case 0x2:
  169. case 0x10:
  170. case 0x11:
  171. qla2x00_mbx_completion(vha, MSW(stat));
  172. status |= MBX_INTERRUPT;
  173. /* Release mailbox registers. */
  174. WRT_REG_WORD(&reg->semaphore, 0);
  175. break;
  176. case 0x12:
  177. mb[0] = MSW(stat);
  178. mb[1] = RD_MAILBOX_REG(ha, reg, 1);
  179. mb[2] = RD_MAILBOX_REG(ha, reg, 2);
  180. mb[3] = RD_MAILBOX_REG(ha, reg, 3);
  181. qla2x00_async_event(vha, rsp, mb);
  182. break;
  183. case 0x13:
  184. qla2x00_process_response_queue(rsp);
  185. break;
  186. case 0x15:
  187. mb[0] = MBA_CMPLT_1_16BIT;
  188. mb[1] = MSW(stat);
  189. qla2x00_async_event(vha, rsp, mb);
  190. break;
  191. case 0x16:
  192. mb[0] = MBA_SCSI_COMPLETION;
  193. mb[1] = MSW(stat);
  194. mb[2] = RD_MAILBOX_REG(ha, reg, 2);
  195. qla2x00_async_event(vha, rsp, mb);
  196. break;
  197. default:
  198. ql_dbg(ql_dbg_async, vha, 0x5028,
  199. "Unrecognized interrupt type (%d).\n", stat & 0xff);
  200. break;
  201. }
  202. WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
  203. RD_REG_WORD_RELAXED(&reg->hccr);
  204. }
  205. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  206. if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) &&
  207. (status & MBX_INTERRUPT) && ha->flags.mbox_int) {
  208. set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
  209. complete(&ha->mbx_intr_comp);
  210. }
  211. return (IRQ_HANDLED);
  212. }
  213. /**
  214. * qla2x00_mbx_completion() - Process mailbox command completions.
  215. * @ha: SCSI driver HA context
  216. * @mb0: Mailbox0 register
  217. */
  218. static void
  219. qla2x00_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0)
  220. {
  221. uint16_t cnt;
  222. uint32_t mboxes;
  223. uint16_t __iomem *wptr;
  224. struct qla_hw_data *ha = vha->hw;
  225. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  226. /* Read all mbox registers? */
  227. mboxes = (1 << ha->mbx_count) - 1;
  228. if (!ha->mcp)
  229. ql_dbg(ql_dbg_async, vha, 0x5001, "MBX pointer ERROR.\n");
  230. else
  231. mboxes = ha->mcp->in_mb;
  232. /* Load return mailbox registers. */
  233. ha->flags.mbox_int = 1;
  234. ha->mailbox_out[0] = mb0;
  235. mboxes >>= 1;
  236. wptr = (uint16_t __iomem *)MAILBOX_REG(ha, reg, 1);
  237. for (cnt = 1; cnt < ha->mbx_count; cnt++) {
  238. if (IS_QLA2200(ha) && cnt == 8)
  239. wptr = (uint16_t __iomem *)MAILBOX_REG(ha, reg, 8);
  240. if ((cnt == 4 || cnt == 5) && (mboxes & BIT_0))
  241. ha->mailbox_out[cnt] = qla2x00_debounce_register(wptr);
  242. else if (mboxes & BIT_0)
  243. ha->mailbox_out[cnt] = RD_REG_WORD(wptr);
  244. wptr++;
  245. mboxes >>= 1;
  246. }
  247. }
  248. static void
  249. qla81xx_idc_event(scsi_qla_host_t *vha, uint16_t aen, uint16_t descr)
  250. {
  251. static char *event[] =
  252. { "Complete", "Request Notification", "Time Extension" };
  253. int rval;
  254. struct device_reg_24xx __iomem *reg24 = &vha->hw->iobase->isp24;
  255. uint16_t __iomem *wptr;
  256. uint16_t cnt, timeout, mb[QLA_IDC_ACK_REGS];
  257. /* Seed data -- mailbox1 -> mailbox7. */
  258. wptr = (uint16_t __iomem *)&reg24->mailbox1;
  259. for (cnt = 0; cnt < QLA_IDC_ACK_REGS; cnt++, wptr++)
  260. mb[cnt] = RD_REG_WORD(wptr);
  261. ql_dbg(ql_dbg_async, vha, 0x5021,
  262. "Inter-Driver Communication %s -- "
  263. "%04x %04x %04x %04x %04x %04x %04x.\n",
  264. event[aen & 0xff], mb[0], mb[1], mb[2], mb[3],
  265. mb[4], mb[5], mb[6]);
  266. if ((aen == MBA_IDC_COMPLETE && mb[1] >> 15)) {
  267. vha->hw->flags.idc_compl_status = 1;
  268. if (vha->hw->notify_dcbx_comp)
  269. complete(&vha->hw->dcbx_comp);
  270. }
  271. /* Acknowledgement needed? [Notify && non-zero timeout]. */
  272. timeout = (descr >> 8) & 0xf;
  273. if (aen != MBA_IDC_NOTIFY || !timeout)
  274. return;
  275. ql_dbg(ql_dbg_async, vha, 0x5022,
  276. "%lu Inter-Driver Communication %s -- ACK timeout=%d.\n",
  277. vha->host_no, event[aen & 0xff], timeout);
  278. rval = qla2x00_post_idc_ack_work(vha, mb);
  279. if (rval != QLA_SUCCESS)
  280. ql_log(ql_log_warn, vha, 0x5023,
  281. "IDC failed to post ACK.\n");
  282. }
  283. #define LS_UNKNOWN 2
  284. const char *
  285. qla2x00_get_link_speed_str(struct qla_hw_data *ha, uint16_t speed)
  286. {
  287. static const char * const link_speeds[] = {
  288. "1", "2", "?", "4", "8", "16", "10"
  289. };
  290. if (IS_QLA2100(ha) || IS_QLA2200(ha))
  291. return link_speeds[0];
  292. else if (speed == 0x13)
  293. return link_speeds[6];
  294. else if (speed < 6)
  295. return link_speeds[speed];
  296. else
  297. return link_speeds[LS_UNKNOWN];
  298. }
  299. static void
  300. qla83xx_handle_8200_aen(scsi_qla_host_t *vha, uint16_t *mb)
  301. {
  302. struct qla_hw_data *ha = vha->hw;
  303. /*
  304. * 8200 AEN Interpretation:
  305. * mb[0] = AEN code
  306. * mb[1] = AEN Reason code
  307. * mb[2] = LSW of Peg-Halt Status-1 Register
  308. * mb[6] = MSW of Peg-Halt Status-1 Register
  309. * mb[3] = LSW of Peg-Halt Status-2 register
  310. * mb[7] = MSW of Peg-Halt Status-2 register
  311. * mb[4] = IDC Device-State Register value
  312. * mb[5] = IDC Driver-Presence Register value
  313. */
  314. ql_dbg(ql_dbg_async, vha, 0x506b, "AEN Code: mb[0] = 0x%x AEN reason: "
  315. "mb[1] = 0x%x PH-status1: mb[2] = 0x%x PH-status1: mb[6] = 0x%x.\n",
  316. mb[0], mb[1], mb[2], mb[6]);
  317. ql_dbg(ql_dbg_async, vha, 0x506c, "PH-status2: mb[3] = 0x%x "
  318. "PH-status2: mb[7] = 0x%x Device-State: mb[4] = 0x%x "
  319. "Drv-Presence: mb[5] = 0x%x.\n", mb[3], mb[7], mb[4], mb[5]);
  320. if (mb[1] & (IDC_PEG_HALT_STATUS_CHANGE | IDC_NIC_FW_REPORTED_FAILURE |
  321. IDC_HEARTBEAT_FAILURE)) {
  322. ha->flags.nic_core_hung = 1;
  323. ql_log(ql_log_warn, vha, 0x5060,
  324. "83XX: F/W Error Reported: Check if reset required.\n");
  325. if (mb[1] & IDC_PEG_HALT_STATUS_CHANGE) {
  326. uint32_t protocol_engine_id, fw_err_code, err_level;
  327. /*
  328. * IDC_PEG_HALT_STATUS_CHANGE interpretation:
  329. * - PEG-Halt Status-1 Register:
  330. * (LSW = mb[2], MSW = mb[6])
  331. * Bits 0-7 = protocol-engine ID
  332. * Bits 8-28 = f/w error code
  333. * Bits 29-31 = Error-level
  334. * Error-level 0x1 = Non-Fatal error
  335. * Error-level 0x2 = Recoverable Fatal error
  336. * Error-level 0x4 = UnRecoverable Fatal error
  337. * - PEG-Halt Status-2 Register:
  338. * (LSW = mb[3], MSW = mb[7])
  339. */
  340. protocol_engine_id = (mb[2] & 0xff);
  341. fw_err_code = (((mb[2] & 0xff00) >> 8) |
  342. ((mb[6] & 0x1fff) << 8));
  343. err_level = ((mb[6] & 0xe000) >> 13);
  344. ql_log(ql_log_warn, vha, 0x5061, "PegHalt Status-1 "
  345. "Register: protocol_engine_id=0x%x "
  346. "fw_err_code=0x%x err_level=0x%x.\n",
  347. protocol_engine_id, fw_err_code, err_level);
  348. ql_log(ql_log_warn, vha, 0x5062, "PegHalt Status-2 "
  349. "Register: 0x%x%x.\n", mb[7], mb[3]);
  350. if (err_level == ERR_LEVEL_NON_FATAL) {
  351. ql_log(ql_log_warn, vha, 0x5063,
  352. "Not a fatal error, f/w has recovered "
  353. "iteself.\n");
  354. } else if (err_level == ERR_LEVEL_RECOVERABLE_FATAL) {
  355. ql_log(ql_log_fatal, vha, 0x5064,
  356. "Recoverable Fatal error: Chip reset "
  357. "required.\n");
  358. qla83xx_schedule_work(vha,
  359. QLA83XX_NIC_CORE_RESET);
  360. } else if (err_level == ERR_LEVEL_UNRECOVERABLE_FATAL) {
  361. ql_log(ql_log_fatal, vha, 0x5065,
  362. "Unrecoverable Fatal error: Set FAILED "
  363. "state, reboot required.\n");
  364. qla83xx_schedule_work(vha,
  365. QLA83XX_NIC_CORE_UNRECOVERABLE);
  366. }
  367. }
  368. if (mb[1] & IDC_NIC_FW_REPORTED_FAILURE) {
  369. uint16_t peg_fw_state, nw_interface_link_up;
  370. uint16_t nw_interface_signal_detect, sfp_status;
  371. uint16_t htbt_counter, htbt_monitor_enable;
  372. uint16_t sfp_additonal_info, sfp_multirate;
  373. uint16_t sfp_tx_fault, link_speed, dcbx_status;
  374. /*
  375. * IDC_NIC_FW_REPORTED_FAILURE interpretation:
  376. * - PEG-to-FC Status Register:
  377. * (LSW = mb[2], MSW = mb[6])
  378. * Bits 0-7 = Peg-Firmware state
  379. * Bit 8 = N/W Interface Link-up
  380. * Bit 9 = N/W Interface signal detected
  381. * Bits 10-11 = SFP Status
  382. * SFP Status 0x0 = SFP+ transceiver not expected
  383. * SFP Status 0x1 = SFP+ transceiver not present
  384. * SFP Status 0x2 = SFP+ transceiver invalid
  385. * SFP Status 0x3 = SFP+ transceiver present and
  386. * valid
  387. * Bits 12-14 = Heartbeat Counter
  388. * Bit 15 = Heartbeat Monitor Enable
  389. * Bits 16-17 = SFP Additional Info
  390. * SFP info 0x0 = Unregocnized transceiver for
  391. * Ethernet
  392. * SFP info 0x1 = SFP+ brand validation failed
  393. * SFP info 0x2 = SFP+ speed validation failed
  394. * SFP info 0x3 = SFP+ access error
  395. * Bit 18 = SFP Multirate
  396. * Bit 19 = SFP Tx Fault
  397. * Bits 20-22 = Link Speed
  398. * Bits 23-27 = Reserved
  399. * Bits 28-30 = DCBX Status
  400. * DCBX Status 0x0 = DCBX Disabled
  401. * DCBX Status 0x1 = DCBX Enabled
  402. * DCBX Status 0x2 = DCBX Exchange error
  403. * Bit 31 = Reserved
  404. */
  405. peg_fw_state = (mb[2] & 0x00ff);
  406. nw_interface_link_up = ((mb[2] & 0x0100) >> 8);
  407. nw_interface_signal_detect = ((mb[2] & 0x0200) >> 9);
  408. sfp_status = ((mb[2] & 0x0c00) >> 10);
  409. htbt_counter = ((mb[2] & 0x7000) >> 12);
  410. htbt_monitor_enable = ((mb[2] & 0x8000) >> 15);
  411. sfp_additonal_info = (mb[6] & 0x0003);
  412. sfp_multirate = ((mb[6] & 0x0004) >> 2);
  413. sfp_tx_fault = ((mb[6] & 0x0008) >> 3);
  414. link_speed = ((mb[6] & 0x0070) >> 4);
  415. dcbx_status = ((mb[6] & 0x7000) >> 12);
  416. ql_log(ql_log_warn, vha, 0x5066,
  417. "Peg-to-Fc Status Register:\n"
  418. "peg_fw_state=0x%x, nw_interface_link_up=0x%x, "
  419. "nw_interface_signal_detect=0x%x"
  420. "\nsfp_statis=0x%x.\n ", peg_fw_state,
  421. nw_interface_link_up, nw_interface_signal_detect,
  422. sfp_status);
  423. ql_log(ql_log_warn, vha, 0x5067,
  424. "htbt_counter=0x%x, htbt_monitor_enable=0x%x, "
  425. "sfp_additonal_info=0x%x, sfp_multirate=0x%x.\n ",
  426. htbt_counter, htbt_monitor_enable,
  427. sfp_additonal_info, sfp_multirate);
  428. ql_log(ql_log_warn, vha, 0x5068,
  429. "sfp_tx_fault=0x%x, link_state=0x%x, "
  430. "dcbx_status=0x%x.\n", sfp_tx_fault, link_speed,
  431. dcbx_status);
  432. qla83xx_schedule_work(vha, QLA83XX_NIC_CORE_RESET);
  433. }
  434. if (mb[1] & IDC_HEARTBEAT_FAILURE) {
  435. ql_log(ql_log_warn, vha, 0x5069,
  436. "Heartbeat Failure encountered, chip reset "
  437. "required.\n");
  438. qla83xx_schedule_work(vha, QLA83XX_NIC_CORE_RESET);
  439. }
  440. }
  441. if (mb[1] & IDC_DEVICE_STATE_CHANGE) {
  442. ql_log(ql_log_info, vha, 0x506a,
  443. "IDC Device-State changed = 0x%x.\n", mb[4]);
  444. qla83xx_schedule_work(vha, MBA_IDC_AEN);
  445. }
  446. }
  447. /**
  448. * qla2x00_async_event() - Process aynchronous events.
  449. * @ha: SCSI driver HA context
  450. * @mb: Mailbox registers (0 - 3)
  451. */
  452. void
  453. qla2x00_async_event(scsi_qla_host_t *vha, struct rsp_que *rsp, uint16_t *mb)
  454. {
  455. uint16_t handle_cnt;
  456. uint16_t cnt, mbx;
  457. uint32_t handles[5];
  458. struct qla_hw_data *ha = vha->hw;
  459. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  460. struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
  461. struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82;
  462. uint32_t rscn_entry, host_pid;
  463. unsigned long flags;
  464. /* Setup to process RIO completion. */
  465. handle_cnt = 0;
  466. if (IS_CNA_CAPABLE(ha))
  467. goto skip_rio;
  468. switch (mb[0]) {
  469. case MBA_SCSI_COMPLETION:
  470. handles[0] = le32_to_cpu((uint32_t)((mb[2] << 16) | mb[1]));
  471. handle_cnt = 1;
  472. break;
  473. case MBA_CMPLT_1_16BIT:
  474. handles[0] = mb[1];
  475. handle_cnt = 1;
  476. mb[0] = MBA_SCSI_COMPLETION;
  477. break;
  478. case MBA_CMPLT_2_16BIT:
  479. handles[0] = mb[1];
  480. handles[1] = mb[2];
  481. handle_cnt = 2;
  482. mb[0] = MBA_SCSI_COMPLETION;
  483. break;
  484. case MBA_CMPLT_3_16BIT:
  485. handles[0] = mb[1];
  486. handles[1] = mb[2];
  487. handles[2] = mb[3];
  488. handle_cnt = 3;
  489. mb[0] = MBA_SCSI_COMPLETION;
  490. break;
  491. case MBA_CMPLT_4_16BIT:
  492. handles[0] = mb[1];
  493. handles[1] = mb[2];
  494. handles[2] = mb[3];
  495. handles[3] = (uint32_t)RD_MAILBOX_REG(ha, reg, 6);
  496. handle_cnt = 4;
  497. mb[0] = MBA_SCSI_COMPLETION;
  498. break;
  499. case MBA_CMPLT_5_16BIT:
  500. handles[0] = mb[1];
  501. handles[1] = mb[2];
  502. handles[2] = mb[3];
  503. handles[3] = (uint32_t)RD_MAILBOX_REG(ha, reg, 6);
  504. handles[4] = (uint32_t)RD_MAILBOX_REG(ha, reg, 7);
  505. handle_cnt = 5;
  506. mb[0] = MBA_SCSI_COMPLETION;
  507. break;
  508. case MBA_CMPLT_2_32BIT:
  509. handles[0] = le32_to_cpu((uint32_t)((mb[2] << 16) | mb[1]));
  510. handles[1] = le32_to_cpu(
  511. ((uint32_t)(RD_MAILBOX_REG(ha, reg, 7) << 16)) |
  512. RD_MAILBOX_REG(ha, reg, 6));
  513. handle_cnt = 2;
  514. mb[0] = MBA_SCSI_COMPLETION;
  515. break;
  516. default:
  517. break;
  518. }
  519. skip_rio:
  520. switch (mb[0]) {
  521. case MBA_SCSI_COMPLETION: /* Fast Post */
  522. if (!vha->flags.online)
  523. break;
  524. for (cnt = 0; cnt < handle_cnt; cnt++)
  525. qla2x00_process_completed_request(vha, rsp->req,
  526. handles[cnt]);
  527. break;
  528. case MBA_RESET: /* Reset */
  529. ql_dbg(ql_dbg_async, vha, 0x5002,
  530. "Asynchronous RESET.\n");
  531. set_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  532. break;
  533. case MBA_SYSTEM_ERR: /* System Error */
  534. mbx = (IS_QLA81XX(ha) || IS_QLA83XX(ha)) ?
  535. RD_REG_WORD(&reg24->mailbox7) : 0;
  536. ql_log(ql_log_warn, vha, 0x5003,
  537. "ISP System Error - mbx1=%xh mbx2=%xh mbx3=%xh "
  538. "mbx7=%xh.\n", mb[1], mb[2], mb[3], mbx);
  539. ha->isp_ops->fw_dump(vha, 1);
  540. if (IS_FWI2_CAPABLE(ha)) {
  541. if (mb[1] == 0 && mb[2] == 0) {
  542. ql_log(ql_log_fatal, vha, 0x5004,
  543. "Unrecoverable Hardware Error: adapter "
  544. "marked OFFLINE!\n");
  545. vha->flags.online = 0;
  546. vha->device_flags |= DFLG_DEV_FAILED;
  547. } else {
  548. /* Check to see if MPI timeout occurred */
  549. if ((mbx & MBX_3) && (ha->flags.port0))
  550. set_bit(MPI_RESET_NEEDED,
  551. &vha->dpc_flags);
  552. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  553. }
  554. } else if (mb[1] == 0) {
  555. ql_log(ql_log_fatal, vha, 0x5005,
  556. "Unrecoverable Hardware Error: adapter marked "
  557. "OFFLINE!\n");
  558. vha->flags.online = 0;
  559. vha->device_flags |= DFLG_DEV_FAILED;
  560. } else
  561. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  562. break;
  563. case MBA_REQ_TRANSFER_ERR: /* Request Transfer Error */
  564. ql_log(ql_log_warn, vha, 0x5006,
  565. "ISP Request Transfer Error (%x).\n", mb[1]);
  566. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  567. break;
  568. case MBA_RSP_TRANSFER_ERR: /* Response Transfer Error */
  569. ql_log(ql_log_warn, vha, 0x5007,
  570. "ISP Response Transfer Error.\n");
  571. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  572. break;
  573. case MBA_WAKEUP_THRES: /* Request Queue Wake-up */
  574. ql_dbg(ql_dbg_async, vha, 0x5008,
  575. "Asynchronous WAKEUP_THRES.\n");
  576. break;
  577. case MBA_LIP_OCCURRED: /* Loop Initialization Procedure */
  578. ql_dbg(ql_dbg_async, vha, 0x5009,
  579. "LIP occurred (%x).\n", mb[1]);
  580. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  581. atomic_set(&vha->loop_state, LOOP_DOWN);
  582. atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
  583. qla2x00_mark_all_devices_lost(vha, 1);
  584. }
  585. if (vha->vp_idx) {
  586. atomic_set(&vha->vp_state, VP_FAILED);
  587. fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
  588. }
  589. set_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags);
  590. set_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags);
  591. vha->flags.management_server_logged_in = 0;
  592. qla2x00_post_aen_work(vha, FCH_EVT_LIP, mb[1]);
  593. break;
  594. case MBA_LOOP_UP: /* Loop Up Event */
  595. if (IS_QLA2100(ha) || IS_QLA2200(ha))
  596. ha->link_data_rate = PORT_SPEED_1GB;
  597. else
  598. ha->link_data_rate = mb[1];
  599. ql_dbg(ql_dbg_async, vha, 0x500a,
  600. "LOOP UP detected (%s Gbps).\n",
  601. qla2x00_get_link_speed_str(ha, ha->link_data_rate));
  602. vha->flags.management_server_logged_in = 0;
  603. qla2x00_post_aen_work(vha, FCH_EVT_LINKUP, ha->link_data_rate);
  604. break;
  605. case MBA_LOOP_DOWN: /* Loop Down Event */
  606. mbx = (IS_QLA81XX(ha) || IS_QLA8031(ha))
  607. ? RD_REG_WORD(&reg24->mailbox4) : 0;
  608. mbx = IS_QLA82XX(ha) ? RD_REG_WORD(&reg82->mailbox_out[4]) : mbx;
  609. ql_dbg(ql_dbg_async, vha, 0x500b,
  610. "LOOP DOWN detected (%x %x %x %x).\n",
  611. mb[1], mb[2], mb[3], mbx);
  612. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  613. atomic_set(&vha->loop_state, LOOP_DOWN);
  614. atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
  615. vha->device_flags |= DFLG_NO_CABLE;
  616. qla2x00_mark_all_devices_lost(vha, 1);
  617. }
  618. if (vha->vp_idx) {
  619. atomic_set(&vha->vp_state, VP_FAILED);
  620. fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
  621. }
  622. vha->flags.management_server_logged_in = 0;
  623. ha->link_data_rate = PORT_SPEED_UNKNOWN;
  624. qla2x00_post_aen_work(vha, FCH_EVT_LINKDOWN, 0);
  625. break;
  626. case MBA_LIP_RESET: /* LIP reset occurred */
  627. ql_dbg(ql_dbg_async, vha, 0x500c,
  628. "LIP reset occurred (%x).\n", mb[1]);
  629. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  630. atomic_set(&vha->loop_state, LOOP_DOWN);
  631. atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
  632. qla2x00_mark_all_devices_lost(vha, 1);
  633. }
  634. if (vha->vp_idx) {
  635. atomic_set(&vha->vp_state, VP_FAILED);
  636. fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
  637. }
  638. set_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  639. ha->operating_mode = LOOP;
  640. vha->flags.management_server_logged_in = 0;
  641. qla2x00_post_aen_work(vha, FCH_EVT_LIPRESET, mb[1]);
  642. break;
  643. /* case MBA_DCBX_COMPLETE: */
  644. case MBA_POINT_TO_POINT: /* Point-to-Point */
  645. if (IS_QLA2100(ha))
  646. break;
  647. if (IS_QLA81XX(ha) || IS_QLA82XX(ha) || IS_QLA8031(ha)) {
  648. ql_dbg(ql_dbg_async, vha, 0x500d,
  649. "DCBX Completed -- %04x %04x %04x.\n",
  650. mb[1], mb[2], mb[3]);
  651. if (ha->notify_dcbx_comp)
  652. complete(&ha->dcbx_comp);
  653. } else
  654. ql_dbg(ql_dbg_async, vha, 0x500e,
  655. "Asynchronous P2P MODE received.\n");
  656. /*
  657. * Until there's a transition from loop down to loop up, treat
  658. * this as loop down only.
  659. */
  660. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  661. atomic_set(&vha->loop_state, LOOP_DOWN);
  662. if (!atomic_read(&vha->loop_down_timer))
  663. atomic_set(&vha->loop_down_timer,
  664. LOOP_DOWN_TIME);
  665. qla2x00_mark_all_devices_lost(vha, 1);
  666. }
  667. if (vha->vp_idx) {
  668. atomic_set(&vha->vp_state, VP_FAILED);
  669. fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
  670. }
  671. if (!(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)))
  672. set_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  673. set_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags);
  674. set_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags);
  675. ha->flags.gpsc_supported = 1;
  676. vha->flags.management_server_logged_in = 0;
  677. break;
  678. case MBA_CHG_IN_CONNECTION: /* Change in connection mode */
  679. if (IS_QLA2100(ha))
  680. break;
  681. ql_dbg(ql_dbg_async, vha, 0x500f,
  682. "Configuration change detected: value=%x.\n", mb[1]);
  683. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  684. atomic_set(&vha->loop_state, LOOP_DOWN);
  685. if (!atomic_read(&vha->loop_down_timer))
  686. atomic_set(&vha->loop_down_timer,
  687. LOOP_DOWN_TIME);
  688. qla2x00_mark_all_devices_lost(vha, 1);
  689. }
  690. if (vha->vp_idx) {
  691. atomic_set(&vha->vp_state, VP_FAILED);
  692. fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
  693. }
  694. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  695. set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
  696. break;
  697. case MBA_PORT_UPDATE: /* Port database update */
  698. /*
  699. * Handle only global and vn-port update events
  700. *
  701. * Relevant inputs:
  702. * mb[1] = N_Port handle of changed port
  703. * OR 0xffff for global event
  704. * mb[2] = New login state
  705. * 7 = Port logged out
  706. * mb[3] = LSB is vp_idx, 0xff = all vps
  707. *
  708. * Skip processing if:
  709. * Event is global, vp_idx is NOT all vps,
  710. * vp_idx does not match
  711. * Event is not global, vp_idx does not match
  712. */
  713. if (IS_QLA2XXX_MIDTYPE(ha) &&
  714. ((mb[1] == 0xffff && (mb[3] & 0xff) != 0xff) ||
  715. (mb[1] != 0xffff)) && vha->vp_idx != (mb[3] & 0xff))
  716. break;
  717. /* Global event -- port logout or port unavailable. */
  718. if (mb[1] == 0xffff && mb[2] == 0x7) {
  719. ql_dbg(ql_dbg_async, vha, 0x5010,
  720. "Port unavailable %04x %04x %04x.\n",
  721. mb[1], mb[2], mb[3]);
  722. ql_log(ql_log_warn, vha, 0x505e,
  723. "Link is offline.\n");
  724. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  725. atomic_set(&vha->loop_state, LOOP_DOWN);
  726. atomic_set(&vha->loop_down_timer,
  727. LOOP_DOWN_TIME);
  728. vha->device_flags |= DFLG_NO_CABLE;
  729. qla2x00_mark_all_devices_lost(vha, 1);
  730. }
  731. if (vha->vp_idx) {
  732. atomic_set(&vha->vp_state, VP_FAILED);
  733. fc_vport_set_state(vha->fc_vport,
  734. FC_VPORT_FAILED);
  735. qla2x00_mark_all_devices_lost(vha, 1);
  736. }
  737. vha->flags.management_server_logged_in = 0;
  738. ha->link_data_rate = PORT_SPEED_UNKNOWN;
  739. break;
  740. }
  741. /*
  742. * If PORT UPDATE is global (received LIP_OCCURRED/LIP_RESET
  743. * event etc. earlier indicating loop is down) then process
  744. * it. Otherwise ignore it and Wait for RSCN to come in.
  745. */
  746. atomic_set(&vha->loop_down_timer, 0);
  747. if (mb[1] != 0xffff || (mb[2] != 0x6 && mb[2] != 0x4)) {
  748. ql_dbg(ql_dbg_async, vha, 0x5011,
  749. "Asynchronous PORT UPDATE ignored %04x/%04x/%04x.\n",
  750. mb[1], mb[2], mb[3]);
  751. qlt_async_event(mb[0], vha, mb);
  752. break;
  753. }
  754. ql_dbg(ql_dbg_async, vha, 0x5012,
  755. "Port database changed %04x %04x %04x.\n",
  756. mb[1], mb[2], mb[3]);
  757. ql_log(ql_log_warn, vha, 0x505f,
  758. "Link is operational (%s Gbps).\n",
  759. qla2x00_get_link_speed_str(ha, ha->link_data_rate));
  760. /*
  761. * Mark all devices as missing so we will login again.
  762. */
  763. atomic_set(&vha->loop_state, LOOP_UP);
  764. qla2x00_mark_all_devices_lost(vha, 1);
  765. if (vha->vp_idx == 0 && !qla_ini_mode_enabled(vha))
  766. set_bit(SCR_PENDING, &vha->dpc_flags);
  767. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  768. set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
  769. qlt_async_event(mb[0], vha, mb);
  770. break;
  771. case MBA_RSCN_UPDATE: /* State Change Registration */
  772. /* Check if the Vport has issued a SCR */
  773. if (vha->vp_idx && test_bit(VP_SCR_NEEDED, &vha->vp_flags))
  774. break;
  775. /* Only handle SCNs for our Vport index. */
  776. if (ha->flags.npiv_supported && vha->vp_idx != (mb[3] & 0xff))
  777. break;
  778. ql_dbg(ql_dbg_async, vha, 0x5013,
  779. "RSCN database changed -- %04x %04x %04x.\n",
  780. mb[1], mb[2], mb[3]);
  781. rscn_entry = ((mb[1] & 0xff) << 16) | mb[2];
  782. host_pid = (vha->d_id.b.domain << 16) | (vha->d_id.b.area << 8)
  783. | vha->d_id.b.al_pa;
  784. if (rscn_entry == host_pid) {
  785. ql_dbg(ql_dbg_async, vha, 0x5014,
  786. "Ignoring RSCN update to local host "
  787. "port ID (%06x).\n", host_pid);
  788. break;
  789. }
  790. /* Ignore reserved bits from RSCN-payload. */
  791. rscn_entry = ((mb[1] & 0x3ff) << 16) | mb[2];
  792. atomic_set(&vha->loop_down_timer, 0);
  793. vha->flags.management_server_logged_in = 0;
  794. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  795. set_bit(RSCN_UPDATE, &vha->dpc_flags);
  796. qla2x00_post_aen_work(vha, FCH_EVT_RSCN, rscn_entry);
  797. break;
  798. /* case MBA_RIO_RESPONSE: */
  799. case MBA_ZIO_RESPONSE:
  800. ql_dbg(ql_dbg_async, vha, 0x5015,
  801. "[R|Z]IO update completion.\n");
  802. if (IS_FWI2_CAPABLE(ha))
  803. qla24xx_process_response_queue(vha, rsp);
  804. else
  805. qla2x00_process_response_queue(rsp);
  806. break;
  807. case MBA_DISCARD_RND_FRAME:
  808. ql_dbg(ql_dbg_async, vha, 0x5016,
  809. "Discard RND Frame -- %04x %04x %04x.\n",
  810. mb[1], mb[2], mb[3]);
  811. break;
  812. case MBA_TRACE_NOTIFICATION:
  813. ql_dbg(ql_dbg_async, vha, 0x5017,
  814. "Trace Notification -- %04x %04x.\n", mb[1], mb[2]);
  815. break;
  816. case MBA_ISP84XX_ALERT:
  817. ql_dbg(ql_dbg_async, vha, 0x5018,
  818. "ISP84XX Alert Notification -- %04x %04x %04x.\n",
  819. mb[1], mb[2], mb[3]);
  820. spin_lock_irqsave(&ha->cs84xx->access_lock, flags);
  821. switch (mb[1]) {
  822. case A84_PANIC_RECOVERY:
  823. ql_log(ql_log_info, vha, 0x5019,
  824. "Alert 84XX: panic recovery %04x %04x.\n",
  825. mb[2], mb[3]);
  826. break;
  827. case A84_OP_LOGIN_COMPLETE:
  828. ha->cs84xx->op_fw_version = mb[3] << 16 | mb[2];
  829. ql_log(ql_log_info, vha, 0x501a,
  830. "Alert 84XX: firmware version %x.\n",
  831. ha->cs84xx->op_fw_version);
  832. break;
  833. case A84_DIAG_LOGIN_COMPLETE:
  834. ha->cs84xx->diag_fw_version = mb[3] << 16 | mb[2];
  835. ql_log(ql_log_info, vha, 0x501b,
  836. "Alert 84XX: diagnostic firmware version %x.\n",
  837. ha->cs84xx->diag_fw_version);
  838. break;
  839. case A84_GOLD_LOGIN_COMPLETE:
  840. ha->cs84xx->diag_fw_version = mb[3] << 16 | mb[2];
  841. ha->cs84xx->fw_update = 1;
  842. ql_log(ql_log_info, vha, 0x501c,
  843. "Alert 84XX: gold firmware version %x.\n",
  844. ha->cs84xx->gold_fw_version);
  845. break;
  846. default:
  847. ql_log(ql_log_warn, vha, 0x501d,
  848. "Alert 84xx: Invalid Alert %04x %04x %04x.\n",
  849. mb[1], mb[2], mb[3]);
  850. }
  851. spin_unlock_irqrestore(&ha->cs84xx->access_lock, flags);
  852. break;
  853. case MBA_DCBX_START:
  854. ql_dbg(ql_dbg_async, vha, 0x501e,
  855. "DCBX Started -- %04x %04x %04x.\n",
  856. mb[1], mb[2], mb[3]);
  857. break;
  858. case MBA_DCBX_PARAM_UPDATE:
  859. ql_dbg(ql_dbg_async, vha, 0x501f,
  860. "DCBX Parameters Updated -- %04x %04x %04x.\n",
  861. mb[1], mb[2], mb[3]);
  862. break;
  863. case MBA_FCF_CONF_ERR:
  864. ql_dbg(ql_dbg_async, vha, 0x5020,
  865. "FCF Configuration Error -- %04x %04x %04x.\n",
  866. mb[1], mb[2], mb[3]);
  867. break;
  868. case MBA_IDC_NOTIFY:
  869. /* See if we need to quiesce any I/O */
  870. if (IS_QLA8031(vha->hw))
  871. if ((mb[2] & 0x7fff) == MBC_PORT_RESET ||
  872. (mb[2] & 0x7fff) == MBC_SET_PORT_CONFIG) {
  873. set_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags);
  874. qla2xxx_wake_dpc(vha);
  875. }
  876. case MBA_IDC_COMPLETE:
  877. case MBA_IDC_TIME_EXT:
  878. if (IS_QLA81XX(vha->hw) || IS_QLA8031(vha->hw))
  879. qla81xx_idc_event(vha, mb[0], mb[1]);
  880. break;
  881. case MBA_IDC_AEN:
  882. mb[4] = RD_REG_WORD(&reg24->mailbox4);
  883. mb[5] = RD_REG_WORD(&reg24->mailbox5);
  884. mb[6] = RD_REG_WORD(&reg24->mailbox6);
  885. mb[7] = RD_REG_WORD(&reg24->mailbox7);
  886. qla83xx_handle_8200_aen(vha, mb);
  887. break;
  888. default:
  889. ql_dbg(ql_dbg_async, vha, 0x5057,
  890. "Unknown AEN:%04x %04x %04x %04x\n",
  891. mb[0], mb[1], mb[2], mb[3]);
  892. }
  893. qlt_async_event(mb[0], vha, mb);
  894. if (!vha->vp_idx && ha->num_vhosts)
  895. qla2x00_alert_all_vps(rsp, mb);
  896. }
  897. /**
  898. * qla2x00_process_completed_request() - Process a Fast Post response.
  899. * @ha: SCSI driver HA context
  900. * @index: SRB index
  901. */
  902. static void
  903. qla2x00_process_completed_request(struct scsi_qla_host *vha,
  904. struct req_que *req, uint32_t index)
  905. {
  906. srb_t *sp;
  907. struct qla_hw_data *ha = vha->hw;
  908. /* Validate handle. */
  909. if (index >= req->num_outstanding_cmds) {
  910. ql_log(ql_log_warn, vha, 0x3014,
  911. "Invalid SCSI command index (%x).\n", index);
  912. if (IS_QLA82XX(ha))
  913. set_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags);
  914. else
  915. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  916. return;
  917. }
  918. sp = req->outstanding_cmds[index];
  919. if (sp) {
  920. /* Free outstanding command slot. */
  921. req->outstanding_cmds[index] = NULL;
  922. /* Save ISP completion status */
  923. sp->done(ha, sp, DID_OK << 16);
  924. } else {
  925. ql_log(ql_log_warn, vha, 0x3016, "Invalid SCSI SRB.\n");
  926. if (IS_QLA82XX(ha))
  927. set_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags);
  928. else
  929. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  930. }
  931. }
  932. static srb_t *
  933. qla2x00_get_sp_from_handle(scsi_qla_host_t *vha, const char *func,
  934. struct req_que *req, void *iocb)
  935. {
  936. struct qla_hw_data *ha = vha->hw;
  937. sts_entry_t *pkt = iocb;
  938. srb_t *sp = NULL;
  939. uint16_t index;
  940. index = LSW(pkt->handle);
  941. if (index >= req->num_outstanding_cmds) {
  942. ql_log(ql_log_warn, vha, 0x5031,
  943. "Invalid command index (%x).\n", index);
  944. if (IS_QLA82XX(ha))
  945. set_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags);
  946. else
  947. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  948. goto done;
  949. }
  950. sp = req->outstanding_cmds[index];
  951. if (!sp) {
  952. ql_log(ql_log_warn, vha, 0x5032,
  953. "Invalid completion handle (%x) -- timed-out.\n", index);
  954. return sp;
  955. }
  956. if (sp->handle != index) {
  957. ql_log(ql_log_warn, vha, 0x5033,
  958. "SRB handle (%x) mismatch %x.\n", sp->handle, index);
  959. return NULL;
  960. }
  961. req->outstanding_cmds[index] = NULL;
  962. done:
  963. return sp;
  964. }
  965. static void
  966. qla2x00_mbx_iocb_entry(scsi_qla_host_t *vha, struct req_que *req,
  967. struct mbx_entry *mbx)
  968. {
  969. const char func[] = "MBX-IOCB";
  970. const char *type;
  971. fc_port_t *fcport;
  972. srb_t *sp;
  973. struct srb_iocb *lio;
  974. uint16_t *data;
  975. uint16_t status;
  976. sp = qla2x00_get_sp_from_handle(vha, func, req, mbx);
  977. if (!sp)
  978. return;
  979. lio = &sp->u.iocb_cmd;
  980. type = sp->name;
  981. fcport = sp->fcport;
  982. data = lio->u.logio.data;
  983. data[0] = MBS_COMMAND_ERROR;
  984. data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ?
  985. QLA_LOGIO_LOGIN_RETRIED : 0;
  986. if (mbx->entry_status) {
  987. ql_dbg(ql_dbg_async, vha, 0x5043,
  988. "Async-%s error entry - hdl=%x portid=%02x%02x%02x "
  989. "entry-status=%x status=%x state-flag=%x "
  990. "status-flags=%x.\n", type, sp->handle,
  991. fcport->d_id.b.domain, fcport->d_id.b.area,
  992. fcport->d_id.b.al_pa, mbx->entry_status,
  993. le16_to_cpu(mbx->status), le16_to_cpu(mbx->state_flags),
  994. le16_to_cpu(mbx->status_flags));
  995. ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, vha, 0x5029,
  996. (uint8_t *)mbx, sizeof(*mbx));
  997. goto logio_done;
  998. }
  999. status = le16_to_cpu(mbx->status);
  1000. if (status == 0x30 && sp->type == SRB_LOGIN_CMD &&
  1001. le16_to_cpu(mbx->mb0) == MBS_COMMAND_COMPLETE)
  1002. status = 0;
  1003. if (!status && le16_to_cpu(mbx->mb0) == MBS_COMMAND_COMPLETE) {
  1004. ql_dbg(ql_dbg_async, vha, 0x5045,
  1005. "Async-%s complete - hdl=%x portid=%02x%02x%02x mbx1=%x.\n",
  1006. type, sp->handle, fcport->d_id.b.domain,
  1007. fcport->d_id.b.area, fcport->d_id.b.al_pa,
  1008. le16_to_cpu(mbx->mb1));
  1009. data[0] = MBS_COMMAND_COMPLETE;
  1010. if (sp->type == SRB_LOGIN_CMD) {
  1011. fcport->port_type = FCT_TARGET;
  1012. if (le16_to_cpu(mbx->mb1) & BIT_0)
  1013. fcport->port_type = FCT_INITIATOR;
  1014. else if (le16_to_cpu(mbx->mb1) & BIT_1)
  1015. fcport->flags |= FCF_FCP2_DEVICE;
  1016. }
  1017. goto logio_done;
  1018. }
  1019. data[0] = le16_to_cpu(mbx->mb0);
  1020. switch (data[0]) {
  1021. case MBS_PORT_ID_USED:
  1022. data[1] = le16_to_cpu(mbx->mb1);
  1023. break;
  1024. case MBS_LOOP_ID_USED:
  1025. break;
  1026. default:
  1027. data[0] = MBS_COMMAND_ERROR;
  1028. break;
  1029. }
  1030. ql_log(ql_log_warn, vha, 0x5046,
  1031. "Async-%s failed - hdl=%x portid=%02x%02x%02x status=%x "
  1032. "mb0=%x mb1=%x mb2=%x mb6=%x mb7=%x.\n", type, sp->handle,
  1033. fcport->d_id.b.domain, fcport->d_id.b.area, fcport->d_id.b.al_pa,
  1034. status, le16_to_cpu(mbx->mb0), le16_to_cpu(mbx->mb1),
  1035. le16_to_cpu(mbx->mb2), le16_to_cpu(mbx->mb6),
  1036. le16_to_cpu(mbx->mb7));
  1037. logio_done:
  1038. sp->done(vha, sp, 0);
  1039. }
  1040. static void
  1041. qla2x00_ct_entry(scsi_qla_host_t *vha, struct req_que *req,
  1042. sts_entry_t *pkt, int iocb_type)
  1043. {
  1044. const char func[] = "CT_IOCB";
  1045. const char *type;
  1046. srb_t *sp;
  1047. struct fc_bsg_job *bsg_job;
  1048. uint16_t comp_status;
  1049. int res;
  1050. sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
  1051. if (!sp)
  1052. return;
  1053. bsg_job = sp->u.bsg_job;
  1054. type = "ct pass-through";
  1055. comp_status = le16_to_cpu(pkt->comp_status);
  1056. /* return FC_CTELS_STATUS_OK and leave the decoding of the ELS/CT
  1057. * fc payload to the caller
  1058. */
  1059. bsg_job->reply->reply_data.ctels_reply.status = FC_CTELS_STATUS_OK;
  1060. bsg_job->reply_len = sizeof(struct fc_bsg_reply);
  1061. if (comp_status != CS_COMPLETE) {
  1062. if (comp_status == CS_DATA_UNDERRUN) {
  1063. res = DID_OK << 16;
  1064. bsg_job->reply->reply_payload_rcv_len =
  1065. le16_to_cpu(((sts_entry_t *)pkt)->rsp_info_len);
  1066. ql_log(ql_log_warn, vha, 0x5048,
  1067. "CT pass-through-%s error "
  1068. "comp_status-status=0x%x total_byte = 0x%x.\n",
  1069. type, comp_status,
  1070. bsg_job->reply->reply_payload_rcv_len);
  1071. } else {
  1072. ql_log(ql_log_warn, vha, 0x5049,
  1073. "CT pass-through-%s error "
  1074. "comp_status-status=0x%x.\n", type, comp_status);
  1075. res = DID_ERROR << 16;
  1076. bsg_job->reply->reply_payload_rcv_len = 0;
  1077. }
  1078. ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, vha, 0x5035,
  1079. (uint8_t *)pkt, sizeof(*pkt));
  1080. } else {
  1081. res = DID_OK << 16;
  1082. bsg_job->reply->reply_payload_rcv_len =
  1083. bsg_job->reply_payload.payload_len;
  1084. bsg_job->reply_len = 0;
  1085. }
  1086. sp->done(vha, sp, res);
  1087. }
  1088. static void
  1089. qla24xx_els_ct_entry(scsi_qla_host_t *vha, struct req_que *req,
  1090. struct sts_entry_24xx *pkt, int iocb_type)
  1091. {
  1092. const char func[] = "ELS_CT_IOCB";
  1093. const char *type;
  1094. srb_t *sp;
  1095. struct fc_bsg_job *bsg_job;
  1096. uint16_t comp_status;
  1097. uint32_t fw_status[3];
  1098. uint8_t* fw_sts_ptr;
  1099. int res;
  1100. sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
  1101. if (!sp)
  1102. return;
  1103. bsg_job = sp->u.bsg_job;
  1104. type = NULL;
  1105. switch (sp->type) {
  1106. case SRB_ELS_CMD_RPT:
  1107. case SRB_ELS_CMD_HST:
  1108. type = "els";
  1109. break;
  1110. case SRB_CT_CMD:
  1111. type = "ct pass-through";
  1112. break;
  1113. default:
  1114. ql_dbg(ql_dbg_user, vha, 0x503e,
  1115. "Unrecognized SRB: (%p) type=%d.\n", sp, sp->type);
  1116. return;
  1117. }
  1118. comp_status = fw_status[0] = le16_to_cpu(pkt->comp_status);
  1119. fw_status[1] = le16_to_cpu(((struct els_sts_entry_24xx*)pkt)->error_subcode_1);
  1120. fw_status[2] = le16_to_cpu(((struct els_sts_entry_24xx*)pkt)->error_subcode_2);
  1121. /* return FC_CTELS_STATUS_OK and leave the decoding of the ELS/CT
  1122. * fc payload to the caller
  1123. */
  1124. bsg_job->reply->reply_data.ctels_reply.status = FC_CTELS_STATUS_OK;
  1125. bsg_job->reply_len = sizeof(struct fc_bsg_reply) + sizeof(fw_status);
  1126. if (comp_status != CS_COMPLETE) {
  1127. if (comp_status == CS_DATA_UNDERRUN) {
  1128. res = DID_OK << 16;
  1129. bsg_job->reply->reply_payload_rcv_len =
  1130. le16_to_cpu(((struct els_sts_entry_24xx *)pkt)->total_byte_count);
  1131. ql_dbg(ql_dbg_user, vha, 0x503f,
  1132. "ELS-CT pass-through-%s error hdl=%x comp_status-status=0x%x "
  1133. "error subcode 1=0x%x error subcode 2=0x%x total_byte = 0x%x.\n",
  1134. type, sp->handle, comp_status, fw_status[1], fw_status[2],
  1135. le16_to_cpu(((struct els_sts_entry_24xx *)
  1136. pkt)->total_byte_count));
  1137. fw_sts_ptr = ((uint8_t*)bsg_job->req->sense) + sizeof(struct fc_bsg_reply);
  1138. memcpy( fw_sts_ptr, fw_status, sizeof(fw_status));
  1139. }
  1140. else {
  1141. ql_dbg(ql_dbg_user, vha, 0x5040,
  1142. "ELS-CT pass-through-%s error hdl=%x comp_status-status=0x%x "
  1143. "error subcode 1=0x%x error subcode 2=0x%x.\n",
  1144. type, sp->handle, comp_status,
  1145. le16_to_cpu(((struct els_sts_entry_24xx *)
  1146. pkt)->error_subcode_1),
  1147. le16_to_cpu(((struct els_sts_entry_24xx *)
  1148. pkt)->error_subcode_2));
  1149. res = DID_ERROR << 16;
  1150. bsg_job->reply->reply_payload_rcv_len = 0;
  1151. fw_sts_ptr = ((uint8_t*)bsg_job->req->sense) + sizeof(struct fc_bsg_reply);
  1152. memcpy( fw_sts_ptr, fw_status, sizeof(fw_status));
  1153. }
  1154. ql_dump_buffer(ql_dbg_user + ql_dbg_buffer, vha, 0x5056,
  1155. (uint8_t *)pkt, sizeof(*pkt));
  1156. }
  1157. else {
  1158. res = DID_OK << 16;
  1159. bsg_job->reply->reply_payload_rcv_len = bsg_job->reply_payload.payload_len;
  1160. bsg_job->reply_len = 0;
  1161. }
  1162. sp->done(vha, sp, res);
  1163. }
  1164. static void
  1165. qla24xx_logio_entry(scsi_qla_host_t *vha, struct req_que *req,
  1166. struct logio_entry_24xx *logio)
  1167. {
  1168. const char func[] = "LOGIO-IOCB";
  1169. const char *type;
  1170. fc_port_t *fcport;
  1171. srb_t *sp;
  1172. struct srb_iocb *lio;
  1173. uint16_t *data;
  1174. uint32_t iop[2];
  1175. sp = qla2x00_get_sp_from_handle(vha, func, req, logio);
  1176. if (!sp)
  1177. return;
  1178. lio = &sp->u.iocb_cmd;
  1179. type = sp->name;
  1180. fcport = sp->fcport;
  1181. data = lio->u.logio.data;
  1182. data[0] = MBS_COMMAND_ERROR;
  1183. data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ?
  1184. QLA_LOGIO_LOGIN_RETRIED : 0;
  1185. if (logio->entry_status) {
  1186. ql_log(ql_log_warn, fcport->vha, 0x5034,
  1187. "Async-%s error entry - hdl=%x"
  1188. "portid=%02x%02x%02x entry-status=%x.\n",
  1189. type, sp->handle, fcport->d_id.b.domain,
  1190. fcport->d_id.b.area, fcport->d_id.b.al_pa,
  1191. logio->entry_status);
  1192. ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, vha, 0x504d,
  1193. (uint8_t *)logio, sizeof(*logio));
  1194. goto logio_done;
  1195. }
  1196. if (le16_to_cpu(logio->comp_status) == CS_COMPLETE) {
  1197. ql_dbg(ql_dbg_async, fcport->vha, 0x5036,
  1198. "Async-%s complete - hdl=%x portid=%02x%02x%02x "
  1199. "iop0=%x.\n", type, sp->handle, fcport->d_id.b.domain,
  1200. fcport->d_id.b.area, fcport->d_id.b.al_pa,
  1201. le32_to_cpu(logio->io_parameter[0]));
  1202. data[0] = MBS_COMMAND_COMPLETE;
  1203. if (sp->type != SRB_LOGIN_CMD)
  1204. goto logio_done;
  1205. iop[0] = le32_to_cpu(logio->io_parameter[0]);
  1206. if (iop[0] & BIT_4) {
  1207. fcport->port_type = FCT_TARGET;
  1208. if (iop[0] & BIT_8)
  1209. fcport->flags |= FCF_FCP2_DEVICE;
  1210. } else if (iop[0] & BIT_5)
  1211. fcport->port_type = FCT_INITIATOR;
  1212. if (iop[0] & BIT_7)
  1213. fcport->flags |= FCF_CONF_COMP_SUPPORTED;
  1214. if (logio->io_parameter[7] || logio->io_parameter[8])
  1215. fcport->supported_classes |= FC_COS_CLASS2;
  1216. if (logio->io_parameter[9] || logio->io_parameter[10])
  1217. fcport->supported_classes |= FC_COS_CLASS3;
  1218. goto logio_done;
  1219. }
  1220. iop[0] = le32_to_cpu(logio->io_parameter[0]);
  1221. iop[1] = le32_to_cpu(logio->io_parameter[1]);
  1222. switch (iop[0]) {
  1223. case LSC_SCODE_PORTID_USED:
  1224. data[0] = MBS_PORT_ID_USED;
  1225. data[1] = LSW(iop[1]);
  1226. break;
  1227. case LSC_SCODE_NPORT_USED:
  1228. data[0] = MBS_LOOP_ID_USED;
  1229. break;
  1230. default:
  1231. data[0] = MBS_COMMAND_ERROR;
  1232. break;
  1233. }
  1234. ql_dbg(ql_dbg_async, fcport->vha, 0x5037,
  1235. "Async-%s failed - hdl=%x portid=%02x%02x%02x comp=%x "
  1236. "iop0=%x iop1=%x.\n", type, sp->handle, fcport->d_id.b.domain,
  1237. fcport->d_id.b.area, fcport->d_id.b.al_pa,
  1238. le16_to_cpu(logio->comp_status),
  1239. le32_to_cpu(logio->io_parameter[0]),
  1240. le32_to_cpu(logio->io_parameter[1]));
  1241. logio_done:
  1242. sp->done(vha, sp, 0);
  1243. }
  1244. static void
  1245. qla24xx_tm_iocb_entry(scsi_qla_host_t *vha, struct req_que *req,
  1246. struct tsk_mgmt_entry *tsk)
  1247. {
  1248. const char func[] = "TMF-IOCB";
  1249. const char *type;
  1250. fc_port_t *fcport;
  1251. srb_t *sp;
  1252. struct srb_iocb *iocb;
  1253. struct sts_entry_24xx *sts = (struct sts_entry_24xx *)tsk;
  1254. int error = 1;
  1255. sp = qla2x00_get_sp_from_handle(vha, func, req, tsk);
  1256. if (!sp)
  1257. return;
  1258. iocb = &sp->u.iocb_cmd;
  1259. type = sp->name;
  1260. fcport = sp->fcport;
  1261. if (sts->entry_status) {
  1262. ql_log(ql_log_warn, fcport->vha, 0x5038,
  1263. "Async-%s error - hdl=%x entry-status(%x).\n",
  1264. type, sp->handle, sts->entry_status);
  1265. } else if (sts->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) {
  1266. ql_log(ql_log_warn, fcport->vha, 0x5039,
  1267. "Async-%s error - hdl=%x completion status(%x).\n",
  1268. type, sp->handle, sts->comp_status);
  1269. } else if (!(le16_to_cpu(sts->scsi_status) &
  1270. SS_RESPONSE_INFO_LEN_VALID)) {
  1271. ql_log(ql_log_warn, fcport->vha, 0x503a,
  1272. "Async-%s error - hdl=%x no response info(%x).\n",
  1273. type, sp->handle, sts->scsi_status);
  1274. } else if (le32_to_cpu(sts->rsp_data_len) < 4) {
  1275. ql_log(ql_log_warn, fcport->vha, 0x503b,
  1276. "Async-%s error - hdl=%x not enough response(%d).\n",
  1277. type, sp->handle, sts->rsp_data_len);
  1278. } else if (sts->data[3]) {
  1279. ql_log(ql_log_warn, fcport->vha, 0x503c,
  1280. "Async-%s error - hdl=%x response(%x).\n",
  1281. type, sp->handle, sts->data[3]);
  1282. } else {
  1283. error = 0;
  1284. }
  1285. if (error) {
  1286. iocb->u.tmf.data = error;
  1287. ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, vha, 0x5055,
  1288. (uint8_t *)sts, sizeof(*sts));
  1289. }
  1290. sp->done(vha, sp, 0);
  1291. }
  1292. /**
  1293. * qla2x00_process_response_queue() - Process response queue entries.
  1294. * @ha: SCSI driver HA context
  1295. */
  1296. void
  1297. qla2x00_process_response_queue(struct rsp_que *rsp)
  1298. {
  1299. struct scsi_qla_host *vha;
  1300. struct qla_hw_data *ha = rsp->hw;
  1301. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  1302. sts_entry_t *pkt;
  1303. uint16_t handle_cnt;
  1304. uint16_t cnt;
  1305. vha = pci_get_drvdata(ha->pdev);
  1306. if (!vha->flags.online)
  1307. return;
  1308. while (rsp->ring_ptr->signature != RESPONSE_PROCESSED) {
  1309. pkt = (sts_entry_t *)rsp->ring_ptr;
  1310. rsp->ring_index++;
  1311. if (rsp->ring_index == rsp->length) {
  1312. rsp->ring_index = 0;
  1313. rsp->ring_ptr = rsp->ring;
  1314. } else {
  1315. rsp->ring_ptr++;
  1316. }
  1317. if (pkt->entry_status != 0) {
  1318. qla2x00_error_entry(vha, rsp, pkt);
  1319. ((response_t *)pkt)->signature = RESPONSE_PROCESSED;
  1320. wmb();
  1321. continue;
  1322. }
  1323. switch (pkt->entry_type) {
  1324. case STATUS_TYPE:
  1325. qla2x00_status_entry(vha, rsp, pkt);
  1326. break;
  1327. case STATUS_TYPE_21:
  1328. handle_cnt = ((sts21_entry_t *)pkt)->handle_count;
  1329. for (cnt = 0; cnt < handle_cnt; cnt++) {
  1330. qla2x00_process_completed_request(vha, rsp->req,
  1331. ((sts21_entry_t *)pkt)->handle[cnt]);
  1332. }
  1333. break;
  1334. case STATUS_TYPE_22:
  1335. handle_cnt = ((sts22_entry_t *)pkt)->handle_count;
  1336. for (cnt = 0; cnt < handle_cnt; cnt++) {
  1337. qla2x00_process_completed_request(vha, rsp->req,
  1338. ((sts22_entry_t *)pkt)->handle[cnt]);
  1339. }
  1340. break;
  1341. case STATUS_CONT_TYPE:
  1342. qla2x00_status_cont_entry(rsp, (sts_cont_entry_t *)pkt);
  1343. break;
  1344. case MBX_IOCB_TYPE:
  1345. qla2x00_mbx_iocb_entry(vha, rsp->req,
  1346. (struct mbx_entry *)pkt);
  1347. break;
  1348. case CT_IOCB_TYPE:
  1349. qla2x00_ct_entry(vha, rsp->req, pkt, CT_IOCB_TYPE);
  1350. break;
  1351. default:
  1352. /* Type Not Supported. */
  1353. ql_log(ql_log_warn, vha, 0x504a,
  1354. "Received unknown response pkt type %x "
  1355. "entry status=%x.\n",
  1356. pkt->entry_type, pkt->entry_status);
  1357. break;
  1358. }
  1359. ((response_t *)pkt)->signature = RESPONSE_PROCESSED;
  1360. wmb();
  1361. }
  1362. /* Adjust ring index */
  1363. WRT_REG_WORD(ISP_RSP_Q_OUT(ha, reg), rsp->ring_index);
  1364. }
  1365. static inline void
  1366. qla2x00_handle_sense(srb_t *sp, uint8_t *sense_data, uint32_t par_sense_len,
  1367. uint32_t sense_len, struct rsp_que *rsp, int res)
  1368. {
  1369. struct scsi_qla_host *vha = sp->fcport->vha;
  1370. struct scsi_cmnd *cp = GET_CMD_SP(sp);
  1371. uint32_t track_sense_len;
  1372. if (sense_len >= SCSI_SENSE_BUFFERSIZE)
  1373. sense_len = SCSI_SENSE_BUFFERSIZE;
  1374. SET_CMD_SENSE_LEN(sp, sense_len);
  1375. SET_CMD_SENSE_PTR(sp, cp->sense_buffer);
  1376. track_sense_len = sense_len;
  1377. if (sense_len > par_sense_len)
  1378. sense_len = par_sense_len;
  1379. memcpy(cp->sense_buffer, sense_data, sense_len);
  1380. SET_CMD_SENSE_PTR(sp, cp->sense_buffer + sense_len);
  1381. track_sense_len -= sense_len;
  1382. SET_CMD_SENSE_LEN(sp, track_sense_len);
  1383. if (track_sense_len != 0) {
  1384. rsp->status_srb = sp;
  1385. cp->result = res;
  1386. }
  1387. if (sense_len) {
  1388. ql_dbg(ql_dbg_io + ql_dbg_buffer, vha, 0x301c,
  1389. "Check condition Sense data, nexus%ld:%d:%d cmd=%p.\n",
  1390. sp->fcport->vha->host_no, cp->device->id, cp->device->lun,
  1391. cp);
  1392. ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x302b,
  1393. cp->sense_buffer, sense_len);
  1394. }
  1395. }
  1396. struct scsi_dif_tuple {
  1397. __be16 guard; /* Checksum */
  1398. __be16 app_tag; /* APPL identifier */
  1399. __be32 ref_tag; /* Target LBA or indirect LBA */
  1400. };
  1401. /*
  1402. * Checks the guard or meta-data for the type of error
  1403. * detected by the HBA. In case of errors, we set the
  1404. * ASC/ASCQ fields in the sense buffer with ILLEGAL_REQUEST
  1405. * to indicate to the kernel that the HBA detected error.
  1406. */
  1407. static inline int
  1408. qla2x00_handle_dif_error(srb_t *sp, struct sts_entry_24xx *sts24)
  1409. {
  1410. struct scsi_qla_host *vha = sp->fcport->vha;
  1411. struct scsi_cmnd *cmd = GET_CMD_SP(sp);
  1412. uint8_t *ap = &sts24->data[12];
  1413. uint8_t *ep = &sts24->data[20];
  1414. uint32_t e_ref_tag, a_ref_tag;
  1415. uint16_t e_app_tag, a_app_tag;
  1416. uint16_t e_guard, a_guard;
  1417. /*
  1418. * swab32 of the "data" field in the beginning of qla2x00_status_entry()
  1419. * would make guard field appear at offset 2
  1420. */
  1421. a_guard = le16_to_cpu(*(uint16_t *)(ap + 2));
  1422. a_app_tag = le16_to_cpu(*(uint16_t *)(ap + 0));
  1423. a_ref_tag = le32_to_cpu(*(uint32_t *)(ap + 4));
  1424. e_guard = le16_to_cpu(*(uint16_t *)(ep + 2));
  1425. e_app_tag = le16_to_cpu(*(uint16_t *)(ep + 0));
  1426. e_ref_tag = le32_to_cpu(*(uint32_t *)(ep + 4));
  1427. ql_dbg(ql_dbg_io, vha, 0x3023,
  1428. "iocb(s) %p Returned STATUS.\n", sts24);
  1429. ql_dbg(ql_dbg_io, vha, 0x3024,
  1430. "DIF ERROR in cmd 0x%x lba 0x%llx act ref"
  1431. " tag=0x%x, exp ref_tag=0x%x, act app tag=0x%x, exp app"
  1432. " tag=0x%x, act guard=0x%x, exp guard=0x%x.\n",
  1433. cmd->cmnd[0], (u64)scsi_get_lba(cmd), a_ref_tag, e_ref_tag,
  1434. a_app_tag, e_app_tag, a_guard, e_guard);
  1435. /*
  1436. * Ignore sector if:
  1437. * For type 3: ref & app tag is all 'f's
  1438. * For type 0,1,2: app tag is all 'f's
  1439. */
  1440. if ((a_app_tag == 0xffff) &&
  1441. ((scsi_get_prot_type(cmd) != SCSI_PROT_DIF_TYPE3) ||
  1442. (a_ref_tag == 0xffffffff))) {
  1443. uint32_t blocks_done, resid;
  1444. sector_t lba_s = scsi_get_lba(cmd);
  1445. /* 2TB boundary case covered automatically with this */
  1446. blocks_done = e_ref_tag - (uint32_t)lba_s + 1;
  1447. resid = scsi_bufflen(cmd) - (blocks_done *
  1448. cmd->device->sector_size);
  1449. scsi_set_resid(cmd, resid);
  1450. cmd->result = DID_OK << 16;
  1451. /* Update protection tag */
  1452. if (scsi_prot_sg_count(cmd)) {
  1453. uint32_t i, j = 0, k = 0, num_ent;
  1454. struct scatterlist *sg;
  1455. struct sd_dif_tuple *spt;
  1456. /* Patch the corresponding protection tags */
  1457. scsi_for_each_prot_sg(cmd, sg,
  1458. scsi_prot_sg_count(cmd), i) {
  1459. num_ent = sg_dma_len(sg) / 8;
  1460. if (k + num_ent < blocks_done) {
  1461. k += num_ent;
  1462. continue;
  1463. }
  1464. j = blocks_done - k - 1;
  1465. k = blocks_done;
  1466. break;
  1467. }
  1468. if (k != blocks_done) {
  1469. ql_log(ql_log_warn, vha, 0x302f,
  1470. "unexpected tag values tag:lba=%x:%llx)\n",
  1471. e_ref_tag, (unsigned long long)lba_s);
  1472. return 1;
  1473. }
  1474. spt = page_address(sg_page(sg)) + sg->offset;
  1475. spt += j;
  1476. spt->app_tag = 0xffff;
  1477. if (scsi_get_prot_type(cmd) == SCSI_PROT_DIF_TYPE3)
  1478. spt->ref_tag = 0xffffffff;
  1479. }
  1480. return 0;
  1481. }
  1482. /* check guard */
  1483. if (e_guard != a_guard) {
  1484. scsi_build_sense_buffer(1, cmd->sense_buffer, ILLEGAL_REQUEST,
  1485. 0x10, 0x1);
  1486. set_driver_byte(cmd, DRIVER_SENSE);
  1487. set_host_byte(cmd, DID_ABORT);
  1488. cmd->result |= SAM_STAT_CHECK_CONDITION << 1;
  1489. return 1;
  1490. }
  1491. /* check ref tag */
  1492. if (e_ref_tag != a_ref_tag) {
  1493. scsi_build_sense_buffer(1, cmd->sense_buffer, ILLEGAL_REQUEST,
  1494. 0x10, 0x3);
  1495. set_driver_byte(cmd, DRIVER_SENSE);
  1496. set_host_byte(cmd, DID_ABORT);
  1497. cmd->result |= SAM_STAT_CHECK_CONDITION << 1;
  1498. return 1;
  1499. }
  1500. /* check appl tag */
  1501. if (e_app_tag != a_app_tag) {
  1502. scsi_build_sense_buffer(1, cmd->sense_buffer, ILLEGAL_REQUEST,
  1503. 0x10, 0x2);
  1504. set_driver_byte(cmd, DRIVER_SENSE);
  1505. set_host_byte(cmd, DID_ABORT);
  1506. cmd->result |= SAM_STAT_CHECK_CONDITION << 1;
  1507. return 1;
  1508. }
  1509. return 1;
  1510. }
  1511. static void
  1512. qla25xx_process_bidir_status_iocb(scsi_qla_host_t *vha, void *pkt,
  1513. struct req_que *req, uint32_t index)
  1514. {
  1515. struct qla_hw_data *ha = vha->hw;
  1516. srb_t *sp;
  1517. uint16_t comp_status;
  1518. uint16_t scsi_status;
  1519. uint16_t thread_id;
  1520. uint32_t rval = EXT_STATUS_OK;
  1521. struct fc_bsg_job *bsg_job = NULL;
  1522. sts_entry_t *sts;
  1523. struct sts_entry_24xx *sts24;
  1524. sts = (sts_entry_t *) pkt;
  1525. sts24 = (struct sts_entry_24xx *) pkt;
  1526. /* Validate handle. */
  1527. if (index >= req->num_outstanding_cmds) {
  1528. ql_log(ql_log_warn, vha, 0x70af,
  1529. "Invalid SCSI completion handle 0x%x.\n", index);
  1530. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1531. return;
  1532. }
  1533. sp = req->outstanding_cmds[index];
  1534. if (sp) {
  1535. /* Free outstanding command slot. */
  1536. req->outstanding_cmds[index] = NULL;
  1537. bsg_job = sp->u.bsg_job;
  1538. } else {
  1539. ql_log(ql_log_warn, vha, 0x70b0,
  1540. "Req:%d: Invalid ISP SCSI completion handle(0x%x)\n",
  1541. req->id, index);
  1542. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1543. return;
  1544. }
  1545. if (IS_FWI2_CAPABLE(ha)) {
  1546. comp_status = le16_to_cpu(sts24->comp_status);
  1547. scsi_status = le16_to_cpu(sts24->scsi_status) & SS_MASK;
  1548. } else {
  1549. comp_status = le16_to_cpu(sts->comp_status);
  1550. scsi_status = le16_to_cpu(sts->scsi_status) & SS_MASK;
  1551. }
  1552. thread_id = bsg_job->request->rqst_data.h_vendor.vendor_cmd[1];
  1553. switch (comp_status) {
  1554. case CS_COMPLETE:
  1555. if (scsi_status == 0) {
  1556. bsg_job->reply->reply_payload_rcv_len =
  1557. bsg_job->reply_payload.payload_len;
  1558. rval = EXT_STATUS_OK;
  1559. }
  1560. goto done;
  1561. case CS_DATA_OVERRUN:
  1562. ql_dbg(ql_dbg_user, vha, 0x70b1,
  1563. "Command completed with date overrun thread_id=%d\n",
  1564. thread_id);
  1565. rval = EXT_STATUS_DATA_OVERRUN;
  1566. break;
  1567. case CS_DATA_UNDERRUN:
  1568. ql_dbg(ql_dbg_user, vha, 0x70b2,
  1569. "Command completed with date underrun thread_id=%d\n",
  1570. thread_id);
  1571. rval = EXT_STATUS_DATA_UNDERRUN;
  1572. break;
  1573. case CS_BIDIR_RD_OVERRUN:
  1574. ql_dbg(ql_dbg_user, vha, 0x70b3,
  1575. "Command completed with read data overrun thread_id=%d\n",
  1576. thread_id);
  1577. rval = EXT_STATUS_DATA_OVERRUN;
  1578. break;
  1579. case CS_BIDIR_RD_WR_OVERRUN:
  1580. ql_dbg(ql_dbg_user, vha, 0x70b4,
  1581. "Command completed with read and write data overrun "
  1582. "thread_id=%d\n", thread_id);
  1583. rval = EXT_STATUS_DATA_OVERRUN;
  1584. break;
  1585. case CS_BIDIR_RD_OVERRUN_WR_UNDERRUN:
  1586. ql_dbg(ql_dbg_user, vha, 0x70b5,
  1587. "Command completed with read data over and write data "
  1588. "underrun thread_id=%d\n", thread_id);
  1589. rval = EXT_STATUS_DATA_OVERRUN;
  1590. break;
  1591. case CS_BIDIR_RD_UNDERRUN:
  1592. ql_dbg(ql_dbg_user, vha, 0x70b6,
  1593. "Command completed with read data data underrun "
  1594. "thread_id=%d\n", thread_id);
  1595. rval = EXT_STATUS_DATA_UNDERRUN;
  1596. break;
  1597. case CS_BIDIR_RD_UNDERRUN_WR_OVERRUN:
  1598. ql_dbg(ql_dbg_user, vha, 0x70b7,
  1599. "Command completed with read data under and write data "
  1600. "overrun thread_id=%d\n", thread_id);
  1601. rval = EXT_STATUS_DATA_UNDERRUN;
  1602. break;
  1603. case CS_BIDIR_RD_WR_UNDERRUN:
  1604. ql_dbg(ql_dbg_user, vha, 0x70b8,
  1605. "Command completed with read and write data underrun "
  1606. "thread_id=%d\n", thread_id);
  1607. rval = EXT_STATUS_DATA_UNDERRUN;
  1608. break;
  1609. case CS_BIDIR_DMA:
  1610. ql_dbg(ql_dbg_user, vha, 0x70b9,
  1611. "Command completed with data DMA error thread_id=%d\n",
  1612. thread_id);
  1613. rval = EXT_STATUS_DMA_ERR;
  1614. break;
  1615. case CS_TIMEOUT:
  1616. ql_dbg(ql_dbg_user, vha, 0x70ba,
  1617. "Command completed with timeout thread_id=%d\n",
  1618. thread_id);
  1619. rval = EXT_STATUS_TIMEOUT;
  1620. break;
  1621. default:
  1622. ql_dbg(ql_dbg_user, vha, 0x70bb,
  1623. "Command completed with completion status=0x%x "
  1624. "thread_id=%d\n", comp_status, thread_id);
  1625. rval = EXT_STATUS_ERR;
  1626. break;
  1627. }
  1628. bsg_job->reply->reply_payload_rcv_len = 0;
  1629. done:
  1630. /* Return the vendor specific reply to API */
  1631. bsg_job->reply->reply_data.vendor_reply.vendor_rsp[0] = rval;
  1632. bsg_job->reply_len = sizeof(struct fc_bsg_reply);
  1633. /* Always return DID_OK, bsg will send the vendor specific response
  1634. * in this case only */
  1635. sp->done(vha, sp, (DID_OK << 6));
  1636. }
  1637. /**
  1638. * qla2x00_status_entry() - Process a Status IOCB entry.
  1639. * @ha: SCSI driver HA context
  1640. * @pkt: Entry pointer
  1641. */
  1642. static void
  1643. qla2x00_status_entry(scsi_qla_host_t *vha, struct rsp_que *rsp, void *pkt)
  1644. {
  1645. srb_t *sp;
  1646. fc_port_t *fcport;
  1647. struct scsi_cmnd *cp;
  1648. sts_entry_t *sts;
  1649. struct sts_entry_24xx *sts24;
  1650. uint16_t comp_status;
  1651. uint16_t scsi_status;
  1652. uint16_t ox_id;
  1653. uint8_t lscsi_status;
  1654. int32_t resid;
  1655. uint32_t sense_len, par_sense_len, rsp_info_len, resid_len,
  1656. fw_resid_len;
  1657. uint8_t *rsp_info, *sense_data;
  1658. struct qla_hw_data *ha = vha->hw;
  1659. uint32_t handle;
  1660. uint16_t que;
  1661. struct req_que *req;
  1662. int logit = 1;
  1663. int res = 0;
  1664. uint16_t state_flags = 0;
  1665. sts = (sts_entry_t *) pkt;
  1666. sts24 = (struct sts_entry_24xx *) pkt;
  1667. if (IS_FWI2_CAPABLE(ha)) {
  1668. comp_status = le16_to_cpu(sts24->comp_status);
  1669. scsi_status = le16_to_cpu(sts24->scsi_status) & SS_MASK;
  1670. state_flags = le16_to_cpu(sts24->state_flags);
  1671. } else {
  1672. comp_status = le16_to_cpu(sts->comp_status);
  1673. scsi_status = le16_to_cpu(sts->scsi_status) & SS_MASK;
  1674. }
  1675. handle = (uint32_t) LSW(sts->handle);
  1676. que = MSW(sts->handle);
  1677. req = ha->req_q_map[que];
  1678. /* Validate handle. */
  1679. if (handle < req->num_outstanding_cmds)
  1680. sp = req->outstanding_cmds[handle];
  1681. else
  1682. sp = NULL;
  1683. if (sp == NULL) {
  1684. ql_dbg(ql_dbg_io, vha, 0x3017,
  1685. "Invalid status handle (0x%x).\n", sts->handle);
  1686. if (IS_QLA82XX(ha))
  1687. set_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags);
  1688. else
  1689. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1690. qla2xxx_wake_dpc(vha);
  1691. return;
  1692. }
  1693. if (unlikely((state_flags & BIT_1) && (sp->type == SRB_BIDI_CMD))) {
  1694. qla25xx_process_bidir_status_iocb(vha, pkt, req, handle);
  1695. return;
  1696. }
  1697. /* Fast path completion. */
  1698. if (comp_status == CS_COMPLETE && scsi_status == 0) {
  1699. qla2x00_do_host_ramp_up(vha);
  1700. qla2x00_process_completed_request(vha, req, handle);
  1701. return;
  1702. }
  1703. req->outstanding_cmds[handle] = NULL;
  1704. cp = GET_CMD_SP(sp);
  1705. if (cp == NULL) {
  1706. ql_dbg(ql_dbg_io, vha, 0x3018,
  1707. "Command already returned (0x%x/%p).\n",
  1708. sts->handle, sp);
  1709. return;
  1710. }
  1711. lscsi_status = scsi_status & STATUS_MASK;
  1712. fcport = sp->fcport;
  1713. ox_id = 0;
  1714. sense_len = par_sense_len = rsp_info_len = resid_len =
  1715. fw_resid_len = 0;
  1716. if (IS_FWI2_CAPABLE(ha)) {
  1717. if (scsi_status & SS_SENSE_LEN_VALID)
  1718. sense_len = le32_to_cpu(sts24->sense_len);
  1719. if (scsi_status & SS_RESPONSE_INFO_LEN_VALID)
  1720. rsp_info_len = le32_to_cpu(sts24->rsp_data_len);
  1721. if (scsi_status & (SS_RESIDUAL_UNDER | SS_RESIDUAL_OVER))
  1722. resid_len = le32_to_cpu(sts24->rsp_residual_count);
  1723. if (comp_status == CS_DATA_UNDERRUN)
  1724. fw_resid_len = le32_to_cpu(sts24->residual_len);
  1725. rsp_info = sts24->data;
  1726. sense_data = sts24->data;
  1727. host_to_fcp_swap(sts24->data, sizeof(sts24->data));
  1728. ox_id = le16_to_cpu(sts24->ox_id);
  1729. par_sense_len = sizeof(sts24->data);
  1730. } else {
  1731. if (scsi_status & SS_SENSE_LEN_VALID)
  1732. sense_len = le16_to_cpu(sts->req_sense_length);
  1733. if (scsi_status & SS_RESPONSE_INFO_LEN_VALID)
  1734. rsp_info_len = le16_to_cpu(sts->rsp_info_len);
  1735. resid_len = le32_to_cpu(sts->residual_length);
  1736. rsp_info = sts->rsp_info;
  1737. sense_data = sts->req_sense_data;
  1738. par_sense_len = sizeof(sts->req_sense_data);
  1739. }
  1740. /* Check for any FCP transport errors. */
  1741. if (scsi_status & SS_RESPONSE_INFO_LEN_VALID) {
  1742. /* Sense data lies beyond any FCP RESPONSE data. */
  1743. if (IS_FWI2_CAPABLE(ha)) {
  1744. sense_data += rsp_info_len;
  1745. par_sense_len -= rsp_info_len;
  1746. }
  1747. if (rsp_info_len > 3 && rsp_info[3]) {
  1748. ql_dbg(ql_dbg_io, fcport->vha, 0x3019,
  1749. "FCP I/O protocol failure (0x%x/0x%x).\n",
  1750. rsp_info_len, rsp_info[3]);
  1751. res = DID_BUS_BUSY << 16;
  1752. goto out;
  1753. }
  1754. }
  1755. /* Check for overrun. */
  1756. if (IS_FWI2_CAPABLE(ha) && comp_status == CS_COMPLETE &&
  1757. scsi_status & SS_RESIDUAL_OVER)
  1758. comp_status = CS_DATA_OVERRUN;
  1759. /*
  1760. * Based on Host and scsi status generate status code for Linux
  1761. */
  1762. switch (comp_status) {
  1763. case CS_COMPLETE:
  1764. case CS_QUEUE_FULL:
  1765. if (scsi_status == 0) {
  1766. res = DID_OK << 16;
  1767. break;
  1768. }
  1769. if (scsi_status & (SS_RESIDUAL_UNDER | SS_RESIDUAL_OVER)) {
  1770. resid = resid_len;
  1771. scsi_set_resid(cp, resid);
  1772. if (!lscsi_status &&
  1773. ((unsigned)(scsi_bufflen(cp) - resid) <
  1774. cp->underflow)) {
  1775. ql_dbg(ql_dbg_io, fcport->vha, 0x301a,
  1776. "Mid-layer underflow "
  1777. "detected (0x%x of 0x%x bytes).\n",
  1778. resid, scsi_bufflen(cp));
  1779. res = DID_ERROR << 16;
  1780. break;
  1781. }
  1782. }
  1783. res = DID_OK << 16 | lscsi_status;
  1784. if (lscsi_status == SAM_STAT_TASK_SET_FULL) {
  1785. ql_dbg(ql_dbg_io, fcport->vha, 0x301b,
  1786. "QUEUE FULL detected.\n");
  1787. break;
  1788. }
  1789. logit = 0;
  1790. if (lscsi_status != SS_CHECK_CONDITION)
  1791. break;
  1792. memset(cp->sense_buffer, 0, SCSI_SENSE_BUFFERSIZE);
  1793. if (!(scsi_status & SS_SENSE_LEN_VALID))
  1794. break;
  1795. qla2x00_handle_sense(sp, sense_data, par_sense_len, sense_len,
  1796. rsp, res);
  1797. break;
  1798. case CS_DATA_UNDERRUN:
  1799. /* Use F/W calculated residual length. */
  1800. resid = IS_FWI2_CAPABLE(ha) ? fw_resid_len : resid_len;
  1801. scsi_set_resid(cp, resid);
  1802. if (scsi_status & SS_RESIDUAL_UNDER) {
  1803. if (IS_FWI2_CAPABLE(ha) && fw_resid_len != resid_len) {
  1804. ql_dbg(ql_dbg_io, fcport->vha, 0x301d,
  1805. "Dropped frame(s) detected "
  1806. "(0x%x of 0x%x bytes).\n",
  1807. resid, scsi_bufflen(cp));
  1808. res = DID_ERROR << 16 | lscsi_status;
  1809. goto check_scsi_status;
  1810. }
  1811. if (!lscsi_status &&
  1812. ((unsigned)(scsi_bufflen(cp) - resid) <
  1813. cp->underflow)) {
  1814. ql_dbg(ql_dbg_io, fcport->vha, 0x301e,
  1815. "Mid-layer underflow "
  1816. "detected (0x%x of 0x%x bytes).\n",
  1817. resid, scsi_bufflen(cp));
  1818. res = DID_ERROR << 16;
  1819. break;
  1820. }
  1821. } else if (lscsi_status != SAM_STAT_TASK_SET_FULL &&
  1822. lscsi_status != SAM_STAT_BUSY) {
  1823. /*
  1824. * scsi status of task set and busy are considered to be
  1825. * task not completed.
  1826. */
  1827. ql_dbg(ql_dbg_io, fcport->vha, 0x301f,
  1828. "Dropped frame(s) detected (0x%x "
  1829. "of 0x%x bytes).\n", resid,
  1830. scsi_bufflen(cp));
  1831. res = DID_ERROR << 16 | lscsi_status;
  1832. goto check_scsi_status;
  1833. } else {
  1834. ql_dbg(ql_dbg_io, fcport->vha, 0x3030,
  1835. "scsi_status: 0x%x, lscsi_status: 0x%x\n",
  1836. scsi_status, lscsi_status);
  1837. }
  1838. res = DID_OK << 16 | lscsi_status;
  1839. logit = 0;
  1840. check_scsi_status:
  1841. /*
  1842. * Check to see if SCSI Status is non zero. If so report SCSI
  1843. * Status.
  1844. */
  1845. if (lscsi_status != 0) {
  1846. if (lscsi_status == SAM_STAT_TASK_SET_FULL) {
  1847. ql_dbg(ql_dbg_io, fcport->vha, 0x3020,
  1848. "QUEUE FULL detected.\n");
  1849. logit = 1;
  1850. break;
  1851. }
  1852. if (lscsi_status != SS_CHECK_CONDITION)
  1853. break;
  1854. memset(cp->sense_buffer, 0, SCSI_SENSE_BUFFERSIZE);
  1855. if (!(scsi_status & SS_SENSE_LEN_VALID))
  1856. break;
  1857. qla2x00_handle_sense(sp, sense_data, par_sense_len,
  1858. sense_len, rsp, res);
  1859. }
  1860. break;
  1861. case CS_PORT_LOGGED_OUT:
  1862. case CS_PORT_CONFIG_CHG:
  1863. case CS_PORT_BUSY:
  1864. case CS_INCOMPLETE:
  1865. case CS_PORT_UNAVAILABLE:
  1866. case CS_TIMEOUT:
  1867. case CS_RESET:
  1868. /*
  1869. * We are going to have the fc class block the rport
  1870. * while we try to recover so instruct the mid layer
  1871. * to requeue until the class decides how to handle this.
  1872. */
  1873. res = DID_TRANSPORT_DISRUPTED << 16;
  1874. if (comp_status == CS_TIMEOUT) {
  1875. if (IS_FWI2_CAPABLE(ha))
  1876. break;
  1877. else if ((le16_to_cpu(sts->status_flags) &
  1878. SF_LOGOUT_SENT) == 0)
  1879. break;
  1880. }
  1881. ql_dbg(ql_dbg_io, fcport->vha, 0x3021,
  1882. "Port down status: port-state=0x%x.\n",
  1883. atomic_read(&fcport->state));
  1884. if (atomic_read(&fcport->state) == FCS_ONLINE)
  1885. qla2x00_mark_device_lost(fcport->vha, fcport, 1, 1);
  1886. break;
  1887. case CS_ABORTED:
  1888. res = DID_RESET << 16;
  1889. break;
  1890. case CS_DIF_ERROR:
  1891. logit = qla2x00_handle_dif_error(sp, sts24);
  1892. res = cp->result;
  1893. break;
  1894. case CS_TRANSPORT:
  1895. res = DID_ERROR << 16;
  1896. if (!IS_PI_SPLIT_DET_CAPABLE(ha))
  1897. break;
  1898. if (state_flags & BIT_4)
  1899. scmd_printk(KERN_WARNING, cp,
  1900. "Unsupported device '%s' found.\n",
  1901. cp->device->vendor);
  1902. break;
  1903. default:
  1904. res = DID_ERROR << 16;
  1905. break;
  1906. }
  1907. out:
  1908. if (logit)
  1909. ql_dbg(ql_dbg_io, fcport->vha, 0x3022,
  1910. "FCP command status: 0x%x-0x%x (0x%x) "
  1911. "nexus=%ld:%d:%d portid=%02x%02x%02x oxid=0x%x "
  1912. "cdb=%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x len=0x%x "
  1913. "rsp_info=0x%x resid=0x%x fw_resid=0x%x.\n",
  1914. comp_status, scsi_status, res, vha->host_no,
  1915. cp->device->id, cp->device->lun, fcport->d_id.b.domain,
  1916. fcport->d_id.b.area, fcport->d_id.b.al_pa, ox_id,
  1917. cp->cmnd[0], cp->cmnd[1], cp->cmnd[2], cp->cmnd[3],
  1918. cp->cmnd[4], cp->cmnd[5], cp->cmnd[6], cp->cmnd[7],
  1919. cp->cmnd[8], cp->cmnd[9], scsi_bufflen(cp), rsp_info_len,
  1920. resid_len, fw_resid_len);
  1921. if (!res)
  1922. qla2x00_do_host_ramp_up(vha);
  1923. if (rsp->status_srb == NULL)
  1924. sp->done(ha, sp, res);
  1925. }
  1926. /**
  1927. * qla2x00_status_cont_entry() - Process a Status Continuations entry.
  1928. * @ha: SCSI driver HA context
  1929. * @pkt: Entry pointer
  1930. *
  1931. * Extended sense data.
  1932. */
  1933. static void
  1934. qla2x00_status_cont_entry(struct rsp_que *rsp, sts_cont_entry_t *pkt)
  1935. {
  1936. uint8_t sense_sz = 0;
  1937. struct qla_hw_data *ha = rsp->hw;
  1938. struct scsi_qla_host *vha = pci_get_drvdata(ha->pdev);
  1939. srb_t *sp = rsp->status_srb;
  1940. struct scsi_cmnd *cp;
  1941. uint32_t sense_len;
  1942. uint8_t *sense_ptr;
  1943. if (!sp || !GET_CMD_SENSE_LEN(sp))
  1944. return;
  1945. sense_len = GET_CMD_SENSE_LEN(sp);
  1946. sense_ptr = GET_CMD_SENSE_PTR(sp);
  1947. cp = GET_CMD_SP(sp);
  1948. if (cp == NULL) {
  1949. ql_log(ql_log_warn, vha, 0x3025,
  1950. "cmd is NULL: already returned to OS (sp=%p).\n", sp);
  1951. rsp->status_srb = NULL;
  1952. return;
  1953. }
  1954. if (sense_len > sizeof(pkt->data))
  1955. sense_sz = sizeof(pkt->data);
  1956. else
  1957. sense_sz = sense_len;
  1958. /* Move sense data. */
  1959. if (IS_FWI2_CAPABLE(ha))
  1960. host_to_fcp_swap(pkt->data, sizeof(pkt->data));
  1961. memcpy(sense_ptr, pkt->data, sense_sz);
  1962. ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x302c,
  1963. sense_ptr, sense_sz);
  1964. sense_len -= sense_sz;
  1965. sense_ptr += sense_sz;
  1966. SET_CMD_SENSE_PTR(sp, sense_ptr);
  1967. SET_CMD_SENSE_LEN(sp, sense_len);
  1968. /* Place command on done queue. */
  1969. if (sense_len == 0) {
  1970. rsp->status_srb = NULL;
  1971. sp->done(ha, sp, cp->result);
  1972. }
  1973. }
  1974. /**
  1975. * qla2x00_error_entry() - Process an error entry.
  1976. * @ha: SCSI driver HA context
  1977. * @pkt: Entry pointer
  1978. */
  1979. static void
  1980. qla2x00_error_entry(scsi_qla_host_t *vha, struct rsp_que *rsp, sts_entry_t *pkt)
  1981. {
  1982. srb_t *sp;
  1983. struct qla_hw_data *ha = vha->hw;
  1984. const char func[] = "ERROR-IOCB";
  1985. uint16_t que = MSW(pkt->handle);
  1986. struct req_que *req = NULL;
  1987. int res = DID_ERROR << 16;
  1988. ql_dbg(ql_dbg_async, vha, 0x502a,
  1989. "type of error status in response: 0x%x\n", pkt->entry_status);
  1990. if (que >= ha->max_req_queues || !ha->req_q_map[que])
  1991. goto fatal;
  1992. req = ha->req_q_map[que];
  1993. if (pkt->entry_status & RF_BUSY)
  1994. res = DID_BUS_BUSY << 16;
  1995. sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
  1996. if (sp) {
  1997. sp->done(ha, sp, res);
  1998. return;
  1999. }
  2000. fatal:
  2001. ql_log(ql_log_warn, vha, 0x5030,
  2002. "Error entry - invalid handle/queue.\n");
  2003. if (IS_QLA82XX(ha))
  2004. set_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags);
  2005. else
  2006. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2007. qla2xxx_wake_dpc(vha);
  2008. }
  2009. /**
  2010. * qla24xx_mbx_completion() - Process mailbox command completions.
  2011. * @ha: SCSI driver HA context
  2012. * @mb0: Mailbox0 register
  2013. */
  2014. static void
  2015. qla24xx_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0)
  2016. {
  2017. uint16_t cnt;
  2018. uint32_t mboxes;
  2019. uint16_t __iomem *wptr;
  2020. struct qla_hw_data *ha = vha->hw;
  2021. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  2022. /* Read all mbox registers? */
  2023. mboxes = (1 << ha->mbx_count) - 1;
  2024. if (!ha->mcp)
  2025. ql_dbg(ql_dbg_async, vha, 0x504e, "MBX pointer ERROR.\n");
  2026. else
  2027. mboxes = ha->mcp->in_mb;
  2028. /* Load return mailbox registers. */
  2029. ha->flags.mbox_int = 1;
  2030. ha->mailbox_out[0] = mb0;
  2031. mboxes >>= 1;
  2032. wptr = (uint16_t __iomem *)&reg->mailbox1;
  2033. for (cnt = 1; cnt < ha->mbx_count; cnt++) {
  2034. if (mboxes & BIT_0)
  2035. ha->mailbox_out[cnt] = RD_REG_WORD(wptr);
  2036. mboxes >>= 1;
  2037. wptr++;
  2038. }
  2039. }
  2040. /**
  2041. * qla24xx_process_response_queue() - Process response queue entries.
  2042. * @ha: SCSI driver HA context
  2043. */
  2044. void qla24xx_process_response_queue(struct scsi_qla_host *vha,
  2045. struct rsp_que *rsp)
  2046. {
  2047. struct sts_entry_24xx *pkt;
  2048. struct qla_hw_data *ha = vha->hw;
  2049. if (!vha->flags.online)
  2050. return;
  2051. while (rsp->ring_ptr->signature != RESPONSE_PROCESSED) {
  2052. pkt = (struct sts_entry_24xx *)rsp->ring_ptr;
  2053. rsp->ring_index++;
  2054. if (rsp->ring_index == rsp->length) {
  2055. rsp->ring_index = 0;
  2056. rsp->ring_ptr = rsp->ring;
  2057. } else {
  2058. rsp->ring_ptr++;
  2059. }
  2060. if (pkt->entry_status != 0) {
  2061. qla2x00_error_entry(vha, rsp, (sts_entry_t *) pkt);
  2062. (void)qlt_24xx_process_response_error(vha, pkt);
  2063. ((response_t *)pkt)->signature = RESPONSE_PROCESSED;
  2064. wmb();
  2065. continue;
  2066. }
  2067. switch (pkt->entry_type) {
  2068. case STATUS_TYPE:
  2069. qla2x00_status_entry(vha, rsp, pkt);
  2070. break;
  2071. case STATUS_CONT_TYPE:
  2072. qla2x00_status_cont_entry(rsp, (sts_cont_entry_t *)pkt);
  2073. break;
  2074. case VP_RPT_ID_IOCB_TYPE:
  2075. qla24xx_report_id_acquisition(vha,
  2076. (struct vp_rpt_id_entry_24xx *)pkt);
  2077. break;
  2078. case LOGINOUT_PORT_IOCB_TYPE:
  2079. qla24xx_logio_entry(vha, rsp->req,
  2080. (struct logio_entry_24xx *)pkt);
  2081. break;
  2082. case TSK_MGMT_IOCB_TYPE:
  2083. qla24xx_tm_iocb_entry(vha, rsp->req,
  2084. (struct tsk_mgmt_entry *)pkt);
  2085. break;
  2086. case CT_IOCB_TYPE:
  2087. qla24xx_els_ct_entry(vha, rsp->req, pkt, CT_IOCB_TYPE);
  2088. break;
  2089. case ELS_IOCB_TYPE:
  2090. qla24xx_els_ct_entry(vha, rsp->req, pkt, ELS_IOCB_TYPE);
  2091. break;
  2092. case ABTS_RECV_24XX:
  2093. /* ensure that the ATIO queue is empty */
  2094. qlt_24xx_process_atio_queue(vha);
  2095. case ABTS_RESP_24XX:
  2096. case CTIO_TYPE7:
  2097. case NOTIFY_ACK_TYPE:
  2098. qlt_response_pkt_all_vps(vha, (response_t *)pkt);
  2099. break;
  2100. case MARKER_TYPE:
  2101. /* Do nothing in this case, this check is to prevent it
  2102. * from falling into default case
  2103. */
  2104. break;
  2105. default:
  2106. /* Type Not Supported. */
  2107. ql_dbg(ql_dbg_async, vha, 0x5042,
  2108. "Received unknown response pkt type %x "
  2109. "entry status=%x.\n",
  2110. pkt->entry_type, pkt->entry_status);
  2111. break;
  2112. }
  2113. ((response_t *)pkt)->signature = RESPONSE_PROCESSED;
  2114. wmb();
  2115. }
  2116. /* Adjust ring index */
  2117. if (IS_QLA82XX(ha)) {
  2118. struct device_reg_82xx __iomem *reg = &ha->iobase->isp82;
  2119. WRT_REG_DWORD(&reg->rsp_q_out[0], rsp->ring_index);
  2120. } else
  2121. WRT_REG_DWORD(rsp->rsp_q_out, rsp->ring_index);
  2122. }
  2123. static void
  2124. qla2xxx_check_risc_status(scsi_qla_host_t *vha)
  2125. {
  2126. int rval;
  2127. uint32_t cnt;
  2128. struct qla_hw_data *ha = vha->hw;
  2129. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  2130. if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha))
  2131. return;
  2132. rval = QLA_SUCCESS;
  2133. WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
  2134. RD_REG_DWORD(&reg->iobase_addr);
  2135. WRT_REG_DWORD(&reg->iobase_window, 0x0001);
  2136. for (cnt = 10000; (RD_REG_DWORD(&reg->iobase_window) & BIT_0) == 0 &&
  2137. rval == QLA_SUCCESS; cnt--) {
  2138. if (cnt) {
  2139. WRT_REG_DWORD(&reg->iobase_window, 0x0001);
  2140. udelay(10);
  2141. } else
  2142. rval = QLA_FUNCTION_TIMEOUT;
  2143. }
  2144. if (rval == QLA_SUCCESS)
  2145. goto next_test;
  2146. WRT_REG_DWORD(&reg->iobase_window, 0x0003);
  2147. for (cnt = 100; (RD_REG_DWORD(&reg->iobase_window) & BIT_0) == 0 &&
  2148. rval == QLA_SUCCESS; cnt--) {
  2149. if (cnt) {
  2150. WRT_REG_DWORD(&reg->iobase_window, 0x0003);
  2151. udelay(10);
  2152. } else
  2153. rval = QLA_FUNCTION_TIMEOUT;
  2154. }
  2155. if (rval != QLA_SUCCESS)
  2156. goto done;
  2157. next_test:
  2158. if (RD_REG_DWORD(&reg->iobase_c8) & BIT_3)
  2159. ql_log(ql_log_info, vha, 0x504c,
  2160. "Additional code -- 0x55AA.\n");
  2161. done:
  2162. WRT_REG_DWORD(&reg->iobase_window, 0x0000);
  2163. RD_REG_DWORD(&reg->iobase_window);
  2164. }
  2165. /**
  2166. * qla24xx_intr_handler() - Process interrupts for the ISP23xx and ISP24xx.
  2167. * @irq:
  2168. * @dev_id: SCSI driver HA context
  2169. *
  2170. * Called by system whenever the host adapter generates an interrupt.
  2171. *
  2172. * Returns handled flag.
  2173. */
  2174. irqreturn_t
  2175. qla24xx_intr_handler(int irq, void *dev_id)
  2176. {
  2177. scsi_qla_host_t *vha;
  2178. struct qla_hw_data *ha;
  2179. struct device_reg_24xx __iomem *reg;
  2180. int status;
  2181. unsigned long iter;
  2182. uint32_t stat;
  2183. uint32_t hccr;
  2184. uint16_t mb[8];
  2185. struct rsp_que *rsp;
  2186. unsigned long flags;
  2187. rsp = (struct rsp_que *) dev_id;
  2188. if (!rsp) {
  2189. ql_log(ql_log_info, NULL, 0x5059,
  2190. "%s: NULL response queue pointer.\n", __func__);
  2191. return IRQ_NONE;
  2192. }
  2193. ha = rsp->hw;
  2194. reg = &ha->iobase->isp24;
  2195. status = 0;
  2196. if (unlikely(pci_channel_offline(ha->pdev)))
  2197. return IRQ_HANDLED;
  2198. spin_lock_irqsave(&ha->hardware_lock, flags);
  2199. vha = pci_get_drvdata(ha->pdev);
  2200. for (iter = 50; iter--; ) {
  2201. stat = RD_REG_DWORD(&reg->host_status);
  2202. if (stat & HSRX_RISC_PAUSED) {
  2203. if (unlikely(pci_channel_offline(ha->pdev)))
  2204. break;
  2205. hccr = RD_REG_DWORD(&reg->hccr);
  2206. ql_log(ql_log_warn, vha, 0x504b,
  2207. "RISC paused -- HCCR=%x, Dumping firmware.\n",
  2208. hccr);
  2209. qla2xxx_check_risc_status(vha);
  2210. ha->isp_ops->fw_dump(vha, 1);
  2211. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2212. break;
  2213. } else if ((stat & HSRX_RISC_INT) == 0)
  2214. break;
  2215. switch (stat & 0xff) {
  2216. case INTR_ROM_MB_SUCCESS:
  2217. case INTR_ROM_MB_FAILED:
  2218. case INTR_MB_SUCCESS:
  2219. case INTR_MB_FAILED:
  2220. qla24xx_mbx_completion(vha, MSW(stat));
  2221. status |= MBX_INTERRUPT;
  2222. break;
  2223. case INTR_ASYNC_EVENT:
  2224. mb[0] = MSW(stat);
  2225. mb[1] = RD_REG_WORD(&reg->mailbox1);
  2226. mb[2] = RD_REG_WORD(&reg->mailbox2);
  2227. mb[3] = RD_REG_WORD(&reg->mailbox3);
  2228. qla2x00_async_event(vha, rsp, mb);
  2229. break;
  2230. case INTR_RSP_QUE_UPDATE:
  2231. case INTR_RSP_QUE_UPDATE_83XX:
  2232. qla24xx_process_response_queue(vha, rsp);
  2233. break;
  2234. case INTR_ATIO_QUE_UPDATE:
  2235. qlt_24xx_process_atio_queue(vha);
  2236. break;
  2237. case INTR_ATIO_RSP_QUE_UPDATE:
  2238. qlt_24xx_process_atio_queue(vha);
  2239. qla24xx_process_response_queue(vha, rsp);
  2240. break;
  2241. default:
  2242. ql_dbg(ql_dbg_async, vha, 0x504f,
  2243. "Unrecognized interrupt type (%d).\n", stat * 0xff);
  2244. break;
  2245. }
  2246. WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
  2247. RD_REG_DWORD_RELAXED(&reg->hccr);
  2248. if (unlikely(IS_QLA83XX(ha) && (ha->pdev->revision == 1)))
  2249. ndelay(3500);
  2250. }
  2251. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2252. if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) &&
  2253. (status & MBX_INTERRUPT) && ha->flags.mbox_int) {
  2254. set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
  2255. complete(&ha->mbx_intr_comp);
  2256. }
  2257. return IRQ_HANDLED;
  2258. }
  2259. static irqreturn_t
  2260. qla24xx_msix_rsp_q(int irq, void *dev_id)
  2261. {
  2262. struct qla_hw_data *ha;
  2263. struct rsp_que *rsp;
  2264. struct device_reg_24xx __iomem *reg;
  2265. struct scsi_qla_host *vha;
  2266. unsigned long flags;
  2267. rsp = (struct rsp_que *) dev_id;
  2268. if (!rsp) {
  2269. ql_log(ql_log_info, NULL, 0x505a,
  2270. "%s: NULL response queue pointer.\n", __func__);
  2271. return IRQ_NONE;
  2272. }
  2273. ha = rsp->hw;
  2274. reg = &ha->iobase->isp24;
  2275. spin_lock_irqsave(&ha->hardware_lock, flags);
  2276. vha = pci_get_drvdata(ha->pdev);
  2277. qla24xx_process_response_queue(vha, rsp);
  2278. if (!ha->flags.disable_msix_handshake) {
  2279. WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
  2280. RD_REG_DWORD_RELAXED(&reg->hccr);
  2281. }
  2282. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2283. return IRQ_HANDLED;
  2284. }
  2285. static irqreturn_t
  2286. qla25xx_msix_rsp_q(int irq, void *dev_id)
  2287. {
  2288. struct qla_hw_data *ha;
  2289. struct rsp_que *rsp;
  2290. struct device_reg_24xx __iomem *reg;
  2291. unsigned long flags;
  2292. rsp = (struct rsp_que *) dev_id;
  2293. if (!rsp) {
  2294. ql_log(ql_log_info, NULL, 0x505b,
  2295. "%s: NULL response queue pointer.\n", __func__);
  2296. return IRQ_NONE;
  2297. }
  2298. ha = rsp->hw;
  2299. /* Clear the interrupt, if enabled, for this response queue */
  2300. if (!ha->flags.disable_msix_handshake) {
  2301. reg = &ha->iobase->isp24;
  2302. spin_lock_irqsave(&ha->hardware_lock, flags);
  2303. WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
  2304. RD_REG_DWORD_RELAXED(&reg->hccr);
  2305. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2306. }
  2307. queue_work_on((int) (rsp->id - 1), ha->wq, &rsp->q_work);
  2308. return IRQ_HANDLED;
  2309. }
  2310. static irqreturn_t
  2311. qla24xx_msix_default(int irq, void *dev_id)
  2312. {
  2313. scsi_qla_host_t *vha;
  2314. struct qla_hw_data *ha;
  2315. struct rsp_que *rsp;
  2316. struct device_reg_24xx __iomem *reg;
  2317. int status;
  2318. uint32_t stat;
  2319. uint32_t hccr;
  2320. uint16_t mb[8];
  2321. unsigned long flags;
  2322. rsp = (struct rsp_que *) dev_id;
  2323. if (!rsp) {
  2324. ql_log(ql_log_info, NULL, 0x505c,
  2325. "%s: NULL response queue pointer.\n", __func__);
  2326. return IRQ_NONE;
  2327. }
  2328. ha = rsp->hw;
  2329. reg = &ha->iobase->isp24;
  2330. status = 0;
  2331. spin_lock_irqsave(&ha->hardware_lock, flags);
  2332. vha = pci_get_drvdata(ha->pdev);
  2333. do {
  2334. stat = RD_REG_DWORD(&reg->host_status);
  2335. if (stat & HSRX_RISC_PAUSED) {
  2336. if (unlikely(pci_channel_offline(ha->pdev)))
  2337. break;
  2338. hccr = RD_REG_DWORD(&reg->hccr);
  2339. ql_log(ql_log_info, vha, 0x5050,
  2340. "RISC paused -- HCCR=%x, Dumping firmware.\n",
  2341. hccr);
  2342. qla2xxx_check_risc_status(vha);
  2343. ha->isp_ops->fw_dump(vha, 1);
  2344. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2345. break;
  2346. } else if ((stat & HSRX_RISC_INT) == 0)
  2347. break;
  2348. switch (stat & 0xff) {
  2349. case INTR_ROM_MB_SUCCESS:
  2350. case INTR_ROM_MB_FAILED:
  2351. case INTR_MB_SUCCESS:
  2352. case INTR_MB_FAILED:
  2353. qla24xx_mbx_completion(vha, MSW(stat));
  2354. status |= MBX_INTERRUPT;
  2355. break;
  2356. case INTR_ASYNC_EVENT:
  2357. mb[0] = MSW(stat);
  2358. mb[1] = RD_REG_WORD(&reg->mailbox1);
  2359. mb[2] = RD_REG_WORD(&reg->mailbox2);
  2360. mb[3] = RD_REG_WORD(&reg->mailbox3);
  2361. qla2x00_async_event(vha, rsp, mb);
  2362. break;
  2363. case INTR_RSP_QUE_UPDATE:
  2364. case INTR_RSP_QUE_UPDATE_83XX:
  2365. qla24xx_process_response_queue(vha, rsp);
  2366. break;
  2367. case INTR_ATIO_QUE_UPDATE:
  2368. qlt_24xx_process_atio_queue(vha);
  2369. break;
  2370. case INTR_ATIO_RSP_QUE_UPDATE:
  2371. qlt_24xx_process_atio_queue(vha);
  2372. qla24xx_process_response_queue(vha, rsp);
  2373. break;
  2374. default:
  2375. ql_dbg(ql_dbg_async, vha, 0x5051,
  2376. "Unrecognized interrupt type (%d).\n", stat & 0xff);
  2377. break;
  2378. }
  2379. WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
  2380. } while (0);
  2381. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2382. if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) &&
  2383. (status & MBX_INTERRUPT) && ha->flags.mbox_int) {
  2384. set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
  2385. complete(&ha->mbx_intr_comp);
  2386. }
  2387. return IRQ_HANDLED;
  2388. }
  2389. /* Interrupt handling helpers. */
  2390. struct qla_init_msix_entry {
  2391. const char *name;
  2392. irq_handler_t handler;
  2393. };
  2394. static struct qla_init_msix_entry msix_entries[3] = {
  2395. { "qla2xxx (default)", qla24xx_msix_default },
  2396. { "qla2xxx (rsp_q)", qla24xx_msix_rsp_q },
  2397. { "qla2xxx (multiq)", qla25xx_msix_rsp_q },
  2398. };
  2399. static struct qla_init_msix_entry qla82xx_msix_entries[2] = {
  2400. { "qla2xxx (default)", qla82xx_msix_default },
  2401. { "qla2xxx (rsp_q)", qla82xx_msix_rsp_q },
  2402. };
  2403. static struct qla_init_msix_entry qla83xx_msix_entries[3] = {
  2404. { "qla2xxx (default)", qla24xx_msix_default },
  2405. { "qla2xxx (rsp_q)", qla24xx_msix_rsp_q },
  2406. { "qla2xxx (atio_q)", qla83xx_msix_atio_q },
  2407. };
  2408. static void
  2409. qla24xx_disable_msix(struct qla_hw_data *ha)
  2410. {
  2411. int i;
  2412. struct qla_msix_entry *qentry;
  2413. scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
  2414. for (i = 0; i < ha->msix_count; i++) {
  2415. qentry = &ha->msix_entries[i];
  2416. if (qentry->have_irq)
  2417. free_irq(qentry->vector, qentry->rsp);
  2418. }
  2419. pci_disable_msix(ha->pdev);
  2420. kfree(ha->msix_entries);
  2421. ha->msix_entries = NULL;
  2422. ha->flags.msix_enabled = 0;
  2423. ql_dbg(ql_dbg_init, vha, 0x0042,
  2424. "Disabled the MSI.\n");
  2425. }
  2426. static int
  2427. qla24xx_enable_msix(struct qla_hw_data *ha, struct rsp_que *rsp)
  2428. {
  2429. #define MIN_MSIX_COUNT 2
  2430. int i, ret;
  2431. struct msix_entry *entries;
  2432. struct qla_msix_entry *qentry;
  2433. scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
  2434. entries = kzalloc(sizeof(struct msix_entry) * ha->msix_count,
  2435. GFP_KERNEL);
  2436. if (!entries) {
  2437. ql_log(ql_log_warn, vha, 0x00bc,
  2438. "Failed to allocate memory for msix_entry.\n");
  2439. return -ENOMEM;
  2440. }
  2441. for (i = 0; i < ha->msix_count; i++)
  2442. entries[i].entry = i;
  2443. ret = pci_enable_msix(ha->pdev, entries, ha->msix_count);
  2444. if (ret) {
  2445. if (ret < MIN_MSIX_COUNT)
  2446. goto msix_failed;
  2447. ql_log(ql_log_warn, vha, 0x00c6,
  2448. "MSI-X: Failed to enable support "
  2449. "-- %d/%d\n Retry with %d vectors.\n",
  2450. ha->msix_count, ret, ret);
  2451. ha->msix_count = ret;
  2452. ret = pci_enable_msix(ha->pdev, entries, ha->msix_count);
  2453. if (ret) {
  2454. msix_failed:
  2455. ql_log(ql_log_fatal, vha, 0x00c7,
  2456. "MSI-X: Failed to enable support, "
  2457. "giving up -- %d/%d.\n",
  2458. ha->msix_count, ret);
  2459. goto msix_out;
  2460. }
  2461. ha->max_rsp_queues = ha->msix_count - 1;
  2462. }
  2463. ha->msix_entries = kzalloc(sizeof(struct qla_msix_entry) *
  2464. ha->msix_count, GFP_KERNEL);
  2465. if (!ha->msix_entries) {
  2466. ql_log(ql_log_fatal, vha, 0x00c8,
  2467. "Failed to allocate memory for ha->msix_entries.\n");
  2468. ret = -ENOMEM;
  2469. goto msix_out;
  2470. }
  2471. ha->flags.msix_enabled = 1;
  2472. for (i = 0; i < ha->msix_count; i++) {
  2473. qentry = &ha->msix_entries[i];
  2474. qentry->vector = entries[i].vector;
  2475. qentry->entry = entries[i].entry;
  2476. qentry->have_irq = 0;
  2477. qentry->rsp = NULL;
  2478. }
  2479. /* Enable MSI-X vectors for the base queue */
  2480. for (i = 0; i < ha->msix_count; i++) {
  2481. qentry = &ha->msix_entries[i];
  2482. if (QLA_TGT_MODE_ENABLED() && IS_ATIO_MSIX_CAPABLE(ha)) {
  2483. ret = request_irq(qentry->vector,
  2484. qla83xx_msix_entries[i].handler,
  2485. 0, qla83xx_msix_entries[i].name, rsp);
  2486. } else if (IS_QLA82XX(ha)) {
  2487. ret = request_irq(qentry->vector,
  2488. qla82xx_msix_entries[i].handler,
  2489. 0, qla82xx_msix_entries[i].name, rsp);
  2490. } else {
  2491. ret = request_irq(qentry->vector,
  2492. msix_entries[i].handler,
  2493. 0, msix_entries[i].name, rsp);
  2494. }
  2495. if (ret) {
  2496. ql_log(ql_log_fatal, vha, 0x00cb,
  2497. "MSI-X: unable to register handler -- %x/%d.\n",
  2498. qentry->vector, ret);
  2499. qla24xx_disable_msix(ha);
  2500. ha->mqenable = 0;
  2501. goto msix_out;
  2502. }
  2503. qentry->have_irq = 1;
  2504. qentry->rsp = rsp;
  2505. rsp->msix = qentry;
  2506. }
  2507. /* Enable MSI-X vector for response queue update for queue 0 */
  2508. if (IS_QLA83XX(ha)) {
  2509. if (ha->msixbase && ha->mqiobase &&
  2510. (ha->max_rsp_queues > 1 || ha->max_req_queues > 1))
  2511. ha->mqenable = 1;
  2512. } else
  2513. if (ha->mqiobase
  2514. && (ha->max_rsp_queues > 1 || ha->max_req_queues > 1))
  2515. ha->mqenable = 1;
  2516. ql_dbg(ql_dbg_multiq, vha, 0xc005,
  2517. "mqiobase=%p, max_rsp_queues=%d, max_req_queues=%d.\n",
  2518. ha->mqiobase, ha->max_rsp_queues, ha->max_req_queues);
  2519. ql_dbg(ql_dbg_init, vha, 0x0055,
  2520. "mqiobase=%p, max_rsp_queues=%d, max_req_queues=%d.\n",
  2521. ha->mqiobase, ha->max_rsp_queues, ha->max_req_queues);
  2522. msix_out:
  2523. kfree(entries);
  2524. return ret;
  2525. }
  2526. int
  2527. qla2x00_request_irqs(struct qla_hw_data *ha, struct rsp_que *rsp)
  2528. {
  2529. int ret;
  2530. device_reg_t __iomem *reg = ha->iobase;
  2531. scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
  2532. /* If possible, enable MSI-X. */
  2533. if (!IS_QLA2432(ha) && !IS_QLA2532(ha) && !IS_QLA8432(ha) &&
  2534. !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha))
  2535. goto skip_msi;
  2536. if (ha->pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
  2537. (ha->pdev->subsystem_device == 0x7040 ||
  2538. ha->pdev->subsystem_device == 0x7041 ||
  2539. ha->pdev->subsystem_device == 0x1705)) {
  2540. ql_log(ql_log_warn, vha, 0x0034,
  2541. "MSI-X: Unsupported ISP 2432 SSVID/SSDID (0x%X,0x%X).\n",
  2542. ha->pdev->subsystem_vendor,
  2543. ha->pdev->subsystem_device);
  2544. goto skip_msi;
  2545. }
  2546. if (IS_QLA2432(ha) && (ha->pdev->revision < QLA_MSIX_CHIP_REV_24XX)) {
  2547. ql_log(ql_log_warn, vha, 0x0035,
  2548. "MSI-X; Unsupported ISP2432 (0x%X, 0x%X).\n",
  2549. ha->pdev->revision, QLA_MSIX_CHIP_REV_24XX);
  2550. goto skip_msix;
  2551. }
  2552. ret = qla24xx_enable_msix(ha, rsp);
  2553. if (!ret) {
  2554. ql_dbg(ql_dbg_init, vha, 0x0036,
  2555. "MSI-X: Enabled (0x%X, 0x%X).\n",
  2556. ha->chip_revision, ha->fw_attributes);
  2557. goto clear_risc_ints;
  2558. }
  2559. ql_log(ql_log_info, vha, 0x0037,
  2560. "MSI-X Falling back-to MSI mode -%d.\n", ret);
  2561. skip_msix:
  2562. if (!IS_QLA24XX(ha) && !IS_QLA2532(ha) && !IS_QLA8432(ha) &&
  2563. !IS_QLA8001(ha) && !IS_QLA82XX(ha))
  2564. goto skip_msi;
  2565. ret = pci_enable_msi(ha->pdev);
  2566. if (!ret) {
  2567. ql_dbg(ql_dbg_init, vha, 0x0038,
  2568. "MSI: Enabled.\n");
  2569. ha->flags.msi_enabled = 1;
  2570. } else
  2571. ql_log(ql_log_warn, vha, 0x0039,
  2572. "MSI-X; Falling back-to INTa mode -- %d.\n", ret);
  2573. /* Skip INTx on ISP82xx. */
  2574. if (!ha->flags.msi_enabled && IS_QLA82XX(ha))
  2575. return QLA_FUNCTION_FAILED;
  2576. skip_msi:
  2577. ret = request_irq(ha->pdev->irq, ha->isp_ops->intr_handler,
  2578. ha->flags.msi_enabled ? 0 : IRQF_SHARED,
  2579. QLA2XXX_DRIVER_NAME, rsp);
  2580. if (ret) {
  2581. ql_log(ql_log_warn, vha, 0x003a,
  2582. "Failed to reserve interrupt %d already in use.\n",
  2583. ha->pdev->irq);
  2584. goto fail;
  2585. } else if (!ha->flags.msi_enabled)
  2586. ql_dbg(ql_dbg_init, vha, 0x0125,
  2587. "INTa mode: Enabled.\n");
  2588. clear_risc_ints:
  2589. spin_lock_irq(&ha->hardware_lock);
  2590. if (!IS_FWI2_CAPABLE(ha))
  2591. WRT_REG_WORD(&reg->isp.semaphore, 0);
  2592. spin_unlock_irq(&ha->hardware_lock);
  2593. fail:
  2594. return ret;
  2595. }
  2596. void
  2597. qla2x00_free_irqs(scsi_qla_host_t *vha)
  2598. {
  2599. struct qla_hw_data *ha = vha->hw;
  2600. struct rsp_que *rsp;
  2601. /*
  2602. * We need to check that ha->rsp_q_map is valid in case we are called
  2603. * from a probe failure context.
  2604. */
  2605. if (!ha->rsp_q_map || !ha->rsp_q_map[0])
  2606. return;
  2607. rsp = ha->rsp_q_map[0];
  2608. if (ha->flags.msix_enabled)
  2609. qla24xx_disable_msix(ha);
  2610. else if (ha->flags.msi_enabled) {
  2611. free_irq(ha->pdev->irq, rsp);
  2612. pci_disable_msi(ha->pdev);
  2613. } else
  2614. free_irq(ha->pdev->irq, rsp);
  2615. }
  2616. int qla25xx_request_irq(struct rsp_que *rsp)
  2617. {
  2618. struct qla_hw_data *ha = rsp->hw;
  2619. struct qla_init_msix_entry *intr = &msix_entries[2];
  2620. struct qla_msix_entry *msix = rsp->msix;
  2621. scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
  2622. int ret;
  2623. ret = request_irq(msix->vector, intr->handler, 0, intr->name, rsp);
  2624. if (ret) {
  2625. ql_log(ql_log_fatal, vha, 0x00e6,
  2626. "MSI-X: Unable to register handler -- %x/%d.\n",
  2627. msix->vector, ret);
  2628. return ret;
  2629. }
  2630. msix->have_irq = 1;
  2631. msix->rsp = rsp;
  2632. return ret;
  2633. }