iwl-agn.c 109 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873187418751876187718781879188018811882188318841885188618871888188918901891189218931894189518961897189818991900190119021903190419051906190719081909191019111912191319141915191619171918191919201921192219231924192519261927192819291930193119321933193419351936193719381939194019411942194319441945194619471948194919501951195219531954195519561957195819591960196119621963196419651966196719681969197019711972197319741975197619771978197919801981198219831984198519861987198819891990199119921993199419951996199719981999200020012002200320042005200620072008200920102011201220132014201520162017201820192020202120222023202420252026202720282029203020312032203320342035203620372038203920402041204220432044204520462047204820492050205120522053205420552056205720582059206020612062206320642065206620672068206920702071207220732074207520762077207820792080208120822083208420852086208720882089209020912092209320942095209620972098209921002101210221032104210521062107210821092110211121122113211421152116211721182119212021212122212321242125212621272128212921302131213221332134213521362137213821392140214121422143214421452146214721482149215021512152215321542155215621572158215921602161216221632164216521662167216821692170217121722173217421752176217721782179218021812182218321842185218621872188218921902191219221932194219521962197219821992200220122022203220422052206220722082209221022112212221322142215221622172218221922202221222222232224222522262227222822292230223122322233223422352236223722382239224022412242224322442245224622472248224922502251225222532254225522562257225822592260226122622263226422652266226722682269227022712272227322742275227622772278227922802281228222832284228522862287228822892290229122922293229422952296229722982299230023012302230323042305230623072308230923102311231223132314231523162317231823192320232123222323232423252326232723282329233023312332233323342335233623372338233923402341234223432344234523462347234823492350235123522353235423552356235723582359236023612362236323642365236623672368236923702371237223732374237523762377237823792380238123822383238423852386238723882389239023912392239323942395239623972398239924002401240224032404240524062407240824092410241124122413241424152416241724182419242024212422242324242425242624272428242924302431243224332434243524362437243824392440244124422443244424452446244724482449245024512452245324542455245624572458245924602461246224632464246524662467246824692470247124722473247424752476247724782479248024812482248324842485248624872488248924902491249224932494249524962497249824992500250125022503250425052506250725082509251025112512251325142515251625172518251925202521252225232524252525262527252825292530253125322533253425352536253725382539254025412542254325442545254625472548254925502551255225532554255525562557255825592560256125622563256425652566256725682569257025712572257325742575257625772578257925802581258225832584258525862587258825892590259125922593259425952596259725982599260026012602260326042605260626072608260926102611261226132614261526162617261826192620262126222623262426252626262726282629263026312632263326342635263626372638263926402641264226432644264526462647264826492650265126522653265426552656265726582659266026612662266326642665266626672668266926702671267226732674267526762677267826792680268126822683268426852686268726882689269026912692269326942695269626972698269927002701270227032704270527062707270827092710271127122713271427152716271727182719272027212722272327242725272627272728272927302731273227332734273527362737273827392740274127422743274427452746274727482749275027512752275327542755275627572758275927602761276227632764276527662767276827692770277127722773277427752776277727782779278027812782278327842785278627872788278927902791279227932794279527962797279827992800280128022803280428052806280728082809281028112812281328142815281628172818281928202821282228232824282528262827282828292830283128322833283428352836283728382839284028412842284328442845284628472848284928502851285228532854285528562857285828592860286128622863286428652866286728682869287028712872287328742875287628772878287928802881288228832884288528862887288828892890289128922893289428952896289728982899290029012902290329042905290629072908290929102911291229132914291529162917291829192920292129222923292429252926292729282929293029312932293329342935293629372938293929402941294229432944294529462947294829492950295129522953295429552956295729582959296029612962296329642965296629672968296929702971297229732974297529762977297829792980298129822983298429852986298729882989299029912992299329942995299629972998299930003001300230033004300530063007300830093010301130123013301430153016301730183019302030213022302330243025302630273028302930303031303230333034303530363037303830393040304130423043304430453046304730483049305030513052305330543055305630573058305930603061306230633064306530663067306830693070307130723073307430753076307730783079308030813082308330843085308630873088308930903091309230933094309530963097309830993100310131023103310431053106310731083109311031113112311331143115311631173118311931203121312231233124312531263127312831293130313131323133313431353136313731383139314031413142314331443145314631473148314931503151315231533154315531563157315831593160316131623163316431653166316731683169317031713172317331743175317631773178317931803181318231833184318531863187318831893190319131923193319431953196319731983199320032013202320332043205320632073208320932103211321232133214321532163217321832193220322132223223322432253226322732283229323032313232323332343235323632373238323932403241324232433244324532463247324832493250325132523253325432553256325732583259326032613262326332643265326632673268326932703271327232733274327532763277327832793280328132823283328432853286328732883289329032913292329332943295329632973298329933003301330233033304330533063307330833093310331133123313331433153316331733183319332033213322332333243325332633273328332933303331333233333334333533363337333833393340334133423343334433453346334733483349335033513352335333543355335633573358335933603361336233633364336533663367336833693370337133723373337433753376337733783379338033813382338333843385338633873388338933903391339233933394339533963397339833993400340134023403340434053406340734083409341034113412341334143415341634173418341934203421342234233424342534263427342834293430343134323433343434353436343734383439344034413442344334443445344634473448344934503451345234533454345534563457345834593460346134623463346434653466346734683469347034713472347334743475347634773478347934803481348234833484348534863487348834893490349134923493349434953496349734983499350035013502350335043505350635073508350935103511351235133514351535163517351835193520352135223523352435253526352735283529353035313532353335343535353635373538353935403541354235433544354535463547354835493550355135523553355435553556355735583559356035613562356335643565356635673568356935703571357235733574357535763577357835793580358135823583358435853586358735883589359035913592359335943595359635973598359936003601360236033604360536063607360836093610361136123613361436153616361736183619362036213622362336243625362636273628362936303631363236333634363536363637363836393640364136423643364436453646364736483649365036513652365336543655365636573658365936603661366236633664366536663667366836693670367136723673367436753676367736783679368036813682368336843685368636873688368936903691369236933694369536963697369836993700370137023703370437053706370737083709371037113712371337143715371637173718371937203721372237233724372537263727372837293730373137323733373437353736373737383739374037413742374337443745374637473748374937503751375237533754375537563757375837593760376137623763376437653766376737683769377037713772377337743775377637773778377937803781378237833784378537863787378837893790379137923793379437953796379737983799380038013802380338043805380638073808380938103811381238133814381538163817381838193820382138223823382438253826382738283829383038313832383338343835383638373838383938403841384238433844384538463847384838493850385138523853385438553856385738583859386038613862386338643865386638673868386938703871387238733874387538763877387838793880
  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #include <linux/kernel.h>
  30. #include <linux/module.h>
  31. #include <linux/init.h>
  32. #include <linux/pci.h>
  33. #include <linux/dma-mapping.h>
  34. #include <linux/delay.h>
  35. #include <linux/sched.h>
  36. #include <linux/skbuff.h>
  37. #include <linux/netdevice.h>
  38. #include <linux/wireless.h>
  39. #include <linux/firmware.h>
  40. #include <linux/etherdevice.h>
  41. #include <linux/if_arp.h>
  42. #include <net/mac80211.h>
  43. #include <asm/div64.h>
  44. #define DRV_NAME "iwlagn"
  45. #include "iwl-eeprom.h"
  46. #include "iwl-dev.h"
  47. #include "iwl-core.h"
  48. #include "iwl-io.h"
  49. #include "iwl-helpers.h"
  50. #include "iwl-sta.h"
  51. #include "iwl-calib.h"
  52. /******************************************************************************
  53. *
  54. * module boiler plate
  55. *
  56. ******************************************************************************/
  57. /*
  58. * module name, copyright, version, etc.
  59. */
  60. #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
  61. #ifdef CONFIG_IWLWIFI_DEBUG
  62. #define VD "d"
  63. #else
  64. #define VD
  65. #endif
  66. #ifdef CONFIG_IWLWIFI_SPECTRUM_MEASUREMENT
  67. #define VS "s"
  68. #else
  69. #define VS
  70. #endif
  71. #define DRV_VERSION IWLWIFI_VERSION VD VS
  72. MODULE_DESCRIPTION(DRV_DESCRIPTION);
  73. MODULE_VERSION(DRV_VERSION);
  74. MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  75. MODULE_LICENSE("GPL");
  76. MODULE_ALIAS("iwl4965");
  77. /*************** STATION TABLE MANAGEMENT ****
  78. * mac80211 should be examined to determine if sta_info is duplicating
  79. * the functionality provided here
  80. */
  81. /**************************************************************/
  82. /**
  83. * iwl_commit_rxon - commit staging_rxon to hardware
  84. *
  85. * The RXON command in staging_rxon is committed to the hardware and
  86. * the active_rxon structure is updated with the new data. This
  87. * function correctly transitions out of the RXON_ASSOC_MSK state if
  88. * a HW tune is required based on the RXON structure changes.
  89. */
  90. int iwl_commit_rxon(struct iwl_priv *priv)
  91. {
  92. /* cast away the const for active_rxon in this function */
  93. struct iwl_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
  94. int ret;
  95. bool new_assoc =
  96. !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
  97. if (!iwl_is_alive(priv))
  98. return -EBUSY;
  99. /* always get timestamp with Rx frame */
  100. priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
  101. ret = iwl_check_rxon_cmd(priv);
  102. if (ret) {
  103. IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
  104. return -EINVAL;
  105. }
  106. /*
  107. * receive commit_rxon request
  108. * abort any previous channel switch if still in process
  109. */
  110. if (priv->switch_rxon.switch_in_progress &&
  111. (priv->switch_rxon.channel != priv->staging_rxon.channel)) {
  112. IWL_DEBUG_11H(priv, "abort channel switch on %d\n",
  113. le16_to_cpu(priv->switch_rxon.channel));
  114. priv->switch_rxon.switch_in_progress = false;
  115. }
  116. /* If we don't need to send a full RXON, we can use
  117. * iwl_rxon_assoc_cmd which is used to reconfigure filter
  118. * and other flags for the current radio configuration. */
  119. if (!iwl_full_rxon_required(priv)) {
  120. ret = iwl_send_rxon_assoc(priv);
  121. if (ret) {
  122. IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret);
  123. return ret;
  124. }
  125. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  126. iwl_print_rx_config_cmd(priv);
  127. return 0;
  128. }
  129. /* station table will be cleared */
  130. priv->assoc_station_added = 0;
  131. /* If we are currently associated and the new config requires
  132. * an RXON_ASSOC and the new config wants the associated mask enabled,
  133. * we must clear the associated from the active configuration
  134. * before we apply the new config */
  135. if (iwl_is_associated(priv) && new_assoc) {
  136. IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
  137. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  138. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  139. sizeof(struct iwl_rxon_cmd),
  140. &priv->active_rxon);
  141. /* If the mask clearing failed then we set
  142. * active_rxon back to what it was previously */
  143. if (ret) {
  144. active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
  145. IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret);
  146. return ret;
  147. }
  148. }
  149. IWL_DEBUG_INFO(priv, "Sending RXON\n"
  150. "* with%s RXON_FILTER_ASSOC_MSK\n"
  151. "* channel = %d\n"
  152. "* bssid = %pM\n",
  153. (new_assoc ? "" : "out"),
  154. le16_to_cpu(priv->staging_rxon.channel),
  155. priv->staging_rxon.bssid_addr);
  156. iwl_set_rxon_hwcrypto(priv, !priv->cfg->mod_params->sw_crypto);
  157. /* Apply the new configuration
  158. * RXON unassoc clears the station table in uCode, send it before
  159. * we add the bcast station. If assoc bit is set, we will send RXON
  160. * after having added the bcast and bssid station.
  161. */
  162. if (!new_assoc) {
  163. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  164. sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
  165. if (ret) {
  166. IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
  167. return ret;
  168. }
  169. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  170. }
  171. iwl_clear_stations_table(priv);
  172. priv->start_calib = 0;
  173. /* Add the broadcast address so we can send broadcast frames */
  174. iwl_add_bcast_station(priv);
  175. /* If we have set the ASSOC_MSK and we are in BSS mode then
  176. * add the IWL_AP_ID to the station rate table */
  177. if (new_assoc) {
  178. if (priv->iw_mode == NL80211_IFTYPE_STATION) {
  179. ret = iwl_rxon_add_station(priv,
  180. priv->active_rxon.bssid_addr, 1);
  181. if (ret == IWL_INVALID_STATION) {
  182. IWL_ERR(priv,
  183. "Error adding AP address for TX.\n");
  184. return -EIO;
  185. }
  186. priv->assoc_station_added = 1;
  187. if (priv->default_wep_key &&
  188. iwl_send_static_wepkey_cmd(priv, 0))
  189. IWL_ERR(priv,
  190. "Could not send WEP static key.\n");
  191. }
  192. /*
  193. * allow CTS-to-self if possible for new association.
  194. * this is relevant only for 5000 series and up,
  195. * but will not damage 4965
  196. */
  197. priv->staging_rxon.flags |= RXON_FLG_SELF_CTS_EN;
  198. /* Apply the new configuration
  199. * RXON assoc doesn't clear the station table in uCode,
  200. */
  201. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  202. sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
  203. if (ret) {
  204. IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
  205. return ret;
  206. }
  207. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  208. }
  209. iwl_print_rx_config_cmd(priv);
  210. iwl_init_sensitivity(priv);
  211. /* If we issue a new RXON command which required a tune then we must
  212. * send a new TXPOWER command or we won't be able to Tx any frames */
  213. ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true);
  214. if (ret) {
  215. IWL_ERR(priv, "Error sending TX power (%d)\n", ret);
  216. return ret;
  217. }
  218. return 0;
  219. }
  220. void iwl_update_chain_flags(struct iwl_priv *priv)
  221. {
  222. if (priv->cfg->ops->hcmd->set_rxon_chain)
  223. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  224. iwlcore_commit_rxon(priv);
  225. }
  226. static void iwl_clear_free_frames(struct iwl_priv *priv)
  227. {
  228. struct list_head *element;
  229. IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
  230. priv->frames_count);
  231. while (!list_empty(&priv->free_frames)) {
  232. element = priv->free_frames.next;
  233. list_del(element);
  234. kfree(list_entry(element, struct iwl_frame, list));
  235. priv->frames_count--;
  236. }
  237. if (priv->frames_count) {
  238. IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
  239. priv->frames_count);
  240. priv->frames_count = 0;
  241. }
  242. }
  243. static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
  244. {
  245. struct iwl_frame *frame;
  246. struct list_head *element;
  247. if (list_empty(&priv->free_frames)) {
  248. frame = kzalloc(sizeof(*frame), GFP_KERNEL);
  249. if (!frame) {
  250. IWL_ERR(priv, "Could not allocate frame!\n");
  251. return NULL;
  252. }
  253. priv->frames_count++;
  254. return frame;
  255. }
  256. element = priv->free_frames.next;
  257. list_del(element);
  258. return list_entry(element, struct iwl_frame, list);
  259. }
  260. static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
  261. {
  262. memset(frame, 0, sizeof(*frame));
  263. list_add(&frame->list, &priv->free_frames);
  264. }
  265. static u32 iwl_fill_beacon_frame(struct iwl_priv *priv,
  266. struct ieee80211_hdr *hdr,
  267. int left)
  268. {
  269. if (!iwl_is_associated(priv) || !priv->ibss_beacon ||
  270. ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
  271. (priv->iw_mode != NL80211_IFTYPE_AP)))
  272. return 0;
  273. if (priv->ibss_beacon->len > left)
  274. return 0;
  275. memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
  276. return priv->ibss_beacon->len;
  277. }
  278. /* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
  279. static void iwl_set_beacon_tim(struct iwl_priv *priv,
  280. struct iwl_tx_beacon_cmd *tx_beacon_cmd,
  281. u8 *beacon, u32 frame_size)
  282. {
  283. u16 tim_idx;
  284. struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
  285. /*
  286. * The index is relative to frame start but we start looking at the
  287. * variable-length part of the beacon.
  288. */
  289. tim_idx = mgmt->u.beacon.variable - beacon;
  290. /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
  291. while ((tim_idx < (frame_size - 2)) &&
  292. (beacon[tim_idx] != WLAN_EID_TIM))
  293. tim_idx += beacon[tim_idx+1] + 2;
  294. /* If TIM field was found, set variables */
  295. if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
  296. tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
  297. tx_beacon_cmd->tim_size = beacon[tim_idx+1];
  298. } else
  299. IWL_WARN(priv, "Unable to find TIM Element in beacon\n");
  300. }
  301. static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
  302. struct iwl_frame *frame)
  303. {
  304. struct iwl_tx_beacon_cmd *tx_beacon_cmd;
  305. u32 frame_size;
  306. u32 rate_flags;
  307. u32 rate;
  308. /*
  309. * We have to set up the TX command, the TX Beacon command, and the
  310. * beacon contents.
  311. */
  312. /* Initialize memory */
  313. tx_beacon_cmd = &frame->u.beacon;
  314. memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
  315. /* Set up TX beacon contents */
  316. frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
  317. sizeof(frame->u) - sizeof(*tx_beacon_cmd));
  318. if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
  319. return 0;
  320. /* Set up TX command fields */
  321. tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
  322. tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
  323. tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  324. tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
  325. TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK;
  326. /* Set up TX beacon command fields */
  327. iwl_set_beacon_tim(priv, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame,
  328. frame_size);
  329. /* Set up packet rate and flags */
  330. rate = iwl_rate_get_lowest_plcp(priv);
  331. priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant);
  332. rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
  333. if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE))
  334. rate_flags |= RATE_MCS_CCK_MSK;
  335. tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate,
  336. rate_flags);
  337. return sizeof(*tx_beacon_cmd) + frame_size;
  338. }
  339. static int iwl_send_beacon_cmd(struct iwl_priv *priv)
  340. {
  341. struct iwl_frame *frame;
  342. unsigned int frame_size;
  343. int rc;
  344. frame = iwl_get_free_frame(priv);
  345. if (!frame) {
  346. IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
  347. "command.\n");
  348. return -ENOMEM;
  349. }
  350. frame_size = iwl_hw_get_beacon_cmd(priv, frame);
  351. if (!frame_size) {
  352. IWL_ERR(priv, "Error configuring the beacon command\n");
  353. iwl_free_frame(priv, frame);
  354. return -EINVAL;
  355. }
  356. rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
  357. &frame->u.cmd[0]);
  358. iwl_free_frame(priv, frame);
  359. return rc;
  360. }
  361. static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
  362. {
  363. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  364. dma_addr_t addr = get_unaligned_le32(&tb->lo);
  365. if (sizeof(dma_addr_t) > sizeof(u32))
  366. addr |=
  367. ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
  368. return addr;
  369. }
  370. static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
  371. {
  372. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  373. return le16_to_cpu(tb->hi_n_len) >> 4;
  374. }
  375. static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
  376. dma_addr_t addr, u16 len)
  377. {
  378. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  379. u16 hi_n_len = len << 4;
  380. put_unaligned_le32(addr, &tb->lo);
  381. if (sizeof(dma_addr_t) > sizeof(u32))
  382. hi_n_len |= ((addr >> 16) >> 16) & 0xF;
  383. tb->hi_n_len = cpu_to_le16(hi_n_len);
  384. tfd->num_tbs = idx + 1;
  385. }
  386. static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
  387. {
  388. return tfd->num_tbs & 0x1f;
  389. }
  390. /**
  391. * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
  392. * @priv - driver private data
  393. * @txq - tx queue
  394. *
  395. * Does NOT advance any TFD circular buffer read/write indexes
  396. * Does NOT free the TFD itself (which is within circular buffer)
  397. */
  398. void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
  399. {
  400. struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
  401. struct iwl_tfd *tfd;
  402. struct pci_dev *dev = priv->pci_dev;
  403. int index = txq->q.read_ptr;
  404. int i;
  405. int num_tbs;
  406. tfd = &tfd_tmp[index];
  407. /* Sanity check on number of chunks */
  408. num_tbs = iwl_tfd_get_num_tbs(tfd);
  409. if (num_tbs >= IWL_NUM_OF_TBS) {
  410. IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
  411. /* @todo issue fatal error, it is quite serious situation */
  412. return;
  413. }
  414. /* Unmap tx_cmd */
  415. if (num_tbs)
  416. pci_unmap_single(dev,
  417. pci_unmap_addr(&txq->meta[index], mapping),
  418. pci_unmap_len(&txq->meta[index], len),
  419. PCI_DMA_BIDIRECTIONAL);
  420. /* Unmap chunks, if any. */
  421. for (i = 1; i < num_tbs; i++) {
  422. pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
  423. iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
  424. if (txq->txb) {
  425. dev_kfree_skb(txq->txb[txq->q.read_ptr].skb[i - 1]);
  426. txq->txb[txq->q.read_ptr].skb[i - 1] = NULL;
  427. }
  428. }
  429. }
  430. int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
  431. struct iwl_tx_queue *txq,
  432. dma_addr_t addr, u16 len,
  433. u8 reset, u8 pad)
  434. {
  435. struct iwl_queue *q;
  436. struct iwl_tfd *tfd, *tfd_tmp;
  437. u32 num_tbs;
  438. q = &txq->q;
  439. tfd_tmp = (struct iwl_tfd *)txq->tfds;
  440. tfd = &tfd_tmp[q->write_ptr];
  441. if (reset)
  442. memset(tfd, 0, sizeof(*tfd));
  443. num_tbs = iwl_tfd_get_num_tbs(tfd);
  444. /* Each TFD can point to a maximum 20 Tx buffers */
  445. if (num_tbs >= IWL_NUM_OF_TBS) {
  446. IWL_ERR(priv, "Error can not send more than %d chunks\n",
  447. IWL_NUM_OF_TBS);
  448. return -EINVAL;
  449. }
  450. BUG_ON(addr & ~DMA_BIT_MASK(36));
  451. if (unlikely(addr & ~IWL_TX_DMA_MASK))
  452. IWL_ERR(priv, "Unaligned address = %llx\n",
  453. (unsigned long long)addr);
  454. iwl_tfd_set_tb(tfd, num_tbs, addr, len);
  455. return 0;
  456. }
  457. /*
  458. * Tell nic where to find circular buffer of Tx Frame Descriptors for
  459. * given Tx queue, and enable the DMA channel used for that queue.
  460. *
  461. * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
  462. * channels supported in hardware.
  463. */
  464. int iwl_hw_tx_queue_init(struct iwl_priv *priv,
  465. struct iwl_tx_queue *txq)
  466. {
  467. int txq_id = txq->q.id;
  468. /* Circular buffer (TFD queue in DRAM) physical base address */
  469. iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
  470. txq->q.dma_addr >> 8);
  471. return 0;
  472. }
  473. /******************************************************************************
  474. *
  475. * Generic RX handler implementations
  476. *
  477. ******************************************************************************/
  478. static void iwl_rx_reply_alive(struct iwl_priv *priv,
  479. struct iwl_rx_mem_buffer *rxb)
  480. {
  481. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  482. struct iwl_alive_resp *palive;
  483. struct delayed_work *pwork;
  484. palive = &pkt->u.alive_frame;
  485. IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
  486. "0x%01X 0x%01X\n",
  487. palive->is_valid, palive->ver_type,
  488. palive->ver_subtype);
  489. if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
  490. IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
  491. memcpy(&priv->card_alive_init,
  492. &pkt->u.alive_frame,
  493. sizeof(struct iwl_init_alive_resp));
  494. pwork = &priv->init_alive_start;
  495. } else {
  496. IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
  497. memcpy(&priv->card_alive, &pkt->u.alive_frame,
  498. sizeof(struct iwl_alive_resp));
  499. pwork = &priv->alive_start;
  500. }
  501. /* We delay the ALIVE response by 5ms to
  502. * give the HW RF Kill time to activate... */
  503. if (palive->is_valid == UCODE_VALID_OK)
  504. queue_delayed_work(priv->workqueue, pwork,
  505. msecs_to_jiffies(5));
  506. else
  507. IWL_WARN(priv, "uCode did not respond OK.\n");
  508. }
  509. static void iwl_bg_beacon_update(struct work_struct *work)
  510. {
  511. struct iwl_priv *priv =
  512. container_of(work, struct iwl_priv, beacon_update);
  513. struct sk_buff *beacon;
  514. /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
  515. beacon = ieee80211_beacon_get(priv->hw, priv->vif);
  516. if (!beacon) {
  517. IWL_ERR(priv, "update beacon failed\n");
  518. return;
  519. }
  520. mutex_lock(&priv->mutex);
  521. /* new beacon skb is allocated every time; dispose previous.*/
  522. if (priv->ibss_beacon)
  523. dev_kfree_skb(priv->ibss_beacon);
  524. priv->ibss_beacon = beacon;
  525. mutex_unlock(&priv->mutex);
  526. iwl_send_beacon_cmd(priv);
  527. }
  528. /**
  529. * iwl_bg_statistics_periodic - Timer callback to queue statistics
  530. *
  531. * This callback is provided in order to send a statistics request.
  532. *
  533. * This timer function is continually reset to execute within
  534. * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
  535. * was received. We need to ensure we receive the statistics in order
  536. * to update the temperature used for calibrating the TXPOWER.
  537. */
  538. static void iwl_bg_statistics_periodic(unsigned long data)
  539. {
  540. struct iwl_priv *priv = (struct iwl_priv *)data;
  541. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  542. return;
  543. /* dont send host command if rf-kill is on */
  544. if (!iwl_is_ready_rf(priv))
  545. return;
  546. iwl_send_statistics_request(priv, CMD_ASYNC, false);
  547. }
  548. static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
  549. u32 start_idx, u32 num_events,
  550. u32 mode)
  551. {
  552. u32 i;
  553. u32 ptr; /* SRAM byte address of log data */
  554. u32 ev, time, data; /* event log data */
  555. unsigned long reg_flags;
  556. if (mode == 0)
  557. ptr = base + (4 * sizeof(u32)) + (start_idx * 2 * sizeof(u32));
  558. else
  559. ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32));
  560. /* Make sure device is powered up for SRAM reads */
  561. spin_lock_irqsave(&priv->reg_lock, reg_flags);
  562. if (iwl_grab_nic_access(priv)) {
  563. spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
  564. return;
  565. }
  566. /* Set starting address; reads will auto-increment */
  567. _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
  568. rmb();
  569. /*
  570. * "time" is actually "data" for mode 0 (no timestamp).
  571. * place event id # at far right for easier visual parsing.
  572. */
  573. for (i = 0; i < num_events; i++) {
  574. ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  575. time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  576. if (mode == 0) {
  577. trace_iwlwifi_dev_ucode_cont_event(priv,
  578. 0, time, ev);
  579. } else {
  580. data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  581. trace_iwlwifi_dev_ucode_cont_event(priv,
  582. time, data, ev);
  583. }
  584. }
  585. /* Allow device to power down */
  586. iwl_release_nic_access(priv);
  587. spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
  588. }
  589. void iwl_continuous_event_trace(struct iwl_priv *priv)
  590. {
  591. u32 capacity; /* event log capacity in # entries */
  592. u32 base; /* SRAM byte address of event log header */
  593. u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
  594. u32 num_wraps; /* # times uCode wrapped to top of log */
  595. u32 next_entry; /* index of next entry to be written by uCode */
  596. if (priv->ucode_type == UCODE_INIT)
  597. base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
  598. else
  599. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  600. if (priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
  601. capacity = iwl_read_targ_mem(priv, base);
  602. num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
  603. mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
  604. next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
  605. } else
  606. return;
  607. if (num_wraps == priv->event_log.num_wraps) {
  608. iwl_print_cont_event_trace(priv,
  609. base, priv->event_log.next_entry,
  610. next_entry - priv->event_log.next_entry,
  611. mode);
  612. priv->event_log.non_wraps_count++;
  613. } else {
  614. if ((num_wraps - priv->event_log.num_wraps) > 1)
  615. priv->event_log.wraps_more_count++;
  616. else
  617. priv->event_log.wraps_once_count++;
  618. trace_iwlwifi_dev_ucode_wrap_event(priv,
  619. num_wraps - priv->event_log.num_wraps,
  620. next_entry, priv->event_log.next_entry);
  621. if (next_entry < priv->event_log.next_entry) {
  622. iwl_print_cont_event_trace(priv, base,
  623. priv->event_log.next_entry,
  624. capacity - priv->event_log.next_entry,
  625. mode);
  626. iwl_print_cont_event_trace(priv, base, 0,
  627. next_entry, mode);
  628. } else {
  629. iwl_print_cont_event_trace(priv, base,
  630. next_entry, capacity - next_entry,
  631. mode);
  632. iwl_print_cont_event_trace(priv, base, 0,
  633. next_entry, mode);
  634. }
  635. }
  636. priv->event_log.num_wraps = num_wraps;
  637. priv->event_log.next_entry = next_entry;
  638. }
  639. /**
  640. * iwl_bg_ucode_trace - Timer callback to log ucode event
  641. *
  642. * The timer is continually set to execute every
  643. * UCODE_TRACE_PERIOD milliseconds after the last timer expired
  644. * this function is to perform continuous uCode event logging operation
  645. * if enabled
  646. */
  647. static void iwl_bg_ucode_trace(unsigned long data)
  648. {
  649. struct iwl_priv *priv = (struct iwl_priv *)data;
  650. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  651. return;
  652. if (priv->event_log.ucode_trace) {
  653. iwl_continuous_event_trace(priv);
  654. /* Reschedule the timer to occur in UCODE_TRACE_PERIOD */
  655. mod_timer(&priv->ucode_trace,
  656. jiffies + msecs_to_jiffies(UCODE_TRACE_PERIOD));
  657. }
  658. }
  659. static void iwl_rx_beacon_notif(struct iwl_priv *priv,
  660. struct iwl_rx_mem_buffer *rxb)
  661. {
  662. #ifdef CONFIG_IWLWIFI_DEBUG
  663. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  664. struct iwl4965_beacon_notif *beacon =
  665. (struct iwl4965_beacon_notif *)pkt->u.raw;
  666. u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
  667. IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
  668. "tsf %d %d rate %d\n",
  669. le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
  670. beacon->beacon_notify_hdr.failure_frame,
  671. le32_to_cpu(beacon->ibss_mgr_status),
  672. le32_to_cpu(beacon->high_tsf),
  673. le32_to_cpu(beacon->low_tsf), rate);
  674. #endif
  675. if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
  676. (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
  677. queue_work(priv->workqueue, &priv->beacon_update);
  678. }
  679. /* Handle notification from uCode that card's power state is changing
  680. * due to software, hardware, or critical temperature RFKILL */
  681. static void iwl_rx_card_state_notif(struct iwl_priv *priv,
  682. struct iwl_rx_mem_buffer *rxb)
  683. {
  684. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  685. u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
  686. unsigned long status = priv->status;
  687. IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s CT:%s\n",
  688. (flags & HW_CARD_DISABLED) ? "Kill" : "On",
  689. (flags & SW_CARD_DISABLED) ? "Kill" : "On",
  690. (flags & CT_CARD_DISABLED) ?
  691. "Reached" : "Not reached");
  692. if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
  693. CT_CARD_DISABLED)) {
  694. iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
  695. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  696. iwl_write_direct32(priv, HBUS_TARG_MBX_C,
  697. HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
  698. if (!(flags & RXON_CARD_DISABLED)) {
  699. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  700. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  701. iwl_write_direct32(priv, HBUS_TARG_MBX_C,
  702. HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
  703. }
  704. if (flags & CT_CARD_DISABLED)
  705. iwl_tt_enter_ct_kill(priv);
  706. }
  707. if (!(flags & CT_CARD_DISABLED))
  708. iwl_tt_exit_ct_kill(priv);
  709. if (flags & HW_CARD_DISABLED)
  710. set_bit(STATUS_RF_KILL_HW, &priv->status);
  711. else
  712. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  713. if (!(flags & RXON_CARD_DISABLED))
  714. iwl_scan_cancel(priv);
  715. if ((test_bit(STATUS_RF_KILL_HW, &status) !=
  716. test_bit(STATUS_RF_KILL_HW, &priv->status)))
  717. wiphy_rfkill_set_hw_state(priv->hw->wiphy,
  718. test_bit(STATUS_RF_KILL_HW, &priv->status));
  719. else
  720. wake_up_interruptible(&priv->wait_command_queue);
  721. }
  722. int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
  723. {
  724. if (src == IWL_PWR_SRC_VAUX) {
  725. if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
  726. iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  727. APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
  728. ~APMG_PS_CTRL_MSK_PWR_SRC);
  729. } else {
  730. iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  731. APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
  732. ~APMG_PS_CTRL_MSK_PWR_SRC);
  733. }
  734. return 0;
  735. }
  736. /**
  737. * iwl_setup_rx_handlers - Initialize Rx handler callbacks
  738. *
  739. * Setup the RX handlers for each of the reply types sent from the uCode
  740. * to the host.
  741. *
  742. * This function chains into the hardware specific files for them to setup
  743. * any hardware specific handlers as well.
  744. */
  745. static void iwl_setup_rx_handlers(struct iwl_priv *priv)
  746. {
  747. priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
  748. priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
  749. priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
  750. priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
  751. priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
  752. iwl_rx_pm_debug_statistics_notif;
  753. priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif;
  754. /*
  755. * The same handler is used for both the REPLY to a discrete
  756. * statistics request from the host as well as for the periodic
  757. * statistics notifications (after received beacons) from the uCode.
  758. */
  759. priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_reply_statistics;
  760. priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
  761. iwl_setup_spectrum_handlers(priv);
  762. iwl_setup_rx_scan_handlers(priv);
  763. /* status change handler */
  764. priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
  765. priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
  766. iwl_rx_missed_beacon_notif;
  767. /* Rx handlers */
  768. priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl_rx_reply_rx_phy;
  769. priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl_rx_reply_rx;
  770. /* block ack */
  771. priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl_rx_reply_compressed_ba;
  772. /* Set up hardware specific Rx handlers */
  773. priv->cfg->ops->lib->rx_handler_setup(priv);
  774. }
  775. /**
  776. * iwl_rx_handle - Main entry function for receiving responses from uCode
  777. *
  778. * Uses the priv->rx_handlers callback function array to invoke
  779. * the appropriate handlers, including command responses,
  780. * frame-received notifications, and other notifications.
  781. */
  782. void iwl_rx_handle(struct iwl_priv *priv)
  783. {
  784. struct iwl_rx_mem_buffer *rxb;
  785. struct iwl_rx_packet *pkt;
  786. struct iwl_rx_queue *rxq = &priv->rxq;
  787. u32 r, i;
  788. int reclaim;
  789. unsigned long flags;
  790. u8 fill_rx = 0;
  791. u32 count = 8;
  792. int total_empty;
  793. /* uCode's read index (stored in shared DRAM) indicates the last Rx
  794. * buffer that the driver may process (last buffer filled by ucode). */
  795. r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
  796. i = rxq->read;
  797. /* Rx interrupt, but nothing sent from uCode */
  798. if (i == r)
  799. IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
  800. /* calculate total frames need to be restock after handling RX */
  801. total_empty = r - rxq->write_actual;
  802. if (total_empty < 0)
  803. total_empty += RX_QUEUE_SIZE;
  804. if (total_empty > (RX_QUEUE_SIZE / 2))
  805. fill_rx = 1;
  806. while (i != r) {
  807. rxb = rxq->queue[i];
  808. /* If an RXB doesn't have a Rx queue slot associated with it,
  809. * then a bug has been introduced in the queue refilling
  810. * routines -- catch it here */
  811. BUG_ON(rxb == NULL);
  812. rxq->queue[i] = NULL;
  813. pci_unmap_page(priv->pci_dev, rxb->page_dma,
  814. PAGE_SIZE << priv->hw_params.rx_page_order,
  815. PCI_DMA_FROMDEVICE);
  816. pkt = rxb_addr(rxb);
  817. trace_iwlwifi_dev_rx(priv, pkt,
  818. le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK);
  819. /* Reclaim a command buffer only if this packet is a response
  820. * to a (driver-originated) command.
  821. * If the packet (e.g. Rx frame) originated from uCode,
  822. * there is no command buffer to reclaim.
  823. * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
  824. * but apparently a few don't get set; catch them here. */
  825. reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
  826. (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
  827. (pkt->hdr.cmd != REPLY_RX) &&
  828. (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
  829. (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
  830. (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
  831. (pkt->hdr.cmd != REPLY_TX);
  832. /* Based on type of command response or notification,
  833. * handle those that need handling via function in
  834. * rx_handlers table. See iwl_setup_rx_handlers() */
  835. if (priv->rx_handlers[pkt->hdr.cmd]) {
  836. IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
  837. i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
  838. priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
  839. priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
  840. } else {
  841. /* No handling needed */
  842. IWL_DEBUG_RX(priv,
  843. "r %d i %d No handler needed for %s, 0x%02x\n",
  844. r, i, get_cmd_string(pkt->hdr.cmd),
  845. pkt->hdr.cmd);
  846. }
  847. /*
  848. * XXX: After here, we should always check rxb->page
  849. * against NULL before touching it or its virtual
  850. * memory (pkt). Because some rx_handler might have
  851. * already taken or freed the pages.
  852. */
  853. if (reclaim) {
  854. /* Invoke any callbacks, transfer the buffer to caller,
  855. * and fire off the (possibly) blocking iwl_send_cmd()
  856. * as we reclaim the driver command queue */
  857. if (rxb->page)
  858. iwl_tx_cmd_complete(priv, rxb);
  859. else
  860. IWL_WARN(priv, "Claim null rxb?\n");
  861. }
  862. /* Reuse the page if possible. For notification packets and
  863. * SKBs that fail to Rx correctly, add them back into the
  864. * rx_free list for reuse later. */
  865. spin_lock_irqsave(&rxq->lock, flags);
  866. if (rxb->page != NULL) {
  867. rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
  868. 0, PAGE_SIZE << priv->hw_params.rx_page_order,
  869. PCI_DMA_FROMDEVICE);
  870. list_add_tail(&rxb->list, &rxq->rx_free);
  871. rxq->free_count++;
  872. } else
  873. list_add_tail(&rxb->list, &rxq->rx_used);
  874. spin_unlock_irqrestore(&rxq->lock, flags);
  875. i = (i + 1) & RX_QUEUE_MASK;
  876. /* If there are a lot of unused frames,
  877. * restock the Rx queue so ucode wont assert. */
  878. if (fill_rx) {
  879. count++;
  880. if (count >= 8) {
  881. rxq->read = i;
  882. iwl_rx_replenish_now(priv);
  883. count = 0;
  884. }
  885. }
  886. }
  887. /* Backtrack one entry */
  888. rxq->read = i;
  889. if (fill_rx)
  890. iwl_rx_replenish_now(priv);
  891. else
  892. iwl_rx_queue_restock(priv);
  893. }
  894. /* call this function to flush any scheduled tasklet */
  895. static inline void iwl_synchronize_irq(struct iwl_priv *priv)
  896. {
  897. /* wait to make sure we flush pending tasklet*/
  898. synchronize_irq(priv->pci_dev->irq);
  899. tasklet_kill(&priv->irq_tasklet);
  900. }
  901. static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
  902. {
  903. u32 inta, handled = 0;
  904. u32 inta_fh;
  905. unsigned long flags;
  906. u32 i;
  907. #ifdef CONFIG_IWLWIFI_DEBUG
  908. u32 inta_mask;
  909. #endif
  910. spin_lock_irqsave(&priv->lock, flags);
  911. /* Ack/clear/reset pending uCode interrupts.
  912. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  913. * and will clear only when CSR_FH_INT_STATUS gets cleared. */
  914. inta = iwl_read32(priv, CSR_INT);
  915. iwl_write32(priv, CSR_INT, inta);
  916. /* Ack/clear/reset pending flow-handler (DMA) interrupts.
  917. * Any new interrupts that happen after this, either while we're
  918. * in this tasklet, or later, will show up in next ISR/tasklet. */
  919. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  920. iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
  921. #ifdef CONFIG_IWLWIFI_DEBUG
  922. if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
  923. /* just for debug */
  924. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  925. IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  926. inta, inta_mask, inta_fh);
  927. }
  928. #endif
  929. spin_unlock_irqrestore(&priv->lock, flags);
  930. /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
  931. * atomic, make sure that inta covers all the interrupts that
  932. * we've discovered, even if FH interrupt came in just after
  933. * reading CSR_INT. */
  934. if (inta_fh & CSR49_FH_INT_RX_MASK)
  935. inta |= CSR_INT_BIT_FH_RX;
  936. if (inta_fh & CSR49_FH_INT_TX_MASK)
  937. inta |= CSR_INT_BIT_FH_TX;
  938. /* Now service all interrupt bits discovered above. */
  939. if (inta & CSR_INT_BIT_HW_ERR) {
  940. IWL_ERR(priv, "Hardware error detected. Restarting.\n");
  941. /* Tell the device to stop sending interrupts */
  942. iwl_disable_interrupts(priv);
  943. priv->isr_stats.hw++;
  944. iwl_irq_handle_error(priv);
  945. handled |= CSR_INT_BIT_HW_ERR;
  946. return;
  947. }
  948. #ifdef CONFIG_IWLWIFI_DEBUG
  949. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  950. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  951. if (inta & CSR_INT_BIT_SCD) {
  952. IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
  953. "the frame/frames.\n");
  954. priv->isr_stats.sch++;
  955. }
  956. /* Alive notification via Rx interrupt will do the real work */
  957. if (inta & CSR_INT_BIT_ALIVE) {
  958. IWL_DEBUG_ISR(priv, "Alive interrupt\n");
  959. priv->isr_stats.alive++;
  960. }
  961. }
  962. #endif
  963. /* Safely ignore these bits for debug checks below */
  964. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  965. /* HW RF KILL switch toggled */
  966. if (inta & CSR_INT_BIT_RF_KILL) {
  967. int hw_rf_kill = 0;
  968. if (!(iwl_read32(priv, CSR_GP_CNTRL) &
  969. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  970. hw_rf_kill = 1;
  971. IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
  972. hw_rf_kill ? "disable radio" : "enable radio");
  973. priv->isr_stats.rfkill++;
  974. /* driver only loads ucode once setting the interface up.
  975. * the driver allows loading the ucode even if the radio
  976. * is killed. Hence update the killswitch state here. The
  977. * rfkill handler will care about restarting if needed.
  978. */
  979. if (!test_bit(STATUS_ALIVE, &priv->status)) {
  980. if (hw_rf_kill)
  981. set_bit(STATUS_RF_KILL_HW, &priv->status);
  982. else
  983. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  984. wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
  985. }
  986. handled |= CSR_INT_BIT_RF_KILL;
  987. }
  988. /* Chip got too hot and stopped itself */
  989. if (inta & CSR_INT_BIT_CT_KILL) {
  990. IWL_ERR(priv, "Microcode CT kill error detected.\n");
  991. priv->isr_stats.ctkill++;
  992. handled |= CSR_INT_BIT_CT_KILL;
  993. }
  994. /* Error detected by uCode */
  995. if (inta & CSR_INT_BIT_SW_ERR) {
  996. IWL_ERR(priv, "Microcode SW error detected. "
  997. " Restarting 0x%X.\n", inta);
  998. priv->isr_stats.sw++;
  999. priv->isr_stats.sw_err = inta;
  1000. iwl_irq_handle_error(priv);
  1001. handled |= CSR_INT_BIT_SW_ERR;
  1002. }
  1003. /*
  1004. * uCode wakes up after power-down sleep.
  1005. * Tell device about any new tx or host commands enqueued,
  1006. * and about any Rx buffers made available while asleep.
  1007. */
  1008. if (inta & CSR_INT_BIT_WAKEUP) {
  1009. IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
  1010. iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
  1011. for (i = 0; i < priv->hw_params.max_txq_num; i++)
  1012. iwl_txq_update_write_ptr(priv, &priv->txq[i]);
  1013. priv->isr_stats.wakeup++;
  1014. handled |= CSR_INT_BIT_WAKEUP;
  1015. }
  1016. /* All uCode command responses, including Tx command responses,
  1017. * Rx "responses" (frame-received notification), and other
  1018. * notifications from uCode come through here*/
  1019. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  1020. iwl_rx_handle(priv);
  1021. priv->isr_stats.rx++;
  1022. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  1023. }
  1024. /* This "Tx" DMA channel is used only for loading uCode */
  1025. if (inta & CSR_INT_BIT_FH_TX) {
  1026. IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
  1027. priv->isr_stats.tx++;
  1028. handled |= CSR_INT_BIT_FH_TX;
  1029. /* Wake up uCode load routine, now that load is complete */
  1030. priv->ucode_write_complete = 1;
  1031. wake_up_interruptible(&priv->wait_command_queue);
  1032. }
  1033. if (inta & ~handled) {
  1034. IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
  1035. priv->isr_stats.unhandled++;
  1036. }
  1037. if (inta & ~(priv->inta_mask)) {
  1038. IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
  1039. inta & ~priv->inta_mask);
  1040. IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
  1041. }
  1042. /* Re-enable all interrupts */
  1043. /* only Re-enable if diabled by irq */
  1044. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  1045. iwl_enable_interrupts(priv);
  1046. #ifdef CONFIG_IWLWIFI_DEBUG
  1047. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  1048. inta = iwl_read32(priv, CSR_INT);
  1049. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  1050. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  1051. IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
  1052. "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
  1053. }
  1054. #endif
  1055. }
  1056. /* tasklet for iwlagn interrupt */
  1057. static void iwl_irq_tasklet(struct iwl_priv *priv)
  1058. {
  1059. u32 inta = 0;
  1060. u32 handled = 0;
  1061. unsigned long flags;
  1062. u32 i;
  1063. #ifdef CONFIG_IWLWIFI_DEBUG
  1064. u32 inta_mask;
  1065. #endif
  1066. spin_lock_irqsave(&priv->lock, flags);
  1067. /* Ack/clear/reset pending uCode interrupts.
  1068. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  1069. */
  1070. iwl_write32(priv, CSR_INT, priv->inta);
  1071. inta = priv->inta;
  1072. #ifdef CONFIG_IWLWIFI_DEBUG
  1073. if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
  1074. /* just for debug */
  1075. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  1076. IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
  1077. inta, inta_mask);
  1078. }
  1079. #endif
  1080. spin_unlock_irqrestore(&priv->lock, flags);
  1081. /* saved interrupt in inta variable now we can reset priv->inta */
  1082. priv->inta = 0;
  1083. /* Now service all interrupt bits discovered above. */
  1084. if (inta & CSR_INT_BIT_HW_ERR) {
  1085. IWL_ERR(priv, "Hardware error detected. Restarting.\n");
  1086. /* Tell the device to stop sending interrupts */
  1087. iwl_disable_interrupts(priv);
  1088. priv->isr_stats.hw++;
  1089. iwl_irq_handle_error(priv);
  1090. handled |= CSR_INT_BIT_HW_ERR;
  1091. return;
  1092. }
  1093. #ifdef CONFIG_IWLWIFI_DEBUG
  1094. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  1095. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  1096. if (inta & CSR_INT_BIT_SCD) {
  1097. IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
  1098. "the frame/frames.\n");
  1099. priv->isr_stats.sch++;
  1100. }
  1101. /* Alive notification via Rx interrupt will do the real work */
  1102. if (inta & CSR_INT_BIT_ALIVE) {
  1103. IWL_DEBUG_ISR(priv, "Alive interrupt\n");
  1104. priv->isr_stats.alive++;
  1105. }
  1106. }
  1107. #endif
  1108. /* Safely ignore these bits for debug checks below */
  1109. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  1110. /* HW RF KILL switch toggled */
  1111. if (inta & CSR_INT_BIT_RF_KILL) {
  1112. int hw_rf_kill = 0;
  1113. if (!(iwl_read32(priv, CSR_GP_CNTRL) &
  1114. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  1115. hw_rf_kill = 1;
  1116. IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
  1117. hw_rf_kill ? "disable radio" : "enable radio");
  1118. priv->isr_stats.rfkill++;
  1119. /* driver only loads ucode once setting the interface up.
  1120. * the driver allows loading the ucode even if the radio
  1121. * is killed. Hence update the killswitch state here. The
  1122. * rfkill handler will care about restarting if needed.
  1123. */
  1124. if (!test_bit(STATUS_ALIVE, &priv->status)) {
  1125. if (hw_rf_kill)
  1126. set_bit(STATUS_RF_KILL_HW, &priv->status);
  1127. else
  1128. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  1129. wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
  1130. }
  1131. handled |= CSR_INT_BIT_RF_KILL;
  1132. }
  1133. /* Chip got too hot and stopped itself */
  1134. if (inta & CSR_INT_BIT_CT_KILL) {
  1135. IWL_ERR(priv, "Microcode CT kill error detected.\n");
  1136. priv->isr_stats.ctkill++;
  1137. handled |= CSR_INT_BIT_CT_KILL;
  1138. }
  1139. /* Error detected by uCode */
  1140. if (inta & CSR_INT_BIT_SW_ERR) {
  1141. IWL_ERR(priv, "Microcode SW error detected. "
  1142. " Restarting 0x%X.\n", inta);
  1143. priv->isr_stats.sw++;
  1144. priv->isr_stats.sw_err = inta;
  1145. iwl_irq_handle_error(priv);
  1146. handled |= CSR_INT_BIT_SW_ERR;
  1147. }
  1148. /* uCode wakes up after power-down sleep */
  1149. if (inta & CSR_INT_BIT_WAKEUP) {
  1150. IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
  1151. iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
  1152. for (i = 0; i < priv->hw_params.max_txq_num; i++)
  1153. iwl_txq_update_write_ptr(priv, &priv->txq[i]);
  1154. priv->isr_stats.wakeup++;
  1155. handled |= CSR_INT_BIT_WAKEUP;
  1156. }
  1157. /* All uCode command responses, including Tx command responses,
  1158. * Rx "responses" (frame-received notification), and other
  1159. * notifications from uCode come through here*/
  1160. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
  1161. CSR_INT_BIT_RX_PERIODIC)) {
  1162. IWL_DEBUG_ISR(priv, "Rx interrupt\n");
  1163. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  1164. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  1165. iwl_write32(priv, CSR_FH_INT_STATUS,
  1166. CSR49_FH_INT_RX_MASK);
  1167. }
  1168. if (inta & CSR_INT_BIT_RX_PERIODIC) {
  1169. handled |= CSR_INT_BIT_RX_PERIODIC;
  1170. iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
  1171. }
  1172. /* Sending RX interrupt require many steps to be done in the
  1173. * the device:
  1174. * 1- write interrupt to current index in ICT table.
  1175. * 2- dma RX frame.
  1176. * 3- update RX shared data to indicate last write index.
  1177. * 4- send interrupt.
  1178. * This could lead to RX race, driver could receive RX interrupt
  1179. * but the shared data changes does not reflect this;
  1180. * periodic interrupt will detect any dangling Rx activity.
  1181. */
  1182. /* Disable periodic interrupt; we use it as just a one-shot. */
  1183. iwl_write8(priv, CSR_INT_PERIODIC_REG,
  1184. CSR_INT_PERIODIC_DIS);
  1185. iwl_rx_handle(priv);
  1186. /*
  1187. * Enable periodic interrupt in 8 msec only if we received
  1188. * real RX interrupt (instead of just periodic int), to catch
  1189. * any dangling Rx interrupt. If it was just the periodic
  1190. * interrupt, there was no dangling Rx activity, and no need
  1191. * to extend the periodic interrupt; one-shot is enough.
  1192. */
  1193. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
  1194. iwl_write8(priv, CSR_INT_PERIODIC_REG,
  1195. CSR_INT_PERIODIC_ENA);
  1196. priv->isr_stats.rx++;
  1197. }
  1198. /* This "Tx" DMA channel is used only for loading uCode */
  1199. if (inta & CSR_INT_BIT_FH_TX) {
  1200. iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
  1201. IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
  1202. priv->isr_stats.tx++;
  1203. handled |= CSR_INT_BIT_FH_TX;
  1204. /* Wake up uCode load routine, now that load is complete */
  1205. priv->ucode_write_complete = 1;
  1206. wake_up_interruptible(&priv->wait_command_queue);
  1207. }
  1208. if (inta & ~handled) {
  1209. IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
  1210. priv->isr_stats.unhandled++;
  1211. }
  1212. if (inta & ~(priv->inta_mask)) {
  1213. IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
  1214. inta & ~priv->inta_mask);
  1215. }
  1216. /* Re-enable all interrupts */
  1217. /* only Re-enable if diabled by irq */
  1218. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  1219. iwl_enable_interrupts(priv);
  1220. }
  1221. /******************************************************************************
  1222. *
  1223. * uCode download functions
  1224. *
  1225. ******************************************************************************/
  1226. static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
  1227. {
  1228. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
  1229. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
  1230. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  1231. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
  1232. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  1233. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
  1234. }
  1235. static void iwl_nic_start(struct iwl_priv *priv)
  1236. {
  1237. /* Remove all resets to allow NIC to operate */
  1238. iwl_write32(priv, CSR_RESET, 0);
  1239. }
  1240. /**
  1241. * iwl_read_ucode - Read uCode images from disk file.
  1242. *
  1243. * Copy into buffers for card to fetch via bus-mastering
  1244. */
  1245. static int iwl_read_ucode(struct iwl_priv *priv)
  1246. {
  1247. struct iwl_ucode_header *ucode;
  1248. int ret = -EINVAL, index;
  1249. const struct firmware *ucode_raw;
  1250. const char *name_pre = priv->cfg->fw_name_pre;
  1251. const unsigned int api_max = priv->cfg->ucode_api_max;
  1252. const unsigned int api_min = priv->cfg->ucode_api_min;
  1253. char buf[25];
  1254. u8 *src;
  1255. size_t len;
  1256. u32 api_ver, build;
  1257. u32 inst_size, data_size, init_size, init_data_size, boot_size;
  1258. u16 eeprom_ver;
  1259. /* Ask kernel firmware_class module to get the boot firmware off disk.
  1260. * request_firmware() is synchronous, file is in memory on return. */
  1261. for (index = api_max; index >= api_min; index--) {
  1262. sprintf(buf, "%s%d%s", name_pre, index, ".ucode");
  1263. ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev);
  1264. if (ret < 0) {
  1265. IWL_ERR(priv, "%s firmware file req failed: %d\n",
  1266. buf, ret);
  1267. if (ret == -ENOENT)
  1268. continue;
  1269. else
  1270. goto error;
  1271. } else {
  1272. if (index < api_max)
  1273. IWL_ERR(priv, "Loaded firmware %s, "
  1274. "which is deprecated. "
  1275. "Please use API v%u instead.\n",
  1276. buf, api_max);
  1277. IWL_DEBUG_INFO(priv, "Got firmware '%s' file (%zd bytes) from disk\n",
  1278. buf, ucode_raw->size);
  1279. break;
  1280. }
  1281. }
  1282. if (ret < 0)
  1283. goto error;
  1284. /* Make sure that we got at least the v1 header! */
  1285. if (ucode_raw->size < priv->cfg->ops->ucode->get_header_size(1)) {
  1286. IWL_ERR(priv, "File size way too small!\n");
  1287. ret = -EINVAL;
  1288. goto err_release;
  1289. }
  1290. /* Data from ucode file: header followed by uCode images */
  1291. ucode = (struct iwl_ucode_header *)ucode_raw->data;
  1292. priv->ucode_ver = le32_to_cpu(ucode->ver);
  1293. api_ver = IWL_UCODE_API(priv->ucode_ver);
  1294. build = priv->cfg->ops->ucode->get_build(ucode, api_ver);
  1295. inst_size = priv->cfg->ops->ucode->get_inst_size(ucode, api_ver);
  1296. data_size = priv->cfg->ops->ucode->get_data_size(ucode, api_ver);
  1297. init_size = priv->cfg->ops->ucode->get_init_size(ucode, api_ver);
  1298. init_data_size =
  1299. priv->cfg->ops->ucode->get_init_data_size(ucode, api_ver);
  1300. boot_size = priv->cfg->ops->ucode->get_boot_size(ucode, api_ver);
  1301. src = priv->cfg->ops->ucode->get_data(ucode, api_ver);
  1302. /* api_ver should match the api version forming part of the
  1303. * firmware filename ... but we don't check for that and only rely
  1304. * on the API version read from firmware header from here on forward */
  1305. if (api_ver < api_min || api_ver > api_max) {
  1306. IWL_ERR(priv, "Driver unable to support your firmware API. "
  1307. "Driver supports v%u, firmware is v%u.\n",
  1308. api_max, api_ver);
  1309. priv->ucode_ver = 0;
  1310. ret = -EINVAL;
  1311. goto err_release;
  1312. }
  1313. if (api_ver != api_max)
  1314. IWL_ERR(priv, "Firmware has old API version. Expected v%u, "
  1315. "got v%u. New firmware can be obtained "
  1316. "from http://www.intellinuxwireless.org.\n",
  1317. api_max, api_ver);
  1318. IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n",
  1319. IWL_UCODE_MAJOR(priv->ucode_ver),
  1320. IWL_UCODE_MINOR(priv->ucode_ver),
  1321. IWL_UCODE_API(priv->ucode_ver),
  1322. IWL_UCODE_SERIAL(priv->ucode_ver));
  1323. snprintf(priv->hw->wiphy->fw_version,
  1324. sizeof(priv->hw->wiphy->fw_version),
  1325. "%u.%u.%u.%u",
  1326. IWL_UCODE_MAJOR(priv->ucode_ver),
  1327. IWL_UCODE_MINOR(priv->ucode_ver),
  1328. IWL_UCODE_API(priv->ucode_ver),
  1329. IWL_UCODE_SERIAL(priv->ucode_ver));
  1330. if (build)
  1331. IWL_DEBUG_INFO(priv, "Build %u\n", build);
  1332. eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
  1333. IWL_DEBUG_INFO(priv, "NVM Type: %s, version: 0x%x\n",
  1334. (priv->nvm_device_type == NVM_DEVICE_TYPE_OTP)
  1335. ? "OTP" : "EEPROM", eeprom_ver);
  1336. IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
  1337. priv->ucode_ver);
  1338. IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %u\n",
  1339. inst_size);
  1340. IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %u\n",
  1341. data_size);
  1342. IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %u\n",
  1343. init_size);
  1344. IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %u\n",
  1345. init_data_size);
  1346. IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %u\n",
  1347. boot_size);
  1348. /* Verify size of file vs. image size info in file's header */
  1349. if (ucode_raw->size !=
  1350. priv->cfg->ops->ucode->get_header_size(api_ver) +
  1351. inst_size + data_size + init_size +
  1352. init_data_size + boot_size) {
  1353. IWL_DEBUG_INFO(priv,
  1354. "uCode file size %d does not match expected size\n",
  1355. (int)ucode_raw->size);
  1356. ret = -EINVAL;
  1357. goto err_release;
  1358. }
  1359. /* Verify that uCode images will fit in card's SRAM */
  1360. if (inst_size > priv->hw_params.max_inst_size) {
  1361. IWL_DEBUG_INFO(priv, "uCode instr len %d too large to fit in\n",
  1362. inst_size);
  1363. ret = -EINVAL;
  1364. goto err_release;
  1365. }
  1366. if (data_size > priv->hw_params.max_data_size) {
  1367. IWL_DEBUG_INFO(priv, "uCode data len %d too large to fit in\n",
  1368. data_size);
  1369. ret = -EINVAL;
  1370. goto err_release;
  1371. }
  1372. if (init_size > priv->hw_params.max_inst_size) {
  1373. IWL_INFO(priv, "uCode init instr len %d too large to fit in\n",
  1374. init_size);
  1375. ret = -EINVAL;
  1376. goto err_release;
  1377. }
  1378. if (init_data_size > priv->hw_params.max_data_size) {
  1379. IWL_INFO(priv, "uCode init data len %d too large to fit in\n",
  1380. init_data_size);
  1381. ret = -EINVAL;
  1382. goto err_release;
  1383. }
  1384. if (boot_size > priv->hw_params.max_bsm_size) {
  1385. IWL_INFO(priv, "uCode boot instr len %d too large to fit in\n",
  1386. boot_size);
  1387. ret = -EINVAL;
  1388. goto err_release;
  1389. }
  1390. /* Allocate ucode buffers for card's bus-master loading ... */
  1391. /* Runtime instructions and 2 copies of data:
  1392. * 1) unmodified from disk
  1393. * 2) backup cache for save/restore during power-downs */
  1394. priv->ucode_code.len = inst_size;
  1395. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
  1396. priv->ucode_data.len = data_size;
  1397. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
  1398. priv->ucode_data_backup.len = data_size;
  1399. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  1400. if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
  1401. !priv->ucode_data_backup.v_addr)
  1402. goto err_pci_alloc;
  1403. /* Initialization instructions and data */
  1404. if (init_size && init_data_size) {
  1405. priv->ucode_init.len = init_size;
  1406. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
  1407. priv->ucode_init_data.len = init_data_size;
  1408. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  1409. if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
  1410. goto err_pci_alloc;
  1411. }
  1412. /* Bootstrap (instructions only, no data) */
  1413. if (boot_size) {
  1414. priv->ucode_boot.len = boot_size;
  1415. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
  1416. if (!priv->ucode_boot.v_addr)
  1417. goto err_pci_alloc;
  1418. }
  1419. /* Copy images into buffers for card's bus-master reads ... */
  1420. /* Runtime instructions (first block of data in file) */
  1421. len = inst_size;
  1422. IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n", len);
  1423. memcpy(priv->ucode_code.v_addr, src, len);
  1424. src += len;
  1425. IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
  1426. priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
  1427. /* Runtime data (2nd block)
  1428. * NOTE: Copy into backup buffer will be done in iwl_up() */
  1429. len = data_size;
  1430. IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n", len);
  1431. memcpy(priv->ucode_data.v_addr, src, len);
  1432. memcpy(priv->ucode_data_backup.v_addr, src, len);
  1433. src += len;
  1434. /* Initialization instructions (3rd block) */
  1435. if (init_size) {
  1436. len = init_size;
  1437. IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
  1438. len);
  1439. memcpy(priv->ucode_init.v_addr, src, len);
  1440. src += len;
  1441. }
  1442. /* Initialization data (4th block) */
  1443. if (init_data_size) {
  1444. len = init_data_size;
  1445. IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
  1446. len);
  1447. memcpy(priv->ucode_init_data.v_addr, src, len);
  1448. src += len;
  1449. }
  1450. /* Bootstrap instructions (5th block) */
  1451. len = boot_size;
  1452. IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n", len);
  1453. memcpy(priv->ucode_boot.v_addr, src, len);
  1454. /* We have our copies now, allow OS release its copies */
  1455. release_firmware(ucode_raw);
  1456. return 0;
  1457. err_pci_alloc:
  1458. IWL_ERR(priv, "failed to allocate pci memory\n");
  1459. ret = -ENOMEM;
  1460. iwl_dealloc_ucode_pci(priv);
  1461. err_release:
  1462. release_firmware(ucode_raw);
  1463. error:
  1464. return ret;
  1465. }
  1466. static const char *desc_lookup_text[] = {
  1467. "OK",
  1468. "FAIL",
  1469. "BAD_PARAM",
  1470. "BAD_CHECKSUM",
  1471. "NMI_INTERRUPT_WDG",
  1472. "SYSASSERT",
  1473. "FATAL_ERROR",
  1474. "BAD_COMMAND",
  1475. "HW_ERROR_TUNE_LOCK",
  1476. "HW_ERROR_TEMPERATURE",
  1477. "ILLEGAL_CHAN_FREQ",
  1478. "VCC_NOT_STABLE",
  1479. "FH_ERROR",
  1480. "NMI_INTERRUPT_HOST",
  1481. "NMI_INTERRUPT_ACTION_PT",
  1482. "NMI_INTERRUPT_UNKNOWN",
  1483. "UCODE_VERSION_MISMATCH",
  1484. "HW_ERROR_ABS_LOCK",
  1485. "HW_ERROR_CAL_LOCK_FAIL",
  1486. "NMI_INTERRUPT_INST_ACTION_PT",
  1487. "NMI_INTERRUPT_DATA_ACTION_PT",
  1488. "NMI_TRM_HW_ER",
  1489. "NMI_INTERRUPT_TRM",
  1490. "NMI_INTERRUPT_BREAK_POINT"
  1491. "DEBUG_0",
  1492. "DEBUG_1",
  1493. "DEBUG_2",
  1494. "DEBUG_3",
  1495. "UNKNOWN"
  1496. };
  1497. static const char *desc_lookup(int i)
  1498. {
  1499. int max = ARRAY_SIZE(desc_lookup_text) - 1;
  1500. if (i < 0 || i > max)
  1501. i = max;
  1502. return desc_lookup_text[i];
  1503. }
  1504. #define ERROR_START_OFFSET (1 * sizeof(u32))
  1505. #define ERROR_ELEM_SIZE (7 * sizeof(u32))
  1506. void iwl_dump_nic_error_log(struct iwl_priv *priv)
  1507. {
  1508. u32 data2, line;
  1509. u32 desc, time, count, base, data1;
  1510. u32 blink1, blink2, ilink1, ilink2;
  1511. if (priv->ucode_type == UCODE_INIT)
  1512. base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
  1513. else
  1514. base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
  1515. if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
  1516. IWL_ERR(priv,
  1517. "Not valid error log pointer 0x%08X for %s uCode\n",
  1518. base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
  1519. return;
  1520. }
  1521. count = iwl_read_targ_mem(priv, base);
  1522. if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
  1523. IWL_ERR(priv, "Start IWL Error Log Dump:\n");
  1524. IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
  1525. priv->status, count);
  1526. }
  1527. desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
  1528. blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
  1529. blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
  1530. ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
  1531. ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
  1532. data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
  1533. data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
  1534. line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
  1535. time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
  1536. trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line,
  1537. blink1, blink2, ilink1, ilink2);
  1538. IWL_ERR(priv, "Desc Time "
  1539. "data1 data2 line\n");
  1540. IWL_ERR(priv, "%-28s (#%02d) %010u 0x%08X 0x%08X %u\n",
  1541. desc_lookup(desc), desc, time, data1, data2, line);
  1542. IWL_ERR(priv, "blink1 blink2 ilink1 ilink2\n");
  1543. IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2,
  1544. ilink1, ilink2);
  1545. }
  1546. #define EVENT_START_OFFSET (4 * sizeof(u32))
  1547. /**
  1548. * iwl_print_event_log - Dump error event log to syslog
  1549. *
  1550. */
  1551. static void iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
  1552. u32 num_events, u32 mode)
  1553. {
  1554. u32 i;
  1555. u32 base; /* SRAM byte address of event log header */
  1556. u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
  1557. u32 ptr; /* SRAM byte address of log data */
  1558. u32 ev, time, data; /* event log data */
  1559. unsigned long reg_flags;
  1560. if (num_events == 0)
  1561. return;
  1562. if (priv->ucode_type == UCODE_INIT)
  1563. base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
  1564. else
  1565. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  1566. if (mode == 0)
  1567. event_size = 2 * sizeof(u32);
  1568. else
  1569. event_size = 3 * sizeof(u32);
  1570. ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
  1571. /* Make sure device is powered up for SRAM reads */
  1572. spin_lock_irqsave(&priv->reg_lock, reg_flags);
  1573. iwl_grab_nic_access(priv);
  1574. /* Set starting address; reads will auto-increment */
  1575. _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
  1576. rmb();
  1577. /* "time" is actually "data" for mode 0 (no timestamp).
  1578. * place event id # at far right for easier visual parsing. */
  1579. for (i = 0; i < num_events; i++) {
  1580. ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1581. time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1582. if (mode == 0) {
  1583. /* data, ev */
  1584. trace_iwlwifi_dev_ucode_event(priv, 0, time, ev);
  1585. IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n", time, ev);
  1586. } else {
  1587. data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1588. IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
  1589. time, data, ev);
  1590. trace_iwlwifi_dev_ucode_event(priv, time, data, ev);
  1591. }
  1592. }
  1593. /* Allow device to power down */
  1594. iwl_release_nic_access(priv);
  1595. spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
  1596. }
  1597. /**
  1598. * iwl_print_last_event_logs - Dump the newest # of event log to syslog
  1599. */
  1600. static void iwl_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
  1601. u32 num_wraps, u32 next_entry,
  1602. u32 size, u32 mode)
  1603. {
  1604. /*
  1605. * display the newest DEFAULT_LOG_ENTRIES entries
  1606. * i.e the entries just before the next ont that uCode would fill.
  1607. */
  1608. if (num_wraps) {
  1609. if (next_entry < size) {
  1610. iwl_print_event_log(priv,
  1611. capacity - (size - next_entry),
  1612. size - next_entry, mode);
  1613. iwl_print_event_log(priv, 0,
  1614. next_entry, mode);
  1615. } else
  1616. iwl_print_event_log(priv, next_entry - size,
  1617. size, mode);
  1618. } else {
  1619. if (next_entry < size)
  1620. iwl_print_event_log(priv, 0, next_entry, mode);
  1621. else
  1622. iwl_print_event_log(priv, next_entry - size,
  1623. size, mode);
  1624. }
  1625. }
  1626. /* For sanity check only. Actual size is determined by uCode, typ. 512 */
  1627. #define MAX_EVENT_LOG_SIZE (512)
  1628. #define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
  1629. void iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log)
  1630. {
  1631. u32 base; /* SRAM byte address of event log header */
  1632. u32 capacity; /* event log capacity in # entries */
  1633. u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
  1634. u32 num_wraps; /* # times uCode wrapped to top of log */
  1635. u32 next_entry; /* index of next entry to be written by uCode */
  1636. u32 size; /* # entries that we'll print */
  1637. if (priv->ucode_type == UCODE_INIT)
  1638. base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
  1639. else
  1640. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  1641. if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
  1642. IWL_ERR(priv,
  1643. "Invalid event log pointer 0x%08X for %s uCode\n",
  1644. base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
  1645. return;
  1646. }
  1647. /* event log header */
  1648. capacity = iwl_read_targ_mem(priv, base);
  1649. mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
  1650. num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
  1651. next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
  1652. if (capacity > MAX_EVENT_LOG_SIZE) {
  1653. IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
  1654. capacity, MAX_EVENT_LOG_SIZE);
  1655. capacity = MAX_EVENT_LOG_SIZE;
  1656. }
  1657. if (next_entry > MAX_EVENT_LOG_SIZE) {
  1658. IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
  1659. next_entry, MAX_EVENT_LOG_SIZE);
  1660. next_entry = MAX_EVENT_LOG_SIZE;
  1661. }
  1662. size = num_wraps ? capacity : next_entry;
  1663. /* bail out if nothing in log */
  1664. if (size == 0) {
  1665. IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
  1666. return;
  1667. }
  1668. #ifdef CONFIG_IWLWIFI_DEBUG
  1669. if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS))
  1670. size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
  1671. ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
  1672. #else
  1673. size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
  1674. ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
  1675. #endif
  1676. IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n",
  1677. size);
  1678. #ifdef CONFIG_IWLWIFI_DEBUG
  1679. if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
  1680. /*
  1681. * if uCode has wrapped back to top of log,
  1682. * start at the oldest entry,
  1683. * i.e the next one that uCode would fill.
  1684. */
  1685. if (num_wraps)
  1686. iwl_print_event_log(priv, next_entry,
  1687. capacity - next_entry, mode);
  1688. /* (then/else) start at top of log */
  1689. iwl_print_event_log(priv, 0, next_entry, mode);
  1690. } else
  1691. iwl_print_last_event_logs(priv, capacity, num_wraps,
  1692. next_entry, size, mode);
  1693. #else
  1694. iwl_print_last_event_logs(priv, capacity, num_wraps,
  1695. next_entry, size, mode);
  1696. #endif
  1697. }
  1698. /**
  1699. * iwl_alive_start - called after REPLY_ALIVE notification received
  1700. * from protocol/runtime uCode (initialization uCode's
  1701. * Alive gets handled by iwl_init_alive_start()).
  1702. */
  1703. static void iwl_alive_start(struct iwl_priv *priv)
  1704. {
  1705. int ret = 0;
  1706. IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
  1707. if (priv->card_alive.is_valid != UCODE_VALID_OK) {
  1708. /* We had an error bringing up the hardware, so take it
  1709. * all the way back down so we can try again */
  1710. IWL_DEBUG_INFO(priv, "Alive failed.\n");
  1711. goto restart;
  1712. }
  1713. /* Initialize uCode has loaded Runtime uCode ... verify inst image.
  1714. * This is a paranoid check, because we would not have gotten the
  1715. * "runtime" alive if code weren't properly loaded. */
  1716. if (iwl_verify_ucode(priv)) {
  1717. /* Runtime instruction load was bad;
  1718. * take it all the way back down so we can try again */
  1719. IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
  1720. goto restart;
  1721. }
  1722. iwl_clear_stations_table(priv);
  1723. ret = priv->cfg->ops->lib->alive_notify(priv);
  1724. if (ret) {
  1725. IWL_WARN(priv,
  1726. "Could not complete ALIVE transition [ntf]: %d\n", ret);
  1727. goto restart;
  1728. }
  1729. /* After the ALIVE response, we can send host commands to the uCode */
  1730. set_bit(STATUS_ALIVE, &priv->status);
  1731. if (iwl_is_rfkill(priv))
  1732. return;
  1733. ieee80211_wake_queues(priv->hw);
  1734. priv->active_rate = priv->rates_mask;
  1735. priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
  1736. /* Configure Tx antenna selection based on H/W config */
  1737. if (priv->cfg->ops->hcmd->set_tx_ant)
  1738. priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
  1739. if (iwl_is_associated(priv)) {
  1740. struct iwl_rxon_cmd *active_rxon =
  1741. (struct iwl_rxon_cmd *)&priv->active_rxon;
  1742. /* apply any changes in staging */
  1743. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  1744. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  1745. } else {
  1746. /* Initialize our rx_config data */
  1747. iwl_connection_init_rx_config(priv, priv->iw_mode);
  1748. if (priv->cfg->ops->hcmd->set_rxon_chain)
  1749. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  1750. memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  1751. }
  1752. /* Configure Bluetooth device coexistence support */
  1753. iwl_send_bt_config(priv);
  1754. iwl_reset_run_time_calib(priv);
  1755. /* Configure the adapter for unassociated operation */
  1756. iwlcore_commit_rxon(priv);
  1757. /* At this point, the NIC is initialized and operational */
  1758. iwl_rf_kill_ct_config(priv);
  1759. iwl_leds_init(priv);
  1760. IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
  1761. set_bit(STATUS_READY, &priv->status);
  1762. wake_up_interruptible(&priv->wait_command_queue);
  1763. iwl_power_update_mode(priv, true);
  1764. /* reassociate for ADHOC mode */
  1765. if (priv->vif && (priv->iw_mode == NL80211_IFTYPE_ADHOC)) {
  1766. struct sk_buff *beacon = ieee80211_beacon_get(priv->hw,
  1767. priv->vif);
  1768. if (beacon)
  1769. iwl_mac_beacon_update(priv->hw, beacon);
  1770. }
  1771. if (test_and_clear_bit(STATUS_MODE_PENDING, &priv->status))
  1772. iwl_set_mode(priv, priv->iw_mode);
  1773. return;
  1774. restart:
  1775. queue_work(priv->workqueue, &priv->restart);
  1776. }
  1777. static void iwl_cancel_deferred_work(struct iwl_priv *priv);
  1778. static void __iwl_down(struct iwl_priv *priv)
  1779. {
  1780. unsigned long flags;
  1781. int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
  1782. IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
  1783. if (!exit_pending)
  1784. set_bit(STATUS_EXIT_PENDING, &priv->status);
  1785. iwl_clear_stations_table(priv);
  1786. /* Unblock any waiting calls */
  1787. wake_up_interruptible_all(&priv->wait_command_queue);
  1788. /* Wipe out the EXIT_PENDING status bit if we are not actually
  1789. * exiting the module */
  1790. if (!exit_pending)
  1791. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  1792. /* stop and reset the on-board processor */
  1793. iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  1794. /* tell the device to stop sending interrupts */
  1795. spin_lock_irqsave(&priv->lock, flags);
  1796. iwl_disable_interrupts(priv);
  1797. spin_unlock_irqrestore(&priv->lock, flags);
  1798. iwl_synchronize_irq(priv);
  1799. if (priv->mac80211_registered)
  1800. ieee80211_stop_queues(priv->hw);
  1801. /* If we have not previously called iwl_init() then
  1802. * clear all bits but the RF Kill bit and return */
  1803. if (!iwl_is_init(priv)) {
  1804. priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  1805. STATUS_RF_KILL_HW |
  1806. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  1807. STATUS_GEO_CONFIGURED |
  1808. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  1809. STATUS_EXIT_PENDING;
  1810. goto exit;
  1811. }
  1812. /* ...otherwise clear out all the status bits but the RF Kill
  1813. * bit and continue taking the NIC down. */
  1814. priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  1815. STATUS_RF_KILL_HW |
  1816. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  1817. STATUS_GEO_CONFIGURED |
  1818. test_bit(STATUS_FW_ERROR, &priv->status) <<
  1819. STATUS_FW_ERROR |
  1820. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  1821. STATUS_EXIT_PENDING;
  1822. /* device going down, Stop using ICT table */
  1823. iwl_disable_ict(priv);
  1824. iwl_txq_ctx_stop(priv);
  1825. iwl_rxq_stop(priv);
  1826. /* Power-down device's busmaster DMA clocks */
  1827. iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
  1828. udelay(5);
  1829. /* Make sure (redundant) we've released our request to stay awake */
  1830. iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  1831. /* Stop the device, and put it in low power state */
  1832. priv->cfg->ops->lib->apm_ops.stop(priv);
  1833. exit:
  1834. memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
  1835. if (priv->ibss_beacon)
  1836. dev_kfree_skb(priv->ibss_beacon);
  1837. priv->ibss_beacon = NULL;
  1838. /* clear out any free frames */
  1839. iwl_clear_free_frames(priv);
  1840. }
  1841. static void iwl_down(struct iwl_priv *priv)
  1842. {
  1843. mutex_lock(&priv->mutex);
  1844. __iwl_down(priv);
  1845. mutex_unlock(&priv->mutex);
  1846. iwl_cancel_deferred_work(priv);
  1847. }
  1848. #define HW_READY_TIMEOUT (50)
  1849. static int iwl_set_hw_ready(struct iwl_priv *priv)
  1850. {
  1851. int ret = 0;
  1852. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  1853. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
  1854. /* See if we got it */
  1855. ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
  1856. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
  1857. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
  1858. HW_READY_TIMEOUT);
  1859. if (ret != -ETIMEDOUT)
  1860. priv->hw_ready = true;
  1861. else
  1862. priv->hw_ready = false;
  1863. IWL_DEBUG_INFO(priv, "hardware %s\n",
  1864. (priv->hw_ready == 1) ? "ready" : "not ready");
  1865. return ret;
  1866. }
  1867. static int iwl_prepare_card_hw(struct iwl_priv *priv)
  1868. {
  1869. int ret = 0;
  1870. IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter \n");
  1871. ret = iwl_set_hw_ready(priv);
  1872. if (priv->hw_ready)
  1873. return ret;
  1874. /* If HW is not ready, prepare the conditions to check again */
  1875. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  1876. CSR_HW_IF_CONFIG_REG_PREPARE);
  1877. ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
  1878. ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
  1879. CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
  1880. /* HW should be ready by now, check again. */
  1881. if (ret != -ETIMEDOUT)
  1882. iwl_set_hw_ready(priv);
  1883. return ret;
  1884. }
  1885. #define MAX_HW_RESTARTS 5
  1886. static int __iwl_up(struct iwl_priv *priv)
  1887. {
  1888. int i;
  1889. int ret;
  1890. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  1891. IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
  1892. return -EIO;
  1893. }
  1894. if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
  1895. IWL_ERR(priv, "ucode not available for device bringup\n");
  1896. return -EIO;
  1897. }
  1898. iwl_prepare_card_hw(priv);
  1899. if (!priv->hw_ready) {
  1900. IWL_WARN(priv, "Exit HW not ready\n");
  1901. return -EIO;
  1902. }
  1903. /* If platform's RF_KILL switch is NOT set to KILL */
  1904. if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  1905. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  1906. else
  1907. set_bit(STATUS_RF_KILL_HW, &priv->status);
  1908. if (iwl_is_rfkill(priv)) {
  1909. wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
  1910. iwl_enable_interrupts(priv);
  1911. IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
  1912. return 0;
  1913. }
  1914. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  1915. ret = iwl_hw_nic_init(priv);
  1916. if (ret) {
  1917. IWL_ERR(priv, "Unable to init nic\n");
  1918. return ret;
  1919. }
  1920. /* make sure rfkill handshake bits are cleared */
  1921. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  1922. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  1923. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  1924. /* clear (again), then enable host interrupts */
  1925. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  1926. iwl_enable_interrupts(priv);
  1927. /* really make sure rfkill handshake bits are cleared */
  1928. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  1929. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  1930. /* Copy original ucode data image from disk into backup cache.
  1931. * This will be used to initialize the on-board processor's
  1932. * data SRAM for a clean start when the runtime program first loads. */
  1933. memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
  1934. priv->ucode_data.len);
  1935. for (i = 0; i < MAX_HW_RESTARTS; i++) {
  1936. iwl_clear_stations_table(priv);
  1937. /* load bootstrap state machine,
  1938. * load bootstrap program into processor's memory,
  1939. * prepare to load the "initialize" uCode */
  1940. ret = priv->cfg->ops->lib->load_ucode(priv);
  1941. if (ret) {
  1942. IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
  1943. ret);
  1944. continue;
  1945. }
  1946. /* start card; "initialize" will load runtime ucode */
  1947. iwl_nic_start(priv);
  1948. IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
  1949. return 0;
  1950. }
  1951. set_bit(STATUS_EXIT_PENDING, &priv->status);
  1952. __iwl_down(priv);
  1953. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  1954. /* tried to restart and config the device for as long as our
  1955. * patience could withstand */
  1956. IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
  1957. return -EIO;
  1958. }
  1959. /*****************************************************************************
  1960. *
  1961. * Workqueue callbacks
  1962. *
  1963. *****************************************************************************/
  1964. static void iwl_bg_init_alive_start(struct work_struct *data)
  1965. {
  1966. struct iwl_priv *priv =
  1967. container_of(data, struct iwl_priv, init_alive_start.work);
  1968. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1969. return;
  1970. mutex_lock(&priv->mutex);
  1971. priv->cfg->ops->lib->init_alive_start(priv);
  1972. mutex_unlock(&priv->mutex);
  1973. }
  1974. static void iwl_bg_alive_start(struct work_struct *data)
  1975. {
  1976. struct iwl_priv *priv =
  1977. container_of(data, struct iwl_priv, alive_start.work);
  1978. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1979. return;
  1980. /* enable dram interrupt */
  1981. iwl_reset_ict(priv);
  1982. mutex_lock(&priv->mutex);
  1983. iwl_alive_start(priv);
  1984. mutex_unlock(&priv->mutex);
  1985. }
  1986. static void iwl_bg_run_time_calib_work(struct work_struct *work)
  1987. {
  1988. struct iwl_priv *priv = container_of(work, struct iwl_priv,
  1989. run_time_calib_work);
  1990. mutex_lock(&priv->mutex);
  1991. if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
  1992. test_bit(STATUS_SCANNING, &priv->status)) {
  1993. mutex_unlock(&priv->mutex);
  1994. return;
  1995. }
  1996. if (priv->start_calib) {
  1997. iwl_chain_noise_calibration(priv, &priv->statistics);
  1998. iwl_sensitivity_calibration(priv, &priv->statistics);
  1999. }
  2000. mutex_unlock(&priv->mutex);
  2001. return;
  2002. }
  2003. static void iwl_bg_up(struct work_struct *data)
  2004. {
  2005. struct iwl_priv *priv = container_of(data, struct iwl_priv, up);
  2006. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2007. return;
  2008. mutex_lock(&priv->mutex);
  2009. __iwl_up(priv);
  2010. mutex_unlock(&priv->mutex);
  2011. }
  2012. static void iwl_bg_restart(struct work_struct *data)
  2013. {
  2014. struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
  2015. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2016. return;
  2017. if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
  2018. mutex_lock(&priv->mutex);
  2019. priv->vif = NULL;
  2020. priv->is_open = 0;
  2021. mutex_unlock(&priv->mutex);
  2022. iwl_down(priv);
  2023. ieee80211_restart_hw(priv->hw);
  2024. } else {
  2025. iwl_down(priv);
  2026. queue_work(priv->workqueue, &priv->up);
  2027. }
  2028. }
  2029. static void iwl_bg_rx_replenish(struct work_struct *data)
  2030. {
  2031. struct iwl_priv *priv =
  2032. container_of(data, struct iwl_priv, rx_replenish);
  2033. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2034. return;
  2035. mutex_lock(&priv->mutex);
  2036. iwl_rx_replenish(priv);
  2037. mutex_unlock(&priv->mutex);
  2038. }
  2039. #define IWL_DELAY_NEXT_SCAN (HZ*2)
  2040. void iwl_post_associate(struct iwl_priv *priv)
  2041. {
  2042. struct ieee80211_conf *conf = NULL;
  2043. int ret = 0;
  2044. unsigned long flags;
  2045. if (priv->iw_mode == NL80211_IFTYPE_AP) {
  2046. IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
  2047. return;
  2048. }
  2049. IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
  2050. priv->assoc_id, priv->active_rxon.bssid_addr);
  2051. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2052. return;
  2053. if (!priv->vif || !priv->is_open)
  2054. return;
  2055. iwl_scan_cancel_timeout(priv, 200);
  2056. conf = ieee80211_get_hw_conf(priv->hw);
  2057. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  2058. iwlcore_commit_rxon(priv);
  2059. iwl_setup_rxon_timing(priv);
  2060. ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  2061. sizeof(priv->rxon_timing), &priv->rxon_timing);
  2062. if (ret)
  2063. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  2064. "Attempting to continue.\n");
  2065. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  2066. iwl_set_rxon_ht(priv, &priv->current_ht_config);
  2067. if (priv->cfg->ops->hcmd->set_rxon_chain)
  2068. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  2069. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  2070. IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
  2071. priv->assoc_id, priv->beacon_int);
  2072. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  2073. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  2074. else
  2075. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  2076. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  2077. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  2078. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  2079. else
  2080. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  2081. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  2082. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  2083. }
  2084. iwlcore_commit_rxon(priv);
  2085. switch (priv->iw_mode) {
  2086. case NL80211_IFTYPE_STATION:
  2087. break;
  2088. case NL80211_IFTYPE_ADHOC:
  2089. /* assume default assoc id */
  2090. priv->assoc_id = 1;
  2091. iwl_rxon_add_station(priv, priv->bssid, 0);
  2092. iwl_send_beacon_cmd(priv);
  2093. break;
  2094. default:
  2095. IWL_ERR(priv, "%s Should not be called in %d mode\n",
  2096. __func__, priv->iw_mode);
  2097. break;
  2098. }
  2099. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  2100. priv->assoc_station_added = 1;
  2101. spin_lock_irqsave(&priv->lock, flags);
  2102. iwl_activate_qos(priv, 0);
  2103. spin_unlock_irqrestore(&priv->lock, flags);
  2104. /* the chain noise calibration will enabled PM upon completion
  2105. * If chain noise has already been run, then we need to enable
  2106. * power management here */
  2107. if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE)
  2108. iwl_power_update_mode(priv, false);
  2109. /* Enable Rx differential gain and sensitivity calibrations */
  2110. iwl_chain_noise_reset(priv);
  2111. priv->start_calib = 1;
  2112. }
  2113. /*****************************************************************************
  2114. *
  2115. * mac80211 entry point functions
  2116. *
  2117. *****************************************************************************/
  2118. #define UCODE_READY_TIMEOUT (4 * HZ)
  2119. /*
  2120. * Not a mac80211 entry point function, but it fits in with all the
  2121. * other mac80211 functions grouped here.
  2122. */
  2123. static int iwl_setup_mac(struct iwl_priv *priv)
  2124. {
  2125. int ret;
  2126. struct ieee80211_hw *hw = priv->hw;
  2127. hw->rate_control_algorithm = "iwl-agn-rs";
  2128. /* Tell mac80211 our characteristics */
  2129. hw->flags = IEEE80211_HW_SIGNAL_DBM |
  2130. IEEE80211_HW_NOISE_DBM |
  2131. IEEE80211_HW_AMPDU_AGGREGATION |
  2132. IEEE80211_HW_SPECTRUM_MGMT;
  2133. if (!priv->cfg->broken_powersave)
  2134. hw->flags |= IEEE80211_HW_SUPPORTS_PS |
  2135. IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
  2136. hw->sta_data_size = sizeof(struct iwl_station_priv);
  2137. hw->wiphy->interface_modes =
  2138. BIT(NL80211_IFTYPE_STATION) |
  2139. BIT(NL80211_IFTYPE_ADHOC);
  2140. hw->wiphy->flags |= WIPHY_FLAG_STRICT_REGULATORY |
  2141. WIPHY_FLAG_DISABLE_BEACON_HINTS;
  2142. /*
  2143. * For now, disable PS by default because it affects
  2144. * RX performance significantly.
  2145. */
  2146. hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
  2147. hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
  2148. /* we create the 802.11 header and a zero-length SSID element */
  2149. hw->wiphy->max_scan_ie_len = IWL_MAX_PROBE_REQUEST - 24 - 2;
  2150. /* Default value; 4 EDCA QOS priorities */
  2151. hw->queues = 4;
  2152. hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
  2153. if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
  2154. priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
  2155. &priv->bands[IEEE80211_BAND_2GHZ];
  2156. if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
  2157. priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
  2158. &priv->bands[IEEE80211_BAND_5GHZ];
  2159. ret = ieee80211_register_hw(priv->hw);
  2160. if (ret) {
  2161. IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
  2162. return ret;
  2163. }
  2164. priv->mac80211_registered = 1;
  2165. return 0;
  2166. }
  2167. static int iwl_mac_start(struct ieee80211_hw *hw)
  2168. {
  2169. struct iwl_priv *priv = hw->priv;
  2170. int ret;
  2171. IWL_DEBUG_MAC80211(priv, "enter\n");
  2172. /* we should be verifying the device is ready to be opened */
  2173. mutex_lock(&priv->mutex);
  2174. /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
  2175. * ucode filename and max sizes are card-specific. */
  2176. if (!priv->ucode_code.len) {
  2177. ret = iwl_read_ucode(priv);
  2178. if (ret) {
  2179. IWL_ERR(priv, "Could not read microcode: %d\n", ret);
  2180. mutex_unlock(&priv->mutex);
  2181. return ret;
  2182. }
  2183. }
  2184. ret = __iwl_up(priv);
  2185. mutex_unlock(&priv->mutex);
  2186. if (ret)
  2187. return ret;
  2188. if (iwl_is_rfkill(priv))
  2189. goto out;
  2190. IWL_DEBUG_INFO(priv, "Start UP work done.\n");
  2191. /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
  2192. * mac80211 will not be run successfully. */
  2193. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  2194. test_bit(STATUS_READY, &priv->status),
  2195. UCODE_READY_TIMEOUT);
  2196. if (!ret) {
  2197. if (!test_bit(STATUS_READY, &priv->status)) {
  2198. IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
  2199. jiffies_to_msecs(UCODE_READY_TIMEOUT));
  2200. return -ETIMEDOUT;
  2201. }
  2202. }
  2203. iwl_led_start(priv);
  2204. out:
  2205. priv->is_open = 1;
  2206. IWL_DEBUG_MAC80211(priv, "leave\n");
  2207. return 0;
  2208. }
  2209. static void iwl_mac_stop(struct ieee80211_hw *hw)
  2210. {
  2211. struct iwl_priv *priv = hw->priv;
  2212. IWL_DEBUG_MAC80211(priv, "enter\n");
  2213. if (!priv->is_open)
  2214. return;
  2215. priv->is_open = 0;
  2216. if (iwl_is_ready_rf(priv) || test_bit(STATUS_SCAN_HW, &priv->status)) {
  2217. /* stop mac, cancel any scan request and clear
  2218. * RXON_FILTER_ASSOC_MSK BIT
  2219. */
  2220. mutex_lock(&priv->mutex);
  2221. iwl_scan_cancel_timeout(priv, 100);
  2222. mutex_unlock(&priv->mutex);
  2223. }
  2224. iwl_down(priv);
  2225. flush_workqueue(priv->workqueue);
  2226. /* enable interrupts again in order to receive rfkill changes */
  2227. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  2228. iwl_enable_interrupts(priv);
  2229. IWL_DEBUG_MAC80211(priv, "leave\n");
  2230. }
  2231. static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  2232. {
  2233. struct iwl_priv *priv = hw->priv;
  2234. IWL_DEBUG_MACDUMP(priv, "enter\n");
  2235. IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
  2236. ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
  2237. if (iwl_tx_skb(priv, skb))
  2238. dev_kfree_skb_any(skb);
  2239. IWL_DEBUG_MACDUMP(priv, "leave\n");
  2240. return NETDEV_TX_OK;
  2241. }
  2242. void iwl_config_ap(struct iwl_priv *priv)
  2243. {
  2244. int ret = 0;
  2245. unsigned long flags;
  2246. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2247. return;
  2248. /* The following should be done only at AP bring up */
  2249. if (!iwl_is_associated(priv)) {
  2250. /* RXON - unassoc (to set timing command) */
  2251. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  2252. iwlcore_commit_rxon(priv);
  2253. /* RXON Timing */
  2254. iwl_setup_rxon_timing(priv);
  2255. ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  2256. sizeof(priv->rxon_timing), &priv->rxon_timing);
  2257. if (ret)
  2258. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  2259. "Attempting to continue.\n");
  2260. /* AP has all antennas */
  2261. priv->chain_noise_data.active_chains =
  2262. priv->hw_params.valid_rx_ant;
  2263. iwl_set_rxon_ht(priv, &priv->current_ht_config);
  2264. if (priv->cfg->ops->hcmd->set_rxon_chain)
  2265. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  2266. /* FIXME: what should be the assoc_id for AP? */
  2267. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  2268. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  2269. priv->staging_rxon.flags |=
  2270. RXON_FLG_SHORT_PREAMBLE_MSK;
  2271. else
  2272. priv->staging_rxon.flags &=
  2273. ~RXON_FLG_SHORT_PREAMBLE_MSK;
  2274. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  2275. if (priv->assoc_capability &
  2276. WLAN_CAPABILITY_SHORT_SLOT_TIME)
  2277. priv->staging_rxon.flags |=
  2278. RXON_FLG_SHORT_SLOT_MSK;
  2279. else
  2280. priv->staging_rxon.flags &=
  2281. ~RXON_FLG_SHORT_SLOT_MSK;
  2282. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  2283. priv->staging_rxon.flags &=
  2284. ~RXON_FLG_SHORT_SLOT_MSK;
  2285. }
  2286. /* restore RXON assoc */
  2287. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  2288. iwlcore_commit_rxon(priv);
  2289. iwl_reset_qos(priv);
  2290. spin_lock_irqsave(&priv->lock, flags);
  2291. iwl_activate_qos(priv, 1);
  2292. spin_unlock_irqrestore(&priv->lock, flags);
  2293. iwl_add_bcast_station(priv);
  2294. }
  2295. iwl_send_beacon_cmd(priv);
  2296. /* FIXME - we need to add code here to detect a totally new
  2297. * configuration, reset the AP, unassoc, rxon timing, assoc,
  2298. * clear sta table, add BCAST sta... */
  2299. }
  2300. static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw,
  2301. struct ieee80211_key_conf *keyconf, const u8 *addr,
  2302. u32 iv32, u16 *phase1key)
  2303. {
  2304. struct iwl_priv *priv = hw->priv;
  2305. IWL_DEBUG_MAC80211(priv, "enter\n");
  2306. iwl_update_tkip_key(priv, keyconf, addr, iv32, phase1key);
  2307. IWL_DEBUG_MAC80211(priv, "leave\n");
  2308. }
  2309. static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
  2310. struct ieee80211_vif *vif,
  2311. struct ieee80211_sta *sta,
  2312. struct ieee80211_key_conf *key)
  2313. {
  2314. struct iwl_priv *priv = hw->priv;
  2315. const u8 *addr;
  2316. int ret;
  2317. u8 sta_id;
  2318. bool is_default_wep_key = false;
  2319. IWL_DEBUG_MAC80211(priv, "enter\n");
  2320. if (priv->cfg->mod_params->sw_crypto) {
  2321. IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
  2322. return -EOPNOTSUPP;
  2323. }
  2324. addr = sta ? sta->addr : iwl_bcast_addr;
  2325. sta_id = iwl_find_station(priv, addr);
  2326. if (sta_id == IWL_INVALID_STATION) {
  2327. IWL_DEBUG_MAC80211(priv, "leave - %pM not in station map.\n",
  2328. addr);
  2329. return -EINVAL;
  2330. }
  2331. mutex_lock(&priv->mutex);
  2332. iwl_scan_cancel_timeout(priv, 100);
  2333. mutex_unlock(&priv->mutex);
  2334. /* If we are getting WEP group key and we didn't receive any key mapping
  2335. * so far, we are in legacy wep mode (group key only), otherwise we are
  2336. * in 1X mode.
  2337. * In legacy wep mode, we use another host command to the uCode */
  2338. if (key->alg == ALG_WEP && sta_id == priv->hw_params.bcast_sta_id &&
  2339. priv->iw_mode != NL80211_IFTYPE_AP) {
  2340. if (cmd == SET_KEY)
  2341. is_default_wep_key = !priv->key_mapping_key;
  2342. else
  2343. is_default_wep_key =
  2344. (key->hw_key_idx == HW_KEY_DEFAULT);
  2345. }
  2346. switch (cmd) {
  2347. case SET_KEY:
  2348. if (is_default_wep_key)
  2349. ret = iwl_set_default_wep_key(priv, key);
  2350. else
  2351. ret = iwl_set_dynamic_key(priv, key, sta_id);
  2352. IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
  2353. break;
  2354. case DISABLE_KEY:
  2355. if (is_default_wep_key)
  2356. ret = iwl_remove_default_wep_key(priv, key);
  2357. else
  2358. ret = iwl_remove_dynamic_key(priv, key, sta_id);
  2359. IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
  2360. break;
  2361. default:
  2362. ret = -EINVAL;
  2363. }
  2364. IWL_DEBUG_MAC80211(priv, "leave\n");
  2365. return ret;
  2366. }
  2367. static int iwl_mac_ampdu_action(struct ieee80211_hw *hw,
  2368. struct ieee80211_vif *vif,
  2369. enum ieee80211_ampdu_mlme_action action,
  2370. struct ieee80211_sta *sta, u16 tid, u16 *ssn)
  2371. {
  2372. struct iwl_priv *priv = hw->priv;
  2373. int ret;
  2374. IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
  2375. sta->addr, tid);
  2376. if (!(priv->cfg->sku & IWL_SKU_N))
  2377. return -EACCES;
  2378. switch (action) {
  2379. case IEEE80211_AMPDU_RX_START:
  2380. IWL_DEBUG_HT(priv, "start Rx\n");
  2381. return iwl_sta_rx_agg_start(priv, sta->addr, tid, *ssn);
  2382. case IEEE80211_AMPDU_RX_STOP:
  2383. IWL_DEBUG_HT(priv, "stop Rx\n");
  2384. ret = iwl_sta_rx_agg_stop(priv, sta->addr, tid);
  2385. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2386. return 0;
  2387. else
  2388. return ret;
  2389. case IEEE80211_AMPDU_TX_START:
  2390. IWL_DEBUG_HT(priv, "start Tx\n");
  2391. return iwl_tx_agg_start(priv, sta->addr, tid, ssn);
  2392. case IEEE80211_AMPDU_TX_STOP:
  2393. IWL_DEBUG_HT(priv, "stop Tx\n");
  2394. ret = iwl_tx_agg_stop(priv, sta->addr, tid);
  2395. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2396. return 0;
  2397. else
  2398. return ret;
  2399. default:
  2400. IWL_DEBUG_HT(priv, "unknown\n");
  2401. return -EINVAL;
  2402. break;
  2403. }
  2404. return 0;
  2405. }
  2406. static int iwl_mac_get_stats(struct ieee80211_hw *hw,
  2407. struct ieee80211_low_level_stats *stats)
  2408. {
  2409. struct iwl_priv *priv = hw->priv;
  2410. priv = hw->priv;
  2411. IWL_DEBUG_MAC80211(priv, "enter\n");
  2412. IWL_DEBUG_MAC80211(priv, "leave\n");
  2413. return 0;
  2414. }
  2415. static void iwl_mac_sta_notify(struct ieee80211_hw *hw,
  2416. struct ieee80211_vif *vif,
  2417. enum sta_notify_cmd cmd,
  2418. struct ieee80211_sta *sta)
  2419. {
  2420. struct iwl_priv *priv = hw->priv;
  2421. struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
  2422. int sta_id;
  2423. /*
  2424. * TODO: We really should use this callback to
  2425. * actually maintain the station table in
  2426. * the device.
  2427. */
  2428. switch (cmd) {
  2429. case STA_NOTIFY_ADD:
  2430. atomic_set(&sta_priv->pending_frames, 0);
  2431. if (vif->type == NL80211_IFTYPE_AP)
  2432. sta_priv->client = true;
  2433. break;
  2434. case STA_NOTIFY_SLEEP:
  2435. WARN_ON(!sta_priv->client);
  2436. sta_priv->asleep = true;
  2437. if (atomic_read(&sta_priv->pending_frames) > 0)
  2438. ieee80211_sta_block_awake(hw, sta, true);
  2439. break;
  2440. case STA_NOTIFY_AWAKE:
  2441. WARN_ON(!sta_priv->client);
  2442. sta_priv->asleep = false;
  2443. sta_id = iwl_find_station(priv, sta->addr);
  2444. if (sta_id != IWL_INVALID_STATION)
  2445. iwl_sta_modify_ps_wake(priv, sta_id);
  2446. break;
  2447. default:
  2448. break;
  2449. }
  2450. }
  2451. /*****************************************************************************
  2452. *
  2453. * sysfs attributes
  2454. *
  2455. *****************************************************************************/
  2456. #ifdef CONFIG_IWLWIFI_DEBUG
  2457. /*
  2458. * The following adds a new attribute to the sysfs representation
  2459. * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
  2460. * used for controlling the debug level.
  2461. *
  2462. * See the level definitions in iwl for details.
  2463. *
  2464. * The debug_level being managed using sysfs below is a per device debug
  2465. * level that is used instead of the global debug level if it (the per
  2466. * device debug level) is set.
  2467. */
  2468. static ssize_t show_debug_level(struct device *d,
  2469. struct device_attribute *attr, char *buf)
  2470. {
  2471. struct iwl_priv *priv = dev_get_drvdata(d);
  2472. return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
  2473. }
  2474. static ssize_t store_debug_level(struct device *d,
  2475. struct device_attribute *attr,
  2476. const char *buf, size_t count)
  2477. {
  2478. struct iwl_priv *priv = dev_get_drvdata(d);
  2479. unsigned long val;
  2480. int ret;
  2481. ret = strict_strtoul(buf, 0, &val);
  2482. if (ret)
  2483. IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
  2484. else {
  2485. priv->debug_level = val;
  2486. if (iwl_alloc_traffic_mem(priv))
  2487. IWL_ERR(priv,
  2488. "Not enough memory to generate traffic log\n");
  2489. }
  2490. return strnlen(buf, count);
  2491. }
  2492. static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
  2493. show_debug_level, store_debug_level);
  2494. #endif /* CONFIG_IWLWIFI_DEBUG */
  2495. static ssize_t show_temperature(struct device *d,
  2496. struct device_attribute *attr, char *buf)
  2497. {
  2498. struct iwl_priv *priv = dev_get_drvdata(d);
  2499. if (!iwl_is_alive(priv))
  2500. return -EAGAIN;
  2501. return sprintf(buf, "%d\n", priv->temperature);
  2502. }
  2503. static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
  2504. static ssize_t show_tx_power(struct device *d,
  2505. struct device_attribute *attr, char *buf)
  2506. {
  2507. struct iwl_priv *priv = dev_get_drvdata(d);
  2508. if (!iwl_is_ready_rf(priv))
  2509. return sprintf(buf, "off\n");
  2510. else
  2511. return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
  2512. }
  2513. static ssize_t store_tx_power(struct device *d,
  2514. struct device_attribute *attr,
  2515. const char *buf, size_t count)
  2516. {
  2517. struct iwl_priv *priv = dev_get_drvdata(d);
  2518. unsigned long val;
  2519. int ret;
  2520. ret = strict_strtoul(buf, 10, &val);
  2521. if (ret)
  2522. IWL_INFO(priv, "%s is not in decimal form.\n", buf);
  2523. else {
  2524. ret = iwl_set_tx_power(priv, val, false);
  2525. if (ret)
  2526. IWL_ERR(priv, "failed setting tx power (0x%d).\n",
  2527. ret);
  2528. else
  2529. ret = count;
  2530. }
  2531. return ret;
  2532. }
  2533. static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
  2534. static ssize_t show_flags(struct device *d,
  2535. struct device_attribute *attr, char *buf)
  2536. {
  2537. struct iwl_priv *priv = dev_get_drvdata(d);
  2538. return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
  2539. }
  2540. static ssize_t store_flags(struct device *d,
  2541. struct device_attribute *attr,
  2542. const char *buf, size_t count)
  2543. {
  2544. struct iwl_priv *priv = dev_get_drvdata(d);
  2545. unsigned long val;
  2546. u32 flags;
  2547. int ret = strict_strtoul(buf, 0, &val);
  2548. if (ret)
  2549. return ret;
  2550. flags = (u32)val;
  2551. mutex_lock(&priv->mutex);
  2552. if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
  2553. /* Cancel any currently running scans... */
  2554. if (iwl_scan_cancel_timeout(priv, 100))
  2555. IWL_WARN(priv, "Could not cancel scan.\n");
  2556. else {
  2557. IWL_DEBUG_INFO(priv, "Commit rxon.flags = 0x%04X\n", flags);
  2558. priv->staging_rxon.flags = cpu_to_le32(flags);
  2559. iwlcore_commit_rxon(priv);
  2560. }
  2561. }
  2562. mutex_unlock(&priv->mutex);
  2563. return count;
  2564. }
  2565. static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
  2566. static ssize_t show_filter_flags(struct device *d,
  2567. struct device_attribute *attr, char *buf)
  2568. {
  2569. struct iwl_priv *priv = dev_get_drvdata(d);
  2570. return sprintf(buf, "0x%04X\n",
  2571. le32_to_cpu(priv->active_rxon.filter_flags));
  2572. }
  2573. static ssize_t store_filter_flags(struct device *d,
  2574. struct device_attribute *attr,
  2575. const char *buf, size_t count)
  2576. {
  2577. struct iwl_priv *priv = dev_get_drvdata(d);
  2578. unsigned long val;
  2579. u32 filter_flags;
  2580. int ret = strict_strtoul(buf, 0, &val);
  2581. if (ret)
  2582. return ret;
  2583. filter_flags = (u32)val;
  2584. mutex_lock(&priv->mutex);
  2585. if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
  2586. /* Cancel any currently running scans... */
  2587. if (iwl_scan_cancel_timeout(priv, 100))
  2588. IWL_WARN(priv, "Could not cancel scan.\n");
  2589. else {
  2590. IWL_DEBUG_INFO(priv, "Committing rxon.filter_flags = "
  2591. "0x%04X\n", filter_flags);
  2592. priv->staging_rxon.filter_flags =
  2593. cpu_to_le32(filter_flags);
  2594. iwlcore_commit_rxon(priv);
  2595. }
  2596. }
  2597. mutex_unlock(&priv->mutex);
  2598. return count;
  2599. }
  2600. static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
  2601. store_filter_flags);
  2602. static ssize_t show_statistics(struct device *d,
  2603. struct device_attribute *attr, char *buf)
  2604. {
  2605. struct iwl_priv *priv = dev_get_drvdata(d);
  2606. u32 size = sizeof(struct iwl_notif_statistics);
  2607. u32 len = 0, ofs = 0;
  2608. u8 *data = (u8 *)&priv->statistics;
  2609. int rc = 0;
  2610. if (!iwl_is_alive(priv))
  2611. return -EAGAIN;
  2612. mutex_lock(&priv->mutex);
  2613. rc = iwl_send_statistics_request(priv, CMD_SYNC, false);
  2614. mutex_unlock(&priv->mutex);
  2615. if (rc) {
  2616. len = sprintf(buf,
  2617. "Error sending statistics request: 0x%08X\n", rc);
  2618. return len;
  2619. }
  2620. while (size && (PAGE_SIZE - len)) {
  2621. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  2622. PAGE_SIZE - len, 1);
  2623. len = strlen(buf);
  2624. if (PAGE_SIZE - len)
  2625. buf[len++] = '\n';
  2626. ofs += 16;
  2627. size -= min(size, 16U);
  2628. }
  2629. return len;
  2630. }
  2631. static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
  2632. static ssize_t show_rts_ht_protection(struct device *d,
  2633. struct device_attribute *attr, char *buf)
  2634. {
  2635. struct iwl_priv *priv = dev_get_drvdata(d);
  2636. return sprintf(buf, "%s\n",
  2637. priv->cfg->use_rts_for_ht ? "RTS/CTS" : "CTS-to-self");
  2638. }
  2639. static ssize_t store_rts_ht_protection(struct device *d,
  2640. struct device_attribute *attr,
  2641. const char *buf, size_t count)
  2642. {
  2643. struct iwl_priv *priv = dev_get_drvdata(d);
  2644. unsigned long val;
  2645. int ret;
  2646. ret = strict_strtoul(buf, 10, &val);
  2647. if (ret)
  2648. IWL_INFO(priv, "Input is not in decimal form.\n");
  2649. else {
  2650. if (!iwl_is_associated(priv))
  2651. priv->cfg->use_rts_for_ht = val ? true : false;
  2652. else
  2653. IWL_ERR(priv, "Sta associated with AP - "
  2654. "Change protection mechanism is not allowed\n");
  2655. ret = count;
  2656. }
  2657. return ret;
  2658. }
  2659. static DEVICE_ATTR(rts_ht_protection, S_IWUSR | S_IRUGO,
  2660. show_rts_ht_protection, store_rts_ht_protection);
  2661. /*****************************************************************************
  2662. *
  2663. * driver setup and teardown
  2664. *
  2665. *****************************************************************************/
  2666. static void iwl_setup_deferred_work(struct iwl_priv *priv)
  2667. {
  2668. priv->workqueue = create_singlethread_workqueue(DRV_NAME);
  2669. init_waitqueue_head(&priv->wait_command_queue);
  2670. INIT_WORK(&priv->up, iwl_bg_up);
  2671. INIT_WORK(&priv->restart, iwl_bg_restart);
  2672. INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
  2673. INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
  2674. INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
  2675. INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
  2676. INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
  2677. iwl_setup_scan_deferred_work(priv);
  2678. if (priv->cfg->ops->lib->setup_deferred_work)
  2679. priv->cfg->ops->lib->setup_deferred_work(priv);
  2680. init_timer(&priv->statistics_periodic);
  2681. priv->statistics_periodic.data = (unsigned long)priv;
  2682. priv->statistics_periodic.function = iwl_bg_statistics_periodic;
  2683. init_timer(&priv->ucode_trace);
  2684. priv->ucode_trace.data = (unsigned long)priv;
  2685. priv->ucode_trace.function = iwl_bg_ucode_trace;
  2686. if (!priv->cfg->use_isr_legacy)
  2687. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  2688. iwl_irq_tasklet, (unsigned long)priv);
  2689. else
  2690. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  2691. iwl_irq_tasklet_legacy, (unsigned long)priv);
  2692. }
  2693. static void iwl_cancel_deferred_work(struct iwl_priv *priv)
  2694. {
  2695. if (priv->cfg->ops->lib->cancel_deferred_work)
  2696. priv->cfg->ops->lib->cancel_deferred_work(priv);
  2697. cancel_delayed_work_sync(&priv->init_alive_start);
  2698. cancel_delayed_work(&priv->scan_check);
  2699. cancel_delayed_work(&priv->alive_start);
  2700. cancel_work_sync(&priv->beacon_update);
  2701. del_timer_sync(&priv->statistics_periodic);
  2702. del_timer_sync(&priv->ucode_trace);
  2703. }
  2704. static void iwl_init_hw_rates(struct iwl_priv *priv,
  2705. struct ieee80211_rate *rates)
  2706. {
  2707. int i;
  2708. for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
  2709. rates[i].bitrate = iwl_rates[i].ieee * 5;
  2710. rates[i].hw_value = i; /* Rate scaling will work on indexes */
  2711. rates[i].hw_value_short = i;
  2712. rates[i].flags = 0;
  2713. if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
  2714. /*
  2715. * If CCK != 1M then set short preamble rate flag.
  2716. */
  2717. rates[i].flags |=
  2718. (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
  2719. 0 : IEEE80211_RATE_SHORT_PREAMBLE;
  2720. }
  2721. }
  2722. }
  2723. static int iwl_init_drv(struct iwl_priv *priv)
  2724. {
  2725. int ret;
  2726. priv->ibss_beacon = NULL;
  2727. spin_lock_init(&priv->lock);
  2728. spin_lock_init(&priv->sta_lock);
  2729. spin_lock_init(&priv->hcmd_lock);
  2730. INIT_LIST_HEAD(&priv->free_frames);
  2731. mutex_init(&priv->mutex);
  2732. /* Clear the driver's (not device's) station table */
  2733. iwl_clear_stations_table(priv);
  2734. priv->ieee_channels = NULL;
  2735. priv->ieee_rates = NULL;
  2736. priv->band = IEEE80211_BAND_2GHZ;
  2737. priv->iw_mode = NL80211_IFTYPE_STATION;
  2738. /* Choose which receivers/antennas to use */
  2739. if (priv->cfg->ops->hcmd->set_rxon_chain)
  2740. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  2741. iwl_init_scan_params(priv);
  2742. iwl_reset_qos(priv);
  2743. priv->qos_data.qos_active = 0;
  2744. priv->qos_data.qos_cap.val = 0;
  2745. priv->rates_mask = IWL_RATES_MASK;
  2746. /* Set the tx_power_user_lmt to the lowest power level
  2747. * this value will get overwritten by channel max power avg
  2748. * from eeprom */
  2749. priv->tx_power_user_lmt = IWL_TX_POWER_TARGET_POWER_MIN;
  2750. ret = iwl_init_channel_map(priv);
  2751. if (ret) {
  2752. IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
  2753. goto err;
  2754. }
  2755. ret = iwlcore_init_geos(priv);
  2756. if (ret) {
  2757. IWL_ERR(priv, "initializing geos failed: %d\n", ret);
  2758. goto err_free_channel_map;
  2759. }
  2760. iwl_init_hw_rates(priv, priv->ieee_rates);
  2761. return 0;
  2762. err_free_channel_map:
  2763. iwl_free_channel_map(priv);
  2764. err:
  2765. return ret;
  2766. }
  2767. static void iwl_uninit_drv(struct iwl_priv *priv)
  2768. {
  2769. iwl_calib_free_results(priv);
  2770. iwlcore_free_geos(priv);
  2771. iwl_free_channel_map(priv);
  2772. kfree(priv->scan);
  2773. }
  2774. static struct attribute *iwl_sysfs_entries[] = {
  2775. &dev_attr_flags.attr,
  2776. &dev_attr_filter_flags.attr,
  2777. &dev_attr_statistics.attr,
  2778. &dev_attr_temperature.attr,
  2779. &dev_attr_tx_power.attr,
  2780. &dev_attr_rts_ht_protection.attr,
  2781. #ifdef CONFIG_IWLWIFI_DEBUG
  2782. &dev_attr_debug_level.attr,
  2783. #endif
  2784. NULL
  2785. };
  2786. static struct attribute_group iwl_attribute_group = {
  2787. .name = NULL, /* put in device directory */
  2788. .attrs = iwl_sysfs_entries,
  2789. };
  2790. static struct ieee80211_ops iwl_hw_ops = {
  2791. .tx = iwl_mac_tx,
  2792. .start = iwl_mac_start,
  2793. .stop = iwl_mac_stop,
  2794. .add_interface = iwl_mac_add_interface,
  2795. .remove_interface = iwl_mac_remove_interface,
  2796. .config = iwl_mac_config,
  2797. .configure_filter = iwl_configure_filter,
  2798. .set_key = iwl_mac_set_key,
  2799. .update_tkip_key = iwl_mac_update_tkip_key,
  2800. .get_stats = iwl_mac_get_stats,
  2801. .get_tx_stats = iwl_mac_get_tx_stats,
  2802. .conf_tx = iwl_mac_conf_tx,
  2803. .reset_tsf = iwl_mac_reset_tsf,
  2804. .bss_info_changed = iwl_bss_info_changed,
  2805. .ampdu_action = iwl_mac_ampdu_action,
  2806. .hw_scan = iwl_mac_hw_scan,
  2807. .sta_notify = iwl_mac_sta_notify,
  2808. };
  2809. static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  2810. {
  2811. int err = 0;
  2812. struct iwl_priv *priv;
  2813. struct ieee80211_hw *hw;
  2814. struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
  2815. unsigned long flags;
  2816. u16 pci_cmd;
  2817. /************************
  2818. * 1. Allocating HW data
  2819. ************************/
  2820. /* Disabling hardware scan means that mac80211 will perform scans
  2821. * "the hard way", rather than using device's scan. */
  2822. if (cfg->mod_params->disable_hw_scan) {
  2823. if (iwl_debug_level & IWL_DL_INFO)
  2824. dev_printk(KERN_DEBUG, &(pdev->dev),
  2825. "Disabling hw_scan\n");
  2826. iwl_hw_ops.hw_scan = NULL;
  2827. }
  2828. hw = iwl_alloc_all(cfg, &iwl_hw_ops);
  2829. if (!hw) {
  2830. err = -ENOMEM;
  2831. goto out;
  2832. }
  2833. priv = hw->priv;
  2834. /* At this point both hw and priv are allocated. */
  2835. SET_IEEE80211_DEV(hw, &pdev->dev);
  2836. IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
  2837. priv->cfg = cfg;
  2838. priv->pci_dev = pdev;
  2839. priv->inta_mask = CSR_INI_SET_MASK;
  2840. #ifdef CONFIG_IWLWIFI_DEBUG
  2841. atomic_set(&priv->restrict_refcnt, 0);
  2842. #endif
  2843. if (iwl_alloc_traffic_mem(priv))
  2844. IWL_ERR(priv, "Not enough memory to generate traffic log\n");
  2845. /**************************
  2846. * 2. Initializing PCI bus
  2847. **************************/
  2848. if (pci_enable_device(pdev)) {
  2849. err = -ENODEV;
  2850. goto out_ieee80211_free_hw;
  2851. }
  2852. pci_set_master(pdev);
  2853. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
  2854. if (!err)
  2855. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
  2856. if (err) {
  2857. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  2858. if (!err)
  2859. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
  2860. /* both attempts failed: */
  2861. if (err) {
  2862. IWL_WARN(priv, "No suitable DMA available.\n");
  2863. goto out_pci_disable_device;
  2864. }
  2865. }
  2866. err = pci_request_regions(pdev, DRV_NAME);
  2867. if (err)
  2868. goto out_pci_disable_device;
  2869. pci_set_drvdata(pdev, priv);
  2870. /***********************
  2871. * 3. Read REV register
  2872. ***********************/
  2873. priv->hw_base = pci_iomap(pdev, 0, 0);
  2874. if (!priv->hw_base) {
  2875. err = -ENODEV;
  2876. goto out_pci_release_regions;
  2877. }
  2878. IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
  2879. (unsigned long long) pci_resource_len(pdev, 0));
  2880. IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
  2881. /* this spin lock will be used in apm_ops.init and EEPROM access
  2882. * we should init now
  2883. */
  2884. spin_lock_init(&priv->reg_lock);
  2885. iwl_hw_detect(priv);
  2886. IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s REV=0x%X\n",
  2887. priv->cfg->name, priv->hw_rev);
  2888. /* We disable the RETRY_TIMEOUT register (0x41) to keep
  2889. * PCI Tx retries from interfering with C3 CPU state */
  2890. pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
  2891. iwl_prepare_card_hw(priv);
  2892. if (!priv->hw_ready) {
  2893. IWL_WARN(priv, "Failed, HW not ready\n");
  2894. goto out_iounmap;
  2895. }
  2896. /*****************
  2897. * 4. Read EEPROM
  2898. *****************/
  2899. /* Read the EEPROM */
  2900. err = iwl_eeprom_init(priv);
  2901. if (err) {
  2902. IWL_ERR(priv, "Unable to init EEPROM\n");
  2903. goto out_iounmap;
  2904. }
  2905. err = iwl_eeprom_check_version(priv);
  2906. if (err)
  2907. goto out_free_eeprom;
  2908. /* extract MAC Address */
  2909. iwl_eeprom_get_mac(priv, priv->mac_addr);
  2910. IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->mac_addr);
  2911. SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
  2912. /************************
  2913. * 5. Setup HW constants
  2914. ************************/
  2915. if (iwl_set_hw_params(priv)) {
  2916. IWL_ERR(priv, "failed to set hw parameters\n");
  2917. goto out_free_eeprom;
  2918. }
  2919. /*******************
  2920. * 6. Setup priv
  2921. *******************/
  2922. err = iwl_init_drv(priv);
  2923. if (err)
  2924. goto out_free_eeprom;
  2925. /* At this point both hw and priv are initialized. */
  2926. /********************
  2927. * 7. Setup services
  2928. ********************/
  2929. spin_lock_irqsave(&priv->lock, flags);
  2930. iwl_disable_interrupts(priv);
  2931. spin_unlock_irqrestore(&priv->lock, flags);
  2932. pci_enable_msi(priv->pci_dev);
  2933. iwl_alloc_isr_ict(priv);
  2934. err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
  2935. IRQF_SHARED, DRV_NAME, priv);
  2936. if (err) {
  2937. IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
  2938. goto out_disable_msi;
  2939. }
  2940. err = sysfs_create_group(&pdev->dev.kobj, &iwl_attribute_group);
  2941. if (err) {
  2942. IWL_ERR(priv, "failed to create sysfs device attributes\n");
  2943. goto out_free_irq;
  2944. }
  2945. iwl_setup_deferred_work(priv);
  2946. iwl_setup_rx_handlers(priv);
  2947. /**********************************
  2948. * 8. Setup and register mac80211
  2949. **********************************/
  2950. /* enable interrupts if needed: hw bug w/a */
  2951. pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
  2952. if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
  2953. pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
  2954. pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
  2955. }
  2956. iwl_enable_interrupts(priv);
  2957. err = iwl_setup_mac(priv);
  2958. if (err)
  2959. goto out_remove_sysfs;
  2960. err = iwl_dbgfs_register(priv, DRV_NAME);
  2961. if (err)
  2962. IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
  2963. /* If platform's RF_KILL switch is NOT set to KILL */
  2964. if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  2965. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  2966. else
  2967. set_bit(STATUS_RF_KILL_HW, &priv->status);
  2968. wiphy_rfkill_set_hw_state(priv->hw->wiphy,
  2969. test_bit(STATUS_RF_KILL_HW, &priv->status));
  2970. iwl_power_initialize(priv);
  2971. iwl_tt_initialize(priv);
  2972. return 0;
  2973. out_remove_sysfs:
  2974. destroy_workqueue(priv->workqueue);
  2975. priv->workqueue = NULL;
  2976. sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
  2977. out_free_irq:
  2978. free_irq(priv->pci_dev->irq, priv);
  2979. iwl_free_isr_ict(priv);
  2980. out_disable_msi:
  2981. pci_disable_msi(priv->pci_dev);
  2982. iwl_uninit_drv(priv);
  2983. out_free_eeprom:
  2984. iwl_eeprom_free(priv);
  2985. out_iounmap:
  2986. pci_iounmap(pdev, priv->hw_base);
  2987. out_pci_release_regions:
  2988. pci_set_drvdata(pdev, NULL);
  2989. pci_release_regions(pdev);
  2990. out_pci_disable_device:
  2991. pci_disable_device(pdev);
  2992. out_ieee80211_free_hw:
  2993. iwl_free_traffic_mem(priv);
  2994. ieee80211_free_hw(priv->hw);
  2995. out:
  2996. return err;
  2997. }
  2998. static void __devexit iwl_pci_remove(struct pci_dev *pdev)
  2999. {
  3000. struct iwl_priv *priv = pci_get_drvdata(pdev);
  3001. unsigned long flags;
  3002. if (!priv)
  3003. return;
  3004. IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
  3005. iwl_dbgfs_unregister(priv);
  3006. sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
  3007. /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
  3008. * to be called and iwl_down since we are removing the device
  3009. * we need to set STATUS_EXIT_PENDING bit.
  3010. */
  3011. set_bit(STATUS_EXIT_PENDING, &priv->status);
  3012. if (priv->mac80211_registered) {
  3013. ieee80211_unregister_hw(priv->hw);
  3014. priv->mac80211_registered = 0;
  3015. } else {
  3016. iwl_down(priv);
  3017. }
  3018. /*
  3019. * Make sure device is reset to low power before unloading driver.
  3020. * This may be redundant with iwl_down(), but there are paths to
  3021. * run iwl_down() without calling apm_ops.stop(), and there are
  3022. * paths to avoid running iwl_down() at all before leaving driver.
  3023. * This (inexpensive) call *makes sure* device is reset.
  3024. */
  3025. priv->cfg->ops->lib->apm_ops.stop(priv);
  3026. iwl_tt_exit(priv);
  3027. /* make sure we flush any pending irq or
  3028. * tasklet for the driver
  3029. */
  3030. spin_lock_irqsave(&priv->lock, flags);
  3031. iwl_disable_interrupts(priv);
  3032. spin_unlock_irqrestore(&priv->lock, flags);
  3033. iwl_synchronize_irq(priv);
  3034. iwl_dealloc_ucode_pci(priv);
  3035. if (priv->rxq.bd)
  3036. iwl_rx_queue_free(priv, &priv->rxq);
  3037. iwl_hw_txq_ctx_free(priv);
  3038. iwl_clear_stations_table(priv);
  3039. iwl_eeprom_free(priv);
  3040. /*netif_stop_queue(dev); */
  3041. flush_workqueue(priv->workqueue);
  3042. /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
  3043. * priv->workqueue... so we can't take down the workqueue
  3044. * until now... */
  3045. destroy_workqueue(priv->workqueue);
  3046. priv->workqueue = NULL;
  3047. iwl_free_traffic_mem(priv);
  3048. free_irq(priv->pci_dev->irq, priv);
  3049. pci_disable_msi(priv->pci_dev);
  3050. pci_iounmap(pdev, priv->hw_base);
  3051. pci_release_regions(pdev);
  3052. pci_disable_device(pdev);
  3053. pci_set_drvdata(pdev, NULL);
  3054. iwl_uninit_drv(priv);
  3055. iwl_free_isr_ict(priv);
  3056. if (priv->ibss_beacon)
  3057. dev_kfree_skb(priv->ibss_beacon);
  3058. ieee80211_free_hw(priv->hw);
  3059. }
  3060. /*****************************************************************************
  3061. *
  3062. * driver and module entry point
  3063. *
  3064. *****************************************************************************/
  3065. /* Hardware specific file defines the PCI IDs table for that hardware module */
  3066. static struct pci_device_id iwl_hw_card_ids[] = {
  3067. #ifdef CONFIG_IWL4965
  3068. {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
  3069. {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
  3070. #endif /* CONFIG_IWL4965 */
  3071. #ifdef CONFIG_IWL5000
  3072. /* 5100 Series WiFi */
  3073. {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
  3074. {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
  3075. {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
  3076. {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */
  3077. {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */
  3078. {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */
  3079. {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */
  3080. {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */
  3081. {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */
  3082. {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */
  3083. {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */
  3084. {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */
  3085. {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */
  3086. {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */
  3087. {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */
  3088. {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */
  3089. {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */
  3090. {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */
  3091. {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */
  3092. {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */
  3093. {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */
  3094. {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */
  3095. {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */
  3096. {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */
  3097. /* 5300 Series WiFi */
  3098. {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */
  3099. {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */
  3100. {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */
  3101. {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */
  3102. {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */
  3103. {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */
  3104. {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */
  3105. {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */
  3106. {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */
  3107. {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */
  3108. {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */
  3109. {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */
  3110. /* 5350 Series WiFi/WiMax */
  3111. {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */
  3112. {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */
  3113. {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */
  3114. /* 5150 Series Wifi/WiMax */
  3115. {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */
  3116. {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */
  3117. {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */
  3118. {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */
  3119. {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */
  3120. {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */
  3121. {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */
  3122. {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */
  3123. {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */
  3124. {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */
  3125. /* 6x00 Series */
  3126. {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
  3127. {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
  3128. {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
  3129. {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
  3130. {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
  3131. {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
  3132. {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
  3133. {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
  3134. {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
  3135. {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
  3136. /* 6x50 WiFi/WiMax Series */
  3137. {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
  3138. {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
  3139. {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
  3140. {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
  3141. {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
  3142. {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
  3143. /* 1000 Series WiFi */
  3144. {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
  3145. {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
  3146. {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
  3147. {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
  3148. {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
  3149. {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
  3150. {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
  3151. {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
  3152. {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
  3153. {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
  3154. {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
  3155. {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
  3156. #endif /* CONFIG_IWL5000 */
  3157. {0}
  3158. };
  3159. MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
  3160. static struct pci_driver iwl_driver = {
  3161. .name = DRV_NAME,
  3162. .id_table = iwl_hw_card_ids,
  3163. .probe = iwl_pci_probe,
  3164. .remove = __devexit_p(iwl_pci_remove),
  3165. #ifdef CONFIG_PM
  3166. .suspend = iwl_pci_suspend,
  3167. .resume = iwl_pci_resume,
  3168. #endif
  3169. };
  3170. static int __init iwl_init(void)
  3171. {
  3172. int ret;
  3173. printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
  3174. printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
  3175. ret = iwlagn_rate_control_register();
  3176. if (ret) {
  3177. printk(KERN_ERR DRV_NAME
  3178. "Unable to register rate control algorithm: %d\n", ret);
  3179. return ret;
  3180. }
  3181. ret = pci_register_driver(&iwl_driver);
  3182. if (ret) {
  3183. printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n");
  3184. goto error_register;
  3185. }
  3186. return ret;
  3187. error_register:
  3188. iwlagn_rate_control_unregister();
  3189. return ret;
  3190. }
  3191. static void __exit iwl_exit(void)
  3192. {
  3193. pci_unregister_driver(&iwl_driver);
  3194. iwlagn_rate_control_unregister();
  3195. }
  3196. module_exit(iwl_exit);
  3197. module_init(iwl_init);
  3198. #ifdef CONFIG_IWLWIFI_DEBUG
  3199. module_param_named(debug50, iwl_debug_level, uint, S_IRUGO);
  3200. MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)");
  3201. module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
  3202. MODULE_PARM_DESC(debug, "debug output mask");
  3203. #endif