iwl-core.c 61 KB

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  1. /******************************************************************************
  2. *
  3. * GPL LICENSE SUMMARY
  4. *
  5. * Copyright(c) 2008 - 2009 Intel Corporation. All rights reserved.
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of version 2 of the GNU General Public License as
  9. * published by the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful, but
  12. * WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  14. * General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
  19. * USA
  20. *
  21. * The full GNU General Public License is included in this distribution
  22. * in the file called LICENSE.GPL.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *****************************************************************************/
  28. #include <linux/kernel.h>
  29. #include <linux/module.h>
  30. #include <linux/etherdevice.h>
  31. #include <net/mac80211.h>
  32. #include "iwl-eeprom.h"
  33. #include "iwl-dev.h" /* FIXME: remove */
  34. #include "iwl-debug.h"
  35. #include "iwl-core.h"
  36. #include "iwl-io.h"
  37. #include "iwl-rfkill.h"
  38. #include "iwl-power.h"
  39. #include "iwl-sta.h"
  40. MODULE_DESCRIPTION("iwl core");
  41. MODULE_VERSION(IWLWIFI_VERSION);
  42. MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  43. MODULE_LICENSE("GPL");
  44. #define IWL_DECLARE_RATE_INFO(r, s, ip, in, rp, rn, pp, np) \
  45. [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
  46. IWL_RATE_SISO_##s##M_PLCP, \
  47. IWL_RATE_MIMO2_##s##M_PLCP,\
  48. IWL_RATE_MIMO3_##s##M_PLCP,\
  49. IWL_RATE_##r##M_IEEE, \
  50. IWL_RATE_##ip##M_INDEX, \
  51. IWL_RATE_##in##M_INDEX, \
  52. IWL_RATE_##rp##M_INDEX, \
  53. IWL_RATE_##rn##M_INDEX, \
  54. IWL_RATE_##pp##M_INDEX, \
  55. IWL_RATE_##np##M_INDEX }
  56. /*
  57. * Parameter order:
  58. * rate, ht rate, prev rate, next rate, prev tgg rate, next tgg rate
  59. *
  60. * If there isn't a valid next or previous rate then INV is used which
  61. * maps to IWL_RATE_INVALID
  62. *
  63. */
  64. const struct iwl_rate_info iwl_rates[IWL_RATE_COUNT] = {
  65. IWL_DECLARE_RATE_INFO(1, INV, INV, 2, INV, 2, INV, 2), /* 1mbps */
  66. IWL_DECLARE_RATE_INFO(2, INV, 1, 5, 1, 5, 1, 5), /* 2mbps */
  67. IWL_DECLARE_RATE_INFO(5, INV, 2, 6, 2, 11, 2, 11), /*5.5mbps */
  68. IWL_DECLARE_RATE_INFO(11, INV, 9, 12, 9, 12, 5, 18), /* 11mbps */
  69. IWL_DECLARE_RATE_INFO(6, 6, 5, 9, 5, 11, 5, 11), /* 6mbps */
  70. IWL_DECLARE_RATE_INFO(9, 6, 6, 11, 6, 11, 5, 11), /* 9mbps */
  71. IWL_DECLARE_RATE_INFO(12, 12, 11, 18, 11, 18, 11, 18), /* 12mbps */
  72. IWL_DECLARE_RATE_INFO(18, 18, 12, 24, 12, 24, 11, 24), /* 18mbps */
  73. IWL_DECLARE_RATE_INFO(24, 24, 18, 36, 18, 36, 18, 36), /* 24mbps */
  74. IWL_DECLARE_RATE_INFO(36, 36, 24, 48, 24, 48, 24, 48), /* 36mbps */
  75. IWL_DECLARE_RATE_INFO(48, 48, 36, 54, 36, 54, 36, 54), /* 48mbps */
  76. IWL_DECLARE_RATE_INFO(54, 54, 48, INV, 48, INV, 48, INV),/* 54mbps */
  77. IWL_DECLARE_RATE_INFO(60, 60, 48, INV, 48, INV, 48, INV),/* 60mbps */
  78. /* FIXME:RS: ^^ should be INV (legacy) */
  79. };
  80. EXPORT_SYMBOL(iwl_rates);
  81. /**
  82. * translate ucode response to mac80211 tx status control values
  83. */
  84. void iwl_hwrate_to_tx_control(struct iwl_priv *priv, u32 rate_n_flags,
  85. struct ieee80211_tx_info *info)
  86. {
  87. int rate_index;
  88. struct ieee80211_tx_rate *r = &info->control.rates[0];
  89. info->antenna_sel_tx =
  90. ((rate_n_flags & RATE_MCS_ANT_ABC_MSK) >> RATE_MCS_ANT_POS);
  91. if (rate_n_flags & RATE_MCS_HT_MSK)
  92. r->flags |= IEEE80211_TX_RC_MCS;
  93. if (rate_n_flags & RATE_MCS_GF_MSK)
  94. r->flags |= IEEE80211_TX_RC_GREEN_FIELD;
  95. if (rate_n_flags & RATE_MCS_FAT_MSK)
  96. r->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH;
  97. if (rate_n_flags & RATE_MCS_DUP_MSK)
  98. r->flags |= IEEE80211_TX_RC_DUP_DATA;
  99. if (rate_n_flags & RATE_MCS_SGI_MSK)
  100. r->flags |= IEEE80211_TX_RC_SHORT_GI;
  101. rate_index = iwl_hwrate_to_plcp_idx(rate_n_flags);
  102. if (info->band == IEEE80211_BAND_5GHZ)
  103. rate_index -= IWL_FIRST_OFDM_RATE;
  104. r->idx = rate_index;
  105. }
  106. EXPORT_SYMBOL(iwl_hwrate_to_tx_control);
  107. int iwl_hwrate_to_plcp_idx(u32 rate_n_flags)
  108. {
  109. int idx = 0;
  110. /* HT rate format */
  111. if (rate_n_flags & RATE_MCS_HT_MSK) {
  112. idx = (rate_n_flags & 0xff);
  113. if (idx >= IWL_RATE_MIMO3_6M_PLCP)
  114. idx = idx - IWL_RATE_MIMO3_6M_PLCP;
  115. else if (idx >= IWL_RATE_MIMO2_6M_PLCP)
  116. idx = idx - IWL_RATE_MIMO2_6M_PLCP;
  117. idx += IWL_FIRST_OFDM_RATE;
  118. /* skip 9M not supported in ht*/
  119. if (idx >= IWL_RATE_9M_INDEX)
  120. idx += 1;
  121. if ((idx >= IWL_FIRST_OFDM_RATE) && (idx <= IWL_LAST_OFDM_RATE))
  122. return idx;
  123. /* legacy rate format, search for match in table */
  124. } else {
  125. for (idx = 0; idx < ARRAY_SIZE(iwl_rates); idx++)
  126. if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF))
  127. return idx;
  128. }
  129. return -1;
  130. }
  131. EXPORT_SYMBOL(iwl_hwrate_to_plcp_idx);
  132. u8 iwl_toggle_tx_ant(struct iwl_priv *priv, u8 ant)
  133. {
  134. int i;
  135. u8 ind = ant;
  136. for (i = 0; i < RATE_ANT_NUM - 1; i++) {
  137. ind = (ind + 1) < RATE_ANT_NUM ? ind + 1 : 0;
  138. if (priv->hw_params.valid_tx_ant & BIT(ind))
  139. return ind;
  140. }
  141. return ant;
  142. }
  143. const u8 iwl_bcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
  144. EXPORT_SYMBOL(iwl_bcast_addr);
  145. /* This function both allocates and initializes hw and priv. */
  146. struct ieee80211_hw *iwl_alloc_all(struct iwl_cfg *cfg,
  147. struct ieee80211_ops *hw_ops)
  148. {
  149. struct iwl_priv *priv;
  150. /* mac80211 allocates memory for this device instance, including
  151. * space for this driver's private structure */
  152. struct ieee80211_hw *hw =
  153. ieee80211_alloc_hw(sizeof(struct iwl_priv), hw_ops);
  154. if (hw == NULL) {
  155. printk(KERN_ERR "%s: Can not allocate network device\n",
  156. cfg->name);
  157. goto out;
  158. }
  159. priv = hw->priv;
  160. priv->hw = hw;
  161. out:
  162. return hw;
  163. }
  164. EXPORT_SYMBOL(iwl_alloc_all);
  165. void iwl_hw_detect(struct iwl_priv *priv)
  166. {
  167. priv->hw_rev = _iwl_read32(priv, CSR_HW_REV);
  168. priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG);
  169. pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &priv->rev_id);
  170. }
  171. EXPORT_SYMBOL(iwl_hw_detect);
  172. int iwl_hw_nic_init(struct iwl_priv *priv)
  173. {
  174. unsigned long flags;
  175. struct iwl_rx_queue *rxq = &priv->rxq;
  176. int ret;
  177. /* nic_init */
  178. spin_lock_irqsave(&priv->lock, flags);
  179. priv->cfg->ops->lib->apm_ops.init(priv);
  180. iwl_write32(priv, CSR_INT_COALESCING, 512 / 32);
  181. spin_unlock_irqrestore(&priv->lock, flags);
  182. ret = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
  183. priv->cfg->ops->lib->apm_ops.config(priv);
  184. /* Allocate the RX queue, or reset if it is already allocated */
  185. if (!rxq->bd) {
  186. ret = iwl_rx_queue_alloc(priv);
  187. if (ret) {
  188. IWL_ERR(priv, "Unable to initialize Rx queue\n");
  189. return -ENOMEM;
  190. }
  191. } else
  192. iwl_rx_queue_reset(priv, rxq);
  193. iwl_rx_replenish(priv);
  194. iwl_rx_init(priv, rxq);
  195. spin_lock_irqsave(&priv->lock, flags);
  196. rxq->need_update = 1;
  197. iwl_rx_queue_update_write_ptr(priv, rxq);
  198. spin_unlock_irqrestore(&priv->lock, flags);
  199. /* Allocate and init all Tx and Command queues */
  200. ret = iwl_txq_ctx_reset(priv);
  201. if (ret)
  202. return ret;
  203. set_bit(STATUS_INIT, &priv->status);
  204. return 0;
  205. }
  206. EXPORT_SYMBOL(iwl_hw_nic_init);
  207. /*
  208. * QoS support
  209. */
  210. void iwl_activate_qos(struct iwl_priv *priv, u8 force)
  211. {
  212. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  213. return;
  214. priv->qos_data.def_qos_parm.qos_flags = 0;
  215. if (priv->qos_data.qos_cap.q_AP.queue_request &&
  216. !priv->qos_data.qos_cap.q_AP.txop_request)
  217. priv->qos_data.def_qos_parm.qos_flags |=
  218. QOS_PARAM_FLG_TXOP_TYPE_MSK;
  219. if (priv->qos_data.qos_active)
  220. priv->qos_data.def_qos_parm.qos_flags |=
  221. QOS_PARAM_FLG_UPDATE_EDCA_MSK;
  222. if (priv->current_ht_config.is_ht)
  223. priv->qos_data.def_qos_parm.qos_flags |= QOS_PARAM_FLG_TGN_MSK;
  224. if (force || iwl_is_associated(priv)) {
  225. IWL_DEBUG_QOS(priv, "send QoS cmd with Qos active=%d FLAGS=0x%X\n",
  226. priv->qos_data.qos_active,
  227. priv->qos_data.def_qos_parm.qos_flags);
  228. iwl_send_cmd_pdu_async(priv, REPLY_QOS_PARAM,
  229. sizeof(struct iwl_qosparam_cmd),
  230. &priv->qos_data.def_qos_parm, NULL);
  231. }
  232. }
  233. EXPORT_SYMBOL(iwl_activate_qos);
  234. void iwl_reset_qos(struct iwl_priv *priv)
  235. {
  236. u16 cw_min = 15;
  237. u16 cw_max = 1023;
  238. u8 aifs = 2;
  239. bool is_legacy = false;
  240. unsigned long flags;
  241. int i;
  242. spin_lock_irqsave(&priv->lock, flags);
  243. /* QoS always active in AP and ADHOC mode
  244. * In STA mode wait for association
  245. */
  246. if (priv->iw_mode == NL80211_IFTYPE_ADHOC ||
  247. priv->iw_mode == NL80211_IFTYPE_AP)
  248. priv->qos_data.qos_active = 1;
  249. else
  250. priv->qos_data.qos_active = 0;
  251. /* check for legacy mode */
  252. if ((priv->iw_mode == NL80211_IFTYPE_ADHOC &&
  253. (priv->active_rate & IWL_OFDM_RATES_MASK) == 0) ||
  254. (priv->iw_mode == NL80211_IFTYPE_STATION &&
  255. (priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK) == 0)) {
  256. cw_min = 31;
  257. is_legacy = 1;
  258. }
  259. if (priv->qos_data.qos_active)
  260. aifs = 3;
  261. priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min);
  262. priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max);
  263. priv->qos_data.def_qos_parm.ac[0].aifsn = aifs;
  264. priv->qos_data.def_qos_parm.ac[0].edca_txop = 0;
  265. priv->qos_data.def_qos_parm.ac[0].reserved1 = 0;
  266. if (priv->qos_data.qos_active) {
  267. i = 1;
  268. priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min);
  269. priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max);
  270. priv->qos_data.def_qos_parm.ac[i].aifsn = 7;
  271. priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
  272. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  273. i = 2;
  274. priv->qos_data.def_qos_parm.ac[i].cw_min =
  275. cpu_to_le16((cw_min + 1) / 2 - 1);
  276. priv->qos_data.def_qos_parm.ac[i].cw_max =
  277. cpu_to_le16(cw_max);
  278. priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
  279. if (is_legacy)
  280. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  281. cpu_to_le16(6016);
  282. else
  283. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  284. cpu_to_le16(3008);
  285. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  286. i = 3;
  287. priv->qos_data.def_qos_parm.ac[i].cw_min =
  288. cpu_to_le16((cw_min + 1) / 4 - 1);
  289. priv->qos_data.def_qos_parm.ac[i].cw_max =
  290. cpu_to_le16((cw_max + 1) / 2 - 1);
  291. priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
  292. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  293. if (is_legacy)
  294. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  295. cpu_to_le16(3264);
  296. else
  297. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  298. cpu_to_le16(1504);
  299. } else {
  300. for (i = 1; i < 4; i++) {
  301. priv->qos_data.def_qos_parm.ac[i].cw_min =
  302. cpu_to_le16(cw_min);
  303. priv->qos_data.def_qos_parm.ac[i].cw_max =
  304. cpu_to_le16(cw_max);
  305. priv->qos_data.def_qos_parm.ac[i].aifsn = aifs;
  306. priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
  307. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  308. }
  309. }
  310. IWL_DEBUG_QOS(priv, "set QoS to default \n");
  311. spin_unlock_irqrestore(&priv->lock, flags);
  312. }
  313. EXPORT_SYMBOL(iwl_reset_qos);
  314. #define MAX_BIT_RATE_40_MHZ 150 /* Mbps */
  315. #define MAX_BIT_RATE_20_MHZ 72 /* Mbps */
  316. static void iwlcore_init_ht_hw_capab(const struct iwl_priv *priv,
  317. struct ieee80211_sta_ht_cap *ht_info,
  318. enum ieee80211_band band)
  319. {
  320. u16 max_bit_rate = 0;
  321. u8 rx_chains_num = priv->hw_params.rx_chains_num;
  322. u8 tx_chains_num = priv->hw_params.tx_chains_num;
  323. ht_info->cap = 0;
  324. memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
  325. ht_info->ht_supported = true;
  326. ht_info->cap |= IEEE80211_HT_CAP_GRN_FLD;
  327. ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
  328. ht_info->cap |= (IEEE80211_HT_CAP_SM_PS &
  329. (WLAN_HT_CAP_SM_PS_DISABLED << 2));
  330. max_bit_rate = MAX_BIT_RATE_20_MHZ;
  331. if (priv->hw_params.fat_channel & BIT(band)) {
  332. ht_info->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
  333. ht_info->cap |= IEEE80211_HT_CAP_SGI_40;
  334. ht_info->mcs.rx_mask[4] = 0x01;
  335. max_bit_rate = MAX_BIT_RATE_40_MHZ;
  336. }
  337. if (priv->cfg->mod_params->amsdu_size_8K)
  338. ht_info->cap |= IEEE80211_HT_CAP_MAX_AMSDU;
  339. ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF;
  340. ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF;
  341. ht_info->mcs.rx_mask[0] = 0xFF;
  342. if (rx_chains_num >= 2)
  343. ht_info->mcs.rx_mask[1] = 0xFF;
  344. if (rx_chains_num >= 3)
  345. ht_info->mcs.rx_mask[2] = 0xFF;
  346. /* Highest supported Rx data rate */
  347. max_bit_rate *= rx_chains_num;
  348. WARN_ON(max_bit_rate & ~IEEE80211_HT_MCS_RX_HIGHEST_MASK);
  349. ht_info->mcs.rx_highest = cpu_to_le16(max_bit_rate);
  350. /* Tx MCS capabilities */
  351. ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
  352. if (tx_chains_num != rx_chains_num) {
  353. ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
  354. ht_info->mcs.tx_params |= ((tx_chains_num - 1) <<
  355. IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
  356. }
  357. }
  358. static void iwlcore_init_hw_rates(struct iwl_priv *priv,
  359. struct ieee80211_rate *rates)
  360. {
  361. int i;
  362. for (i = 0; i < IWL_RATE_COUNT; i++) {
  363. rates[i].bitrate = iwl_rates[i].ieee * 5;
  364. rates[i].hw_value = i; /* Rate scaling will work on indexes */
  365. rates[i].hw_value_short = i;
  366. rates[i].flags = 0;
  367. if ((i > IWL_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
  368. /*
  369. * If CCK != 1M then set short preamble rate flag.
  370. */
  371. rates[i].flags |=
  372. (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
  373. 0 : IEEE80211_RATE_SHORT_PREAMBLE;
  374. }
  375. }
  376. }
  377. /**
  378. * iwlcore_init_geos - Initialize mac80211's geo/channel info based from eeprom
  379. */
  380. int iwlcore_init_geos(struct iwl_priv *priv)
  381. {
  382. struct iwl_channel_info *ch;
  383. struct ieee80211_supported_band *sband;
  384. struct ieee80211_channel *channels;
  385. struct ieee80211_channel *geo_ch;
  386. struct ieee80211_rate *rates;
  387. int i = 0;
  388. if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
  389. priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
  390. IWL_DEBUG_INFO(priv, "Geography modes already initialized.\n");
  391. set_bit(STATUS_GEO_CONFIGURED, &priv->status);
  392. return 0;
  393. }
  394. channels = kzalloc(sizeof(struct ieee80211_channel) *
  395. priv->channel_count, GFP_KERNEL);
  396. if (!channels)
  397. return -ENOMEM;
  398. rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_RATE_COUNT + 1)),
  399. GFP_KERNEL);
  400. if (!rates) {
  401. kfree(channels);
  402. return -ENOMEM;
  403. }
  404. /* 5.2GHz channels start after the 2.4GHz channels */
  405. sband = &priv->bands[IEEE80211_BAND_5GHZ];
  406. sband->channels = &channels[ARRAY_SIZE(iwl_eeprom_band_1)];
  407. /* just OFDM */
  408. sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
  409. sband->n_bitrates = IWL_RATE_COUNT - IWL_FIRST_OFDM_RATE;
  410. if (priv->cfg->sku & IWL_SKU_N)
  411. iwlcore_init_ht_hw_capab(priv, &sband->ht_cap,
  412. IEEE80211_BAND_5GHZ);
  413. sband = &priv->bands[IEEE80211_BAND_2GHZ];
  414. sband->channels = channels;
  415. /* OFDM & CCK */
  416. sband->bitrates = rates;
  417. sband->n_bitrates = IWL_RATE_COUNT;
  418. if (priv->cfg->sku & IWL_SKU_N)
  419. iwlcore_init_ht_hw_capab(priv, &sband->ht_cap,
  420. IEEE80211_BAND_2GHZ);
  421. priv->ieee_channels = channels;
  422. priv->ieee_rates = rates;
  423. for (i = 0; i < priv->channel_count; i++) {
  424. ch = &priv->channel_info[i];
  425. /* FIXME: might be removed if scan is OK */
  426. if (!is_channel_valid(ch))
  427. continue;
  428. if (is_channel_a_band(ch))
  429. sband = &priv->bands[IEEE80211_BAND_5GHZ];
  430. else
  431. sband = &priv->bands[IEEE80211_BAND_2GHZ];
  432. geo_ch = &sband->channels[sband->n_channels++];
  433. geo_ch->center_freq =
  434. ieee80211_channel_to_frequency(ch->channel);
  435. geo_ch->max_power = ch->max_power_avg;
  436. geo_ch->max_antenna_gain = 0xff;
  437. geo_ch->hw_value = ch->channel;
  438. if (is_channel_valid(ch)) {
  439. if (!(ch->flags & EEPROM_CHANNEL_IBSS))
  440. geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
  441. if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
  442. geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
  443. if (ch->flags & EEPROM_CHANNEL_RADAR)
  444. geo_ch->flags |= IEEE80211_CHAN_RADAR;
  445. geo_ch->flags |= ch->fat_extension_channel;
  446. if (ch->max_power_avg > priv->tx_power_channel_lmt)
  447. priv->tx_power_channel_lmt = ch->max_power_avg;
  448. } else {
  449. geo_ch->flags |= IEEE80211_CHAN_DISABLED;
  450. }
  451. /* Save flags for reg domain usage */
  452. geo_ch->orig_flags = geo_ch->flags;
  453. IWL_DEBUG_INFO(priv, "Channel %d Freq=%d[%sGHz] %s flag=0x%X\n",
  454. ch->channel, geo_ch->center_freq,
  455. is_channel_a_band(ch) ? "5.2" : "2.4",
  456. geo_ch->flags & IEEE80211_CHAN_DISABLED ?
  457. "restricted" : "valid",
  458. geo_ch->flags);
  459. }
  460. if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
  461. priv->cfg->sku & IWL_SKU_A) {
  462. IWL_INFO(priv, "Incorrectly detected BG card as ABG. "
  463. "Please send your PCI ID 0x%04X:0x%04X to maintainer.\n",
  464. priv->pci_dev->device,
  465. priv->pci_dev->subsystem_device);
  466. priv->cfg->sku &= ~IWL_SKU_A;
  467. }
  468. IWL_INFO(priv, "Tunable channels: %d 802.11bg, %d 802.11a channels\n",
  469. priv->bands[IEEE80211_BAND_2GHZ].n_channels,
  470. priv->bands[IEEE80211_BAND_5GHZ].n_channels);
  471. set_bit(STATUS_GEO_CONFIGURED, &priv->status);
  472. return 0;
  473. }
  474. EXPORT_SYMBOL(iwlcore_init_geos);
  475. /*
  476. * iwlcore_free_geos - undo allocations in iwlcore_init_geos
  477. */
  478. void iwlcore_free_geos(struct iwl_priv *priv)
  479. {
  480. kfree(priv->ieee_channels);
  481. kfree(priv->ieee_rates);
  482. clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
  483. }
  484. EXPORT_SYMBOL(iwlcore_free_geos);
  485. static bool is_single_rx_stream(struct iwl_priv *priv)
  486. {
  487. return !priv->current_ht_config.is_ht ||
  488. ((priv->current_ht_config.mcs.rx_mask[1] == 0) &&
  489. (priv->current_ht_config.mcs.rx_mask[2] == 0));
  490. }
  491. static u8 iwl_is_channel_extension(struct iwl_priv *priv,
  492. enum ieee80211_band band,
  493. u16 channel, u8 extension_chan_offset)
  494. {
  495. const struct iwl_channel_info *ch_info;
  496. ch_info = iwl_get_channel_info(priv, band, channel);
  497. if (!is_channel_valid(ch_info))
  498. return 0;
  499. if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE)
  500. return !(ch_info->fat_extension_channel &
  501. IEEE80211_CHAN_NO_FAT_ABOVE);
  502. else if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW)
  503. return !(ch_info->fat_extension_channel &
  504. IEEE80211_CHAN_NO_FAT_BELOW);
  505. return 0;
  506. }
  507. u8 iwl_is_fat_tx_allowed(struct iwl_priv *priv,
  508. struct ieee80211_sta_ht_cap *sta_ht_inf)
  509. {
  510. struct iwl_ht_info *iwl_ht_conf = &priv->current_ht_config;
  511. if ((!iwl_ht_conf->is_ht) ||
  512. (iwl_ht_conf->supported_chan_width != IWL_CHANNEL_WIDTH_40MHZ) ||
  513. (iwl_ht_conf->extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_NONE))
  514. return 0;
  515. if (sta_ht_inf) {
  516. if ((!sta_ht_inf->ht_supported) ||
  517. (!(sta_ht_inf->cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)))
  518. return 0;
  519. }
  520. return iwl_is_channel_extension(priv, priv->band,
  521. le16_to_cpu(priv->staging_rxon.channel),
  522. iwl_ht_conf->extension_chan_offset);
  523. }
  524. EXPORT_SYMBOL(iwl_is_fat_tx_allowed);
  525. void iwl_set_rxon_hwcrypto(struct iwl_priv *priv, int hw_decrypt)
  526. {
  527. struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
  528. if (hw_decrypt)
  529. rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
  530. else
  531. rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
  532. }
  533. EXPORT_SYMBOL(iwl_set_rxon_hwcrypto);
  534. /**
  535. * iwl_check_rxon_cmd - validate RXON structure is valid
  536. *
  537. * NOTE: This is really only useful during development and can eventually
  538. * be #ifdef'd out once the driver is stable and folks aren't actively
  539. * making changes
  540. */
  541. int iwl_check_rxon_cmd(struct iwl_priv *priv)
  542. {
  543. int error = 0;
  544. int counter = 1;
  545. struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
  546. if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
  547. error |= le32_to_cpu(rxon->flags &
  548. (RXON_FLG_TGJ_NARROW_BAND_MSK |
  549. RXON_FLG_RADAR_DETECT_MSK));
  550. if (error)
  551. IWL_WARN(priv, "check 24G fields %d | %d\n",
  552. counter++, error);
  553. } else {
  554. error |= (rxon->flags & RXON_FLG_SHORT_SLOT_MSK) ?
  555. 0 : le32_to_cpu(RXON_FLG_SHORT_SLOT_MSK);
  556. if (error)
  557. IWL_WARN(priv, "check 52 fields %d | %d\n",
  558. counter++, error);
  559. error |= le32_to_cpu(rxon->flags & RXON_FLG_CCK_MSK);
  560. if (error)
  561. IWL_WARN(priv, "check 52 CCK %d | %d\n",
  562. counter++, error);
  563. }
  564. error |= (rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1;
  565. if (error)
  566. IWL_WARN(priv, "check mac addr %d | %d\n", counter++, error);
  567. /* make sure basic rates 6Mbps and 1Mbps are supported */
  568. error |= (((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0) &&
  569. ((rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0));
  570. if (error)
  571. IWL_WARN(priv, "check basic rate %d | %d\n", counter++, error);
  572. error |= (le16_to_cpu(rxon->assoc_id) > 2007);
  573. if (error)
  574. IWL_WARN(priv, "check assoc id %d | %d\n", counter++, error);
  575. error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK))
  576. == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK));
  577. if (error)
  578. IWL_WARN(priv, "check CCK and short slot %d | %d\n",
  579. counter++, error);
  580. error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK))
  581. == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK));
  582. if (error)
  583. IWL_WARN(priv, "check CCK & auto detect %d | %d\n",
  584. counter++, error);
  585. error |= ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK |
  586. RXON_FLG_TGG_PROTECT_MSK)) == RXON_FLG_TGG_PROTECT_MSK);
  587. if (error)
  588. IWL_WARN(priv, "check TGG and auto detect %d | %d\n",
  589. counter++, error);
  590. if (error)
  591. IWL_WARN(priv, "Tuning to channel %d\n",
  592. le16_to_cpu(rxon->channel));
  593. if (error) {
  594. IWL_ERR(priv, "Not a valid iwl_rxon_assoc_cmd field values\n");
  595. return -1;
  596. }
  597. return 0;
  598. }
  599. EXPORT_SYMBOL(iwl_check_rxon_cmd);
  600. /**
  601. * iwl_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
  602. * @priv: staging_rxon is compared to active_rxon
  603. *
  604. * If the RXON structure is changing enough to require a new tune,
  605. * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
  606. * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
  607. */
  608. int iwl_full_rxon_required(struct iwl_priv *priv)
  609. {
  610. /* These items are only settable from the full RXON command */
  611. if (!(iwl_is_associated(priv)) ||
  612. compare_ether_addr(priv->staging_rxon.bssid_addr,
  613. priv->active_rxon.bssid_addr) ||
  614. compare_ether_addr(priv->staging_rxon.node_addr,
  615. priv->active_rxon.node_addr) ||
  616. compare_ether_addr(priv->staging_rxon.wlap_bssid_addr,
  617. priv->active_rxon.wlap_bssid_addr) ||
  618. (priv->staging_rxon.dev_type != priv->active_rxon.dev_type) ||
  619. (priv->staging_rxon.channel != priv->active_rxon.channel) ||
  620. (priv->staging_rxon.air_propagation !=
  621. priv->active_rxon.air_propagation) ||
  622. (priv->staging_rxon.ofdm_ht_single_stream_basic_rates !=
  623. priv->active_rxon.ofdm_ht_single_stream_basic_rates) ||
  624. (priv->staging_rxon.ofdm_ht_dual_stream_basic_rates !=
  625. priv->active_rxon.ofdm_ht_dual_stream_basic_rates) ||
  626. (priv->staging_rxon.assoc_id != priv->active_rxon.assoc_id))
  627. return 1;
  628. /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
  629. * be updated with the RXON_ASSOC command -- however only some
  630. * flag transitions are allowed using RXON_ASSOC */
  631. /* Check if we are not switching bands */
  632. if ((priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) !=
  633. (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK))
  634. return 1;
  635. /* Check if we are switching association toggle */
  636. if ((priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) !=
  637. (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK))
  638. return 1;
  639. return 0;
  640. }
  641. EXPORT_SYMBOL(iwl_full_rxon_required);
  642. u8 iwl_rate_get_lowest_plcp(struct iwl_priv *priv)
  643. {
  644. int i;
  645. int rate_mask;
  646. /* Set rate mask*/
  647. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)
  648. rate_mask = priv->active_rate_basic & IWL_CCK_RATES_MASK;
  649. else
  650. rate_mask = priv->active_rate_basic & IWL_OFDM_RATES_MASK;
  651. /* Find lowest valid rate */
  652. for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID;
  653. i = iwl_rates[i].next_ieee) {
  654. if (rate_mask & (1 << i))
  655. return iwl_rates[i].plcp;
  656. }
  657. /* No valid rate was found. Assign the lowest one */
  658. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)
  659. return IWL_RATE_1M_PLCP;
  660. else
  661. return IWL_RATE_6M_PLCP;
  662. }
  663. EXPORT_SYMBOL(iwl_rate_get_lowest_plcp);
  664. void iwl_set_rxon_ht(struct iwl_priv *priv, struct iwl_ht_info *ht_info)
  665. {
  666. struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
  667. u32 val;
  668. if (!ht_info->is_ht) {
  669. rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED_MSK |
  670. RXON_FLG_CHANNEL_MODE_PURE_40_MSK |
  671. RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK |
  672. RXON_FLG_FAT_PROT_MSK |
  673. RXON_FLG_HT_PROT_MSK);
  674. return;
  675. }
  676. /* Set up channel bandwidth: 20 MHz only, or 20/40 mixed if fat ok */
  677. if (iwl_is_fat_tx_allowed(priv, NULL))
  678. rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED_MSK;
  679. else
  680. rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED_MSK |
  681. RXON_FLG_CHANNEL_MODE_PURE_40_MSK);
  682. /* Note: control channel is opposite of extension channel */
  683. switch (ht_info->extension_chan_offset) {
  684. case IEEE80211_HT_PARAM_CHA_SEC_ABOVE:
  685. rxon->flags &= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
  686. break;
  687. case IEEE80211_HT_PARAM_CHA_SEC_BELOW:
  688. rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
  689. break;
  690. case IEEE80211_HT_PARAM_CHA_SEC_NONE:
  691. default:
  692. rxon->flags &= ~RXON_FLG_CHANNEL_MODE_MIXED_MSK;
  693. break;
  694. }
  695. val = ht_info->ht_protection;
  696. rxon->flags |= cpu_to_le32(val << RXON_FLG_HT_OPERATING_MODE_POS);
  697. iwl_set_rxon_chain(priv);
  698. IWL_DEBUG_ASSOC(priv, "supported HT rate 0x%X 0x%X 0x%X "
  699. "rxon flags 0x%X operation mode :0x%X "
  700. "extension channel offset 0x%x\n",
  701. ht_info->mcs.rx_mask[0],
  702. ht_info->mcs.rx_mask[1],
  703. ht_info->mcs.rx_mask[2],
  704. le32_to_cpu(rxon->flags), ht_info->ht_protection,
  705. ht_info->extension_chan_offset);
  706. return;
  707. }
  708. EXPORT_SYMBOL(iwl_set_rxon_ht);
  709. #define IWL_NUM_RX_CHAINS_MULTIPLE 3
  710. #define IWL_NUM_RX_CHAINS_SINGLE 2
  711. #define IWL_NUM_IDLE_CHAINS_DUAL 2
  712. #define IWL_NUM_IDLE_CHAINS_SINGLE 1
  713. /* Determine how many receiver/antenna chains to use.
  714. * More provides better reception via diversity. Fewer saves power.
  715. * MIMO (dual stream) requires at least 2, but works better with 3.
  716. * This does not determine *which* chains to use, just how many.
  717. */
  718. static int iwl_get_active_rx_chain_count(struct iwl_priv *priv)
  719. {
  720. bool is_single = is_single_rx_stream(priv);
  721. bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
  722. /* # of Rx chains to use when expecting MIMO. */
  723. if (is_single || (!is_cam && (priv->current_ht_config.sm_ps ==
  724. WLAN_HT_CAP_SM_PS_STATIC)))
  725. return IWL_NUM_RX_CHAINS_SINGLE;
  726. else
  727. return IWL_NUM_RX_CHAINS_MULTIPLE;
  728. }
  729. static int iwl_get_idle_rx_chain_count(struct iwl_priv *priv, int active_cnt)
  730. {
  731. int idle_cnt;
  732. bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
  733. /* # Rx chains when idling and maybe trying to save power */
  734. switch (priv->current_ht_config.sm_ps) {
  735. case WLAN_HT_CAP_SM_PS_STATIC:
  736. case WLAN_HT_CAP_SM_PS_DYNAMIC:
  737. idle_cnt = (is_cam) ? IWL_NUM_IDLE_CHAINS_DUAL :
  738. IWL_NUM_IDLE_CHAINS_SINGLE;
  739. break;
  740. case WLAN_HT_CAP_SM_PS_DISABLED:
  741. idle_cnt = (is_cam) ? active_cnt : IWL_NUM_IDLE_CHAINS_SINGLE;
  742. break;
  743. case WLAN_HT_CAP_SM_PS_INVALID:
  744. default:
  745. IWL_ERR(priv, "invalid mimo ps mode %d\n",
  746. priv->current_ht_config.sm_ps);
  747. WARN_ON(1);
  748. idle_cnt = -1;
  749. break;
  750. }
  751. return idle_cnt;
  752. }
  753. /* up to 4 chains */
  754. static u8 iwl_count_chain_bitmap(u32 chain_bitmap)
  755. {
  756. u8 res;
  757. res = (chain_bitmap & BIT(0)) >> 0;
  758. res += (chain_bitmap & BIT(1)) >> 1;
  759. res += (chain_bitmap & BIT(2)) >> 2;
  760. res += (chain_bitmap & BIT(4)) >> 4;
  761. return res;
  762. }
  763. /**
  764. * iwl_is_monitor_mode - Determine if interface in monitor mode
  765. *
  766. * priv->iw_mode is set in add_interface, but add_interface is
  767. * never called for monitor mode. The only way mac80211 informs us about
  768. * monitor mode is through configuring filters (call to configure_filter).
  769. */
  770. static bool iwl_is_monitor_mode(struct iwl_priv *priv)
  771. {
  772. return !!(priv->staging_rxon.filter_flags & RXON_FILTER_PROMISC_MSK);
  773. }
  774. /**
  775. * iwl_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
  776. *
  777. * Selects how many and which Rx receivers/antennas/chains to use.
  778. * This should not be used for scan command ... it puts data in wrong place.
  779. */
  780. void iwl_set_rxon_chain(struct iwl_priv *priv)
  781. {
  782. bool is_single = is_single_rx_stream(priv);
  783. bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
  784. u8 idle_rx_cnt, active_rx_cnt, valid_rx_cnt;
  785. u32 active_chains;
  786. u16 rx_chain;
  787. /* Tell uCode which antennas are actually connected.
  788. * Before first association, we assume all antennas are connected.
  789. * Just after first association, iwl_chain_noise_calibration()
  790. * checks which antennas actually *are* connected. */
  791. if (priv->chain_noise_data.active_chains)
  792. active_chains = priv->chain_noise_data.active_chains;
  793. else
  794. active_chains = priv->hw_params.valid_rx_ant;
  795. rx_chain = active_chains << RXON_RX_CHAIN_VALID_POS;
  796. /* How many receivers should we use? */
  797. active_rx_cnt = iwl_get_active_rx_chain_count(priv);
  798. idle_rx_cnt = iwl_get_idle_rx_chain_count(priv, active_rx_cnt);
  799. /* correct rx chain count according hw settings
  800. * and chain noise calibration
  801. */
  802. valid_rx_cnt = iwl_count_chain_bitmap(active_chains);
  803. if (valid_rx_cnt < active_rx_cnt)
  804. active_rx_cnt = valid_rx_cnt;
  805. if (valid_rx_cnt < idle_rx_cnt)
  806. idle_rx_cnt = valid_rx_cnt;
  807. rx_chain |= active_rx_cnt << RXON_RX_CHAIN_MIMO_CNT_POS;
  808. rx_chain |= idle_rx_cnt << RXON_RX_CHAIN_CNT_POS;
  809. /* copied from 'iwl_bg_request_scan()' */
  810. /* Force use of chains B and C (0x6) for Rx for 4965
  811. * Avoid A (0x1) because of its off-channel reception on A-band.
  812. * MIMO is not used here, but value is required */
  813. if (iwl_is_monitor_mode(priv) &&
  814. !(priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) &&
  815. ((priv->hw_rev & CSR_HW_REV_TYPE_MSK) == CSR_HW_REV_TYPE_4965)) {
  816. rx_chain = 0x07 << RXON_RX_CHAIN_VALID_POS;
  817. rx_chain |= 0x06 << RXON_RX_CHAIN_FORCE_SEL_POS;
  818. rx_chain |= 0x07 << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS;
  819. rx_chain |= 0x01 << RXON_RX_CHAIN_DRIVER_FORCE_POS;
  820. }
  821. priv->staging_rxon.rx_chain = cpu_to_le16(rx_chain);
  822. if (!is_single && (active_rx_cnt >= IWL_NUM_RX_CHAINS_SINGLE) && is_cam)
  823. priv->staging_rxon.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
  824. else
  825. priv->staging_rxon.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
  826. IWL_DEBUG_ASSOC(priv, "rx_chain=0x%X active=%d idle=%d\n",
  827. priv->staging_rxon.rx_chain,
  828. active_rx_cnt, idle_rx_cnt);
  829. WARN_ON(active_rx_cnt == 0 || idle_rx_cnt == 0 ||
  830. active_rx_cnt < idle_rx_cnt);
  831. }
  832. EXPORT_SYMBOL(iwl_set_rxon_chain);
  833. /**
  834. * iwl_set_rxon_channel - Set the phymode and channel values in staging RXON
  835. * @phymode: MODE_IEEE80211A sets to 5.2GHz; all else set to 2.4GHz
  836. * @channel: Any channel valid for the requested phymode
  837. * In addition to setting the staging RXON, priv->phymode is also set.
  838. *
  839. * NOTE: Does not commit to the hardware; it sets appropriate bit fields
  840. * in the staging RXON flag structure based on the phymode
  841. */
  842. int iwl_set_rxon_channel(struct iwl_priv *priv, struct ieee80211_channel *ch)
  843. {
  844. enum ieee80211_band band = ch->band;
  845. u16 channel = ieee80211_frequency_to_channel(ch->center_freq);
  846. if (!iwl_get_channel_info(priv, band, channel)) {
  847. IWL_DEBUG_INFO(priv, "Could not set channel to %d [%d]\n",
  848. channel, band);
  849. return -EINVAL;
  850. }
  851. if ((le16_to_cpu(priv->staging_rxon.channel) == channel) &&
  852. (priv->band == band))
  853. return 0;
  854. priv->staging_rxon.channel = cpu_to_le16(channel);
  855. if (band == IEEE80211_BAND_5GHZ)
  856. priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
  857. else
  858. priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
  859. priv->band = band;
  860. IWL_DEBUG_INFO(priv, "Staging channel set to %d [%d]\n", channel, band);
  861. return 0;
  862. }
  863. EXPORT_SYMBOL(iwl_set_rxon_channel);
  864. void iwl_set_flags_for_band(struct iwl_priv *priv,
  865. enum ieee80211_band band)
  866. {
  867. if (band == IEEE80211_BAND_5GHZ) {
  868. priv->staging_rxon.flags &=
  869. ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK
  870. | RXON_FLG_CCK_MSK);
  871. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  872. } else {
  873. /* Copied from iwl_post_associate() */
  874. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  875. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  876. else
  877. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  878. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  879. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  880. priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
  881. priv->staging_rxon.flags |= RXON_FLG_AUTO_DETECT_MSK;
  882. priv->staging_rxon.flags &= ~RXON_FLG_CCK_MSK;
  883. }
  884. }
  885. EXPORT_SYMBOL(iwl_set_flags_for_band);
  886. /*
  887. * initialize rxon structure with default values from eeprom
  888. */
  889. void iwl_connection_init_rx_config(struct iwl_priv *priv, int mode)
  890. {
  891. const struct iwl_channel_info *ch_info;
  892. memset(&priv->staging_rxon, 0, sizeof(priv->staging_rxon));
  893. switch (mode) {
  894. case NL80211_IFTYPE_AP:
  895. priv->staging_rxon.dev_type = RXON_DEV_TYPE_AP;
  896. break;
  897. case NL80211_IFTYPE_STATION:
  898. priv->staging_rxon.dev_type = RXON_DEV_TYPE_ESS;
  899. priv->staging_rxon.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
  900. break;
  901. case NL80211_IFTYPE_ADHOC:
  902. priv->staging_rxon.dev_type = RXON_DEV_TYPE_IBSS;
  903. priv->staging_rxon.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
  904. priv->staging_rxon.filter_flags = RXON_FILTER_BCON_AWARE_MSK |
  905. RXON_FILTER_ACCEPT_GRP_MSK;
  906. break;
  907. case NL80211_IFTYPE_MONITOR:
  908. priv->staging_rxon.dev_type = RXON_DEV_TYPE_SNIFFER;
  909. priv->staging_rxon.filter_flags = RXON_FILTER_PROMISC_MSK |
  910. RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_ACCEPT_GRP_MSK;
  911. break;
  912. default:
  913. IWL_ERR(priv, "Unsupported interface type %d\n", mode);
  914. break;
  915. }
  916. #if 0
  917. /* TODO: Figure out when short_preamble would be set and cache from
  918. * that */
  919. if (!hw_to_local(priv->hw)->short_preamble)
  920. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  921. else
  922. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  923. #endif
  924. ch_info = iwl_get_channel_info(priv, priv->band,
  925. le16_to_cpu(priv->active_rxon.channel));
  926. if (!ch_info)
  927. ch_info = &priv->channel_info[0];
  928. /*
  929. * in some case A channels are all non IBSS
  930. * in this case force B/G channel
  931. */
  932. if ((priv->iw_mode == NL80211_IFTYPE_ADHOC) &&
  933. !(is_channel_ibss(ch_info)))
  934. ch_info = &priv->channel_info[0];
  935. priv->staging_rxon.channel = cpu_to_le16(ch_info->channel);
  936. priv->band = ch_info->band;
  937. iwl_set_flags_for_band(priv, priv->band);
  938. priv->staging_rxon.ofdm_basic_rates =
  939. (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
  940. priv->staging_rxon.cck_basic_rates =
  941. (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
  942. priv->staging_rxon.flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED_MSK |
  943. RXON_FLG_CHANNEL_MODE_PURE_40_MSK);
  944. memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  945. memcpy(priv->staging_rxon.wlap_bssid_addr, priv->mac_addr, ETH_ALEN);
  946. priv->staging_rxon.ofdm_ht_single_stream_basic_rates = 0xff;
  947. priv->staging_rxon.ofdm_ht_dual_stream_basic_rates = 0xff;
  948. }
  949. EXPORT_SYMBOL(iwl_connection_init_rx_config);
  950. void iwl_set_rate(struct iwl_priv *priv)
  951. {
  952. const struct ieee80211_supported_band *hw = NULL;
  953. struct ieee80211_rate *rate;
  954. int i;
  955. hw = iwl_get_hw_mode(priv, priv->band);
  956. if (!hw) {
  957. IWL_ERR(priv, "Failed to set rate: unable to get hw mode\n");
  958. return;
  959. }
  960. priv->active_rate = 0;
  961. priv->active_rate_basic = 0;
  962. for (i = 0; i < hw->n_bitrates; i++) {
  963. rate = &(hw->bitrates[i]);
  964. if (rate->hw_value < IWL_RATE_COUNT)
  965. priv->active_rate |= (1 << rate->hw_value);
  966. }
  967. IWL_DEBUG_RATE(priv, "Set active_rate = %0x, active_rate_basic = %0x\n",
  968. priv->active_rate, priv->active_rate_basic);
  969. /*
  970. * If a basic rate is configured, then use it (adding IWL_RATE_1M_MASK)
  971. * otherwise set it to the default of all CCK rates and 6, 12, 24 for
  972. * OFDM
  973. */
  974. if (priv->active_rate_basic & IWL_CCK_BASIC_RATES_MASK)
  975. priv->staging_rxon.cck_basic_rates =
  976. ((priv->active_rate_basic &
  977. IWL_CCK_RATES_MASK) >> IWL_FIRST_CCK_RATE) & 0xF;
  978. else
  979. priv->staging_rxon.cck_basic_rates =
  980. (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
  981. if (priv->active_rate_basic & IWL_OFDM_BASIC_RATES_MASK)
  982. priv->staging_rxon.ofdm_basic_rates =
  983. ((priv->active_rate_basic &
  984. (IWL_OFDM_BASIC_RATES_MASK | IWL_RATE_6M_MASK)) >>
  985. IWL_FIRST_OFDM_RATE) & 0xFF;
  986. else
  987. priv->staging_rxon.ofdm_basic_rates =
  988. (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
  989. }
  990. EXPORT_SYMBOL(iwl_set_rate);
  991. void iwl_rx_csa(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
  992. {
  993. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  994. struct iwl_rxon_cmd *rxon = (void *)&priv->active_rxon;
  995. struct iwl_csa_notification *csa = &(pkt->u.csa_notif);
  996. IWL_DEBUG_11H(priv, "CSA notif: channel %d, status %d\n",
  997. le16_to_cpu(csa->channel), le32_to_cpu(csa->status));
  998. rxon->channel = csa->channel;
  999. priv->staging_rxon.channel = csa->channel;
  1000. }
  1001. EXPORT_SYMBOL(iwl_rx_csa);
  1002. #ifdef CONFIG_IWLWIFI_DEBUG
  1003. static void iwl_print_rx_config_cmd(struct iwl_priv *priv)
  1004. {
  1005. struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
  1006. IWL_DEBUG_RADIO(priv, "RX CONFIG:\n");
  1007. iwl_print_hex_dump(priv, IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
  1008. IWL_DEBUG_RADIO(priv, "u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
  1009. IWL_DEBUG_RADIO(priv, "u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
  1010. IWL_DEBUG_RADIO(priv, "u32 filter_flags: 0x%08x\n",
  1011. le32_to_cpu(rxon->filter_flags));
  1012. IWL_DEBUG_RADIO(priv, "u8 dev_type: 0x%x\n", rxon->dev_type);
  1013. IWL_DEBUG_RADIO(priv, "u8 ofdm_basic_rates: 0x%02x\n",
  1014. rxon->ofdm_basic_rates);
  1015. IWL_DEBUG_RADIO(priv, "u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
  1016. IWL_DEBUG_RADIO(priv, "u8[6] node_addr: %pM\n", rxon->node_addr);
  1017. IWL_DEBUG_RADIO(priv, "u8[6] bssid_addr: %pM\n", rxon->bssid_addr);
  1018. IWL_DEBUG_RADIO(priv, "u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
  1019. }
  1020. #endif
  1021. /**
  1022. * iwl_irq_handle_error - called for HW or SW error interrupt from card
  1023. */
  1024. void iwl_irq_handle_error(struct iwl_priv *priv)
  1025. {
  1026. /* Set the FW error flag -- cleared on iwl_down */
  1027. set_bit(STATUS_FW_ERROR, &priv->status);
  1028. /* Cancel currently queued command. */
  1029. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  1030. #ifdef CONFIG_IWLWIFI_DEBUG
  1031. if (priv->debug_level & IWL_DL_FW_ERRORS) {
  1032. iwl_dump_nic_error_log(priv);
  1033. iwl_dump_nic_event_log(priv);
  1034. iwl_print_rx_config_cmd(priv);
  1035. }
  1036. #endif
  1037. wake_up_interruptible(&priv->wait_command_queue);
  1038. /* Keep the restart process from trying to send host
  1039. * commands by clearing the INIT status bit */
  1040. clear_bit(STATUS_READY, &priv->status);
  1041. if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  1042. IWL_DEBUG(priv, IWL_DL_FW_ERRORS,
  1043. "Restarting adapter due to uCode error.\n");
  1044. if (iwl_is_associated(priv)) {
  1045. memcpy(&priv->recovery_rxon, &priv->active_rxon,
  1046. sizeof(priv->recovery_rxon));
  1047. priv->error_recovering = 1;
  1048. }
  1049. if (priv->cfg->mod_params->restart_fw)
  1050. queue_work(priv->workqueue, &priv->restart);
  1051. }
  1052. }
  1053. EXPORT_SYMBOL(iwl_irq_handle_error);
  1054. void iwl_configure_filter(struct ieee80211_hw *hw,
  1055. unsigned int changed_flags,
  1056. unsigned int *total_flags,
  1057. int mc_count, struct dev_addr_list *mc_list)
  1058. {
  1059. struct iwl_priv *priv = hw->priv;
  1060. __le32 *filter_flags = &priv->staging_rxon.filter_flags;
  1061. IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n",
  1062. changed_flags, *total_flags);
  1063. if (changed_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS)) {
  1064. if (*total_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS))
  1065. *filter_flags |= RXON_FILTER_PROMISC_MSK;
  1066. else
  1067. *filter_flags &= ~RXON_FILTER_PROMISC_MSK;
  1068. }
  1069. if (changed_flags & FIF_ALLMULTI) {
  1070. if (*total_flags & FIF_ALLMULTI)
  1071. *filter_flags |= RXON_FILTER_ACCEPT_GRP_MSK;
  1072. else
  1073. *filter_flags &= ~RXON_FILTER_ACCEPT_GRP_MSK;
  1074. }
  1075. if (changed_flags & FIF_CONTROL) {
  1076. if (*total_flags & FIF_CONTROL)
  1077. *filter_flags |= RXON_FILTER_CTL2HOST_MSK;
  1078. else
  1079. *filter_flags &= ~RXON_FILTER_CTL2HOST_MSK;
  1080. }
  1081. if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
  1082. if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
  1083. *filter_flags |= RXON_FILTER_BCON_AWARE_MSK;
  1084. else
  1085. *filter_flags &= ~RXON_FILTER_BCON_AWARE_MSK;
  1086. }
  1087. /* We avoid iwl_commit_rxon here to commit the new filter flags
  1088. * since mac80211 will call ieee80211_hw_config immediately.
  1089. * (mc_list is not supported at this time). Otherwise, we need to
  1090. * queue a background iwl_commit_rxon work.
  1091. */
  1092. *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
  1093. FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
  1094. }
  1095. EXPORT_SYMBOL(iwl_configure_filter);
  1096. int iwl_setup_mac(struct iwl_priv *priv)
  1097. {
  1098. int ret;
  1099. struct ieee80211_hw *hw = priv->hw;
  1100. hw->rate_control_algorithm = "iwl-agn-rs";
  1101. /* Tell mac80211 our characteristics */
  1102. hw->flags = IEEE80211_HW_SIGNAL_DBM |
  1103. IEEE80211_HW_NOISE_DBM |
  1104. IEEE80211_HW_AMPDU_AGGREGATION |
  1105. IEEE80211_HW_SUPPORTS_PS;
  1106. hw->wiphy->interface_modes =
  1107. BIT(NL80211_IFTYPE_STATION) |
  1108. BIT(NL80211_IFTYPE_ADHOC);
  1109. hw->wiphy->custom_regulatory = true;
  1110. hw->wiphy->max_scan_ssids = 1;
  1111. /* Default value; 4 EDCA QOS priorities */
  1112. hw->queues = 4;
  1113. /* queues to support 11n aggregation */
  1114. if (priv->cfg->sku & IWL_SKU_N)
  1115. hw->ampdu_queues = priv->cfg->mod_params->num_of_ampdu_queues;
  1116. hw->conf.beacon_int = 100;
  1117. hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
  1118. if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
  1119. priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
  1120. &priv->bands[IEEE80211_BAND_2GHZ];
  1121. if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
  1122. priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
  1123. &priv->bands[IEEE80211_BAND_5GHZ];
  1124. ret = ieee80211_register_hw(priv->hw);
  1125. if (ret) {
  1126. IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
  1127. return ret;
  1128. }
  1129. priv->mac80211_registered = 1;
  1130. return 0;
  1131. }
  1132. EXPORT_SYMBOL(iwl_setup_mac);
  1133. int iwl_set_hw_params(struct iwl_priv *priv)
  1134. {
  1135. priv->hw_params.sw_crypto = priv->cfg->mod_params->sw_crypto;
  1136. priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
  1137. priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
  1138. if (priv->cfg->mod_params->amsdu_size_8K)
  1139. priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_8K;
  1140. else
  1141. priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_4K;
  1142. priv->hw_params.max_pkt_size = priv->hw_params.rx_buf_size - 256;
  1143. if (priv->cfg->mod_params->disable_11n)
  1144. priv->cfg->sku &= ~IWL_SKU_N;
  1145. /* Device-specific setup */
  1146. return priv->cfg->ops->lib->set_hw_params(priv);
  1147. }
  1148. EXPORT_SYMBOL(iwl_set_hw_params);
  1149. int iwl_init_drv(struct iwl_priv *priv)
  1150. {
  1151. int ret;
  1152. priv->ibss_beacon = NULL;
  1153. spin_lock_init(&priv->lock);
  1154. spin_lock_init(&priv->power_data.lock);
  1155. spin_lock_init(&priv->sta_lock);
  1156. spin_lock_init(&priv->hcmd_lock);
  1157. INIT_LIST_HEAD(&priv->free_frames);
  1158. mutex_init(&priv->mutex);
  1159. /* Clear the driver's (not device's) station table */
  1160. iwl_clear_stations_table(priv);
  1161. priv->data_retry_limit = -1;
  1162. priv->ieee_channels = NULL;
  1163. priv->ieee_rates = NULL;
  1164. priv->band = IEEE80211_BAND_2GHZ;
  1165. priv->iw_mode = NL80211_IFTYPE_STATION;
  1166. priv->current_ht_config.sm_ps = WLAN_HT_CAP_SM_PS_DISABLED;
  1167. /* Choose which receivers/antennas to use */
  1168. iwl_set_rxon_chain(priv);
  1169. iwl_init_scan_params(priv);
  1170. iwl_reset_qos(priv);
  1171. priv->qos_data.qos_active = 0;
  1172. priv->qos_data.qos_cap.val = 0;
  1173. priv->rates_mask = IWL_RATES_MASK;
  1174. /* If power management is turned on, default to CAM mode */
  1175. priv->power_mode = IWL_POWER_MODE_CAM;
  1176. priv->tx_power_user_lmt = IWL_TX_POWER_TARGET_POWER_MAX;
  1177. ret = iwl_init_channel_map(priv);
  1178. if (ret) {
  1179. IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
  1180. goto err;
  1181. }
  1182. ret = iwlcore_init_geos(priv);
  1183. if (ret) {
  1184. IWL_ERR(priv, "initializing geos failed: %d\n", ret);
  1185. goto err_free_channel_map;
  1186. }
  1187. iwlcore_init_hw_rates(priv, priv->ieee_rates);
  1188. return 0;
  1189. err_free_channel_map:
  1190. iwl_free_channel_map(priv);
  1191. err:
  1192. return ret;
  1193. }
  1194. EXPORT_SYMBOL(iwl_init_drv);
  1195. int iwl_set_tx_power(struct iwl_priv *priv, s8 tx_power, bool force)
  1196. {
  1197. int ret = 0;
  1198. if (tx_power < IWL_TX_POWER_TARGET_POWER_MIN) {
  1199. IWL_WARN(priv, "Requested user TXPOWER %d below lower limit %d.\n",
  1200. tx_power,
  1201. IWL_TX_POWER_TARGET_POWER_MIN);
  1202. return -EINVAL;
  1203. }
  1204. if (tx_power > IWL_TX_POWER_TARGET_POWER_MAX) {
  1205. IWL_WARN(priv, "Requested user TXPOWER %d above upper limit %d.\n",
  1206. tx_power,
  1207. IWL_TX_POWER_TARGET_POWER_MAX);
  1208. return -EINVAL;
  1209. }
  1210. if (priv->tx_power_user_lmt != tx_power)
  1211. force = true;
  1212. priv->tx_power_user_lmt = tx_power;
  1213. if (force && priv->cfg->ops->lib->send_tx_power)
  1214. ret = priv->cfg->ops->lib->send_tx_power(priv);
  1215. return ret;
  1216. }
  1217. EXPORT_SYMBOL(iwl_set_tx_power);
  1218. void iwl_uninit_drv(struct iwl_priv *priv)
  1219. {
  1220. iwl_calib_free_results(priv);
  1221. iwlcore_free_geos(priv);
  1222. iwl_free_channel_map(priv);
  1223. kfree(priv->scan);
  1224. }
  1225. EXPORT_SYMBOL(iwl_uninit_drv);
  1226. void iwl_disable_interrupts(struct iwl_priv *priv)
  1227. {
  1228. clear_bit(STATUS_INT_ENABLED, &priv->status);
  1229. /* disable interrupts from uCode/NIC to host */
  1230. iwl_write32(priv, CSR_INT_MASK, 0x00000000);
  1231. /* acknowledge/clear/reset any interrupts still pending
  1232. * from uCode or flow handler (Rx/Tx DMA) */
  1233. iwl_write32(priv, CSR_INT, 0xffffffff);
  1234. iwl_write32(priv, CSR_FH_INT_STATUS, 0xffffffff);
  1235. IWL_DEBUG_ISR(priv, "Disabled interrupts\n");
  1236. }
  1237. EXPORT_SYMBOL(iwl_disable_interrupts);
  1238. void iwl_enable_interrupts(struct iwl_priv *priv)
  1239. {
  1240. IWL_DEBUG_ISR(priv, "Enabling interrupts\n");
  1241. set_bit(STATUS_INT_ENABLED, &priv->status);
  1242. iwl_write32(priv, CSR_INT_MASK, CSR_INI_SET_MASK);
  1243. }
  1244. EXPORT_SYMBOL(iwl_enable_interrupts);
  1245. irqreturn_t iwl_isr(int irq, void *data)
  1246. {
  1247. struct iwl_priv *priv = data;
  1248. u32 inta, inta_mask;
  1249. u32 inta_fh;
  1250. if (!priv)
  1251. return IRQ_NONE;
  1252. spin_lock(&priv->lock);
  1253. /* Disable (but don't clear!) interrupts here to avoid
  1254. * back-to-back ISRs and sporadic interrupts from our NIC.
  1255. * If we have something to service, the tasklet will re-enable ints.
  1256. * If we *don't* have something, we'll re-enable before leaving here. */
  1257. inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */
  1258. iwl_write32(priv, CSR_INT_MASK, 0x00000000);
  1259. /* Discover which interrupts are active/pending */
  1260. inta = iwl_read32(priv, CSR_INT);
  1261. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  1262. /* Ignore interrupt if there's nothing in NIC to service.
  1263. * This may be due to IRQ shared with another device,
  1264. * or due to sporadic interrupts thrown from our NIC. */
  1265. if (!inta && !inta_fh) {
  1266. IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0, inta_fh == 0\n");
  1267. goto none;
  1268. }
  1269. if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
  1270. /* Hardware disappeared. It might have already raised
  1271. * an interrupt */
  1272. IWL_WARN(priv, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
  1273. goto unplugged;
  1274. }
  1275. IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  1276. inta, inta_mask, inta_fh);
  1277. inta &= ~CSR_INT_BIT_SCD;
  1278. /* iwl_irq_tasklet() will service interrupts and re-enable them */
  1279. if (likely(inta || inta_fh))
  1280. tasklet_schedule(&priv->irq_tasklet);
  1281. unplugged:
  1282. spin_unlock(&priv->lock);
  1283. return IRQ_HANDLED;
  1284. none:
  1285. /* re-enable interrupts here since we don't have anything to service. */
  1286. /* only Re-enable if diabled by irq */
  1287. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  1288. iwl_enable_interrupts(priv);
  1289. spin_unlock(&priv->lock);
  1290. return IRQ_NONE;
  1291. }
  1292. EXPORT_SYMBOL(iwl_isr);
  1293. int iwl_send_bt_config(struct iwl_priv *priv)
  1294. {
  1295. struct iwl_bt_cmd bt_cmd = {
  1296. .flags = 3,
  1297. .lead_time = 0xAA,
  1298. .max_kill = 1,
  1299. .kill_ack_mask = 0,
  1300. .kill_cts_mask = 0,
  1301. };
  1302. return iwl_send_cmd_pdu(priv, REPLY_BT_CONFIG,
  1303. sizeof(struct iwl_bt_cmd), &bt_cmd);
  1304. }
  1305. EXPORT_SYMBOL(iwl_send_bt_config);
  1306. int iwl_send_statistics_request(struct iwl_priv *priv, u8 flags)
  1307. {
  1308. u32 stat_flags = 0;
  1309. struct iwl_host_cmd cmd = {
  1310. .id = REPLY_STATISTICS_CMD,
  1311. .meta.flags = flags,
  1312. .len = sizeof(stat_flags),
  1313. .data = (u8 *) &stat_flags,
  1314. };
  1315. return iwl_send_cmd(priv, &cmd);
  1316. }
  1317. EXPORT_SYMBOL(iwl_send_statistics_request);
  1318. /**
  1319. * iwl_verify_inst_sparse - verify runtime uCode image in card vs. host,
  1320. * using sample data 100 bytes apart. If these sample points are good,
  1321. * it's a pretty good bet that everything between them is good, too.
  1322. */
  1323. static int iwlcore_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len)
  1324. {
  1325. u32 val;
  1326. int ret = 0;
  1327. u32 errcnt = 0;
  1328. u32 i;
  1329. IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
  1330. ret = iwl_grab_nic_access(priv);
  1331. if (ret)
  1332. return ret;
  1333. for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
  1334. /* read data comes through single port, auto-incr addr */
  1335. /* NOTE: Use the debugless read so we don't flood kernel log
  1336. * if IWL_DL_IO is set */
  1337. iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
  1338. i + IWL49_RTC_INST_LOWER_BOUND);
  1339. val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1340. if (val != le32_to_cpu(*image)) {
  1341. ret = -EIO;
  1342. errcnt++;
  1343. if (errcnt >= 3)
  1344. break;
  1345. }
  1346. }
  1347. iwl_release_nic_access(priv);
  1348. return ret;
  1349. }
  1350. /**
  1351. * iwlcore_verify_inst_full - verify runtime uCode image in card vs. host,
  1352. * looking at all data.
  1353. */
  1354. static int iwl_verify_inst_full(struct iwl_priv *priv, __le32 *image,
  1355. u32 len)
  1356. {
  1357. u32 val;
  1358. u32 save_len = len;
  1359. int ret = 0;
  1360. u32 errcnt;
  1361. IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
  1362. ret = iwl_grab_nic_access(priv);
  1363. if (ret)
  1364. return ret;
  1365. iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
  1366. IWL49_RTC_INST_LOWER_BOUND);
  1367. errcnt = 0;
  1368. for (; len > 0; len -= sizeof(u32), image++) {
  1369. /* read data comes through single port, auto-incr addr */
  1370. /* NOTE: Use the debugless read so we don't flood kernel log
  1371. * if IWL_DL_IO is set */
  1372. val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1373. if (val != le32_to_cpu(*image)) {
  1374. IWL_ERR(priv, "uCode INST section is invalid at "
  1375. "offset 0x%x, is 0x%x, s/b 0x%x\n",
  1376. save_len - len, val, le32_to_cpu(*image));
  1377. ret = -EIO;
  1378. errcnt++;
  1379. if (errcnt >= 20)
  1380. break;
  1381. }
  1382. }
  1383. iwl_release_nic_access(priv);
  1384. if (!errcnt)
  1385. IWL_DEBUG_INFO(priv,
  1386. "ucode image in INSTRUCTION memory is good\n");
  1387. return ret;
  1388. }
  1389. /**
  1390. * iwl_verify_ucode - determine which instruction image is in SRAM,
  1391. * and verify its contents
  1392. */
  1393. int iwl_verify_ucode(struct iwl_priv *priv)
  1394. {
  1395. __le32 *image;
  1396. u32 len;
  1397. int ret;
  1398. /* Try bootstrap */
  1399. image = (__le32 *)priv->ucode_boot.v_addr;
  1400. len = priv->ucode_boot.len;
  1401. ret = iwlcore_verify_inst_sparse(priv, image, len);
  1402. if (!ret) {
  1403. IWL_DEBUG_INFO(priv, "Bootstrap uCode is good in inst SRAM\n");
  1404. return 0;
  1405. }
  1406. /* Try initialize */
  1407. image = (__le32 *)priv->ucode_init.v_addr;
  1408. len = priv->ucode_init.len;
  1409. ret = iwlcore_verify_inst_sparse(priv, image, len);
  1410. if (!ret) {
  1411. IWL_DEBUG_INFO(priv, "Initialize uCode is good in inst SRAM\n");
  1412. return 0;
  1413. }
  1414. /* Try runtime/protocol */
  1415. image = (__le32 *)priv->ucode_code.v_addr;
  1416. len = priv->ucode_code.len;
  1417. ret = iwlcore_verify_inst_sparse(priv, image, len);
  1418. if (!ret) {
  1419. IWL_DEBUG_INFO(priv, "Runtime uCode is good in inst SRAM\n");
  1420. return 0;
  1421. }
  1422. IWL_ERR(priv, "NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
  1423. /* Since nothing seems to match, show first several data entries in
  1424. * instruction SRAM, so maybe visual inspection will give a clue.
  1425. * Selection of bootstrap image (vs. other images) is arbitrary. */
  1426. image = (__le32 *)priv->ucode_boot.v_addr;
  1427. len = priv->ucode_boot.len;
  1428. ret = iwl_verify_inst_full(priv, image, len);
  1429. return ret;
  1430. }
  1431. EXPORT_SYMBOL(iwl_verify_ucode);
  1432. static const char *desc_lookup_text[] = {
  1433. "OK",
  1434. "FAIL",
  1435. "BAD_PARAM",
  1436. "BAD_CHECKSUM",
  1437. "NMI_INTERRUPT_WDG",
  1438. "SYSASSERT",
  1439. "FATAL_ERROR",
  1440. "BAD_COMMAND",
  1441. "HW_ERROR_TUNE_LOCK",
  1442. "HW_ERROR_TEMPERATURE",
  1443. "ILLEGAL_CHAN_FREQ",
  1444. "VCC_NOT_STABLE",
  1445. "FH_ERROR",
  1446. "NMI_INTERRUPT_HOST",
  1447. "NMI_INTERRUPT_ACTION_PT",
  1448. "NMI_INTERRUPT_UNKNOWN",
  1449. "UCODE_VERSION_MISMATCH",
  1450. "HW_ERROR_ABS_LOCK",
  1451. "HW_ERROR_CAL_LOCK_FAIL",
  1452. "NMI_INTERRUPT_INST_ACTION_PT",
  1453. "NMI_INTERRUPT_DATA_ACTION_PT",
  1454. "NMI_TRM_HW_ER",
  1455. "NMI_INTERRUPT_TRM",
  1456. "NMI_INTERRUPT_BREAK_POINT"
  1457. "DEBUG_0",
  1458. "DEBUG_1",
  1459. "DEBUG_2",
  1460. "DEBUG_3",
  1461. "UNKNOWN"
  1462. };
  1463. static const char *desc_lookup(int i)
  1464. {
  1465. int max = ARRAY_SIZE(desc_lookup_text) - 1;
  1466. if (i < 0 || i > max)
  1467. i = max;
  1468. return desc_lookup_text[i];
  1469. }
  1470. #define ERROR_START_OFFSET (1 * sizeof(u32))
  1471. #define ERROR_ELEM_SIZE (7 * sizeof(u32))
  1472. void iwl_dump_nic_error_log(struct iwl_priv *priv)
  1473. {
  1474. u32 data2, line;
  1475. u32 desc, time, count, base, data1;
  1476. u32 blink1, blink2, ilink1, ilink2;
  1477. int ret;
  1478. if (priv->ucode_type == UCODE_INIT)
  1479. base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
  1480. else
  1481. base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
  1482. if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
  1483. IWL_ERR(priv, "Not valid error log pointer 0x%08X\n", base);
  1484. return;
  1485. }
  1486. ret = iwl_grab_nic_access(priv);
  1487. if (ret) {
  1488. IWL_WARN(priv, "Can not read from adapter at this time.\n");
  1489. return;
  1490. }
  1491. count = iwl_read_targ_mem(priv, base);
  1492. if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
  1493. IWL_ERR(priv, "Start IWL Error Log Dump:\n");
  1494. IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
  1495. priv->status, count);
  1496. }
  1497. desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
  1498. blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
  1499. blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
  1500. ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
  1501. ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
  1502. data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
  1503. data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
  1504. line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
  1505. time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
  1506. IWL_ERR(priv, "Desc Time "
  1507. "data1 data2 line\n");
  1508. IWL_ERR(priv, "%-28s (#%02d) %010u 0x%08X 0x%08X %u\n",
  1509. desc_lookup(desc), desc, time, data1, data2, line);
  1510. IWL_ERR(priv, "blink1 blink2 ilink1 ilink2\n");
  1511. IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2,
  1512. ilink1, ilink2);
  1513. iwl_release_nic_access(priv);
  1514. }
  1515. EXPORT_SYMBOL(iwl_dump_nic_error_log);
  1516. #define EVENT_START_OFFSET (4 * sizeof(u32))
  1517. /**
  1518. * iwl_print_event_log - Dump error event log to syslog
  1519. *
  1520. * NOTE: Must be called with iwl_grab_nic_access() already obtained!
  1521. */
  1522. static void iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
  1523. u32 num_events, u32 mode)
  1524. {
  1525. u32 i;
  1526. u32 base; /* SRAM byte address of event log header */
  1527. u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
  1528. u32 ptr; /* SRAM byte address of log data */
  1529. u32 ev, time, data; /* event log data */
  1530. if (num_events == 0)
  1531. return;
  1532. if (priv->ucode_type == UCODE_INIT)
  1533. base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
  1534. else
  1535. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  1536. if (mode == 0)
  1537. event_size = 2 * sizeof(u32);
  1538. else
  1539. event_size = 3 * sizeof(u32);
  1540. ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
  1541. /* "time" is actually "data" for mode 0 (no timestamp).
  1542. * place event id # at far right for easier visual parsing. */
  1543. for (i = 0; i < num_events; i++) {
  1544. ev = iwl_read_targ_mem(priv, ptr);
  1545. ptr += sizeof(u32);
  1546. time = iwl_read_targ_mem(priv, ptr);
  1547. ptr += sizeof(u32);
  1548. if (mode == 0) {
  1549. /* data, ev */
  1550. IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n", time, ev);
  1551. } else {
  1552. data = iwl_read_targ_mem(priv, ptr);
  1553. ptr += sizeof(u32);
  1554. IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
  1555. time, data, ev);
  1556. }
  1557. }
  1558. }
  1559. void iwl_dump_nic_event_log(struct iwl_priv *priv)
  1560. {
  1561. int ret;
  1562. u32 base; /* SRAM byte address of event log header */
  1563. u32 capacity; /* event log capacity in # entries */
  1564. u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
  1565. u32 num_wraps; /* # times uCode wrapped to top of log */
  1566. u32 next_entry; /* index of next entry to be written by uCode */
  1567. u32 size; /* # entries that we'll print */
  1568. if (priv->ucode_type == UCODE_INIT)
  1569. base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
  1570. else
  1571. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  1572. if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
  1573. IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
  1574. return;
  1575. }
  1576. ret = iwl_grab_nic_access(priv);
  1577. if (ret) {
  1578. IWL_WARN(priv, "Can not read from adapter at this time.\n");
  1579. return;
  1580. }
  1581. /* event log header */
  1582. capacity = iwl_read_targ_mem(priv, base);
  1583. mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
  1584. num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
  1585. next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
  1586. size = num_wraps ? capacity : next_entry;
  1587. /* bail out if nothing in log */
  1588. if (size == 0) {
  1589. IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
  1590. iwl_release_nic_access(priv);
  1591. return;
  1592. }
  1593. IWL_ERR(priv, "Start IWL Event Log Dump: display count %d, wraps %d\n",
  1594. size, num_wraps);
  1595. /* if uCode has wrapped back to top of log, start at the oldest entry,
  1596. * i.e the next one that uCode would fill. */
  1597. if (num_wraps)
  1598. iwl_print_event_log(priv, next_entry,
  1599. capacity - next_entry, mode);
  1600. /* (then/else) start at top of log */
  1601. iwl_print_event_log(priv, 0, next_entry, mode);
  1602. iwl_release_nic_access(priv);
  1603. }
  1604. EXPORT_SYMBOL(iwl_dump_nic_event_log);
  1605. void iwl_rf_kill_ct_config(struct iwl_priv *priv)
  1606. {
  1607. struct iwl_ct_kill_config cmd;
  1608. unsigned long flags;
  1609. int ret = 0;
  1610. spin_lock_irqsave(&priv->lock, flags);
  1611. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  1612. CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
  1613. spin_unlock_irqrestore(&priv->lock, flags);
  1614. cmd.critical_temperature_R =
  1615. cpu_to_le32(priv->hw_params.ct_kill_threshold);
  1616. ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
  1617. sizeof(cmd), &cmd);
  1618. if (ret)
  1619. IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
  1620. else
  1621. IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD succeeded, "
  1622. "critical temperature is %d\n",
  1623. cmd.critical_temperature_R);
  1624. }
  1625. EXPORT_SYMBOL(iwl_rf_kill_ct_config);
  1626. /*
  1627. * CARD_STATE_CMD
  1628. *
  1629. * Use: Sets the device's internal card state to enable, disable, or halt
  1630. *
  1631. * When in the 'enable' state the card operates as normal.
  1632. * When in the 'disable' state, the card enters into a low power mode.
  1633. * When in the 'halt' state, the card is shut down and must be fully
  1634. * restarted to come back on.
  1635. */
  1636. int iwl_send_card_state(struct iwl_priv *priv, u32 flags, u8 meta_flag)
  1637. {
  1638. struct iwl_host_cmd cmd = {
  1639. .id = REPLY_CARD_STATE_CMD,
  1640. .len = sizeof(u32),
  1641. .data = &flags,
  1642. .meta.flags = meta_flag,
  1643. };
  1644. return iwl_send_cmd(priv, &cmd);
  1645. }
  1646. EXPORT_SYMBOL(iwl_send_card_state);
  1647. void iwl_radio_kill_sw_disable_radio(struct iwl_priv *priv)
  1648. {
  1649. unsigned long flags;
  1650. if (test_bit(STATUS_RF_KILL_SW, &priv->status))
  1651. return;
  1652. IWL_DEBUG_RF_KILL(priv, "Manual SW RF KILL set to: RADIO OFF\n");
  1653. iwl_scan_cancel(priv);
  1654. /* FIXME: This is a workaround for AP */
  1655. if (priv->iw_mode != NL80211_IFTYPE_AP) {
  1656. spin_lock_irqsave(&priv->lock, flags);
  1657. iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
  1658. CSR_UCODE_SW_BIT_RFKILL);
  1659. spin_unlock_irqrestore(&priv->lock, flags);
  1660. /* call the host command only if no hw rf-kill set */
  1661. if (!test_bit(STATUS_RF_KILL_HW, &priv->status) &&
  1662. iwl_is_ready(priv))
  1663. iwl_send_card_state(priv,
  1664. CARD_STATE_CMD_DISABLE, 0);
  1665. set_bit(STATUS_RF_KILL_SW, &priv->status);
  1666. /* make sure mac80211 stop sending Tx frame */
  1667. if (priv->mac80211_registered)
  1668. ieee80211_stop_queues(priv->hw);
  1669. }
  1670. }
  1671. EXPORT_SYMBOL(iwl_radio_kill_sw_disable_radio);
  1672. int iwl_radio_kill_sw_enable_radio(struct iwl_priv *priv)
  1673. {
  1674. unsigned long flags;
  1675. if (!test_bit(STATUS_RF_KILL_SW, &priv->status))
  1676. return 0;
  1677. IWL_DEBUG_RF_KILL(priv, "Manual SW RF KILL set to: RADIO ON\n");
  1678. spin_lock_irqsave(&priv->lock, flags);
  1679. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  1680. /* If the driver is up it will receive CARD_STATE_NOTIFICATION
  1681. * notification where it will clear SW rfkill status.
  1682. * Setting it here would break the handler. Only if the
  1683. * interface is down we can set here since we don't
  1684. * receive any further notification.
  1685. */
  1686. if (!priv->is_open)
  1687. clear_bit(STATUS_RF_KILL_SW, &priv->status);
  1688. spin_unlock_irqrestore(&priv->lock, flags);
  1689. /* wake up ucode */
  1690. msleep(10);
  1691. spin_lock_irqsave(&priv->lock, flags);
  1692. iwl_read32(priv, CSR_UCODE_DRV_GP1);
  1693. if (!iwl_grab_nic_access(priv))
  1694. iwl_release_nic_access(priv);
  1695. spin_unlock_irqrestore(&priv->lock, flags);
  1696. if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
  1697. IWL_DEBUG_RF_KILL(priv, "Can not turn radio back on - "
  1698. "disabled by HW switch\n");
  1699. return 0;
  1700. }
  1701. /* when driver is up while rfkill is on, it wont receive
  1702. * any CARD_STATE_NOTIFICATION notifications so we have to
  1703. * restart it in here
  1704. */
  1705. if (priv->is_open && !test_bit(STATUS_ALIVE, &priv->status)) {
  1706. clear_bit(STATUS_RF_KILL_SW, &priv->status);
  1707. if (!iwl_is_rfkill(priv))
  1708. queue_work(priv->workqueue, &priv->up);
  1709. }
  1710. /* If the driver is already loaded, it will receive
  1711. * CARD_STATE_NOTIFICATION notifications and the handler will
  1712. * call restart to reload the driver.
  1713. */
  1714. return 1;
  1715. }
  1716. EXPORT_SYMBOL(iwl_radio_kill_sw_enable_radio);
  1717. void iwl_bg_rf_kill(struct work_struct *work)
  1718. {
  1719. struct iwl_priv *priv = container_of(work, struct iwl_priv, rf_kill);
  1720. wake_up_interruptible(&priv->wait_command_queue);
  1721. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1722. return;
  1723. mutex_lock(&priv->mutex);
  1724. if (!iwl_is_rfkill(priv)) {
  1725. IWL_DEBUG_RF_KILL(priv,
  1726. "HW and/or SW RF Kill no longer active, restarting "
  1727. "device\n");
  1728. if (!test_bit(STATUS_EXIT_PENDING, &priv->status) &&
  1729. test_bit(STATUS_ALIVE, &priv->status))
  1730. queue_work(priv->workqueue, &priv->restart);
  1731. } else {
  1732. /* make sure mac80211 stop sending Tx frame */
  1733. if (priv->mac80211_registered)
  1734. ieee80211_stop_queues(priv->hw);
  1735. if (!test_bit(STATUS_RF_KILL_HW, &priv->status))
  1736. IWL_DEBUG_RF_KILL(priv, "Can not turn radio back on - "
  1737. "disabled by SW switch\n");
  1738. else
  1739. IWL_WARN(priv, "Radio Frequency Kill Switch is On:\n"
  1740. "Kill switch must be turned off for "
  1741. "wireless networking to work.\n");
  1742. }
  1743. mutex_unlock(&priv->mutex);
  1744. iwl_rfkill_set_hw_state(priv);
  1745. }
  1746. EXPORT_SYMBOL(iwl_bg_rf_kill);
  1747. void iwl_rx_pm_sleep_notif(struct iwl_priv *priv,
  1748. struct iwl_rx_mem_buffer *rxb)
  1749. {
  1750. #ifdef CONFIG_IWLWIFI_DEBUG
  1751. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  1752. struct iwl_sleep_notification *sleep = &(pkt->u.sleep_notif);
  1753. IWL_DEBUG_RX(priv, "sleep mode: %d, src: %d\n",
  1754. sleep->pm_sleep_mode, sleep->pm_wakeup_src);
  1755. #endif
  1756. }
  1757. EXPORT_SYMBOL(iwl_rx_pm_sleep_notif);
  1758. void iwl_rx_pm_debug_statistics_notif(struct iwl_priv *priv,
  1759. struct iwl_rx_mem_buffer *rxb)
  1760. {
  1761. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  1762. IWL_DEBUG_RADIO(priv, "Dumping %d bytes of unhandled "
  1763. "notification for %s:\n",
  1764. le32_to_cpu(pkt->len), get_cmd_string(pkt->hdr.cmd));
  1765. iwl_print_hex_dump(priv, IWL_DL_RADIO, pkt->u.raw, le32_to_cpu(pkt->len));
  1766. }
  1767. EXPORT_SYMBOL(iwl_rx_pm_debug_statistics_notif);
  1768. void iwl_rx_reply_error(struct iwl_priv *priv,
  1769. struct iwl_rx_mem_buffer *rxb)
  1770. {
  1771. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  1772. IWL_ERR(priv, "Error Reply type 0x%08X cmd %s (0x%02X) "
  1773. "seq 0x%04X ser 0x%08X\n",
  1774. le32_to_cpu(pkt->u.err_resp.error_type),
  1775. get_cmd_string(pkt->u.err_resp.cmd_id),
  1776. pkt->u.err_resp.cmd_id,
  1777. le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
  1778. le32_to_cpu(pkt->u.err_resp.error_info));
  1779. }
  1780. EXPORT_SYMBOL(iwl_rx_reply_error);