snps-dma.txt 2.0 KB

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  1. * Synopsys Designware DMA Controller
  2. Required properties:
  3. - compatible: "snps,dma-spear1340"
  4. - reg: Address range of the DMAC registers
  5. - interrupt-parent: Should be the phandle for the interrupt controller
  6. that services interrupts for this device
  7. - interrupt: Should contain the DMAC interrupt number
  8. - nr_channels: Number of channels supported by hardware
  9. - is_private: The device channels should be marked as private and not for by the
  10. general purpose DMA channel allocator. False if not passed.
  11. - chan_allocation_order: order of allocation of channel, 0 (default): ascending,
  12. 1: descending
  13. - chan_priority: priority of channels. 0 (default): increase from chan 0->n, 1:
  14. increase from chan n->0
  15. - block_size: Maximum block size supported by the controller
  16. - nr_masters: Number of AHB masters supported by the controller
  17. - data_width: Maximum data width supported by hardware per AHB master
  18. (0 - 8bits, 1 - 16bits, ..., 5 - 256bits)
  19. - slave_info:
  20. - bus_id: name of this device channel, not just a device name since
  21. devices may have more than one channel e.g. "foo_tx". For using the
  22. dw_generic_filter(), slave drivers must pass exactly this string as
  23. param to filter function.
  24. - cfg_hi: Platform-specific initializer for the CFG_HI register
  25. - cfg_lo: Platform-specific initializer for the CFG_LO register
  26. - src_master: src master for transfers on allocated channel.
  27. - dst_master: dest master for transfers on allocated channel.
  28. Example:
  29. dma@fc000000 {
  30. compatible = "snps,dma-spear1340";
  31. reg = <0xfc000000 0x1000>;
  32. interrupt-parent = <&vic1>;
  33. interrupts = <12>;
  34. nr_channels = <8>;
  35. chan_allocation_order = <1>;
  36. chan_priority = <1>;
  37. block_size = <0xfff>;
  38. nr_masters = <2>;
  39. data_width = <3 3 0 0>;
  40. slave_info {
  41. uart0-tx {
  42. bus_id = "uart0-tx";
  43. cfg_hi = <0x4000>; /* 0x8 << 11 */
  44. cfg_lo = <0>;
  45. src_master = <0>;
  46. dst_master = <1>;
  47. };
  48. spi0-tx {
  49. bus_id = "spi0-tx";
  50. cfg_hi = <0x2000>; /* 0x4 << 11 */
  51. cfg_lo = <0>;
  52. src_master = <0>;
  53. dst_master = <0>;
  54. };
  55. };
  56. };