radeon_ttm.c 18 KB

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  1. /*
  2. * Copyright 2009 Jerome Glisse.
  3. * All Rights Reserved.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining a
  6. * copy of this software and associated documentation files (the
  7. * "Software"), to deal in the Software without restriction, including
  8. * without limitation the rights to use, copy, modify, merge, publish,
  9. * distribute, sub license, and/or sell copies of the Software, and to
  10. * permit persons to whom the Software is furnished to do so, subject to
  11. * the following conditions:
  12. *
  13. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15. * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16. * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17. * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18. * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19. * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20. *
  21. * The above copyright notice and this permission notice (including the
  22. * next paragraph) shall be included in all copies or substantial portions
  23. * of the Software.
  24. *
  25. */
  26. /*
  27. * Authors:
  28. * Jerome Glisse <glisse@freedesktop.org>
  29. * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30. * Dave Airlie
  31. */
  32. #include <ttm/ttm_bo_api.h>
  33. #include <ttm/ttm_bo_driver.h>
  34. #include <ttm/ttm_placement.h>
  35. #include <ttm/ttm_module.h>
  36. #include <drm/drmP.h>
  37. #include <drm/radeon_drm.h>
  38. #include "radeon_reg.h"
  39. #include "radeon.h"
  40. #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
  41. static struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev)
  42. {
  43. struct radeon_mman *mman;
  44. struct radeon_device *rdev;
  45. mman = container_of(bdev, struct radeon_mman, bdev);
  46. rdev = container_of(mman, struct radeon_device, mman);
  47. return rdev;
  48. }
  49. /*
  50. * Global memory.
  51. */
  52. static int radeon_ttm_mem_global_init(struct ttm_global_reference *ref)
  53. {
  54. return ttm_mem_global_init(ref->object);
  55. }
  56. static void radeon_ttm_mem_global_release(struct ttm_global_reference *ref)
  57. {
  58. ttm_mem_global_release(ref->object);
  59. }
  60. static int radeon_ttm_global_init(struct radeon_device *rdev)
  61. {
  62. struct ttm_global_reference *global_ref;
  63. int r;
  64. rdev->mman.mem_global_referenced = false;
  65. global_ref = &rdev->mman.mem_global_ref;
  66. global_ref->global_type = TTM_GLOBAL_TTM_MEM;
  67. global_ref->size = sizeof(struct ttm_mem_global);
  68. global_ref->init = &radeon_ttm_mem_global_init;
  69. global_ref->release = &radeon_ttm_mem_global_release;
  70. r = ttm_global_item_ref(global_ref);
  71. if (r != 0) {
  72. DRM_ERROR("Failed setting up TTM memory accounting "
  73. "subsystem.\n");
  74. return r;
  75. }
  76. rdev->mman.bo_global_ref.mem_glob =
  77. rdev->mman.mem_global_ref.object;
  78. global_ref = &rdev->mman.bo_global_ref.ref;
  79. global_ref->global_type = TTM_GLOBAL_TTM_BO;
  80. global_ref->size = sizeof(struct ttm_mem_global);
  81. global_ref->init = &ttm_bo_global_init;
  82. global_ref->release = &ttm_bo_global_release;
  83. r = ttm_global_item_ref(global_ref);
  84. if (r != 0) {
  85. DRM_ERROR("Failed setting up TTM BO subsystem.\n");
  86. ttm_global_item_unref(&rdev->mman.mem_global_ref);
  87. return r;
  88. }
  89. rdev->mman.mem_global_referenced = true;
  90. return 0;
  91. }
  92. static void radeon_ttm_global_fini(struct radeon_device *rdev)
  93. {
  94. if (rdev->mman.mem_global_referenced) {
  95. ttm_global_item_unref(&rdev->mman.bo_global_ref.ref);
  96. ttm_global_item_unref(&rdev->mman.mem_global_ref);
  97. rdev->mman.mem_global_referenced = false;
  98. }
  99. }
  100. struct ttm_backend *radeon_ttm_backend_create(struct radeon_device *rdev);
  101. static struct ttm_backend*
  102. radeon_create_ttm_backend_entry(struct ttm_bo_device *bdev)
  103. {
  104. struct radeon_device *rdev;
  105. rdev = radeon_get_rdev(bdev);
  106. #if __OS_HAS_AGP
  107. if (rdev->flags & RADEON_IS_AGP) {
  108. return ttm_agp_backend_init(bdev, rdev->ddev->agp->bridge);
  109. } else
  110. #endif
  111. {
  112. return radeon_ttm_backend_create(rdev);
  113. }
  114. }
  115. static int radeon_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
  116. {
  117. return 0;
  118. }
  119. static int radeon_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
  120. struct ttm_mem_type_manager *man)
  121. {
  122. struct radeon_device *rdev;
  123. rdev = radeon_get_rdev(bdev);
  124. switch (type) {
  125. case TTM_PL_SYSTEM:
  126. /* System memory */
  127. man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
  128. man->available_caching = TTM_PL_MASK_CACHING;
  129. man->default_caching = TTM_PL_FLAG_CACHED;
  130. break;
  131. case TTM_PL_TT:
  132. man->gpu_offset = 0;
  133. man->available_caching = TTM_PL_MASK_CACHING;
  134. man->default_caching = TTM_PL_FLAG_CACHED;
  135. man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
  136. #if __OS_HAS_AGP
  137. if (rdev->flags & RADEON_IS_AGP) {
  138. if (!(drm_core_has_AGP(rdev->ddev) && rdev->ddev->agp)) {
  139. DRM_ERROR("AGP is not enabled for memory type %u\n",
  140. (unsigned)type);
  141. return -EINVAL;
  142. }
  143. man->io_offset = rdev->mc.agp_base;
  144. man->io_size = rdev->mc.gtt_size;
  145. man->io_addr = NULL;
  146. if (!rdev->ddev->agp->cant_use_aperture)
  147. man->flags = TTM_MEMTYPE_FLAG_NEEDS_IOREMAP |
  148. TTM_MEMTYPE_FLAG_MAPPABLE;
  149. man->available_caching = TTM_PL_FLAG_UNCACHED |
  150. TTM_PL_FLAG_WC;
  151. man->default_caching = TTM_PL_FLAG_WC;
  152. } else
  153. #endif
  154. {
  155. man->io_offset = 0;
  156. man->io_size = 0;
  157. man->io_addr = NULL;
  158. }
  159. break;
  160. case TTM_PL_VRAM:
  161. /* "On-card" video ram */
  162. man->gpu_offset = 0;
  163. man->flags = TTM_MEMTYPE_FLAG_FIXED |
  164. TTM_MEMTYPE_FLAG_NEEDS_IOREMAP |
  165. TTM_MEMTYPE_FLAG_MAPPABLE;
  166. man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
  167. man->default_caching = TTM_PL_FLAG_WC;
  168. man->io_addr = NULL;
  169. man->io_offset = rdev->mc.aper_base;
  170. man->io_size = rdev->mc.aper_size;
  171. break;
  172. default:
  173. DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
  174. return -EINVAL;
  175. }
  176. return 0;
  177. }
  178. static uint32_t radeon_evict_flags(struct ttm_buffer_object *bo)
  179. {
  180. uint32_t cur_placement = bo->mem.placement & ~TTM_PL_MASK_MEMTYPE;
  181. switch (bo->mem.mem_type) {
  182. default:
  183. return (cur_placement & ~TTM_PL_MASK_CACHING) |
  184. TTM_PL_FLAG_SYSTEM |
  185. TTM_PL_FLAG_CACHED;
  186. }
  187. }
  188. static int radeon_verify_access(struct ttm_buffer_object *bo, struct file *filp)
  189. {
  190. return 0;
  191. }
  192. static void radeon_move_null(struct ttm_buffer_object *bo,
  193. struct ttm_mem_reg *new_mem)
  194. {
  195. struct ttm_mem_reg *old_mem = &bo->mem;
  196. BUG_ON(old_mem->mm_node != NULL);
  197. *old_mem = *new_mem;
  198. new_mem->mm_node = NULL;
  199. }
  200. static int radeon_move_blit(struct ttm_buffer_object *bo,
  201. bool evict, int no_wait,
  202. struct ttm_mem_reg *new_mem,
  203. struct ttm_mem_reg *old_mem)
  204. {
  205. struct radeon_device *rdev;
  206. uint64_t old_start, new_start;
  207. struct radeon_fence *fence;
  208. int r;
  209. rdev = radeon_get_rdev(bo->bdev);
  210. r = radeon_fence_create(rdev, &fence);
  211. if (unlikely(r)) {
  212. return r;
  213. }
  214. old_start = old_mem->mm_node->start << PAGE_SHIFT;
  215. new_start = new_mem->mm_node->start << PAGE_SHIFT;
  216. switch (old_mem->mem_type) {
  217. case TTM_PL_VRAM:
  218. old_start += rdev->mc.vram_location;
  219. break;
  220. case TTM_PL_TT:
  221. old_start += rdev->mc.gtt_location;
  222. break;
  223. default:
  224. DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
  225. return -EINVAL;
  226. }
  227. switch (new_mem->mem_type) {
  228. case TTM_PL_VRAM:
  229. new_start += rdev->mc.vram_location;
  230. break;
  231. case TTM_PL_TT:
  232. new_start += rdev->mc.gtt_location;
  233. break;
  234. default:
  235. DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
  236. return -EINVAL;
  237. }
  238. if (!rdev->cp.ready) {
  239. DRM_ERROR("Trying to move memory with CP turned off.\n");
  240. return -EINVAL;
  241. }
  242. r = radeon_copy(rdev, old_start, new_start, new_mem->num_pages, fence);
  243. /* FIXME: handle copy error */
  244. r = ttm_bo_move_accel_cleanup(bo, (void *)fence, NULL,
  245. evict, no_wait, new_mem);
  246. radeon_fence_unref(&fence);
  247. return r;
  248. }
  249. static int radeon_move_vram_ram(struct ttm_buffer_object *bo,
  250. bool evict, bool interruptible, bool no_wait,
  251. struct ttm_mem_reg *new_mem)
  252. {
  253. struct radeon_device *rdev;
  254. struct ttm_mem_reg *old_mem = &bo->mem;
  255. struct ttm_mem_reg tmp_mem;
  256. uint32_t proposed_placement;
  257. int r;
  258. rdev = radeon_get_rdev(bo->bdev);
  259. tmp_mem = *new_mem;
  260. tmp_mem.mm_node = NULL;
  261. proposed_placement = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
  262. r = ttm_bo_mem_space(bo, proposed_placement, &tmp_mem,
  263. interruptible, no_wait);
  264. if (unlikely(r)) {
  265. return r;
  266. }
  267. r = ttm_tt_bind(bo->ttm, &tmp_mem);
  268. if (unlikely(r)) {
  269. goto out_cleanup;
  270. }
  271. r = radeon_move_blit(bo, true, no_wait, &tmp_mem, old_mem);
  272. if (unlikely(r)) {
  273. goto out_cleanup;
  274. }
  275. r = ttm_bo_move_ttm(bo, true, no_wait, new_mem);
  276. out_cleanup:
  277. if (tmp_mem.mm_node) {
  278. struct ttm_bo_global *glob = rdev->mman.bdev.glob;
  279. spin_lock(&glob->lru_lock);
  280. drm_mm_put_block(tmp_mem.mm_node);
  281. spin_unlock(&glob->lru_lock);
  282. return r;
  283. }
  284. return r;
  285. }
  286. static int radeon_move_ram_vram(struct ttm_buffer_object *bo,
  287. bool evict, bool interruptible, bool no_wait,
  288. struct ttm_mem_reg *new_mem)
  289. {
  290. struct radeon_device *rdev;
  291. struct ttm_mem_reg *old_mem = &bo->mem;
  292. struct ttm_mem_reg tmp_mem;
  293. uint32_t proposed_flags;
  294. int r;
  295. rdev = radeon_get_rdev(bo->bdev);
  296. tmp_mem = *new_mem;
  297. tmp_mem.mm_node = NULL;
  298. proposed_flags = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
  299. r = ttm_bo_mem_space(bo, proposed_flags, &tmp_mem,
  300. interruptible, no_wait);
  301. if (unlikely(r)) {
  302. return r;
  303. }
  304. r = ttm_bo_move_ttm(bo, true, no_wait, &tmp_mem);
  305. if (unlikely(r)) {
  306. goto out_cleanup;
  307. }
  308. r = radeon_move_blit(bo, true, no_wait, new_mem, old_mem);
  309. if (unlikely(r)) {
  310. goto out_cleanup;
  311. }
  312. out_cleanup:
  313. if (tmp_mem.mm_node) {
  314. struct ttm_bo_global *glob = rdev->mman.bdev.glob;
  315. spin_lock(&glob->lru_lock);
  316. drm_mm_put_block(tmp_mem.mm_node);
  317. spin_unlock(&glob->lru_lock);
  318. return r;
  319. }
  320. return r;
  321. }
  322. static int radeon_bo_move(struct ttm_buffer_object *bo,
  323. bool evict, bool interruptible, bool no_wait,
  324. struct ttm_mem_reg *new_mem)
  325. {
  326. struct radeon_device *rdev;
  327. struct ttm_mem_reg *old_mem = &bo->mem;
  328. int r;
  329. rdev = radeon_get_rdev(bo->bdev);
  330. if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
  331. radeon_move_null(bo, new_mem);
  332. return 0;
  333. }
  334. if ((old_mem->mem_type == TTM_PL_TT &&
  335. new_mem->mem_type == TTM_PL_SYSTEM) ||
  336. (old_mem->mem_type == TTM_PL_SYSTEM &&
  337. new_mem->mem_type == TTM_PL_TT)) {
  338. /* bind is enought */
  339. radeon_move_null(bo, new_mem);
  340. return 0;
  341. }
  342. if (!rdev->cp.ready) {
  343. /* use memcpy */
  344. DRM_ERROR("CP is not ready use memcpy.\n");
  345. return ttm_bo_move_memcpy(bo, evict, no_wait, new_mem);
  346. }
  347. if (old_mem->mem_type == TTM_PL_VRAM &&
  348. new_mem->mem_type == TTM_PL_SYSTEM) {
  349. return radeon_move_vram_ram(bo, evict, interruptible,
  350. no_wait, new_mem);
  351. } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
  352. new_mem->mem_type == TTM_PL_VRAM) {
  353. return radeon_move_ram_vram(bo, evict, interruptible,
  354. no_wait, new_mem);
  355. } else {
  356. r = radeon_move_blit(bo, evict, no_wait, new_mem, old_mem);
  357. if (unlikely(r)) {
  358. return r;
  359. }
  360. }
  361. return r;
  362. }
  363. const uint32_t radeon_mem_prios[] = {
  364. TTM_PL_VRAM,
  365. TTM_PL_TT,
  366. TTM_PL_SYSTEM,
  367. };
  368. const uint32_t radeon_busy_prios[] = {
  369. TTM_PL_TT,
  370. TTM_PL_VRAM,
  371. TTM_PL_SYSTEM,
  372. };
  373. static int radeon_sync_obj_wait(void *sync_obj, void *sync_arg,
  374. bool lazy, bool interruptible)
  375. {
  376. return radeon_fence_wait((struct radeon_fence *)sync_obj, interruptible);
  377. }
  378. static int radeon_sync_obj_flush(void *sync_obj, void *sync_arg)
  379. {
  380. return 0;
  381. }
  382. static void radeon_sync_obj_unref(void **sync_obj)
  383. {
  384. radeon_fence_unref((struct radeon_fence **)sync_obj);
  385. }
  386. static void *radeon_sync_obj_ref(void *sync_obj)
  387. {
  388. return radeon_fence_ref((struct radeon_fence *)sync_obj);
  389. }
  390. static bool radeon_sync_obj_signaled(void *sync_obj, void *sync_arg)
  391. {
  392. return radeon_fence_signaled((struct radeon_fence *)sync_obj);
  393. }
  394. static struct ttm_bo_driver radeon_bo_driver = {
  395. .mem_type_prio = radeon_mem_prios,
  396. .mem_busy_prio = radeon_busy_prios,
  397. .num_mem_type_prio = ARRAY_SIZE(radeon_mem_prios),
  398. .num_mem_busy_prio = ARRAY_SIZE(radeon_busy_prios),
  399. .create_ttm_backend_entry = &radeon_create_ttm_backend_entry,
  400. .invalidate_caches = &radeon_invalidate_caches,
  401. .init_mem_type = &radeon_init_mem_type,
  402. .evict_flags = &radeon_evict_flags,
  403. .move = &radeon_bo_move,
  404. .verify_access = &radeon_verify_access,
  405. .sync_obj_signaled = &radeon_sync_obj_signaled,
  406. .sync_obj_wait = &radeon_sync_obj_wait,
  407. .sync_obj_flush = &radeon_sync_obj_flush,
  408. .sync_obj_unref = &radeon_sync_obj_unref,
  409. .sync_obj_ref = &radeon_sync_obj_ref,
  410. };
  411. int radeon_ttm_init(struct radeon_device *rdev)
  412. {
  413. int r;
  414. r = radeon_ttm_global_init(rdev);
  415. if (r) {
  416. return r;
  417. }
  418. /* No others user of address space so set it to 0 */
  419. r = ttm_bo_device_init(&rdev->mman.bdev,
  420. rdev->mman.bo_global_ref.ref.object,
  421. &radeon_bo_driver, DRM_FILE_PAGE_OFFSET);
  422. if (r) {
  423. DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
  424. return r;
  425. }
  426. r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_VRAM, 0,
  427. ((rdev->mc.aper_size) >> PAGE_SHIFT));
  428. if (r) {
  429. DRM_ERROR("Failed initializing VRAM heap.\n");
  430. return r;
  431. }
  432. r = radeon_object_create(rdev, NULL, 256 * 1024, true,
  433. RADEON_GEM_DOMAIN_VRAM, false,
  434. &rdev->stollen_vga_memory);
  435. if (r) {
  436. return r;
  437. }
  438. r = radeon_object_pin(rdev->stollen_vga_memory, RADEON_GEM_DOMAIN_VRAM, NULL);
  439. if (r) {
  440. radeon_object_unref(&rdev->stollen_vga_memory);
  441. return r;
  442. }
  443. DRM_INFO("radeon: %uM of VRAM memory ready\n",
  444. rdev->mc.vram_size / (1024 * 1024));
  445. r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_TT, 0,
  446. ((rdev->mc.gtt_size) >> PAGE_SHIFT));
  447. if (r) {
  448. DRM_ERROR("Failed initializing GTT heap.\n");
  449. return r;
  450. }
  451. DRM_INFO("radeon: %uM of GTT memory ready.\n",
  452. rdev->mc.gtt_size / (1024 * 1024));
  453. if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) {
  454. rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping;
  455. }
  456. return 0;
  457. }
  458. void radeon_ttm_fini(struct radeon_device *rdev)
  459. {
  460. if (rdev->stollen_vga_memory) {
  461. radeon_object_unpin(rdev->stollen_vga_memory);
  462. radeon_object_unref(&rdev->stollen_vga_memory);
  463. }
  464. ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_VRAM);
  465. ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_TT);
  466. ttm_bo_device_release(&rdev->mman.bdev);
  467. radeon_gart_fini(rdev);
  468. radeon_ttm_global_fini(rdev);
  469. DRM_INFO("radeon: ttm finalized\n");
  470. }
  471. static struct vm_operations_struct radeon_ttm_vm_ops;
  472. static struct vm_operations_struct *ttm_vm_ops = NULL;
  473. static int radeon_ttm_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
  474. {
  475. struct ttm_buffer_object *bo;
  476. int r;
  477. bo = (struct ttm_buffer_object *)vma->vm_private_data;
  478. if (bo == NULL) {
  479. return VM_FAULT_NOPAGE;
  480. }
  481. r = ttm_vm_ops->fault(vma, vmf);
  482. return r;
  483. }
  484. int radeon_mmap(struct file *filp, struct vm_area_struct *vma)
  485. {
  486. struct drm_file *file_priv;
  487. struct radeon_device *rdev;
  488. int r;
  489. if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET)) {
  490. return drm_mmap(filp, vma);
  491. }
  492. file_priv = (struct drm_file *)filp->private_data;
  493. rdev = file_priv->minor->dev->dev_private;
  494. if (rdev == NULL) {
  495. return -EINVAL;
  496. }
  497. r = ttm_bo_mmap(filp, vma, &rdev->mman.bdev);
  498. if (unlikely(r != 0)) {
  499. return r;
  500. }
  501. if (unlikely(ttm_vm_ops == NULL)) {
  502. ttm_vm_ops = vma->vm_ops;
  503. radeon_ttm_vm_ops = *ttm_vm_ops;
  504. radeon_ttm_vm_ops.fault = &radeon_ttm_fault;
  505. }
  506. vma->vm_ops = &radeon_ttm_vm_ops;
  507. return 0;
  508. }
  509. /*
  510. * TTM backend functions.
  511. */
  512. struct radeon_ttm_backend {
  513. struct ttm_backend backend;
  514. struct radeon_device *rdev;
  515. unsigned long num_pages;
  516. struct page **pages;
  517. struct page *dummy_read_page;
  518. bool populated;
  519. bool bound;
  520. unsigned offset;
  521. };
  522. static int radeon_ttm_backend_populate(struct ttm_backend *backend,
  523. unsigned long num_pages,
  524. struct page **pages,
  525. struct page *dummy_read_page)
  526. {
  527. struct radeon_ttm_backend *gtt;
  528. gtt = container_of(backend, struct radeon_ttm_backend, backend);
  529. gtt->pages = pages;
  530. gtt->num_pages = num_pages;
  531. gtt->dummy_read_page = dummy_read_page;
  532. gtt->populated = true;
  533. return 0;
  534. }
  535. static void radeon_ttm_backend_clear(struct ttm_backend *backend)
  536. {
  537. struct radeon_ttm_backend *gtt;
  538. gtt = container_of(backend, struct radeon_ttm_backend, backend);
  539. gtt->pages = NULL;
  540. gtt->num_pages = 0;
  541. gtt->dummy_read_page = NULL;
  542. gtt->populated = false;
  543. gtt->bound = false;
  544. }
  545. static int radeon_ttm_backend_bind(struct ttm_backend *backend,
  546. struct ttm_mem_reg *bo_mem)
  547. {
  548. struct radeon_ttm_backend *gtt;
  549. int r;
  550. gtt = container_of(backend, struct radeon_ttm_backend, backend);
  551. gtt->offset = bo_mem->mm_node->start << PAGE_SHIFT;
  552. if (!gtt->num_pages) {
  553. WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n", gtt->num_pages, bo_mem, backend);
  554. }
  555. r = radeon_gart_bind(gtt->rdev, gtt->offset,
  556. gtt->num_pages, gtt->pages);
  557. if (r) {
  558. DRM_ERROR("failed to bind %lu pages at 0x%08X\n",
  559. gtt->num_pages, gtt->offset);
  560. return r;
  561. }
  562. gtt->bound = true;
  563. return 0;
  564. }
  565. static int radeon_ttm_backend_unbind(struct ttm_backend *backend)
  566. {
  567. struct radeon_ttm_backend *gtt;
  568. gtt = container_of(backend, struct radeon_ttm_backend, backend);
  569. radeon_gart_unbind(gtt->rdev, gtt->offset, gtt->num_pages);
  570. gtt->bound = false;
  571. return 0;
  572. }
  573. static void radeon_ttm_backend_destroy(struct ttm_backend *backend)
  574. {
  575. struct radeon_ttm_backend *gtt;
  576. gtt = container_of(backend, struct radeon_ttm_backend, backend);
  577. if (gtt->bound) {
  578. radeon_ttm_backend_unbind(backend);
  579. }
  580. kfree(gtt);
  581. }
  582. static struct ttm_backend_func radeon_backend_func = {
  583. .populate = &radeon_ttm_backend_populate,
  584. .clear = &radeon_ttm_backend_clear,
  585. .bind = &radeon_ttm_backend_bind,
  586. .unbind = &radeon_ttm_backend_unbind,
  587. .destroy = &radeon_ttm_backend_destroy,
  588. };
  589. struct ttm_backend *radeon_ttm_backend_create(struct radeon_device *rdev)
  590. {
  591. struct radeon_ttm_backend *gtt;
  592. gtt = kzalloc(sizeof(struct radeon_ttm_backend), GFP_KERNEL);
  593. if (gtt == NULL) {
  594. return NULL;
  595. }
  596. gtt->backend.bdev = &rdev->mman.bdev;
  597. gtt->backend.flags = 0;
  598. gtt->backend.func = &radeon_backend_func;
  599. gtt->rdev = rdev;
  600. gtt->pages = NULL;
  601. gtt->num_pages = 0;
  602. gtt->dummy_read_page = NULL;
  603. gtt->populated = false;
  604. gtt->bound = false;
  605. return &gtt->backend;
  606. }