cnic.c 118 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914191519161917191819191920192119221923192419251926192719281929193019311932193319341935193619371938193919401941194219431944194519461947194819491950195119521953195419551956195719581959196019611962196319641965196619671968196919701971197219731974197519761977197819791980198119821983198419851986198719881989199019911992199319941995199619971998199920002001200220032004200520062007200820092010201120122013201420152016201720182019202020212022202320242025202620272028202920302031203220332034203520362037203820392040204120422043204420452046204720482049205020512052205320542055205620572058205920602061206220632064206520662067206820692070207120722073207420752076207720782079208020812082208320842085208620872088208920902091209220932094209520962097209820992100210121022103210421052106210721082109211021112112211321142115211621172118211921202121212221232124212521262127212821292130213121322133213421352136213721382139214021412142214321442145214621472148214921502151215221532154215521562157215821592160216121622163216421652166216721682169217021712172217321742175217621772178217921802181218221832184218521862187218821892190219121922193219421952196219721982199220022012202220322042205220622072208220922102211221222132214221522162217221822192220222122222223222422252226222722282229223022312232223322342235223622372238223922402241224222432244224522462247224822492250225122522253225422552256225722582259226022612262226322642265226622672268226922702271227222732274227522762277227822792280228122822283228422852286228722882289229022912292229322942295229622972298229923002301230223032304230523062307230823092310231123122313231423152316231723182319232023212322232323242325232623272328232923302331233223332334233523362337233823392340234123422343234423452346234723482349235023512352235323542355235623572358235923602361236223632364236523662367236823692370237123722373237423752376237723782379238023812382238323842385238623872388238923902391239223932394239523962397239823992400240124022403240424052406240724082409241024112412241324142415241624172418241924202421242224232424242524262427242824292430243124322433243424352436243724382439244024412442244324442445244624472448244924502451245224532454245524562457245824592460246124622463246424652466246724682469247024712472247324742475247624772478247924802481248224832484248524862487248824892490249124922493249424952496249724982499250025012502250325042505250625072508250925102511251225132514251525162517251825192520252125222523252425252526252725282529253025312532253325342535253625372538253925402541254225432544254525462547254825492550255125522553255425552556255725582559256025612562256325642565256625672568256925702571257225732574257525762577257825792580258125822583258425852586258725882589259025912592259325942595259625972598259926002601260226032604260526062607260826092610261126122613261426152616261726182619262026212622262326242625262626272628262926302631263226332634263526362637263826392640264126422643264426452646264726482649265026512652265326542655265626572658265926602661266226632664266526662667266826692670267126722673267426752676267726782679268026812682268326842685268626872688268926902691269226932694269526962697269826992700270127022703270427052706270727082709271027112712271327142715271627172718271927202721272227232724272527262727272827292730273127322733273427352736273727382739274027412742274327442745274627472748274927502751275227532754275527562757275827592760276127622763276427652766276727682769277027712772277327742775277627772778277927802781278227832784278527862787278827892790279127922793279427952796279727982799280028012802280328042805280628072808280928102811281228132814281528162817281828192820282128222823282428252826282728282829283028312832283328342835283628372838283928402841284228432844284528462847284828492850285128522853285428552856285728582859286028612862286328642865286628672868286928702871287228732874287528762877287828792880288128822883288428852886288728882889289028912892289328942895289628972898289929002901290229032904290529062907290829092910291129122913291429152916291729182919292029212922292329242925292629272928292929302931293229332934293529362937293829392940294129422943294429452946294729482949295029512952295329542955295629572958295929602961296229632964296529662967296829692970297129722973297429752976297729782979298029812982298329842985298629872988298929902991299229932994299529962997299829993000300130023003300430053006300730083009301030113012301330143015301630173018301930203021302230233024302530263027302830293030303130323033303430353036303730383039304030413042304330443045304630473048304930503051305230533054305530563057305830593060306130623063306430653066306730683069307030713072307330743075307630773078307930803081308230833084308530863087308830893090309130923093309430953096309730983099310031013102310331043105310631073108310931103111311231133114311531163117311831193120312131223123312431253126312731283129313031313132313331343135313631373138313931403141314231433144314531463147314831493150315131523153315431553156315731583159316031613162316331643165316631673168316931703171317231733174317531763177317831793180318131823183318431853186318731883189319031913192319331943195319631973198319932003201320232033204320532063207320832093210321132123213321432153216321732183219322032213222322332243225322632273228322932303231323232333234323532363237323832393240324132423243324432453246324732483249325032513252325332543255325632573258325932603261326232633264326532663267326832693270327132723273327432753276327732783279328032813282328332843285328632873288328932903291329232933294329532963297329832993300330133023303330433053306330733083309331033113312331333143315331633173318331933203321332233233324332533263327332833293330333133323333333433353336333733383339334033413342334333443345334633473348334933503351335233533354335533563357335833593360336133623363336433653366336733683369337033713372337333743375337633773378337933803381338233833384338533863387338833893390339133923393339433953396339733983399340034013402340334043405340634073408340934103411341234133414341534163417341834193420342134223423342434253426342734283429343034313432343334343435343634373438343934403441344234433444344534463447344834493450345134523453345434553456345734583459346034613462346334643465346634673468346934703471347234733474347534763477347834793480348134823483348434853486348734883489349034913492349334943495349634973498349935003501350235033504350535063507350835093510351135123513351435153516351735183519352035213522352335243525352635273528352935303531353235333534353535363537353835393540354135423543354435453546354735483549355035513552355335543555355635573558355935603561356235633564356535663567356835693570357135723573357435753576357735783579358035813582358335843585358635873588358935903591359235933594359535963597359835993600360136023603360436053606360736083609361036113612361336143615361636173618361936203621362236233624362536263627362836293630363136323633363436353636363736383639364036413642364336443645364636473648364936503651365236533654365536563657365836593660366136623663366436653666366736683669367036713672367336743675367636773678367936803681368236833684368536863687368836893690369136923693369436953696369736983699370037013702370337043705370637073708370937103711371237133714371537163717371837193720372137223723372437253726372737283729373037313732373337343735373637373738373937403741374237433744374537463747374837493750375137523753375437553756375737583759376037613762376337643765376637673768376937703771377237733774377537763777377837793780378137823783378437853786378737883789379037913792379337943795379637973798379938003801380238033804380538063807380838093810381138123813381438153816381738183819382038213822382338243825382638273828382938303831383238333834383538363837383838393840384138423843384438453846384738483849385038513852385338543855385638573858385938603861386238633864386538663867386838693870387138723873387438753876387738783879388038813882388338843885388638873888388938903891389238933894389538963897389838993900390139023903390439053906390739083909391039113912391339143915391639173918391939203921392239233924392539263927392839293930393139323933393439353936393739383939394039413942394339443945394639473948394939503951395239533954395539563957395839593960396139623963396439653966396739683969397039713972397339743975397639773978397939803981398239833984398539863987398839893990399139923993399439953996399739983999400040014002400340044005400640074008400940104011401240134014401540164017401840194020402140224023402440254026402740284029403040314032403340344035403640374038403940404041404240434044404540464047404840494050405140524053405440554056405740584059406040614062406340644065406640674068406940704071407240734074407540764077407840794080408140824083408440854086408740884089409040914092409340944095409640974098409941004101410241034104410541064107410841094110411141124113411441154116411741184119412041214122412341244125412641274128412941304131413241334134413541364137413841394140414141424143414441454146414741484149415041514152415341544155415641574158415941604161416241634164416541664167416841694170417141724173417441754176417741784179418041814182418341844185418641874188418941904191419241934194419541964197419841994200420142024203420442054206420742084209421042114212421342144215421642174218421942204221422242234224422542264227422842294230423142324233423442354236423742384239424042414242424342444245424642474248424942504251425242534254425542564257425842594260426142624263426442654266426742684269427042714272427342744275427642774278427942804281428242834284428542864287428842894290429142924293429442954296429742984299430043014302430343044305430643074308430943104311431243134314431543164317431843194320432143224323432443254326432743284329433043314332433343344335433643374338433943404341434243434344434543464347434843494350435143524353435443554356435743584359436043614362436343644365436643674368436943704371437243734374437543764377437843794380438143824383438443854386438743884389439043914392439343944395439643974398439944004401440244034404440544064407440844094410441144124413441444154416441744184419442044214422442344244425442644274428442944304431443244334434443544364437443844394440444144424443444444454446444744484449445044514452445344544455445644574458445944604461446244634464446544664467446844694470447144724473447444754476447744784479448044814482448344844485448644874488448944904491449244934494449544964497449844994500450145024503450445054506450745084509451045114512451345144515451645174518451945204521452245234524452545264527452845294530453145324533453445354536453745384539454045414542454345444545454645474548454945504551455245534554455545564557455845594560456145624563456445654566456745684569457045714572457345744575457645774578457945804581458245834584458545864587458845894590459145924593459445954596459745984599460046014602460346044605460646074608460946104611461246134614461546164617461846194620462146224623462446254626462746284629
  1. /* cnic.c: Broadcom CNIC core network driver.
  2. *
  3. * Copyright (c) 2006-2009 Broadcom Corporation
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation.
  8. *
  9. * Original skeleton written by: John(Zongxi) Chen (zongxi@broadcom.com)
  10. * Modified and maintained by: Michael Chan <mchan@broadcom.com>
  11. */
  12. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  13. #include <linux/module.h>
  14. #include <linux/kernel.h>
  15. #include <linux/errno.h>
  16. #include <linux/list.h>
  17. #include <linux/slab.h>
  18. #include <linux/pci.h>
  19. #include <linux/init.h>
  20. #include <linux/netdevice.h>
  21. #include <linux/uio_driver.h>
  22. #include <linux/in.h>
  23. #include <linux/dma-mapping.h>
  24. #include <linux/delay.h>
  25. #include <linux/ethtool.h>
  26. #include <linux/if_vlan.h>
  27. #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  28. #define BCM_VLAN 1
  29. #endif
  30. #include <net/ip.h>
  31. #include <net/tcp.h>
  32. #include <net/route.h>
  33. #include <net/ipv6.h>
  34. #include <net/ip6_route.h>
  35. #include <net/ip6_checksum.h>
  36. #include <scsi/iscsi_if.h>
  37. #include "cnic_if.h"
  38. #include "bnx2.h"
  39. #include "bnx2x_reg.h"
  40. #include "bnx2x_fw_defs.h"
  41. #include "bnx2x_hsi.h"
  42. #include "../scsi/bnx2i/57xx_iscsi_constants.h"
  43. #include "../scsi/bnx2i/57xx_iscsi_hsi.h"
  44. #include "cnic.h"
  45. #include "cnic_defs.h"
  46. #define DRV_MODULE_NAME "cnic"
  47. static char version[] __devinitdata =
  48. "Broadcom NetXtreme II CNIC Driver " DRV_MODULE_NAME " v" CNIC_MODULE_VERSION " (" CNIC_MODULE_RELDATE ")\n";
  49. MODULE_AUTHOR("Michael Chan <mchan@broadcom.com> and John(Zongxi) "
  50. "Chen (zongxi@broadcom.com");
  51. MODULE_DESCRIPTION("Broadcom NetXtreme II CNIC Driver");
  52. MODULE_LICENSE("GPL");
  53. MODULE_VERSION(CNIC_MODULE_VERSION);
  54. static LIST_HEAD(cnic_dev_list);
  55. static DEFINE_RWLOCK(cnic_dev_lock);
  56. static DEFINE_MUTEX(cnic_lock);
  57. static struct cnic_ulp_ops *cnic_ulp_tbl[MAX_CNIC_ULP_TYPE];
  58. static int cnic_service_bnx2(void *, void *);
  59. static int cnic_service_bnx2x(void *, void *);
  60. static int cnic_ctl(void *, struct cnic_ctl_info *);
  61. static struct cnic_ops cnic_bnx2_ops = {
  62. .cnic_owner = THIS_MODULE,
  63. .cnic_handler = cnic_service_bnx2,
  64. .cnic_ctl = cnic_ctl,
  65. };
  66. static struct cnic_ops cnic_bnx2x_ops = {
  67. .cnic_owner = THIS_MODULE,
  68. .cnic_handler = cnic_service_bnx2x,
  69. .cnic_ctl = cnic_ctl,
  70. };
  71. static void cnic_shutdown_rings(struct cnic_dev *);
  72. static void cnic_init_rings(struct cnic_dev *);
  73. static int cnic_cm_set_pg(struct cnic_sock *);
  74. static int cnic_uio_open(struct uio_info *uinfo, struct inode *inode)
  75. {
  76. struct cnic_dev *dev = uinfo->priv;
  77. struct cnic_local *cp = dev->cnic_priv;
  78. if (!capable(CAP_NET_ADMIN))
  79. return -EPERM;
  80. if (cp->uio_dev != -1)
  81. return -EBUSY;
  82. rtnl_lock();
  83. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  84. rtnl_unlock();
  85. return -ENODEV;
  86. }
  87. cp->uio_dev = iminor(inode);
  88. cnic_init_rings(dev);
  89. rtnl_unlock();
  90. return 0;
  91. }
  92. static int cnic_uio_close(struct uio_info *uinfo, struct inode *inode)
  93. {
  94. struct cnic_dev *dev = uinfo->priv;
  95. struct cnic_local *cp = dev->cnic_priv;
  96. cnic_shutdown_rings(dev);
  97. cp->uio_dev = -1;
  98. return 0;
  99. }
  100. static inline void cnic_hold(struct cnic_dev *dev)
  101. {
  102. atomic_inc(&dev->ref_count);
  103. }
  104. static inline void cnic_put(struct cnic_dev *dev)
  105. {
  106. atomic_dec(&dev->ref_count);
  107. }
  108. static inline void csk_hold(struct cnic_sock *csk)
  109. {
  110. atomic_inc(&csk->ref_count);
  111. }
  112. static inline void csk_put(struct cnic_sock *csk)
  113. {
  114. atomic_dec(&csk->ref_count);
  115. }
  116. static struct cnic_dev *cnic_from_netdev(struct net_device *netdev)
  117. {
  118. struct cnic_dev *cdev;
  119. read_lock(&cnic_dev_lock);
  120. list_for_each_entry(cdev, &cnic_dev_list, list) {
  121. if (netdev == cdev->netdev) {
  122. cnic_hold(cdev);
  123. read_unlock(&cnic_dev_lock);
  124. return cdev;
  125. }
  126. }
  127. read_unlock(&cnic_dev_lock);
  128. return NULL;
  129. }
  130. static inline void ulp_get(struct cnic_ulp_ops *ulp_ops)
  131. {
  132. atomic_inc(&ulp_ops->ref_count);
  133. }
  134. static inline void ulp_put(struct cnic_ulp_ops *ulp_ops)
  135. {
  136. atomic_dec(&ulp_ops->ref_count);
  137. }
  138. static void cnic_ctx_wr(struct cnic_dev *dev, u32 cid_addr, u32 off, u32 val)
  139. {
  140. struct cnic_local *cp = dev->cnic_priv;
  141. struct cnic_eth_dev *ethdev = cp->ethdev;
  142. struct drv_ctl_info info;
  143. struct drv_ctl_io *io = &info.data.io;
  144. info.cmd = DRV_CTL_CTX_WR_CMD;
  145. io->cid_addr = cid_addr;
  146. io->offset = off;
  147. io->data = val;
  148. ethdev->drv_ctl(dev->netdev, &info);
  149. }
  150. static void cnic_ctx_tbl_wr(struct cnic_dev *dev, u32 off, dma_addr_t addr)
  151. {
  152. struct cnic_local *cp = dev->cnic_priv;
  153. struct cnic_eth_dev *ethdev = cp->ethdev;
  154. struct drv_ctl_info info;
  155. struct drv_ctl_io *io = &info.data.io;
  156. info.cmd = DRV_CTL_CTXTBL_WR_CMD;
  157. io->offset = off;
  158. io->dma_addr = addr;
  159. ethdev->drv_ctl(dev->netdev, &info);
  160. }
  161. static void cnic_ring_ctl(struct cnic_dev *dev, u32 cid, u32 cl_id, int start)
  162. {
  163. struct cnic_local *cp = dev->cnic_priv;
  164. struct cnic_eth_dev *ethdev = cp->ethdev;
  165. struct drv_ctl_info info;
  166. struct drv_ctl_l2_ring *ring = &info.data.ring;
  167. if (start)
  168. info.cmd = DRV_CTL_START_L2_CMD;
  169. else
  170. info.cmd = DRV_CTL_STOP_L2_CMD;
  171. ring->cid = cid;
  172. ring->client_id = cl_id;
  173. ethdev->drv_ctl(dev->netdev, &info);
  174. }
  175. static void cnic_reg_wr_ind(struct cnic_dev *dev, u32 off, u32 val)
  176. {
  177. struct cnic_local *cp = dev->cnic_priv;
  178. struct cnic_eth_dev *ethdev = cp->ethdev;
  179. struct drv_ctl_info info;
  180. struct drv_ctl_io *io = &info.data.io;
  181. info.cmd = DRV_CTL_IO_WR_CMD;
  182. io->offset = off;
  183. io->data = val;
  184. ethdev->drv_ctl(dev->netdev, &info);
  185. }
  186. static u32 cnic_reg_rd_ind(struct cnic_dev *dev, u32 off)
  187. {
  188. struct cnic_local *cp = dev->cnic_priv;
  189. struct cnic_eth_dev *ethdev = cp->ethdev;
  190. struct drv_ctl_info info;
  191. struct drv_ctl_io *io = &info.data.io;
  192. info.cmd = DRV_CTL_IO_RD_CMD;
  193. io->offset = off;
  194. ethdev->drv_ctl(dev->netdev, &info);
  195. return io->data;
  196. }
  197. static int cnic_in_use(struct cnic_sock *csk)
  198. {
  199. return test_bit(SK_F_INUSE, &csk->flags);
  200. }
  201. static void cnic_kwq_completion(struct cnic_dev *dev, u32 count)
  202. {
  203. struct cnic_local *cp = dev->cnic_priv;
  204. struct cnic_eth_dev *ethdev = cp->ethdev;
  205. struct drv_ctl_info info;
  206. info.cmd = DRV_CTL_COMPLETION_CMD;
  207. info.data.comp.comp_count = count;
  208. ethdev->drv_ctl(dev->netdev, &info);
  209. }
  210. static int cnic_get_l5_cid(struct cnic_local *cp, u32 cid, u32 *l5_cid)
  211. {
  212. u32 i;
  213. for (i = 0; i < MAX_ISCSI_TBL_SZ; i++) {
  214. if (cp->ctx_tbl[i].cid == cid) {
  215. *l5_cid = i;
  216. return 0;
  217. }
  218. }
  219. return -EINVAL;
  220. }
  221. static int cnic_send_nlmsg(struct cnic_local *cp, u32 type,
  222. struct cnic_sock *csk)
  223. {
  224. struct iscsi_path path_req;
  225. char *buf = NULL;
  226. u16 len = 0;
  227. u32 msg_type = ISCSI_KEVENT_IF_DOWN;
  228. struct cnic_ulp_ops *ulp_ops;
  229. if (cp->uio_dev == -1)
  230. return -ENODEV;
  231. if (csk) {
  232. len = sizeof(path_req);
  233. buf = (char *) &path_req;
  234. memset(&path_req, 0, len);
  235. msg_type = ISCSI_KEVENT_PATH_REQ;
  236. path_req.handle = (u64) csk->l5_cid;
  237. if (test_bit(SK_F_IPV6, &csk->flags)) {
  238. memcpy(&path_req.dst.v6_addr, &csk->dst_ip[0],
  239. sizeof(struct in6_addr));
  240. path_req.ip_addr_len = 16;
  241. } else {
  242. memcpy(&path_req.dst.v4_addr, &csk->dst_ip[0],
  243. sizeof(struct in_addr));
  244. path_req.ip_addr_len = 4;
  245. }
  246. path_req.vlan_id = csk->vlan_id;
  247. path_req.pmtu = csk->mtu;
  248. }
  249. rcu_read_lock();
  250. ulp_ops = rcu_dereference(cnic_ulp_tbl[CNIC_ULP_ISCSI]);
  251. if (ulp_ops)
  252. ulp_ops->iscsi_nl_send_msg(cp->dev, msg_type, buf, len);
  253. rcu_read_unlock();
  254. return 0;
  255. }
  256. static int cnic_iscsi_nl_msg_recv(struct cnic_dev *dev, u32 msg_type,
  257. char *buf, u16 len)
  258. {
  259. int rc = -EINVAL;
  260. switch (msg_type) {
  261. case ISCSI_UEVENT_PATH_UPDATE: {
  262. struct cnic_local *cp;
  263. u32 l5_cid;
  264. struct cnic_sock *csk;
  265. struct iscsi_path *path_resp;
  266. if (len < sizeof(*path_resp))
  267. break;
  268. path_resp = (struct iscsi_path *) buf;
  269. cp = dev->cnic_priv;
  270. l5_cid = (u32) path_resp->handle;
  271. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  272. break;
  273. csk = &cp->csk_tbl[l5_cid];
  274. csk_hold(csk);
  275. if (cnic_in_use(csk)) {
  276. memcpy(csk->ha, path_resp->mac_addr, 6);
  277. if (test_bit(SK_F_IPV6, &csk->flags))
  278. memcpy(&csk->src_ip[0], &path_resp->src.v6_addr,
  279. sizeof(struct in6_addr));
  280. else
  281. memcpy(&csk->src_ip[0], &path_resp->src.v4_addr,
  282. sizeof(struct in_addr));
  283. if (is_valid_ether_addr(csk->ha))
  284. cnic_cm_set_pg(csk);
  285. }
  286. csk_put(csk);
  287. rc = 0;
  288. }
  289. }
  290. return rc;
  291. }
  292. static int cnic_offld_prep(struct cnic_sock *csk)
  293. {
  294. if (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  295. return 0;
  296. if (!test_bit(SK_F_CONNECT_START, &csk->flags)) {
  297. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  298. return 0;
  299. }
  300. return 1;
  301. }
  302. static int cnic_close_prep(struct cnic_sock *csk)
  303. {
  304. clear_bit(SK_F_CONNECT_START, &csk->flags);
  305. smp_mb__after_clear_bit();
  306. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  307. while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  308. msleep(1);
  309. return 1;
  310. }
  311. return 0;
  312. }
  313. static int cnic_abort_prep(struct cnic_sock *csk)
  314. {
  315. clear_bit(SK_F_CONNECT_START, &csk->flags);
  316. smp_mb__after_clear_bit();
  317. while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  318. msleep(1);
  319. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  320. csk->state = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  321. return 1;
  322. }
  323. return 0;
  324. }
  325. static void cnic_uio_stop(void)
  326. {
  327. struct cnic_dev *dev;
  328. read_lock(&cnic_dev_lock);
  329. list_for_each_entry(dev, &cnic_dev_list, list) {
  330. struct cnic_local *cp = dev->cnic_priv;
  331. if (cp->cnic_uinfo)
  332. cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
  333. }
  334. read_unlock(&cnic_dev_lock);
  335. }
  336. int cnic_register_driver(int ulp_type, struct cnic_ulp_ops *ulp_ops)
  337. {
  338. struct cnic_dev *dev;
  339. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  340. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  341. return -EINVAL;
  342. }
  343. mutex_lock(&cnic_lock);
  344. if (cnic_ulp_tbl[ulp_type]) {
  345. pr_err("%s: Type %d has already been registered\n",
  346. __func__, ulp_type);
  347. mutex_unlock(&cnic_lock);
  348. return -EBUSY;
  349. }
  350. read_lock(&cnic_dev_lock);
  351. list_for_each_entry(dev, &cnic_dev_list, list) {
  352. struct cnic_local *cp = dev->cnic_priv;
  353. clear_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]);
  354. }
  355. read_unlock(&cnic_dev_lock);
  356. atomic_set(&ulp_ops->ref_count, 0);
  357. rcu_assign_pointer(cnic_ulp_tbl[ulp_type], ulp_ops);
  358. mutex_unlock(&cnic_lock);
  359. /* Prevent race conditions with netdev_event */
  360. rtnl_lock();
  361. read_lock(&cnic_dev_lock);
  362. list_for_each_entry(dev, &cnic_dev_list, list) {
  363. struct cnic_local *cp = dev->cnic_priv;
  364. if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]))
  365. ulp_ops->cnic_init(dev);
  366. }
  367. read_unlock(&cnic_dev_lock);
  368. rtnl_unlock();
  369. return 0;
  370. }
  371. int cnic_unregister_driver(int ulp_type)
  372. {
  373. struct cnic_dev *dev;
  374. struct cnic_ulp_ops *ulp_ops;
  375. int i = 0;
  376. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  377. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  378. return -EINVAL;
  379. }
  380. mutex_lock(&cnic_lock);
  381. ulp_ops = cnic_ulp_tbl[ulp_type];
  382. if (!ulp_ops) {
  383. pr_err("%s: Type %d has not been registered\n",
  384. __func__, ulp_type);
  385. goto out_unlock;
  386. }
  387. read_lock(&cnic_dev_lock);
  388. list_for_each_entry(dev, &cnic_dev_list, list) {
  389. struct cnic_local *cp = dev->cnic_priv;
  390. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  391. pr_err("%s: Type %d still has devices registered\n",
  392. __func__, ulp_type);
  393. read_unlock(&cnic_dev_lock);
  394. goto out_unlock;
  395. }
  396. }
  397. read_unlock(&cnic_dev_lock);
  398. if (ulp_type == CNIC_ULP_ISCSI)
  399. cnic_uio_stop();
  400. rcu_assign_pointer(cnic_ulp_tbl[ulp_type], NULL);
  401. mutex_unlock(&cnic_lock);
  402. synchronize_rcu();
  403. while ((atomic_read(&ulp_ops->ref_count) != 0) && (i < 20)) {
  404. msleep(100);
  405. i++;
  406. }
  407. if (atomic_read(&ulp_ops->ref_count) != 0)
  408. netdev_warn(dev->netdev, "Failed waiting for ref count to go to zero\n");
  409. return 0;
  410. out_unlock:
  411. mutex_unlock(&cnic_lock);
  412. return -EINVAL;
  413. }
  414. static int cnic_start_hw(struct cnic_dev *);
  415. static void cnic_stop_hw(struct cnic_dev *);
  416. static int cnic_register_device(struct cnic_dev *dev, int ulp_type,
  417. void *ulp_ctx)
  418. {
  419. struct cnic_local *cp = dev->cnic_priv;
  420. struct cnic_ulp_ops *ulp_ops;
  421. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  422. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  423. return -EINVAL;
  424. }
  425. mutex_lock(&cnic_lock);
  426. if (cnic_ulp_tbl[ulp_type] == NULL) {
  427. pr_err("%s: Driver with type %d has not been registered\n",
  428. __func__, ulp_type);
  429. mutex_unlock(&cnic_lock);
  430. return -EAGAIN;
  431. }
  432. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  433. pr_err("%s: Type %d has already been registered to this device\n",
  434. __func__, ulp_type);
  435. mutex_unlock(&cnic_lock);
  436. return -EBUSY;
  437. }
  438. clear_bit(ULP_F_START, &cp->ulp_flags[ulp_type]);
  439. cp->ulp_handle[ulp_type] = ulp_ctx;
  440. ulp_ops = cnic_ulp_tbl[ulp_type];
  441. rcu_assign_pointer(cp->ulp_ops[ulp_type], ulp_ops);
  442. cnic_hold(dev);
  443. if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
  444. if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[ulp_type]))
  445. ulp_ops->cnic_start(cp->ulp_handle[ulp_type]);
  446. mutex_unlock(&cnic_lock);
  447. return 0;
  448. }
  449. EXPORT_SYMBOL(cnic_register_driver);
  450. static int cnic_unregister_device(struct cnic_dev *dev, int ulp_type)
  451. {
  452. struct cnic_local *cp = dev->cnic_priv;
  453. int i = 0;
  454. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  455. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  456. return -EINVAL;
  457. }
  458. mutex_lock(&cnic_lock);
  459. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  460. rcu_assign_pointer(cp->ulp_ops[ulp_type], NULL);
  461. cnic_put(dev);
  462. } else {
  463. pr_err("%s: device not registered to this ulp type %d\n",
  464. __func__, ulp_type);
  465. mutex_unlock(&cnic_lock);
  466. return -EINVAL;
  467. }
  468. mutex_unlock(&cnic_lock);
  469. synchronize_rcu();
  470. while (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]) &&
  471. i < 20) {
  472. msleep(100);
  473. i++;
  474. }
  475. if (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]))
  476. netdev_warn(dev->netdev, "Failed waiting for ULP up call to complete\n");
  477. return 0;
  478. }
  479. EXPORT_SYMBOL(cnic_unregister_driver);
  480. static int cnic_init_id_tbl(struct cnic_id_tbl *id_tbl, u32 size, u32 start_id)
  481. {
  482. id_tbl->start = start_id;
  483. id_tbl->max = size;
  484. id_tbl->next = 0;
  485. spin_lock_init(&id_tbl->lock);
  486. id_tbl->table = kzalloc(DIV_ROUND_UP(size, 32) * 4, GFP_KERNEL);
  487. if (!id_tbl->table)
  488. return -ENOMEM;
  489. return 0;
  490. }
  491. static void cnic_free_id_tbl(struct cnic_id_tbl *id_tbl)
  492. {
  493. kfree(id_tbl->table);
  494. id_tbl->table = NULL;
  495. }
  496. static int cnic_alloc_id(struct cnic_id_tbl *id_tbl, u32 id)
  497. {
  498. int ret = -1;
  499. id -= id_tbl->start;
  500. if (id >= id_tbl->max)
  501. return ret;
  502. spin_lock(&id_tbl->lock);
  503. if (!test_bit(id, id_tbl->table)) {
  504. set_bit(id, id_tbl->table);
  505. ret = 0;
  506. }
  507. spin_unlock(&id_tbl->lock);
  508. return ret;
  509. }
  510. /* Returns -1 if not successful */
  511. static u32 cnic_alloc_new_id(struct cnic_id_tbl *id_tbl)
  512. {
  513. u32 id;
  514. spin_lock(&id_tbl->lock);
  515. id = find_next_zero_bit(id_tbl->table, id_tbl->max, id_tbl->next);
  516. if (id >= id_tbl->max) {
  517. id = -1;
  518. if (id_tbl->next != 0) {
  519. id = find_first_zero_bit(id_tbl->table, id_tbl->next);
  520. if (id >= id_tbl->next)
  521. id = -1;
  522. }
  523. }
  524. if (id < id_tbl->max) {
  525. set_bit(id, id_tbl->table);
  526. id_tbl->next = (id + 1) & (id_tbl->max - 1);
  527. id += id_tbl->start;
  528. }
  529. spin_unlock(&id_tbl->lock);
  530. return id;
  531. }
  532. static void cnic_free_id(struct cnic_id_tbl *id_tbl, u32 id)
  533. {
  534. if (id == -1)
  535. return;
  536. id -= id_tbl->start;
  537. if (id >= id_tbl->max)
  538. return;
  539. clear_bit(id, id_tbl->table);
  540. }
  541. static void cnic_free_dma(struct cnic_dev *dev, struct cnic_dma *dma)
  542. {
  543. int i;
  544. if (!dma->pg_arr)
  545. return;
  546. for (i = 0; i < dma->num_pages; i++) {
  547. if (dma->pg_arr[i]) {
  548. dma_free_coherent(&dev->pcidev->dev, BCM_PAGE_SIZE,
  549. dma->pg_arr[i], dma->pg_map_arr[i]);
  550. dma->pg_arr[i] = NULL;
  551. }
  552. }
  553. if (dma->pgtbl) {
  554. dma_free_coherent(&dev->pcidev->dev, dma->pgtbl_size,
  555. dma->pgtbl, dma->pgtbl_map);
  556. dma->pgtbl = NULL;
  557. }
  558. kfree(dma->pg_arr);
  559. dma->pg_arr = NULL;
  560. dma->num_pages = 0;
  561. }
  562. static void cnic_setup_page_tbl(struct cnic_dev *dev, struct cnic_dma *dma)
  563. {
  564. int i;
  565. u32 *page_table = dma->pgtbl;
  566. for (i = 0; i < dma->num_pages; i++) {
  567. /* Each entry needs to be in big endian format. */
  568. *page_table = (u32) ((u64) dma->pg_map_arr[i] >> 32);
  569. page_table++;
  570. *page_table = (u32) dma->pg_map_arr[i];
  571. page_table++;
  572. }
  573. }
  574. static void cnic_setup_page_tbl_le(struct cnic_dev *dev, struct cnic_dma *dma)
  575. {
  576. int i;
  577. u32 *page_table = dma->pgtbl;
  578. for (i = 0; i < dma->num_pages; i++) {
  579. /* Each entry needs to be in little endian format. */
  580. *page_table = dma->pg_map_arr[i] & 0xffffffff;
  581. page_table++;
  582. *page_table = (u32) ((u64) dma->pg_map_arr[i] >> 32);
  583. page_table++;
  584. }
  585. }
  586. static int cnic_alloc_dma(struct cnic_dev *dev, struct cnic_dma *dma,
  587. int pages, int use_pg_tbl)
  588. {
  589. int i, size;
  590. struct cnic_local *cp = dev->cnic_priv;
  591. size = pages * (sizeof(void *) + sizeof(dma_addr_t));
  592. dma->pg_arr = kzalloc(size, GFP_ATOMIC);
  593. if (dma->pg_arr == NULL)
  594. return -ENOMEM;
  595. dma->pg_map_arr = (dma_addr_t *) (dma->pg_arr + pages);
  596. dma->num_pages = pages;
  597. for (i = 0; i < pages; i++) {
  598. dma->pg_arr[i] = dma_alloc_coherent(&dev->pcidev->dev,
  599. BCM_PAGE_SIZE,
  600. &dma->pg_map_arr[i],
  601. GFP_ATOMIC);
  602. if (dma->pg_arr[i] == NULL)
  603. goto error;
  604. }
  605. if (!use_pg_tbl)
  606. return 0;
  607. dma->pgtbl_size = ((pages * 8) + BCM_PAGE_SIZE - 1) &
  608. ~(BCM_PAGE_SIZE - 1);
  609. dma->pgtbl = dma_alloc_coherent(&dev->pcidev->dev, dma->pgtbl_size,
  610. &dma->pgtbl_map, GFP_ATOMIC);
  611. if (dma->pgtbl == NULL)
  612. goto error;
  613. cp->setup_pgtbl(dev, dma);
  614. return 0;
  615. error:
  616. cnic_free_dma(dev, dma);
  617. return -ENOMEM;
  618. }
  619. static void cnic_free_context(struct cnic_dev *dev)
  620. {
  621. struct cnic_local *cp = dev->cnic_priv;
  622. int i;
  623. for (i = 0; i < cp->ctx_blks; i++) {
  624. if (cp->ctx_arr[i].ctx) {
  625. dma_free_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
  626. cp->ctx_arr[i].ctx,
  627. cp->ctx_arr[i].mapping);
  628. cp->ctx_arr[i].ctx = NULL;
  629. }
  630. }
  631. }
  632. static void cnic_free_resc(struct cnic_dev *dev)
  633. {
  634. struct cnic_local *cp = dev->cnic_priv;
  635. int i = 0;
  636. if (cp->cnic_uinfo) {
  637. while (cp->uio_dev != -1 && i < 15) {
  638. msleep(100);
  639. i++;
  640. }
  641. uio_unregister_device(cp->cnic_uinfo);
  642. kfree(cp->cnic_uinfo);
  643. cp->cnic_uinfo = NULL;
  644. }
  645. if (cp->l2_buf) {
  646. dma_free_coherent(&dev->pcidev->dev, cp->l2_buf_size,
  647. cp->l2_buf, cp->l2_buf_map);
  648. cp->l2_buf = NULL;
  649. }
  650. if (cp->l2_ring) {
  651. dma_free_coherent(&dev->pcidev->dev, cp->l2_ring_size,
  652. cp->l2_ring, cp->l2_ring_map);
  653. cp->l2_ring = NULL;
  654. }
  655. cnic_free_context(dev);
  656. kfree(cp->ctx_arr);
  657. cp->ctx_arr = NULL;
  658. cp->ctx_blks = 0;
  659. cnic_free_dma(dev, &cp->gbl_buf_info);
  660. cnic_free_dma(dev, &cp->conn_buf_info);
  661. cnic_free_dma(dev, &cp->kwq_info);
  662. cnic_free_dma(dev, &cp->kwq_16_data_info);
  663. cnic_free_dma(dev, &cp->kcq_info);
  664. kfree(cp->iscsi_tbl);
  665. cp->iscsi_tbl = NULL;
  666. kfree(cp->ctx_tbl);
  667. cp->ctx_tbl = NULL;
  668. cnic_free_id_tbl(&cp->cid_tbl);
  669. }
  670. static int cnic_alloc_context(struct cnic_dev *dev)
  671. {
  672. struct cnic_local *cp = dev->cnic_priv;
  673. if (CHIP_NUM(cp) == CHIP_NUM_5709) {
  674. int i, k, arr_size;
  675. cp->ctx_blk_size = BCM_PAGE_SIZE;
  676. cp->cids_per_blk = BCM_PAGE_SIZE / 128;
  677. arr_size = BNX2_MAX_CID / cp->cids_per_blk *
  678. sizeof(struct cnic_ctx);
  679. cp->ctx_arr = kzalloc(arr_size, GFP_KERNEL);
  680. if (cp->ctx_arr == NULL)
  681. return -ENOMEM;
  682. k = 0;
  683. for (i = 0; i < 2; i++) {
  684. u32 j, reg, off, lo, hi;
  685. if (i == 0)
  686. off = BNX2_PG_CTX_MAP;
  687. else
  688. off = BNX2_ISCSI_CTX_MAP;
  689. reg = cnic_reg_rd_ind(dev, off);
  690. lo = reg >> 16;
  691. hi = reg & 0xffff;
  692. for (j = lo; j < hi; j += cp->cids_per_blk, k++)
  693. cp->ctx_arr[k].cid = j;
  694. }
  695. cp->ctx_blks = k;
  696. if (cp->ctx_blks >= (BNX2_MAX_CID / cp->cids_per_blk)) {
  697. cp->ctx_blks = 0;
  698. return -ENOMEM;
  699. }
  700. for (i = 0; i < cp->ctx_blks; i++) {
  701. cp->ctx_arr[i].ctx =
  702. dma_alloc_coherent(&dev->pcidev->dev,
  703. BCM_PAGE_SIZE,
  704. &cp->ctx_arr[i].mapping,
  705. GFP_KERNEL);
  706. if (cp->ctx_arr[i].ctx == NULL)
  707. return -ENOMEM;
  708. }
  709. }
  710. return 0;
  711. }
  712. static int cnic_alloc_l2_rings(struct cnic_dev *dev, int pages)
  713. {
  714. struct cnic_local *cp = dev->cnic_priv;
  715. cp->l2_ring_size = pages * BCM_PAGE_SIZE;
  716. cp->l2_ring = dma_alloc_coherent(&dev->pcidev->dev, cp->l2_ring_size,
  717. &cp->l2_ring_map,
  718. GFP_KERNEL | __GFP_COMP);
  719. if (!cp->l2_ring)
  720. return -ENOMEM;
  721. cp->l2_buf_size = (cp->l2_rx_ring_size + 1) * cp->l2_single_buf_size;
  722. cp->l2_buf_size = PAGE_ALIGN(cp->l2_buf_size);
  723. cp->l2_buf = dma_alloc_coherent(&dev->pcidev->dev, cp->l2_buf_size,
  724. &cp->l2_buf_map,
  725. GFP_KERNEL | __GFP_COMP);
  726. if (!cp->l2_buf)
  727. return -ENOMEM;
  728. return 0;
  729. }
  730. static int cnic_alloc_uio(struct cnic_dev *dev) {
  731. struct cnic_local *cp = dev->cnic_priv;
  732. struct uio_info *uinfo;
  733. int ret;
  734. uinfo = kzalloc(sizeof(*uinfo), GFP_ATOMIC);
  735. if (!uinfo)
  736. return -ENOMEM;
  737. uinfo->mem[0].addr = dev->netdev->base_addr;
  738. uinfo->mem[0].internal_addr = dev->regview;
  739. uinfo->mem[0].size = dev->netdev->mem_end - dev->netdev->mem_start;
  740. uinfo->mem[0].memtype = UIO_MEM_PHYS;
  741. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  742. uinfo->mem[1].addr = (unsigned long) cp->status_blk & PAGE_MASK;
  743. if (cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
  744. uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE * 9;
  745. else
  746. uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE;
  747. uinfo->name = "bnx2_cnic";
  748. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  749. uinfo->mem[1].addr = (unsigned long) cp->bnx2x_def_status_blk &
  750. PAGE_MASK;
  751. uinfo->mem[1].size = sizeof(struct host_def_status_block);
  752. uinfo->name = "bnx2x_cnic";
  753. }
  754. uinfo->mem[1].memtype = UIO_MEM_LOGICAL;
  755. uinfo->mem[2].addr = (unsigned long) cp->l2_ring;
  756. uinfo->mem[2].size = cp->l2_ring_size;
  757. uinfo->mem[2].memtype = UIO_MEM_LOGICAL;
  758. uinfo->mem[3].addr = (unsigned long) cp->l2_buf;
  759. uinfo->mem[3].size = cp->l2_buf_size;
  760. uinfo->mem[3].memtype = UIO_MEM_LOGICAL;
  761. uinfo->version = CNIC_MODULE_VERSION;
  762. uinfo->irq = UIO_IRQ_CUSTOM;
  763. uinfo->open = cnic_uio_open;
  764. uinfo->release = cnic_uio_close;
  765. uinfo->priv = dev;
  766. ret = uio_register_device(&dev->pcidev->dev, uinfo);
  767. if (ret) {
  768. kfree(uinfo);
  769. return ret;
  770. }
  771. cp->cnic_uinfo = uinfo;
  772. return 0;
  773. }
  774. static int cnic_alloc_bnx2_resc(struct cnic_dev *dev)
  775. {
  776. struct cnic_local *cp = dev->cnic_priv;
  777. int ret;
  778. ret = cnic_alloc_dma(dev, &cp->kwq_info, KWQ_PAGE_CNT, 1);
  779. if (ret)
  780. goto error;
  781. cp->kwq = (struct kwqe **) cp->kwq_info.pg_arr;
  782. ret = cnic_alloc_dma(dev, &cp->kcq_info, KCQ_PAGE_CNT, 1);
  783. if (ret)
  784. goto error;
  785. cp->kcq = (struct kcqe **) cp->kcq_info.pg_arr;
  786. ret = cnic_alloc_context(dev);
  787. if (ret)
  788. goto error;
  789. ret = cnic_alloc_l2_rings(dev, 2);
  790. if (ret)
  791. goto error;
  792. ret = cnic_alloc_uio(dev);
  793. if (ret)
  794. goto error;
  795. return 0;
  796. error:
  797. cnic_free_resc(dev);
  798. return ret;
  799. }
  800. static int cnic_alloc_bnx2x_context(struct cnic_dev *dev)
  801. {
  802. struct cnic_local *cp = dev->cnic_priv;
  803. struct cnic_eth_dev *ethdev = cp->ethdev;
  804. int ctx_blk_size = cp->ethdev->ctx_blk_size;
  805. int total_mem, blks, i, cid_space;
  806. if (BNX2X_ISCSI_START_CID < ethdev->starting_cid)
  807. return -EINVAL;
  808. cid_space = MAX_ISCSI_TBL_SZ +
  809. (BNX2X_ISCSI_START_CID - ethdev->starting_cid);
  810. total_mem = BNX2X_CONTEXT_MEM_SIZE * cid_space;
  811. blks = total_mem / ctx_blk_size;
  812. if (total_mem % ctx_blk_size)
  813. blks++;
  814. if (blks > cp->ethdev->ctx_tbl_len)
  815. return -ENOMEM;
  816. cp->ctx_arr = kzalloc(blks * sizeof(struct cnic_ctx), GFP_KERNEL);
  817. if (cp->ctx_arr == NULL)
  818. return -ENOMEM;
  819. cp->ctx_blks = blks;
  820. cp->ctx_blk_size = ctx_blk_size;
  821. if (BNX2X_CHIP_IS_E1H(cp->chip_id))
  822. cp->ctx_align = 0;
  823. else
  824. cp->ctx_align = ctx_blk_size;
  825. cp->cids_per_blk = ctx_blk_size / BNX2X_CONTEXT_MEM_SIZE;
  826. for (i = 0; i < blks; i++) {
  827. cp->ctx_arr[i].ctx =
  828. dma_alloc_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
  829. &cp->ctx_arr[i].mapping,
  830. GFP_KERNEL);
  831. if (cp->ctx_arr[i].ctx == NULL)
  832. return -ENOMEM;
  833. if (cp->ctx_align && cp->ctx_blk_size == ctx_blk_size) {
  834. if (cp->ctx_arr[i].mapping & (cp->ctx_align - 1)) {
  835. cnic_free_context(dev);
  836. cp->ctx_blk_size += cp->ctx_align;
  837. i = -1;
  838. continue;
  839. }
  840. }
  841. }
  842. return 0;
  843. }
  844. static int cnic_alloc_bnx2x_resc(struct cnic_dev *dev)
  845. {
  846. struct cnic_local *cp = dev->cnic_priv;
  847. int i, j, n, ret, pages;
  848. struct cnic_dma *kwq_16_dma = &cp->kwq_16_data_info;
  849. cp->iscsi_tbl = kzalloc(sizeof(struct cnic_iscsi) * MAX_ISCSI_TBL_SZ,
  850. GFP_KERNEL);
  851. if (!cp->iscsi_tbl)
  852. goto error;
  853. cp->ctx_tbl = kzalloc(sizeof(struct cnic_context) *
  854. MAX_CNIC_L5_CONTEXT, GFP_KERNEL);
  855. if (!cp->ctx_tbl)
  856. goto error;
  857. for (i = 0; i < MAX_ISCSI_TBL_SZ; i++) {
  858. cp->ctx_tbl[i].proto.iscsi = &cp->iscsi_tbl[i];
  859. cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_ISCSI;
  860. }
  861. pages = PAGE_ALIGN(MAX_CNIC_L5_CONTEXT * CNIC_KWQ16_DATA_SIZE) /
  862. PAGE_SIZE;
  863. ret = cnic_alloc_dma(dev, kwq_16_dma, pages, 0);
  864. if (ret)
  865. return -ENOMEM;
  866. n = PAGE_SIZE / CNIC_KWQ16_DATA_SIZE;
  867. for (i = 0, j = 0; i < MAX_ISCSI_TBL_SZ; i++) {
  868. long off = CNIC_KWQ16_DATA_SIZE * (i % n);
  869. cp->ctx_tbl[i].kwqe_data = kwq_16_dma->pg_arr[j] + off;
  870. cp->ctx_tbl[i].kwqe_data_mapping = kwq_16_dma->pg_map_arr[j] +
  871. off;
  872. if ((i % n) == (n - 1))
  873. j++;
  874. }
  875. ret = cnic_alloc_dma(dev, &cp->kcq_info, KCQ_PAGE_CNT, 0);
  876. if (ret)
  877. goto error;
  878. cp->kcq = (struct kcqe **) cp->kcq_info.pg_arr;
  879. for (i = 0; i < KCQ_PAGE_CNT; i++) {
  880. struct bnx2x_bd_chain_next *next =
  881. (struct bnx2x_bd_chain_next *)
  882. &cp->kcq[i][MAX_KCQE_CNT];
  883. int j = i + 1;
  884. if (j >= KCQ_PAGE_CNT)
  885. j = 0;
  886. next->addr_hi = (u64) cp->kcq_info.pg_map_arr[j] >> 32;
  887. next->addr_lo = cp->kcq_info.pg_map_arr[j] & 0xffffffff;
  888. }
  889. pages = PAGE_ALIGN(BNX2X_ISCSI_NUM_CONNECTIONS *
  890. BNX2X_ISCSI_CONN_BUF_SIZE) / PAGE_SIZE;
  891. ret = cnic_alloc_dma(dev, &cp->conn_buf_info, pages, 1);
  892. if (ret)
  893. goto error;
  894. pages = PAGE_ALIGN(BNX2X_ISCSI_GLB_BUF_SIZE) / PAGE_SIZE;
  895. ret = cnic_alloc_dma(dev, &cp->gbl_buf_info, pages, 0);
  896. if (ret)
  897. goto error;
  898. ret = cnic_alloc_bnx2x_context(dev);
  899. if (ret)
  900. goto error;
  901. cp->bnx2x_status_blk = cp->status_blk;
  902. cp->bnx2x_def_status_blk = cp->ethdev->irq_arr[1].status_blk;
  903. memset(cp->bnx2x_status_blk, 0, sizeof(struct host_status_block));
  904. cp->l2_rx_ring_size = 15;
  905. ret = cnic_alloc_l2_rings(dev, 4);
  906. if (ret)
  907. goto error;
  908. ret = cnic_alloc_uio(dev);
  909. if (ret)
  910. goto error;
  911. return 0;
  912. error:
  913. cnic_free_resc(dev);
  914. return -ENOMEM;
  915. }
  916. static inline u32 cnic_kwq_avail(struct cnic_local *cp)
  917. {
  918. return cp->max_kwq_idx -
  919. ((cp->kwq_prod_idx - cp->kwq_con_idx) & cp->max_kwq_idx);
  920. }
  921. static int cnic_submit_bnx2_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
  922. u32 num_wqes)
  923. {
  924. struct cnic_local *cp = dev->cnic_priv;
  925. struct kwqe *prod_qe;
  926. u16 prod, sw_prod, i;
  927. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  928. return -EAGAIN; /* bnx2 is down */
  929. spin_lock_bh(&cp->cnic_ulp_lock);
  930. if (num_wqes > cnic_kwq_avail(cp) &&
  931. !(cp->cnic_local_flags & CNIC_LCL_FL_KWQ_INIT)) {
  932. spin_unlock_bh(&cp->cnic_ulp_lock);
  933. return -EAGAIN;
  934. }
  935. cp->cnic_local_flags &= ~CNIC_LCL_FL_KWQ_INIT;
  936. prod = cp->kwq_prod_idx;
  937. sw_prod = prod & MAX_KWQ_IDX;
  938. for (i = 0; i < num_wqes; i++) {
  939. prod_qe = &cp->kwq[KWQ_PG(sw_prod)][KWQ_IDX(sw_prod)];
  940. memcpy(prod_qe, wqes[i], sizeof(struct kwqe));
  941. prod++;
  942. sw_prod = prod & MAX_KWQ_IDX;
  943. }
  944. cp->kwq_prod_idx = prod;
  945. CNIC_WR16(dev, cp->kwq_io_addr, cp->kwq_prod_idx);
  946. spin_unlock_bh(&cp->cnic_ulp_lock);
  947. return 0;
  948. }
  949. static void *cnic_get_kwqe_16_data(struct cnic_local *cp, u32 l5_cid,
  950. union l5cm_specific_data *l5_data)
  951. {
  952. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  953. dma_addr_t map;
  954. map = ctx->kwqe_data_mapping;
  955. l5_data->phy_address.lo = (u64) map & 0xffffffff;
  956. l5_data->phy_address.hi = (u64) map >> 32;
  957. return ctx->kwqe_data;
  958. }
  959. static int cnic_submit_kwqe_16(struct cnic_dev *dev, u32 cmd, u32 cid,
  960. u32 type, union l5cm_specific_data *l5_data)
  961. {
  962. struct cnic_local *cp = dev->cnic_priv;
  963. struct l5cm_spe kwqe;
  964. struct kwqe_16 *kwq[1];
  965. int ret;
  966. kwqe.hdr.conn_and_cmd_data =
  967. cpu_to_le32(((cmd << SPE_HDR_CMD_ID_SHIFT) |
  968. BNX2X_HW_CID(cid, cp->func)));
  969. kwqe.hdr.type = cpu_to_le16(type);
  970. kwqe.hdr.reserved = 0;
  971. kwqe.data.phy_address.lo = cpu_to_le32(l5_data->phy_address.lo);
  972. kwqe.data.phy_address.hi = cpu_to_le32(l5_data->phy_address.hi);
  973. kwq[0] = (struct kwqe_16 *) &kwqe;
  974. spin_lock_bh(&cp->cnic_ulp_lock);
  975. ret = cp->ethdev->drv_submit_kwqes_16(dev->netdev, kwq, 1);
  976. spin_unlock_bh(&cp->cnic_ulp_lock);
  977. if (ret == 1)
  978. return 0;
  979. return -EBUSY;
  980. }
  981. static void cnic_reply_bnx2x_kcqes(struct cnic_dev *dev, int ulp_type,
  982. struct kcqe *cqes[], u32 num_cqes)
  983. {
  984. struct cnic_local *cp = dev->cnic_priv;
  985. struct cnic_ulp_ops *ulp_ops;
  986. rcu_read_lock();
  987. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  988. if (likely(ulp_ops)) {
  989. ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
  990. cqes, num_cqes);
  991. }
  992. rcu_read_unlock();
  993. }
  994. static int cnic_bnx2x_iscsi_init1(struct cnic_dev *dev, struct kwqe *kwqe)
  995. {
  996. struct cnic_local *cp = dev->cnic_priv;
  997. struct iscsi_kwqe_init1 *req1 = (struct iscsi_kwqe_init1 *) kwqe;
  998. int func = cp->func, pages;
  999. int hq_bds;
  1000. cp->num_iscsi_tasks = req1->num_tasks_per_conn;
  1001. cp->num_ccells = req1->num_ccells_per_conn;
  1002. cp->task_array_size = BNX2X_ISCSI_TASK_CONTEXT_SIZE *
  1003. cp->num_iscsi_tasks;
  1004. cp->r2tq_size = cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS *
  1005. BNX2X_ISCSI_R2TQE_SIZE;
  1006. cp->hq_size = cp->num_ccells * BNX2X_ISCSI_HQ_BD_SIZE;
  1007. pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE;
  1008. hq_bds = pages * (PAGE_SIZE / BNX2X_ISCSI_HQ_BD_SIZE);
  1009. cp->num_cqs = req1->num_cqs;
  1010. if (!dev->max_iscsi_conn)
  1011. return 0;
  1012. /* init Tstorm RAM */
  1013. CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_RQ_SIZE_OFFSET(func),
  1014. req1->rq_num_wqes);
  1015. CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_PAGE_SIZE_OFFSET(func),
  1016. PAGE_SIZE);
  1017. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1018. TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(func), PAGE_SHIFT);
  1019. CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
  1020. TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(func),
  1021. req1->num_tasks_per_conn);
  1022. /* init Ustorm RAM */
  1023. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1024. USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(func),
  1025. req1->rq_buffer_size);
  1026. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_PAGE_SIZE_OFFSET(func),
  1027. PAGE_SIZE);
  1028. CNIC_WR8(dev, BAR_USTRORM_INTMEM +
  1029. USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(func), PAGE_SHIFT);
  1030. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1031. USTORM_ISCSI_NUM_OF_TASKS_OFFSET(func),
  1032. req1->num_tasks_per_conn);
  1033. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_RQ_SIZE_OFFSET(func),
  1034. req1->rq_num_wqes);
  1035. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_CQ_SIZE_OFFSET(func),
  1036. req1->cq_num_wqes);
  1037. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_R2TQ_SIZE_OFFSET(func),
  1038. cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
  1039. /* init Xstorm RAM */
  1040. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_PAGE_SIZE_OFFSET(func),
  1041. PAGE_SIZE);
  1042. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1043. XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(func), PAGE_SHIFT);
  1044. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  1045. XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(func),
  1046. req1->num_tasks_per_conn);
  1047. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_HQ_SIZE_OFFSET(func),
  1048. hq_bds);
  1049. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_SQ_SIZE_OFFSET(func),
  1050. req1->num_tasks_per_conn);
  1051. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_R2TQ_SIZE_OFFSET(func),
  1052. cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
  1053. /* init Cstorm RAM */
  1054. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_PAGE_SIZE_OFFSET(func),
  1055. PAGE_SIZE);
  1056. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  1057. CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(func), PAGE_SHIFT);
  1058. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  1059. CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(func),
  1060. req1->num_tasks_per_conn);
  1061. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_CQ_SIZE_OFFSET(func),
  1062. req1->cq_num_wqes);
  1063. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_HQ_SIZE_OFFSET(func),
  1064. hq_bds);
  1065. return 0;
  1066. }
  1067. static int cnic_bnx2x_iscsi_init2(struct cnic_dev *dev, struct kwqe *kwqe)
  1068. {
  1069. struct iscsi_kwqe_init2 *req2 = (struct iscsi_kwqe_init2 *) kwqe;
  1070. struct cnic_local *cp = dev->cnic_priv;
  1071. int func = cp->func;
  1072. struct iscsi_kcqe kcqe;
  1073. struct kcqe *cqes[1];
  1074. memset(&kcqe, 0, sizeof(kcqe));
  1075. if (!dev->max_iscsi_conn) {
  1076. kcqe.completion_status =
  1077. ISCSI_KCQE_COMPLETION_STATUS_ISCSI_NOT_SUPPORTED;
  1078. goto done;
  1079. }
  1080. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  1081. TSTORM_ISCSI_ERROR_BITMAP_OFFSET(func), req2->error_bit_map[0]);
  1082. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  1083. TSTORM_ISCSI_ERROR_BITMAP_OFFSET(func) + 4,
  1084. req2->error_bit_map[1]);
  1085. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1086. USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(func), req2->max_cq_sqn);
  1087. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  1088. USTORM_ISCSI_ERROR_BITMAP_OFFSET(func), req2->error_bit_map[0]);
  1089. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  1090. USTORM_ISCSI_ERROR_BITMAP_OFFSET(func) + 4,
  1091. req2->error_bit_map[1]);
  1092. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  1093. CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(func), req2->max_cq_sqn);
  1094. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1095. done:
  1096. kcqe.op_code = ISCSI_KCQE_OPCODE_INIT;
  1097. cqes[0] = (struct kcqe *) &kcqe;
  1098. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1099. return 0;
  1100. }
  1101. static void cnic_free_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
  1102. {
  1103. struct cnic_local *cp = dev->cnic_priv;
  1104. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1105. if (ctx->ulp_proto_id == CNIC_ULP_ISCSI) {
  1106. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1107. cnic_free_dma(dev, &iscsi->hq_info);
  1108. cnic_free_dma(dev, &iscsi->r2tq_info);
  1109. cnic_free_dma(dev, &iscsi->task_array_info);
  1110. }
  1111. cnic_free_id(&cp->cid_tbl, ctx->cid);
  1112. ctx->cid = 0;
  1113. }
  1114. static int cnic_alloc_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
  1115. {
  1116. u32 cid;
  1117. int ret, pages;
  1118. struct cnic_local *cp = dev->cnic_priv;
  1119. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1120. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1121. cid = cnic_alloc_new_id(&cp->cid_tbl);
  1122. if (cid == -1) {
  1123. ret = -ENOMEM;
  1124. goto error;
  1125. }
  1126. ctx->cid = cid;
  1127. pages = PAGE_ALIGN(cp->task_array_size) / PAGE_SIZE;
  1128. ret = cnic_alloc_dma(dev, &iscsi->task_array_info, pages, 1);
  1129. if (ret)
  1130. goto error;
  1131. pages = PAGE_ALIGN(cp->r2tq_size) / PAGE_SIZE;
  1132. ret = cnic_alloc_dma(dev, &iscsi->r2tq_info, pages, 1);
  1133. if (ret)
  1134. goto error;
  1135. pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE;
  1136. ret = cnic_alloc_dma(dev, &iscsi->hq_info, pages, 1);
  1137. if (ret)
  1138. goto error;
  1139. return 0;
  1140. error:
  1141. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1142. return ret;
  1143. }
  1144. static void *cnic_get_bnx2x_ctx(struct cnic_dev *dev, u32 cid, int init,
  1145. struct regpair *ctx_addr)
  1146. {
  1147. struct cnic_local *cp = dev->cnic_priv;
  1148. struct cnic_eth_dev *ethdev = cp->ethdev;
  1149. int blk = (cid - ethdev->starting_cid) / cp->cids_per_blk;
  1150. int off = (cid - ethdev->starting_cid) % cp->cids_per_blk;
  1151. unsigned long align_off = 0;
  1152. dma_addr_t ctx_map;
  1153. void *ctx;
  1154. if (cp->ctx_align) {
  1155. unsigned long mask = cp->ctx_align - 1;
  1156. if (cp->ctx_arr[blk].mapping & mask)
  1157. align_off = cp->ctx_align -
  1158. (cp->ctx_arr[blk].mapping & mask);
  1159. }
  1160. ctx_map = cp->ctx_arr[blk].mapping + align_off +
  1161. (off * BNX2X_CONTEXT_MEM_SIZE);
  1162. ctx = cp->ctx_arr[blk].ctx + align_off +
  1163. (off * BNX2X_CONTEXT_MEM_SIZE);
  1164. if (init)
  1165. memset(ctx, 0, BNX2X_CONTEXT_MEM_SIZE);
  1166. ctx_addr->lo = ctx_map & 0xffffffff;
  1167. ctx_addr->hi = (u64) ctx_map >> 32;
  1168. return ctx;
  1169. }
  1170. static int cnic_setup_bnx2x_ctx(struct cnic_dev *dev, struct kwqe *wqes[],
  1171. u32 num)
  1172. {
  1173. struct cnic_local *cp = dev->cnic_priv;
  1174. struct iscsi_kwqe_conn_offload1 *req1 =
  1175. (struct iscsi_kwqe_conn_offload1 *) wqes[0];
  1176. struct iscsi_kwqe_conn_offload2 *req2 =
  1177. (struct iscsi_kwqe_conn_offload2 *) wqes[1];
  1178. struct iscsi_kwqe_conn_offload3 *req3;
  1179. struct cnic_context *ctx = &cp->ctx_tbl[req1->iscsi_conn_id];
  1180. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1181. u32 cid = ctx->cid;
  1182. u32 hw_cid = BNX2X_HW_CID(cid, cp->func);
  1183. struct iscsi_context *ictx;
  1184. struct regpair context_addr;
  1185. int i, j, n = 2, n_max;
  1186. ctx->ctx_flags = 0;
  1187. if (!req2->num_additional_wqes)
  1188. return -EINVAL;
  1189. n_max = req2->num_additional_wqes + 2;
  1190. ictx = cnic_get_bnx2x_ctx(dev, cid, 1, &context_addr);
  1191. if (ictx == NULL)
  1192. return -ENOMEM;
  1193. req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
  1194. ictx->xstorm_ag_context.hq_prod = 1;
  1195. ictx->xstorm_st_context.iscsi.first_burst_length =
  1196. ISCSI_DEF_FIRST_BURST_LEN;
  1197. ictx->xstorm_st_context.iscsi.max_send_pdu_length =
  1198. ISCSI_DEF_MAX_RECV_SEG_LEN;
  1199. ictx->xstorm_st_context.iscsi.sq_pbl_base.lo =
  1200. req1->sq_page_table_addr_lo;
  1201. ictx->xstorm_st_context.iscsi.sq_pbl_base.hi =
  1202. req1->sq_page_table_addr_hi;
  1203. ictx->xstorm_st_context.iscsi.sq_curr_pbe.lo = req2->sq_first_pte.hi;
  1204. ictx->xstorm_st_context.iscsi.sq_curr_pbe.hi = req2->sq_first_pte.lo;
  1205. ictx->xstorm_st_context.iscsi.hq_pbl_base.lo =
  1206. iscsi->hq_info.pgtbl_map & 0xffffffff;
  1207. ictx->xstorm_st_context.iscsi.hq_pbl_base.hi =
  1208. (u64) iscsi->hq_info.pgtbl_map >> 32;
  1209. ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.lo =
  1210. iscsi->hq_info.pgtbl[0];
  1211. ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.hi =
  1212. iscsi->hq_info.pgtbl[1];
  1213. ictx->xstorm_st_context.iscsi.r2tq_pbl_base.lo =
  1214. iscsi->r2tq_info.pgtbl_map & 0xffffffff;
  1215. ictx->xstorm_st_context.iscsi.r2tq_pbl_base.hi =
  1216. (u64) iscsi->r2tq_info.pgtbl_map >> 32;
  1217. ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.lo =
  1218. iscsi->r2tq_info.pgtbl[0];
  1219. ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.hi =
  1220. iscsi->r2tq_info.pgtbl[1];
  1221. ictx->xstorm_st_context.iscsi.task_pbl_base.lo =
  1222. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1223. ictx->xstorm_st_context.iscsi.task_pbl_base.hi =
  1224. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1225. ictx->xstorm_st_context.iscsi.task_pbl_cache_idx =
  1226. BNX2X_ISCSI_PBL_NOT_CACHED;
  1227. ictx->xstorm_st_context.iscsi.flags.flags |=
  1228. XSTORM_ISCSI_CONTEXT_FLAGS_B_IMMEDIATE_DATA;
  1229. ictx->xstorm_st_context.iscsi.flags.flags |=
  1230. XSTORM_ISCSI_CONTEXT_FLAGS_B_INITIAL_R2T;
  1231. ictx->tstorm_st_context.iscsi.hdr_bytes_2_fetch = ISCSI_HEADER_SIZE;
  1232. /* TSTORM requires the base address of RQ DB & not PTE */
  1233. ictx->tstorm_st_context.iscsi.rq_db_phy_addr.lo =
  1234. req2->rq_page_table_addr_lo & PAGE_MASK;
  1235. ictx->tstorm_st_context.iscsi.rq_db_phy_addr.hi =
  1236. req2->rq_page_table_addr_hi;
  1237. ictx->tstorm_st_context.iscsi.iscsi_conn_id = req1->iscsi_conn_id;
  1238. ictx->tstorm_st_context.tcp.cwnd = 0x5A8;
  1239. ictx->tstorm_st_context.tcp.flags2 |=
  1240. TSTORM_TCP_ST_CONTEXT_SECTION_DA_EN;
  1241. ictx->timers_context.flags |= ISCSI_TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG;
  1242. ictx->ustorm_st_context.ring.rq.pbl_base.lo =
  1243. req2->rq_page_table_addr_lo;
  1244. ictx->ustorm_st_context.ring.rq.pbl_base.hi =
  1245. req2->rq_page_table_addr_hi;
  1246. ictx->ustorm_st_context.ring.rq.curr_pbe.lo = req3->qp_first_pte[0].hi;
  1247. ictx->ustorm_st_context.ring.rq.curr_pbe.hi = req3->qp_first_pte[0].lo;
  1248. ictx->ustorm_st_context.ring.r2tq.pbl_base.lo =
  1249. iscsi->r2tq_info.pgtbl_map & 0xffffffff;
  1250. ictx->ustorm_st_context.ring.r2tq.pbl_base.hi =
  1251. (u64) iscsi->r2tq_info.pgtbl_map >> 32;
  1252. ictx->ustorm_st_context.ring.r2tq.curr_pbe.lo =
  1253. iscsi->r2tq_info.pgtbl[0];
  1254. ictx->ustorm_st_context.ring.r2tq.curr_pbe.hi =
  1255. iscsi->r2tq_info.pgtbl[1];
  1256. ictx->ustorm_st_context.ring.cq_pbl_base.lo =
  1257. req1->cq_page_table_addr_lo;
  1258. ictx->ustorm_st_context.ring.cq_pbl_base.hi =
  1259. req1->cq_page_table_addr_hi;
  1260. ictx->ustorm_st_context.ring.cq[0].cq_sn = ISCSI_INITIAL_SN;
  1261. ictx->ustorm_st_context.ring.cq[0].curr_pbe.lo = req2->cq_first_pte.hi;
  1262. ictx->ustorm_st_context.ring.cq[0].curr_pbe.hi = req2->cq_first_pte.lo;
  1263. ictx->ustorm_st_context.task_pbe_cache_index =
  1264. BNX2X_ISCSI_PBL_NOT_CACHED;
  1265. ictx->ustorm_st_context.task_pdu_cache_index =
  1266. BNX2X_ISCSI_PDU_HEADER_NOT_CACHED;
  1267. for (i = 1, j = 1; i < cp->num_cqs; i++, j++) {
  1268. if (j == 3) {
  1269. if (n >= n_max)
  1270. break;
  1271. req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
  1272. j = 0;
  1273. }
  1274. ictx->ustorm_st_context.ring.cq[i].cq_sn = ISCSI_INITIAL_SN;
  1275. ictx->ustorm_st_context.ring.cq[i].curr_pbe.lo =
  1276. req3->qp_first_pte[j].hi;
  1277. ictx->ustorm_st_context.ring.cq[i].curr_pbe.hi =
  1278. req3->qp_first_pte[j].lo;
  1279. }
  1280. ictx->ustorm_st_context.task_pbl_base.lo =
  1281. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1282. ictx->ustorm_st_context.task_pbl_base.hi =
  1283. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1284. ictx->ustorm_st_context.tce_phy_addr.lo =
  1285. iscsi->task_array_info.pgtbl[0];
  1286. ictx->ustorm_st_context.tce_phy_addr.hi =
  1287. iscsi->task_array_info.pgtbl[1];
  1288. ictx->ustorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
  1289. ictx->ustorm_st_context.num_cqs = cp->num_cqs;
  1290. ictx->ustorm_st_context.negotiated_rx |= ISCSI_DEF_MAX_RECV_SEG_LEN;
  1291. ictx->ustorm_st_context.negotiated_rx_and_flags |=
  1292. ISCSI_DEF_MAX_BURST_LEN;
  1293. ictx->ustorm_st_context.negotiated_rx |=
  1294. ISCSI_DEFAULT_MAX_OUTSTANDING_R2T <<
  1295. USTORM_ISCSI_ST_CONTEXT_MAX_OUTSTANDING_R2TS_SHIFT;
  1296. ictx->cstorm_st_context.hq_pbl_base.lo =
  1297. iscsi->hq_info.pgtbl_map & 0xffffffff;
  1298. ictx->cstorm_st_context.hq_pbl_base.hi =
  1299. (u64) iscsi->hq_info.pgtbl_map >> 32;
  1300. ictx->cstorm_st_context.hq_curr_pbe.lo = iscsi->hq_info.pgtbl[0];
  1301. ictx->cstorm_st_context.hq_curr_pbe.hi = iscsi->hq_info.pgtbl[1];
  1302. ictx->cstorm_st_context.task_pbl_base.lo =
  1303. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1304. ictx->cstorm_st_context.task_pbl_base.hi =
  1305. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1306. /* CSTORM and USTORM initialization is different, CSTORM requires
  1307. * CQ DB base & not PTE addr */
  1308. ictx->cstorm_st_context.cq_db_base.lo =
  1309. req1->cq_page_table_addr_lo & PAGE_MASK;
  1310. ictx->cstorm_st_context.cq_db_base.hi = req1->cq_page_table_addr_hi;
  1311. ictx->cstorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
  1312. ictx->cstorm_st_context.cq_proc_en_bit_map = (1 << cp->num_cqs) - 1;
  1313. for (i = 0; i < cp->num_cqs; i++) {
  1314. ictx->cstorm_st_context.cq_c_prod_sqn_arr.sqn[i] =
  1315. ISCSI_INITIAL_SN;
  1316. ictx->cstorm_st_context.cq_c_sqn_2_notify_arr.sqn[i] =
  1317. ISCSI_INITIAL_SN;
  1318. }
  1319. ictx->xstorm_ag_context.cdu_reserved =
  1320. CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_XCM_AG,
  1321. ISCSI_CONNECTION_TYPE);
  1322. ictx->ustorm_ag_context.cdu_usage =
  1323. CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_UCM_AG,
  1324. ISCSI_CONNECTION_TYPE);
  1325. return 0;
  1326. }
  1327. static int cnic_bnx2x_iscsi_ofld1(struct cnic_dev *dev, struct kwqe *wqes[],
  1328. u32 num, int *work)
  1329. {
  1330. struct iscsi_kwqe_conn_offload1 *req1;
  1331. struct iscsi_kwqe_conn_offload2 *req2;
  1332. struct cnic_local *cp = dev->cnic_priv;
  1333. struct iscsi_kcqe kcqe;
  1334. struct kcqe *cqes[1];
  1335. u32 l5_cid;
  1336. int ret;
  1337. if (num < 2) {
  1338. *work = num;
  1339. return -EINVAL;
  1340. }
  1341. req1 = (struct iscsi_kwqe_conn_offload1 *) wqes[0];
  1342. req2 = (struct iscsi_kwqe_conn_offload2 *) wqes[1];
  1343. if ((num - 2) < req2->num_additional_wqes) {
  1344. *work = num;
  1345. return -EINVAL;
  1346. }
  1347. *work = 2 + req2->num_additional_wqes;;
  1348. l5_cid = req1->iscsi_conn_id;
  1349. if (l5_cid >= MAX_ISCSI_TBL_SZ)
  1350. return -EINVAL;
  1351. memset(&kcqe, 0, sizeof(kcqe));
  1352. kcqe.op_code = ISCSI_KCQE_OPCODE_OFFLOAD_CONN;
  1353. kcqe.iscsi_conn_id = l5_cid;
  1354. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE;
  1355. if (atomic_inc_return(&cp->iscsi_conn) > dev->max_iscsi_conn) {
  1356. atomic_dec(&cp->iscsi_conn);
  1357. ret = 0;
  1358. goto done;
  1359. }
  1360. ret = cnic_alloc_bnx2x_conn_resc(dev, l5_cid);
  1361. if (ret) {
  1362. atomic_dec(&cp->iscsi_conn);
  1363. ret = 0;
  1364. goto done;
  1365. }
  1366. ret = cnic_setup_bnx2x_ctx(dev, wqes, num);
  1367. if (ret < 0) {
  1368. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1369. atomic_dec(&cp->iscsi_conn);
  1370. goto done;
  1371. }
  1372. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1373. kcqe.iscsi_conn_context_id = BNX2X_HW_CID(cp->ctx_tbl[l5_cid].cid,
  1374. cp->func);
  1375. done:
  1376. cqes[0] = (struct kcqe *) &kcqe;
  1377. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1378. return ret;
  1379. }
  1380. static int cnic_bnx2x_iscsi_update(struct cnic_dev *dev, struct kwqe *kwqe)
  1381. {
  1382. struct cnic_local *cp = dev->cnic_priv;
  1383. struct iscsi_kwqe_conn_update *req =
  1384. (struct iscsi_kwqe_conn_update *) kwqe;
  1385. void *data;
  1386. union l5cm_specific_data l5_data;
  1387. u32 l5_cid, cid = BNX2X_SW_CID(req->context_id);
  1388. int ret;
  1389. if (cnic_get_l5_cid(cp, cid, &l5_cid) != 0)
  1390. return -EINVAL;
  1391. data = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1392. if (!data)
  1393. return -ENOMEM;
  1394. memcpy(data, kwqe, sizeof(struct kwqe));
  1395. ret = cnic_submit_kwqe_16(dev, ISCSI_RAMROD_CMD_ID_UPDATE_CONN,
  1396. req->context_id, ISCSI_CONNECTION_TYPE, &l5_data);
  1397. return ret;
  1398. }
  1399. static int cnic_bnx2x_iscsi_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
  1400. {
  1401. struct cnic_local *cp = dev->cnic_priv;
  1402. struct iscsi_kwqe_conn_destroy *req =
  1403. (struct iscsi_kwqe_conn_destroy *) kwqe;
  1404. union l5cm_specific_data l5_data;
  1405. u32 l5_cid = req->reserved0;
  1406. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1407. int ret = 0;
  1408. struct iscsi_kcqe kcqe;
  1409. struct kcqe *cqes[1];
  1410. if (!(ctx->ctx_flags & CTX_FL_OFFLD_START))
  1411. goto skip_cfc_delete;
  1412. while (!time_after(jiffies, ctx->timestamp + (2 * HZ)))
  1413. msleep(250);
  1414. init_waitqueue_head(&ctx->waitq);
  1415. ctx->wait_cond = 0;
  1416. memset(&l5_data, 0, sizeof(l5_data));
  1417. ret = cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_CFC_DEL,
  1418. req->context_id,
  1419. ETH_CONNECTION_TYPE |
  1420. (1 << SPE_HDR_COMMON_RAMROD_SHIFT),
  1421. &l5_data);
  1422. if (ret == 0)
  1423. wait_event(ctx->waitq, ctx->wait_cond);
  1424. skip_cfc_delete:
  1425. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1426. atomic_dec(&cp->iscsi_conn);
  1427. memset(&kcqe, 0, sizeof(kcqe));
  1428. kcqe.op_code = ISCSI_KCQE_OPCODE_DESTROY_CONN;
  1429. kcqe.iscsi_conn_id = l5_cid;
  1430. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1431. kcqe.iscsi_conn_context_id = req->context_id;
  1432. cqes[0] = (struct kcqe *) &kcqe;
  1433. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1434. return ret;
  1435. }
  1436. static void cnic_init_storm_conn_bufs(struct cnic_dev *dev,
  1437. struct l4_kwq_connect_req1 *kwqe1,
  1438. struct l4_kwq_connect_req3 *kwqe3,
  1439. struct l5cm_active_conn_buffer *conn_buf)
  1440. {
  1441. struct l5cm_conn_addr_params *conn_addr = &conn_buf->conn_addr_buf;
  1442. struct l5cm_xstorm_conn_buffer *xstorm_buf =
  1443. &conn_buf->xstorm_conn_buffer;
  1444. struct l5cm_tstorm_conn_buffer *tstorm_buf =
  1445. &conn_buf->tstorm_conn_buffer;
  1446. struct regpair context_addr;
  1447. u32 cid = BNX2X_SW_CID(kwqe1->cid);
  1448. struct in6_addr src_ip, dst_ip;
  1449. int i;
  1450. u32 *addrp;
  1451. addrp = (u32 *) &conn_addr->local_ip_addr;
  1452. for (i = 0; i < 4; i++, addrp++)
  1453. src_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
  1454. addrp = (u32 *) &conn_addr->remote_ip_addr;
  1455. for (i = 0; i < 4; i++, addrp++)
  1456. dst_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
  1457. cnic_get_bnx2x_ctx(dev, cid, 0, &context_addr);
  1458. xstorm_buf->context_addr.hi = context_addr.hi;
  1459. xstorm_buf->context_addr.lo = context_addr.lo;
  1460. xstorm_buf->mss = 0xffff;
  1461. xstorm_buf->rcv_buf = kwqe3->rcv_buf;
  1462. if (kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE)
  1463. xstorm_buf->params |= L5CM_XSTORM_CONN_BUFFER_NAGLE_ENABLE;
  1464. xstorm_buf->pseudo_header_checksum =
  1465. swab16(~csum_ipv6_magic(&src_ip, &dst_ip, 0, IPPROTO_TCP, 0));
  1466. if (!(kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK))
  1467. tstorm_buf->params |=
  1468. L5CM_TSTORM_CONN_BUFFER_DELAYED_ACK_ENABLE;
  1469. if (kwqe3->ka_timeout) {
  1470. tstorm_buf->ka_enable = 1;
  1471. tstorm_buf->ka_timeout = kwqe3->ka_timeout;
  1472. tstorm_buf->ka_interval = kwqe3->ka_interval;
  1473. tstorm_buf->ka_max_probe_count = kwqe3->ka_max_probe_count;
  1474. }
  1475. tstorm_buf->rcv_buf = kwqe3->rcv_buf;
  1476. tstorm_buf->snd_buf = kwqe3->snd_buf;
  1477. tstorm_buf->max_rt_time = 0xffffffff;
  1478. }
  1479. static void cnic_init_bnx2x_mac(struct cnic_dev *dev)
  1480. {
  1481. struct cnic_local *cp = dev->cnic_priv;
  1482. int func = CNIC_FUNC(cp);
  1483. u8 *mac = dev->mac_addr;
  1484. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1485. XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(func), mac[0]);
  1486. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1487. XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(func), mac[1]);
  1488. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1489. XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(func), mac[2]);
  1490. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1491. XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(func), mac[3]);
  1492. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1493. XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(func), mac[4]);
  1494. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1495. XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(func), mac[5]);
  1496. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1497. TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(func), mac[5]);
  1498. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1499. TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(func) + 1,
  1500. mac[4]);
  1501. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1502. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(func), mac[3]);
  1503. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1504. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(func) + 1,
  1505. mac[2]);
  1506. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1507. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(func) + 2,
  1508. mac[1]);
  1509. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1510. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(func) + 3,
  1511. mac[0]);
  1512. }
  1513. static void cnic_bnx2x_set_tcp_timestamp(struct cnic_dev *dev, int tcp_ts)
  1514. {
  1515. struct cnic_local *cp = dev->cnic_priv;
  1516. u8 xstorm_flags = XSTORM_L5CM_TCP_FLAGS_WND_SCL_EN;
  1517. u16 tstorm_flags = 0;
  1518. if (tcp_ts) {
  1519. xstorm_flags |= XSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
  1520. tstorm_flags |= TSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
  1521. }
  1522. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1523. XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(cp->func), xstorm_flags);
  1524. CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
  1525. TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(cp->func), tstorm_flags);
  1526. }
  1527. static int cnic_bnx2x_connect(struct cnic_dev *dev, struct kwqe *wqes[],
  1528. u32 num, int *work)
  1529. {
  1530. struct cnic_local *cp = dev->cnic_priv;
  1531. struct l4_kwq_connect_req1 *kwqe1 =
  1532. (struct l4_kwq_connect_req1 *) wqes[0];
  1533. struct l4_kwq_connect_req3 *kwqe3;
  1534. struct l5cm_active_conn_buffer *conn_buf;
  1535. struct l5cm_conn_addr_params *conn_addr;
  1536. union l5cm_specific_data l5_data;
  1537. u32 l5_cid = kwqe1->pg_cid;
  1538. struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
  1539. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1540. int ret;
  1541. if (num < 2) {
  1542. *work = num;
  1543. return -EINVAL;
  1544. }
  1545. if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6)
  1546. *work = 3;
  1547. else
  1548. *work = 2;
  1549. if (num < *work) {
  1550. *work = num;
  1551. return -EINVAL;
  1552. }
  1553. if (sizeof(*conn_buf) > CNIC_KWQ16_DATA_SIZE) {
  1554. netdev_err(dev->netdev, "conn_buf size too big\n");
  1555. return -ENOMEM;
  1556. }
  1557. conn_buf = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1558. if (!conn_buf)
  1559. return -ENOMEM;
  1560. memset(conn_buf, 0, sizeof(*conn_buf));
  1561. conn_addr = &conn_buf->conn_addr_buf;
  1562. conn_addr->remote_addr_0 = csk->ha[0];
  1563. conn_addr->remote_addr_1 = csk->ha[1];
  1564. conn_addr->remote_addr_2 = csk->ha[2];
  1565. conn_addr->remote_addr_3 = csk->ha[3];
  1566. conn_addr->remote_addr_4 = csk->ha[4];
  1567. conn_addr->remote_addr_5 = csk->ha[5];
  1568. if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6) {
  1569. struct l4_kwq_connect_req2 *kwqe2 =
  1570. (struct l4_kwq_connect_req2 *) wqes[1];
  1571. conn_addr->local_ip_addr.ip_addr_hi_hi = kwqe2->src_ip_v6_4;
  1572. conn_addr->local_ip_addr.ip_addr_hi_lo = kwqe2->src_ip_v6_3;
  1573. conn_addr->local_ip_addr.ip_addr_lo_hi = kwqe2->src_ip_v6_2;
  1574. conn_addr->remote_ip_addr.ip_addr_hi_hi = kwqe2->dst_ip_v6_4;
  1575. conn_addr->remote_ip_addr.ip_addr_hi_lo = kwqe2->dst_ip_v6_3;
  1576. conn_addr->remote_ip_addr.ip_addr_lo_hi = kwqe2->dst_ip_v6_2;
  1577. conn_addr->params |= L5CM_CONN_ADDR_PARAMS_IP_VERSION;
  1578. }
  1579. kwqe3 = (struct l4_kwq_connect_req3 *) wqes[*work - 1];
  1580. conn_addr->local_ip_addr.ip_addr_lo_lo = kwqe1->src_ip;
  1581. conn_addr->remote_ip_addr.ip_addr_lo_lo = kwqe1->dst_ip;
  1582. conn_addr->local_tcp_port = kwqe1->src_port;
  1583. conn_addr->remote_tcp_port = kwqe1->dst_port;
  1584. conn_addr->pmtu = kwqe3->pmtu;
  1585. cnic_init_storm_conn_bufs(dev, kwqe1, kwqe3, conn_buf);
  1586. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  1587. XSTORM_ISCSI_LOCAL_VLAN_OFFSET(cp->func), csk->vlan_id);
  1588. cnic_bnx2x_set_tcp_timestamp(dev,
  1589. kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_TIME_STAMP);
  1590. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_TCP_CONNECT,
  1591. kwqe1->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1592. if (!ret)
  1593. ctx->ctx_flags |= CTX_FL_OFFLD_START;
  1594. return ret;
  1595. }
  1596. static int cnic_bnx2x_close(struct cnic_dev *dev, struct kwqe *kwqe)
  1597. {
  1598. struct l4_kwq_close_req *req = (struct l4_kwq_close_req *) kwqe;
  1599. union l5cm_specific_data l5_data;
  1600. int ret;
  1601. memset(&l5_data, 0, sizeof(l5_data));
  1602. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_CLOSE,
  1603. req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1604. return ret;
  1605. }
  1606. static int cnic_bnx2x_reset(struct cnic_dev *dev, struct kwqe *kwqe)
  1607. {
  1608. struct l4_kwq_reset_req *req = (struct l4_kwq_reset_req *) kwqe;
  1609. union l5cm_specific_data l5_data;
  1610. int ret;
  1611. memset(&l5_data, 0, sizeof(l5_data));
  1612. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_ABORT,
  1613. req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1614. return ret;
  1615. }
  1616. static int cnic_bnx2x_offload_pg(struct cnic_dev *dev, struct kwqe *kwqe)
  1617. {
  1618. struct l4_kwq_offload_pg *req = (struct l4_kwq_offload_pg *) kwqe;
  1619. struct l4_kcq kcqe;
  1620. struct kcqe *cqes[1];
  1621. memset(&kcqe, 0, sizeof(kcqe));
  1622. kcqe.pg_host_opaque = req->host_opaque;
  1623. kcqe.pg_cid = req->host_opaque;
  1624. kcqe.op_code = L4_KCQE_OPCODE_VALUE_OFFLOAD_PG;
  1625. cqes[0] = (struct kcqe *) &kcqe;
  1626. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
  1627. return 0;
  1628. }
  1629. static int cnic_bnx2x_update_pg(struct cnic_dev *dev, struct kwqe *kwqe)
  1630. {
  1631. struct l4_kwq_update_pg *req = (struct l4_kwq_update_pg *) kwqe;
  1632. struct l4_kcq kcqe;
  1633. struct kcqe *cqes[1];
  1634. memset(&kcqe, 0, sizeof(kcqe));
  1635. kcqe.pg_host_opaque = req->pg_host_opaque;
  1636. kcqe.pg_cid = req->pg_cid;
  1637. kcqe.op_code = L4_KCQE_OPCODE_VALUE_UPDATE_PG;
  1638. cqes[0] = (struct kcqe *) &kcqe;
  1639. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
  1640. return 0;
  1641. }
  1642. static int cnic_submit_bnx2x_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
  1643. u32 num_wqes)
  1644. {
  1645. int i, work, ret;
  1646. u32 opcode;
  1647. struct kwqe *kwqe;
  1648. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  1649. return -EAGAIN; /* bnx2 is down */
  1650. for (i = 0; i < num_wqes; ) {
  1651. kwqe = wqes[i];
  1652. opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
  1653. work = 1;
  1654. switch (opcode) {
  1655. case ISCSI_KWQE_OPCODE_INIT1:
  1656. ret = cnic_bnx2x_iscsi_init1(dev, kwqe);
  1657. break;
  1658. case ISCSI_KWQE_OPCODE_INIT2:
  1659. ret = cnic_bnx2x_iscsi_init2(dev, kwqe);
  1660. break;
  1661. case ISCSI_KWQE_OPCODE_OFFLOAD_CONN1:
  1662. ret = cnic_bnx2x_iscsi_ofld1(dev, &wqes[i],
  1663. num_wqes - i, &work);
  1664. break;
  1665. case ISCSI_KWQE_OPCODE_UPDATE_CONN:
  1666. ret = cnic_bnx2x_iscsi_update(dev, kwqe);
  1667. break;
  1668. case ISCSI_KWQE_OPCODE_DESTROY_CONN:
  1669. ret = cnic_bnx2x_iscsi_destroy(dev, kwqe);
  1670. break;
  1671. case L4_KWQE_OPCODE_VALUE_CONNECT1:
  1672. ret = cnic_bnx2x_connect(dev, &wqes[i], num_wqes - i,
  1673. &work);
  1674. break;
  1675. case L4_KWQE_OPCODE_VALUE_CLOSE:
  1676. ret = cnic_bnx2x_close(dev, kwqe);
  1677. break;
  1678. case L4_KWQE_OPCODE_VALUE_RESET:
  1679. ret = cnic_bnx2x_reset(dev, kwqe);
  1680. break;
  1681. case L4_KWQE_OPCODE_VALUE_OFFLOAD_PG:
  1682. ret = cnic_bnx2x_offload_pg(dev, kwqe);
  1683. break;
  1684. case L4_KWQE_OPCODE_VALUE_UPDATE_PG:
  1685. ret = cnic_bnx2x_update_pg(dev, kwqe);
  1686. break;
  1687. case L4_KWQE_OPCODE_VALUE_UPLOAD_PG:
  1688. ret = 0;
  1689. break;
  1690. default:
  1691. ret = 0;
  1692. netdev_err(dev->netdev, "Unknown type of KWQE(0x%x)\n",
  1693. opcode);
  1694. break;
  1695. }
  1696. if (ret < 0)
  1697. netdev_err(dev->netdev, "KWQE(0x%x) failed\n",
  1698. opcode);
  1699. i += work;
  1700. }
  1701. return 0;
  1702. }
  1703. static void service_kcqes(struct cnic_dev *dev, int num_cqes)
  1704. {
  1705. struct cnic_local *cp = dev->cnic_priv;
  1706. int i, j;
  1707. i = 0;
  1708. j = 1;
  1709. while (num_cqes) {
  1710. struct cnic_ulp_ops *ulp_ops;
  1711. int ulp_type;
  1712. u32 kcqe_op_flag = cp->completed_kcq[i]->kcqe_op_flag;
  1713. u32 kcqe_layer = kcqe_op_flag & KCQE_FLAGS_LAYER_MASK;
  1714. if (unlikely(kcqe_op_flag & KCQE_RAMROD_COMPLETION))
  1715. cnic_kwq_completion(dev, 1);
  1716. while (j < num_cqes) {
  1717. u32 next_op = cp->completed_kcq[i + j]->kcqe_op_flag;
  1718. if ((next_op & KCQE_FLAGS_LAYER_MASK) != kcqe_layer)
  1719. break;
  1720. if (unlikely(next_op & KCQE_RAMROD_COMPLETION))
  1721. cnic_kwq_completion(dev, 1);
  1722. j++;
  1723. }
  1724. if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_RDMA)
  1725. ulp_type = CNIC_ULP_RDMA;
  1726. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_ISCSI)
  1727. ulp_type = CNIC_ULP_ISCSI;
  1728. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L4)
  1729. ulp_type = CNIC_ULP_L4;
  1730. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L2)
  1731. goto end;
  1732. else {
  1733. netdev_err(dev->netdev, "Unknown type of KCQE(0x%x)\n",
  1734. kcqe_op_flag);
  1735. goto end;
  1736. }
  1737. rcu_read_lock();
  1738. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  1739. if (likely(ulp_ops)) {
  1740. ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
  1741. cp->completed_kcq + i, j);
  1742. }
  1743. rcu_read_unlock();
  1744. end:
  1745. num_cqes -= j;
  1746. i += j;
  1747. j = 1;
  1748. }
  1749. return;
  1750. }
  1751. static u16 cnic_bnx2_next_idx(u16 idx)
  1752. {
  1753. return idx + 1;
  1754. }
  1755. static u16 cnic_bnx2_hw_idx(u16 idx)
  1756. {
  1757. return idx;
  1758. }
  1759. static u16 cnic_bnx2x_next_idx(u16 idx)
  1760. {
  1761. idx++;
  1762. if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
  1763. idx++;
  1764. return idx;
  1765. }
  1766. static u16 cnic_bnx2x_hw_idx(u16 idx)
  1767. {
  1768. if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
  1769. idx++;
  1770. return idx;
  1771. }
  1772. static int cnic_get_kcqes(struct cnic_dev *dev, u16 hw_prod, u16 *sw_prod)
  1773. {
  1774. struct cnic_local *cp = dev->cnic_priv;
  1775. u16 i, ri, last;
  1776. struct kcqe *kcqe;
  1777. int kcqe_cnt = 0, last_cnt = 0;
  1778. i = ri = last = *sw_prod;
  1779. ri &= MAX_KCQ_IDX;
  1780. while ((i != hw_prod) && (kcqe_cnt < MAX_COMPLETED_KCQE)) {
  1781. kcqe = &cp->kcq[KCQ_PG(ri)][KCQ_IDX(ri)];
  1782. cp->completed_kcq[kcqe_cnt++] = kcqe;
  1783. i = cp->next_idx(i);
  1784. ri = i & MAX_KCQ_IDX;
  1785. if (likely(!(kcqe->kcqe_op_flag & KCQE_FLAGS_NEXT))) {
  1786. last_cnt = kcqe_cnt;
  1787. last = i;
  1788. }
  1789. }
  1790. *sw_prod = last;
  1791. return last_cnt;
  1792. }
  1793. static void cnic_chk_pkt_rings(struct cnic_local *cp)
  1794. {
  1795. u16 rx_cons = *cp->rx_cons_ptr;
  1796. u16 tx_cons = *cp->tx_cons_ptr;
  1797. if (cp->tx_cons != tx_cons || cp->rx_cons != rx_cons) {
  1798. cp->tx_cons = tx_cons;
  1799. cp->rx_cons = rx_cons;
  1800. uio_event_notify(cp->cnic_uinfo);
  1801. }
  1802. }
  1803. static int cnic_service_bnx2(void *data, void *status_blk)
  1804. {
  1805. struct cnic_dev *dev = data;
  1806. struct status_block *sblk = status_blk;
  1807. struct cnic_local *cp = dev->cnic_priv;
  1808. u32 status_idx = sblk->status_idx;
  1809. u16 hw_prod, sw_prod;
  1810. int kcqe_cnt;
  1811. if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags)))
  1812. return status_idx;
  1813. cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
  1814. hw_prod = sblk->status_completion_producer_index;
  1815. sw_prod = cp->kcq_prod_idx;
  1816. while (sw_prod != hw_prod) {
  1817. kcqe_cnt = cnic_get_kcqes(dev, hw_prod, &sw_prod);
  1818. if (kcqe_cnt == 0)
  1819. goto done;
  1820. service_kcqes(dev, kcqe_cnt);
  1821. /* Tell compiler that status_blk fields can change. */
  1822. barrier();
  1823. if (status_idx != sblk->status_idx) {
  1824. status_idx = sblk->status_idx;
  1825. cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
  1826. hw_prod = sblk->status_completion_producer_index;
  1827. } else
  1828. break;
  1829. }
  1830. done:
  1831. CNIC_WR16(dev, cp->kcq_io_addr, sw_prod);
  1832. cp->kcq_prod_idx = sw_prod;
  1833. cnic_chk_pkt_rings(cp);
  1834. return status_idx;
  1835. }
  1836. static void cnic_service_bnx2_msix(unsigned long data)
  1837. {
  1838. struct cnic_dev *dev = (struct cnic_dev *) data;
  1839. struct cnic_local *cp = dev->cnic_priv;
  1840. struct status_block_msix *status_blk = cp->bnx2_status_blk;
  1841. u32 status_idx = status_blk->status_idx;
  1842. u16 hw_prod, sw_prod;
  1843. int kcqe_cnt;
  1844. cp->kwq_con_idx = status_blk->status_cmd_consumer_index;
  1845. hw_prod = status_blk->status_completion_producer_index;
  1846. sw_prod = cp->kcq_prod_idx;
  1847. while (sw_prod != hw_prod) {
  1848. kcqe_cnt = cnic_get_kcqes(dev, hw_prod, &sw_prod);
  1849. if (kcqe_cnt == 0)
  1850. goto done;
  1851. service_kcqes(dev, kcqe_cnt);
  1852. /* Tell compiler that status_blk fields can change. */
  1853. barrier();
  1854. if (status_idx != status_blk->status_idx) {
  1855. status_idx = status_blk->status_idx;
  1856. cp->kwq_con_idx = status_blk->status_cmd_consumer_index;
  1857. hw_prod = status_blk->status_completion_producer_index;
  1858. } else
  1859. break;
  1860. }
  1861. done:
  1862. CNIC_WR16(dev, cp->kcq_io_addr, sw_prod);
  1863. cp->kcq_prod_idx = sw_prod;
  1864. cnic_chk_pkt_rings(cp);
  1865. cp->last_status_idx = status_idx;
  1866. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  1867. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
  1868. }
  1869. static irqreturn_t cnic_irq(int irq, void *dev_instance)
  1870. {
  1871. struct cnic_dev *dev = dev_instance;
  1872. struct cnic_local *cp = dev->cnic_priv;
  1873. u16 prod = cp->kcq_prod_idx & MAX_KCQ_IDX;
  1874. if (cp->ack_int)
  1875. cp->ack_int(dev);
  1876. prefetch(cp->status_blk);
  1877. prefetch(&cp->kcq[KCQ_PG(prod)][KCQ_IDX(prod)]);
  1878. if (likely(test_bit(CNIC_F_CNIC_UP, &dev->flags)))
  1879. tasklet_schedule(&cp->cnic_irq_task);
  1880. return IRQ_HANDLED;
  1881. }
  1882. static inline void cnic_ack_bnx2x_int(struct cnic_dev *dev, u8 id, u8 storm,
  1883. u16 index, u8 op, u8 update)
  1884. {
  1885. struct cnic_local *cp = dev->cnic_priv;
  1886. u32 hc_addr = (HC_REG_COMMAND_REG + CNIC_PORT(cp) * 32 +
  1887. COMMAND_REG_INT_ACK);
  1888. struct igu_ack_register igu_ack;
  1889. igu_ack.status_block_index = index;
  1890. igu_ack.sb_id_and_flags =
  1891. ((id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
  1892. (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
  1893. (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
  1894. (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
  1895. CNIC_WR(dev, hc_addr, (*(u32 *)&igu_ack));
  1896. }
  1897. static void cnic_ack_bnx2x_msix(struct cnic_dev *dev)
  1898. {
  1899. struct cnic_local *cp = dev->cnic_priv;
  1900. cnic_ack_bnx2x_int(dev, cp->status_blk_num, CSTORM_ID, 0,
  1901. IGU_INT_DISABLE, 0);
  1902. }
  1903. static void cnic_service_bnx2x_bh(unsigned long data)
  1904. {
  1905. struct cnic_dev *dev = (struct cnic_dev *) data;
  1906. struct cnic_local *cp = dev->cnic_priv;
  1907. u16 hw_prod, sw_prod;
  1908. struct cstorm_status_block_c *sblk =
  1909. &cp->bnx2x_status_blk->c_status_block;
  1910. u32 status_idx = sblk->status_block_index;
  1911. int kcqe_cnt;
  1912. if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags)))
  1913. return;
  1914. hw_prod = sblk->index_values[HC_INDEX_C_ISCSI_EQ_CONS];
  1915. hw_prod = cp->hw_idx(hw_prod);
  1916. sw_prod = cp->kcq_prod_idx;
  1917. while (sw_prod != hw_prod) {
  1918. kcqe_cnt = cnic_get_kcqes(dev, hw_prod, &sw_prod);
  1919. if (kcqe_cnt == 0)
  1920. goto done;
  1921. service_kcqes(dev, kcqe_cnt);
  1922. /* Tell compiler that sblk fields can change. */
  1923. barrier();
  1924. if (status_idx == sblk->status_block_index)
  1925. break;
  1926. status_idx = sblk->status_block_index;
  1927. hw_prod = sblk->index_values[HC_INDEX_C_ISCSI_EQ_CONS];
  1928. hw_prod = cp->hw_idx(hw_prod);
  1929. }
  1930. done:
  1931. CNIC_WR16(dev, cp->kcq_io_addr, sw_prod + MAX_KCQ_IDX);
  1932. cnic_ack_bnx2x_int(dev, cp->status_blk_num, CSTORM_ID,
  1933. status_idx, IGU_INT_ENABLE, 1);
  1934. cp->kcq_prod_idx = sw_prod;
  1935. return;
  1936. }
  1937. static int cnic_service_bnx2x(void *data, void *status_blk)
  1938. {
  1939. struct cnic_dev *dev = data;
  1940. struct cnic_local *cp = dev->cnic_priv;
  1941. u16 prod = cp->kcq_prod_idx & MAX_KCQ_IDX;
  1942. prefetch(cp->status_blk);
  1943. prefetch(&cp->kcq[KCQ_PG(prod)][KCQ_IDX(prod)]);
  1944. if (likely(test_bit(CNIC_F_CNIC_UP, &dev->flags)))
  1945. tasklet_schedule(&cp->cnic_irq_task);
  1946. cnic_chk_pkt_rings(cp);
  1947. return 0;
  1948. }
  1949. static void cnic_ulp_stop(struct cnic_dev *dev)
  1950. {
  1951. struct cnic_local *cp = dev->cnic_priv;
  1952. int if_type;
  1953. if (cp->cnic_uinfo)
  1954. cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
  1955. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  1956. struct cnic_ulp_ops *ulp_ops;
  1957. mutex_lock(&cnic_lock);
  1958. ulp_ops = cp->ulp_ops[if_type];
  1959. if (!ulp_ops) {
  1960. mutex_unlock(&cnic_lock);
  1961. continue;
  1962. }
  1963. set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  1964. mutex_unlock(&cnic_lock);
  1965. if (test_and_clear_bit(ULP_F_START, &cp->ulp_flags[if_type]))
  1966. ulp_ops->cnic_stop(cp->ulp_handle[if_type]);
  1967. clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  1968. }
  1969. }
  1970. static void cnic_ulp_start(struct cnic_dev *dev)
  1971. {
  1972. struct cnic_local *cp = dev->cnic_priv;
  1973. int if_type;
  1974. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  1975. struct cnic_ulp_ops *ulp_ops;
  1976. mutex_lock(&cnic_lock);
  1977. ulp_ops = cp->ulp_ops[if_type];
  1978. if (!ulp_ops || !ulp_ops->cnic_start) {
  1979. mutex_unlock(&cnic_lock);
  1980. continue;
  1981. }
  1982. set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  1983. mutex_unlock(&cnic_lock);
  1984. if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[if_type]))
  1985. ulp_ops->cnic_start(cp->ulp_handle[if_type]);
  1986. clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  1987. }
  1988. }
  1989. static int cnic_ctl(void *data, struct cnic_ctl_info *info)
  1990. {
  1991. struct cnic_dev *dev = data;
  1992. switch (info->cmd) {
  1993. case CNIC_CTL_STOP_CMD:
  1994. cnic_hold(dev);
  1995. cnic_ulp_stop(dev);
  1996. cnic_stop_hw(dev);
  1997. cnic_put(dev);
  1998. break;
  1999. case CNIC_CTL_START_CMD:
  2000. cnic_hold(dev);
  2001. if (!cnic_start_hw(dev))
  2002. cnic_ulp_start(dev);
  2003. cnic_put(dev);
  2004. break;
  2005. case CNIC_CTL_COMPLETION_CMD: {
  2006. u32 cid = BNX2X_SW_CID(info->data.comp.cid);
  2007. u32 l5_cid;
  2008. struct cnic_local *cp = dev->cnic_priv;
  2009. if (cnic_get_l5_cid(cp, cid, &l5_cid) == 0) {
  2010. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  2011. ctx->wait_cond = 1;
  2012. wake_up(&ctx->waitq);
  2013. }
  2014. break;
  2015. }
  2016. default:
  2017. return -EINVAL;
  2018. }
  2019. return 0;
  2020. }
  2021. static void cnic_ulp_init(struct cnic_dev *dev)
  2022. {
  2023. int i;
  2024. struct cnic_local *cp = dev->cnic_priv;
  2025. for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
  2026. struct cnic_ulp_ops *ulp_ops;
  2027. mutex_lock(&cnic_lock);
  2028. ulp_ops = cnic_ulp_tbl[i];
  2029. if (!ulp_ops || !ulp_ops->cnic_init) {
  2030. mutex_unlock(&cnic_lock);
  2031. continue;
  2032. }
  2033. ulp_get(ulp_ops);
  2034. mutex_unlock(&cnic_lock);
  2035. if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[i]))
  2036. ulp_ops->cnic_init(dev);
  2037. ulp_put(ulp_ops);
  2038. }
  2039. }
  2040. static void cnic_ulp_exit(struct cnic_dev *dev)
  2041. {
  2042. int i;
  2043. struct cnic_local *cp = dev->cnic_priv;
  2044. for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
  2045. struct cnic_ulp_ops *ulp_ops;
  2046. mutex_lock(&cnic_lock);
  2047. ulp_ops = cnic_ulp_tbl[i];
  2048. if (!ulp_ops || !ulp_ops->cnic_exit) {
  2049. mutex_unlock(&cnic_lock);
  2050. continue;
  2051. }
  2052. ulp_get(ulp_ops);
  2053. mutex_unlock(&cnic_lock);
  2054. if (test_and_clear_bit(ULP_F_INIT, &cp->ulp_flags[i]))
  2055. ulp_ops->cnic_exit(dev);
  2056. ulp_put(ulp_ops);
  2057. }
  2058. }
  2059. static int cnic_cm_offload_pg(struct cnic_sock *csk)
  2060. {
  2061. struct cnic_dev *dev = csk->dev;
  2062. struct l4_kwq_offload_pg *l4kwqe;
  2063. struct kwqe *wqes[1];
  2064. l4kwqe = (struct l4_kwq_offload_pg *) &csk->kwqe1;
  2065. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2066. wqes[0] = (struct kwqe *) l4kwqe;
  2067. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_OFFLOAD_PG;
  2068. l4kwqe->flags =
  2069. L4_LAYER_CODE << L4_KWQ_OFFLOAD_PG_LAYER_CODE_SHIFT;
  2070. l4kwqe->l2hdr_nbytes = ETH_HLEN;
  2071. l4kwqe->da0 = csk->ha[0];
  2072. l4kwqe->da1 = csk->ha[1];
  2073. l4kwqe->da2 = csk->ha[2];
  2074. l4kwqe->da3 = csk->ha[3];
  2075. l4kwqe->da4 = csk->ha[4];
  2076. l4kwqe->da5 = csk->ha[5];
  2077. l4kwqe->sa0 = dev->mac_addr[0];
  2078. l4kwqe->sa1 = dev->mac_addr[1];
  2079. l4kwqe->sa2 = dev->mac_addr[2];
  2080. l4kwqe->sa3 = dev->mac_addr[3];
  2081. l4kwqe->sa4 = dev->mac_addr[4];
  2082. l4kwqe->sa5 = dev->mac_addr[5];
  2083. l4kwqe->etype = ETH_P_IP;
  2084. l4kwqe->ipid_start = DEF_IPID_START;
  2085. l4kwqe->host_opaque = csk->l5_cid;
  2086. if (csk->vlan_id) {
  2087. l4kwqe->pg_flags |= L4_KWQ_OFFLOAD_PG_VLAN_TAGGING;
  2088. l4kwqe->vlan_tag = csk->vlan_id;
  2089. l4kwqe->l2hdr_nbytes += 4;
  2090. }
  2091. return dev->submit_kwqes(dev, wqes, 1);
  2092. }
  2093. static int cnic_cm_update_pg(struct cnic_sock *csk)
  2094. {
  2095. struct cnic_dev *dev = csk->dev;
  2096. struct l4_kwq_update_pg *l4kwqe;
  2097. struct kwqe *wqes[1];
  2098. l4kwqe = (struct l4_kwq_update_pg *) &csk->kwqe1;
  2099. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2100. wqes[0] = (struct kwqe *) l4kwqe;
  2101. l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPDATE_PG;
  2102. l4kwqe->flags =
  2103. L4_LAYER_CODE << L4_KWQ_UPDATE_PG_LAYER_CODE_SHIFT;
  2104. l4kwqe->pg_cid = csk->pg_cid;
  2105. l4kwqe->da0 = csk->ha[0];
  2106. l4kwqe->da1 = csk->ha[1];
  2107. l4kwqe->da2 = csk->ha[2];
  2108. l4kwqe->da3 = csk->ha[3];
  2109. l4kwqe->da4 = csk->ha[4];
  2110. l4kwqe->da5 = csk->ha[5];
  2111. l4kwqe->pg_host_opaque = csk->l5_cid;
  2112. l4kwqe->pg_valids = L4_KWQ_UPDATE_PG_VALIDS_DA;
  2113. return dev->submit_kwqes(dev, wqes, 1);
  2114. }
  2115. static int cnic_cm_upload_pg(struct cnic_sock *csk)
  2116. {
  2117. struct cnic_dev *dev = csk->dev;
  2118. struct l4_kwq_upload *l4kwqe;
  2119. struct kwqe *wqes[1];
  2120. l4kwqe = (struct l4_kwq_upload *) &csk->kwqe1;
  2121. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2122. wqes[0] = (struct kwqe *) l4kwqe;
  2123. l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPLOAD_PG;
  2124. l4kwqe->flags =
  2125. L4_LAYER_CODE << L4_KWQ_UPLOAD_LAYER_CODE_SHIFT;
  2126. l4kwqe->cid = csk->pg_cid;
  2127. return dev->submit_kwqes(dev, wqes, 1);
  2128. }
  2129. static int cnic_cm_conn_req(struct cnic_sock *csk)
  2130. {
  2131. struct cnic_dev *dev = csk->dev;
  2132. struct l4_kwq_connect_req1 *l4kwqe1;
  2133. struct l4_kwq_connect_req2 *l4kwqe2;
  2134. struct l4_kwq_connect_req3 *l4kwqe3;
  2135. struct kwqe *wqes[3];
  2136. u8 tcp_flags = 0;
  2137. int num_wqes = 2;
  2138. l4kwqe1 = (struct l4_kwq_connect_req1 *) &csk->kwqe1;
  2139. l4kwqe2 = (struct l4_kwq_connect_req2 *) &csk->kwqe2;
  2140. l4kwqe3 = (struct l4_kwq_connect_req3 *) &csk->kwqe3;
  2141. memset(l4kwqe1, 0, sizeof(*l4kwqe1));
  2142. memset(l4kwqe2, 0, sizeof(*l4kwqe2));
  2143. memset(l4kwqe3, 0, sizeof(*l4kwqe3));
  2144. l4kwqe3->op_code = L4_KWQE_OPCODE_VALUE_CONNECT3;
  2145. l4kwqe3->flags =
  2146. L4_LAYER_CODE << L4_KWQ_CONNECT_REQ3_LAYER_CODE_SHIFT;
  2147. l4kwqe3->ka_timeout = csk->ka_timeout;
  2148. l4kwqe3->ka_interval = csk->ka_interval;
  2149. l4kwqe3->ka_max_probe_count = csk->ka_max_probe_count;
  2150. l4kwqe3->tos = csk->tos;
  2151. l4kwqe3->ttl = csk->ttl;
  2152. l4kwqe3->snd_seq_scale = csk->snd_seq_scale;
  2153. l4kwqe3->pmtu = csk->mtu;
  2154. l4kwqe3->rcv_buf = csk->rcv_buf;
  2155. l4kwqe3->snd_buf = csk->snd_buf;
  2156. l4kwqe3->seed = csk->seed;
  2157. wqes[0] = (struct kwqe *) l4kwqe1;
  2158. if (test_bit(SK_F_IPV6, &csk->flags)) {
  2159. wqes[1] = (struct kwqe *) l4kwqe2;
  2160. wqes[2] = (struct kwqe *) l4kwqe3;
  2161. num_wqes = 3;
  2162. l4kwqe1->conn_flags = L4_KWQ_CONNECT_REQ1_IP_V6;
  2163. l4kwqe2->op_code = L4_KWQE_OPCODE_VALUE_CONNECT2;
  2164. l4kwqe2->flags =
  2165. L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT |
  2166. L4_LAYER_CODE << L4_KWQ_CONNECT_REQ2_LAYER_CODE_SHIFT;
  2167. l4kwqe2->src_ip_v6_2 = be32_to_cpu(csk->src_ip[1]);
  2168. l4kwqe2->src_ip_v6_3 = be32_to_cpu(csk->src_ip[2]);
  2169. l4kwqe2->src_ip_v6_4 = be32_to_cpu(csk->src_ip[3]);
  2170. l4kwqe2->dst_ip_v6_2 = be32_to_cpu(csk->dst_ip[1]);
  2171. l4kwqe2->dst_ip_v6_3 = be32_to_cpu(csk->dst_ip[2]);
  2172. l4kwqe2->dst_ip_v6_4 = be32_to_cpu(csk->dst_ip[3]);
  2173. l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct ipv6hdr) -
  2174. sizeof(struct tcphdr);
  2175. } else {
  2176. wqes[1] = (struct kwqe *) l4kwqe3;
  2177. l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct iphdr) -
  2178. sizeof(struct tcphdr);
  2179. }
  2180. l4kwqe1->op_code = L4_KWQE_OPCODE_VALUE_CONNECT1;
  2181. l4kwqe1->flags =
  2182. (L4_LAYER_CODE << L4_KWQ_CONNECT_REQ1_LAYER_CODE_SHIFT) |
  2183. L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT;
  2184. l4kwqe1->cid = csk->cid;
  2185. l4kwqe1->pg_cid = csk->pg_cid;
  2186. l4kwqe1->src_ip = be32_to_cpu(csk->src_ip[0]);
  2187. l4kwqe1->dst_ip = be32_to_cpu(csk->dst_ip[0]);
  2188. l4kwqe1->src_port = be16_to_cpu(csk->src_port);
  2189. l4kwqe1->dst_port = be16_to_cpu(csk->dst_port);
  2190. if (csk->tcp_flags & SK_TCP_NO_DELAY_ACK)
  2191. tcp_flags |= L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK;
  2192. if (csk->tcp_flags & SK_TCP_KEEP_ALIVE)
  2193. tcp_flags |= L4_KWQ_CONNECT_REQ1_KEEP_ALIVE;
  2194. if (csk->tcp_flags & SK_TCP_NAGLE)
  2195. tcp_flags |= L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE;
  2196. if (csk->tcp_flags & SK_TCP_TIMESTAMP)
  2197. tcp_flags |= L4_KWQ_CONNECT_REQ1_TIME_STAMP;
  2198. if (csk->tcp_flags & SK_TCP_SACK)
  2199. tcp_flags |= L4_KWQ_CONNECT_REQ1_SACK;
  2200. if (csk->tcp_flags & SK_TCP_SEG_SCALING)
  2201. tcp_flags |= L4_KWQ_CONNECT_REQ1_SEG_SCALING;
  2202. l4kwqe1->tcp_flags = tcp_flags;
  2203. return dev->submit_kwqes(dev, wqes, num_wqes);
  2204. }
  2205. static int cnic_cm_close_req(struct cnic_sock *csk)
  2206. {
  2207. struct cnic_dev *dev = csk->dev;
  2208. struct l4_kwq_close_req *l4kwqe;
  2209. struct kwqe *wqes[1];
  2210. l4kwqe = (struct l4_kwq_close_req *) &csk->kwqe2;
  2211. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2212. wqes[0] = (struct kwqe *) l4kwqe;
  2213. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_CLOSE;
  2214. l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_CLOSE_REQ_LAYER_CODE_SHIFT;
  2215. l4kwqe->cid = csk->cid;
  2216. return dev->submit_kwqes(dev, wqes, 1);
  2217. }
  2218. static int cnic_cm_abort_req(struct cnic_sock *csk)
  2219. {
  2220. struct cnic_dev *dev = csk->dev;
  2221. struct l4_kwq_reset_req *l4kwqe;
  2222. struct kwqe *wqes[1];
  2223. l4kwqe = (struct l4_kwq_reset_req *) &csk->kwqe2;
  2224. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2225. wqes[0] = (struct kwqe *) l4kwqe;
  2226. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_RESET;
  2227. l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_RESET_REQ_LAYER_CODE_SHIFT;
  2228. l4kwqe->cid = csk->cid;
  2229. return dev->submit_kwqes(dev, wqes, 1);
  2230. }
  2231. static int cnic_cm_create(struct cnic_dev *dev, int ulp_type, u32 cid,
  2232. u32 l5_cid, struct cnic_sock **csk, void *context)
  2233. {
  2234. struct cnic_local *cp = dev->cnic_priv;
  2235. struct cnic_sock *csk1;
  2236. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  2237. return -EINVAL;
  2238. csk1 = &cp->csk_tbl[l5_cid];
  2239. if (atomic_read(&csk1->ref_count))
  2240. return -EAGAIN;
  2241. if (test_and_set_bit(SK_F_INUSE, &csk1->flags))
  2242. return -EBUSY;
  2243. csk1->dev = dev;
  2244. csk1->cid = cid;
  2245. csk1->l5_cid = l5_cid;
  2246. csk1->ulp_type = ulp_type;
  2247. csk1->context = context;
  2248. csk1->ka_timeout = DEF_KA_TIMEOUT;
  2249. csk1->ka_interval = DEF_KA_INTERVAL;
  2250. csk1->ka_max_probe_count = DEF_KA_MAX_PROBE_COUNT;
  2251. csk1->tos = DEF_TOS;
  2252. csk1->ttl = DEF_TTL;
  2253. csk1->snd_seq_scale = DEF_SND_SEQ_SCALE;
  2254. csk1->rcv_buf = DEF_RCV_BUF;
  2255. csk1->snd_buf = DEF_SND_BUF;
  2256. csk1->seed = DEF_SEED;
  2257. *csk = csk1;
  2258. return 0;
  2259. }
  2260. static void cnic_cm_cleanup(struct cnic_sock *csk)
  2261. {
  2262. if (csk->src_port) {
  2263. struct cnic_dev *dev = csk->dev;
  2264. struct cnic_local *cp = dev->cnic_priv;
  2265. cnic_free_id(&cp->csk_port_tbl, csk->src_port);
  2266. csk->src_port = 0;
  2267. }
  2268. }
  2269. static void cnic_close_conn(struct cnic_sock *csk)
  2270. {
  2271. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags)) {
  2272. cnic_cm_upload_pg(csk);
  2273. clear_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
  2274. }
  2275. cnic_cm_cleanup(csk);
  2276. }
  2277. static int cnic_cm_destroy(struct cnic_sock *csk)
  2278. {
  2279. if (!cnic_in_use(csk))
  2280. return -EINVAL;
  2281. csk_hold(csk);
  2282. clear_bit(SK_F_INUSE, &csk->flags);
  2283. smp_mb__after_clear_bit();
  2284. while (atomic_read(&csk->ref_count) != 1)
  2285. msleep(1);
  2286. cnic_cm_cleanup(csk);
  2287. csk->flags = 0;
  2288. csk_put(csk);
  2289. return 0;
  2290. }
  2291. static inline u16 cnic_get_vlan(struct net_device *dev,
  2292. struct net_device **vlan_dev)
  2293. {
  2294. if (dev->priv_flags & IFF_802_1Q_VLAN) {
  2295. *vlan_dev = vlan_dev_real_dev(dev);
  2296. return vlan_dev_vlan_id(dev);
  2297. }
  2298. *vlan_dev = dev;
  2299. return 0;
  2300. }
  2301. static int cnic_get_v4_route(struct sockaddr_in *dst_addr,
  2302. struct dst_entry **dst)
  2303. {
  2304. #if defined(CONFIG_INET)
  2305. struct flowi fl;
  2306. int err;
  2307. struct rtable *rt;
  2308. memset(&fl, 0, sizeof(fl));
  2309. fl.nl_u.ip4_u.daddr = dst_addr->sin_addr.s_addr;
  2310. err = ip_route_output_key(&init_net, &rt, &fl);
  2311. if (!err)
  2312. *dst = &rt->u.dst;
  2313. return err;
  2314. #else
  2315. return -ENETUNREACH;
  2316. #endif
  2317. }
  2318. static int cnic_get_v6_route(struct sockaddr_in6 *dst_addr,
  2319. struct dst_entry **dst)
  2320. {
  2321. #if defined(CONFIG_IPV6) || (defined(CONFIG_IPV6_MODULE) && defined(MODULE))
  2322. struct flowi fl;
  2323. memset(&fl, 0, sizeof(fl));
  2324. ipv6_addr_copy(&fl.fl6_dst, &dst_addr->sin6_addr);
  2325. if (ipv6_addr_type(&fl.fl6_dst) & IPV6_ADDR_LINKLOCAL)
  2326. fl.oif = dst_addr->sin6_scope_id;
  2327. *dst = ip6_route_output(&init_net, NULL, &fl);
  2328. if (*dst)
  2329. return 0;
  2330. #endif
  2331. return -ENETUNREACH;
  2332. }
  2333. static struct cnic_dev *cnic_cm_select_dev(struct sockaddr_in *dst_addr,
  2334. int ulp_type)
  2335. {
  2336. struct cnic_dev *dev = NULL;
  2337. struct dst_entry *dst;
  2338. struct net_device *netdev = NULL;
  2339. int err = -ENETUNREACH;
  2340. if (dst_addr->sin_family == AF_INET)
  2341. err = cnic_get_v4_route(dst_addr, &dst);
  2342. else if (dst_addr->sin_family == AF_INET6) {
  2343. struct sockaddr_in6 *dst_addr6 =
  2344. (struct sockaddr_in6 *) dst_addr;
  2345. err = cnic_get_v6_route(dst_addr6, &dst);
  2346. } else
  2347. return NULL;
  2348. if (err)
  2349. return NULL;
  2350. if (!dst->dev)
  2351. goto done;
  2352. cnic_get_vlan(dst->dev, &netdev);
  2353. dev = cnic_from_netdev(netdev);
  2354. done:
  2355. dst_release(dst);
  2356. if (dev)
  2357. cnic_put(dev);
  2358. return dev;
  2359. }
  2360. static int cnic_resolve_addr(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  2361. {
  2362. struct cnic_dev *dev = csk->dev;
  2363. struct cnic_local *cp = dev->cnic_priv;
  2364. return cnic_send_nlmsg(cp, ISCSI_KEVENT_PATH_REQ, csk);
  2365. }
  2366. static int cnic_get_route(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  2367. {
  2368. struct cnic_dev *dev = csk->dev;
  2369. struct cnic_local *cp = dev->cnic_priv;
  2370. int is_v6, err, rc = -ENETUNREACH;
  2371. struct dst_entry *dst;
  2372. struct net_device *realdev;
  2373. u32 local_port;
  2374. if (saddr->local.v6.sin6_family == AF_INET6 &&
  2375. saddr->remote.v6.sin6_family == AF_INET6)
  2376. is_v6 = 1;
  2377. else if (saddr->local.v4.sin_family == AF_INET &&
  2378. saddr->remote.v4.sin_family == AF_INET)
  2379. is_v6 = 0;
  2380. else
  2381. return -EINVAL;
  2382. clear_bit(SK_F_IPV6, &csk->flags);
  2383. if (is_v6) {
  2384. #if defined(CONFIG_IPV6) || (defined(CONFIG_IPV6_MODULE) && defined(MODULE))
  2385. set_bit(SK_F_IPV6, &csk->flags);
  2386. err = cnic_get_v6_route(&saddr->remote.v6, &dst);
  2387. if (err)
  2388. return err;
  2389. if (!dst || dst->error || !dst->dev)
  2390. goto err_out;
  2391. memcpy(&csk->dst_ip[0], &saddr->remote.v6.sin6_addr,
  2392. sizeof(struct in6_addr));
  2393. csk->dst_port = saddr->remote.v6.sin6_port;
  2394. local_port = saddr->local.v6.sin6_port;
  2395. #else
  2396. return rc;
  2397. #endif
  2398. } else {
  2399. err = cnic_get_v4_route(&saddr->remote.v4, &dst);
  2400. if (err)
  2401. return err;
  2402. if (!dst || dst->error || !dst->dev)
  2403. goto err_out;
  2404. csk->dst_ip[0] = saddr->remote.v4.sin_addr.s_addr;
  2405. csk->dst_port = saddr->remote.v4.sin_port;
  2406. local_port = saddr->local.v4.sin_port;
  2407. }
  2408. csk->vlan_id = cnic_get_vlan(dst->dev, &realdev);
  2409. if (realdev != dev->netdev)
  2410. goto err_out;
  2411. if (local_port >= CNIC_LOCAL_PORT_MIN &&
  2412. local_port < CNIC_LOCAL_PORT_MAX) {
  2413. if (cnic_alloc_id(&cp->csk_port_tbl, local_port))
  2414. local_port = 0;
  2415. } else
  2416. local_port = 0;
  2417. if (!local_port) {
  2418. local_port = cnic_alloc_new_id(&cp->csk_port_tbl);
  2419. if (local_port == -1) {
  2420. rc = -ENOMEM;
  2421. goto err_out;
  2422. }
  2423. }
  2424. csk->src_port = local_port;
  2425. csk->mtu = dst_mtu(dst);
  2426. rc = 0;
  2427. err_out:
  2428. dst_release(dst);
  2429. return rc;
  2430. }
  2431. static void cnic_init_csk_state(struct cnic_sock *csk)
  2432. {
  2433. csk->state = 0;
  2434. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  2435. clear_bit(SK_F_CLOSING, &csk->flags);
  2436. }
  2437. static int cnic_cm_connect(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  2438. {
  2439. int err = 0;
  2440. if (!cnic_in_use(csk))
  2441. return -EINVAL;
  2442. if (test_and_set_bit(SK_F_CONNECT_START, &csk->flags))
  2443. return -EINVAL;
  2444. cnic_init_csk_state(csk);
  2445. err = cnic_get_route(csk, saddr);
  2446. if (err)
  2447. goto err_out;
  2448. err = cnic_resolve_addr(csk, saddr);
  2449. if (!err)
  2450. return 0;
  2451. err_out:
  2452. clear_bit(SK_F_CONNECT_START, &csk->flags);
  2453. return err;
  2454. }
  2455. static int cnic_cm_abort(struct cnic_sock *csk)
  2456. {
  2457. struct cnic_local *cp = csk->dev->cnic_priv;
  2458. u32 opcode;
  2459. if (!cnic_in_use(csk))
  2460. return -EINVAL;
  2461. if (cnic_abort_prep(csk))
  2462. return cnic_cm_abort_req(csk);
  2463. /* Getting here means that we haven't started connect, or
  2464. * connect was not successful.
  2465. */
  2466. csk->state = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  2467. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
  2468. opcode = csk->state;
  2469. else
  2470. opcode = L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD;
  2471. cp->close_conn(csk, opcode);
  2472. return 0;
  2473. }
  2474. static int cnic_cm_close(struct cnic_sock *csk)
  2475. {
  2476. if (!cnic_in_use(csk))
  2477. return -EINVAL;
  2478. if (cnic_close_prep(csk)) {
  2479. csk->state = L4_KCQE_OPCODE_VALUE_CLOSE_COMP;
  2480. return cnic_cm_close_req(csk);
  2481. }
  2482. return 0;
  2483. }
  2484. static void cnic_cm_upcall(struct cnic_local *cp, struct cnic_sock *csk,
  2485. u8 opcode)
  2486. {
  2487. struct cnic_ulp_ops *ulp_ops;
  2488. int ulp_type = csk->ulp_type;
  2489. rcu_read_lock();
  2490. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  2491. if (ulp_ops) {
  2492. if (opcode == L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE)
  2493. ulp_ops->cm_connect_complete(csk);
  2494. else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_COMP)
  2495. ulp_ops->cm_close_complete(csk);
  2496. else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED)
  2497. ulp_ops->cm_remote_abort(csk);
  2498. else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_COMP)
  2499. ulp_ops->cm_abort_complete(csk);
  2500. else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED)
  2501. ulp_ops->cm_remote_close(csk);
  2502. }
  2503. rcu_read_unlock();
  2504. }
  2505. static int cnic_cm_set_pg(struct cnic_sock *csk)
  2506. {
  2507. if (cnic_offld_prep(csk)) {
  2508. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
  2509. cnic_cm_update_pg(csk);
  2510. else
  2511. cnic_cm_offload_pg(csk);
  2512. }
  2513. return 0;
  2514. }
  2515. static void cnic_cm_process_offld_pg(struct cnic_dev *dev, struct l4_kcq *kcqe)
  2516. {
  2517. struct cnic_local *cp = dev->cnic_priv;
  2518. u32 l5_cid = kcqe->pg_host_opaque;
  2519. u8 opcode = kcqe->op_code;
  2520. struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
  2521. csk_hold(csk);
  2522. if (!cnic_in_use(csk))
  2523. goto done;
  2524. if (opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
  2525. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  2526. goto done;
  2527. }
  2528. /* Possible PG kcqe status: SUCCESS, OFFLOADED_PG, or CTX_ALLOC_FAIL */
  2529. if (kcqe->status == L4_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAIL) {
  2530. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  2531. cnic_cm_upcall(cp, csk,
  2532. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  2533. goto done;
  2534. }
  2535. csk->pg_cid = kcqe->pg_cid;
  2536. set_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
  2537. cnic_cm_conn_req(csk);
  2538. done:
  2539. csk_put(csk);
  2540. }
  2541. static void cnic_cm_process_kcqe(struct cnic_dev *dev, struct kcqe *kcqe)
  2542. {
  2543. struct cnic_local *cp = dev->cnic_priv;
  2544. struct l4_kcq *l4kcqe = (struct l4_kcq *) kcqe;
  2545. u8 opcode = l4kcqe->op_code;
  2546. u32 l5_cid;
  2547. struct cnic_sock *csk;
  2548. if (opcode == L4_KCQE_OPCODE_VALUE_OFFLOAD_PG ||
  2549. opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
  2550. cnic_cm_process_offld_pg(dev, l4kcqe);
  2551. return;
  2552. }
  2553. l5_cid = l4kcqe->conn_id;
  2554. if (opcode & 0x80)
  2555. l5_cid = l4kcqe->cid;
  2556. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  2557. return;
  2558. csk = &cp->csk_tbl[l5_cid];
  2559. csk_hold(csk);
  2560. if (!cnic_in_use(csk)) {
  2561. csk_put(csk);
  2562. return;
  2563. }
  2564. switch (opcode) {
  2565. case L5CM_RAMROD_CMD_ID_TCP_CONNECT:
  2566. if (l4kcqe->status != 0) {
  2567. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  2568. cnic_cm_upcall(cp, csk,
  2569. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  2570. }
  2571. break;
  2572. case L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE:
  2573. if (l4kcqe->status == 0)
  2574. set_bit(SK_F_OFFLD_COMPLETE, &csk->flags);
  2575. smp_mb__before_clear_bit();
  2576. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  2577. cnic_cm_upcall(cp, csk, opcode);
  2578. break;
  2579. case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
  2580. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags))
  2581. csk->state = opcode;
  2582. /* fall through */
  2583. case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
  2584. case L4_KCQE_OPCODE_VALUE_RESET_COMP:
  2585. case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
  2586. case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
  2587. cp->close_conn(csk, opcode);
  2588. break;
  2589. case L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED:
  2590. cnic_cm_upcall(cp, csk, opcode);
  2591. break;
  2592. }
  2593. csk_put(csk);
  2594. }
  2595. static void cnic_cm_indicate_kcqe(void *data, struct kcqe *kcqe[], u32 num)
  2596. {
  2597. struct cnic_dev *dev = data;
  2598. int i;
  2599. for (i = 0; i < num; i++)
  2600. cnic_cm_process_kcqe(dev, kcqe[i]);
  2601. }
  2602. static struct cnic_ulp_ops cm_ulp_ops = {
  2603. .indicate_kcqes = cnic_cm_indicate_kcqe,
  2604. };
  2605. static void cnic_cm_free_mem(struct cnic_dev *dev)
  2606. {
  2607. struct cnic_local *cp = dev->cnic_priv;
  2608. kfree(cp->csk_tbl);
  2609. cp->csk_tbl = NULL;
  2610. cnic_free_id_tbl(&cp->csk_port_tbl);
  2611. }
  2612. static int cnic_cm_alloc_mem(struct cnic_dev *dev)
  2613. {
  2614. struct cnic_local *cp = dev->cnic_priv;
  2615. cp->csk_tbl = kzalloc(sizeof(struct cnic_sock) * MAX_CM_SK_TBL_SZ,
  2616. GFP_KERNEL);
  2617. if (!cp->csk_tbl)
  2618. return -ENOMEM;
  2619. if (cnic_init_id_tbl(&cp->csk_port_tbl, CNIC_LOCAL_PORT_RANGE,
  2620. CNIC_LOCAL_PORT_MIN)) {
  2621. cnic_cm_free_mem(dev);
  2622. return -ENOMEM;
  2623. }
  2624. return 0;
  2625. }
  2626. static int cnic_ready_to_close(struct cnic_sock *csk, u32 opcode)
  2627. {
  2628. if ((opcode == csk->state) ||
  2629. (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED &&
  2630. csk->state == L4_KCQE_OPCODE_VALUE_CLOSE_COMP)) {
  2631. if (!test_and_set_bit(SK_F_CLOSING, &csk->flags))
  2632. return 1;
  2633. }
  2634. return 0;
  2635. }
  2636. static void cnic_close_bnx2_conn(struct cnic_sock *csk, u32 opcode)
  2637. {
  2638. struct cnic_dev *dev = csk->dev;
  2639. struct cnic_local *cp = dev->cnic_priv;
  2640. clear_bit(SK_F_CONNECT_START, &csk->flags);
  2641. if (cnic_ready_to_close(csk, opcode)) {
  2642. cnic_close_conn(csk);
  2643. cnic_cm_upcall(cp, csk, opcode);
  2644. }
  2645. }
  2646. static void cnic_cm_stop_bnx2_hw(struct cnic_dev *dev)
  2647. {
  2648. }
  2649. static int cnic_cm_init_bnx2_hw(struct cnic_dev *dev)
  2650. {
  2651. u32 seed;
  2652. get_random_bytes(&seed, 4);
  2653. cnic_ctx_wr(dev, 45, 0, seed);
  2654. return 0;
  2655. }
  2656. static void cnic_close_bnx2x_conn(struct cnic_sock *csk, u32 opcode)
  2657. {
  2658. struct cnic_dev *dev = csk->dev;
  2659. struct cnic_local *cp = dev->cnic_priv;
  2660. struct cnic_context *ctx = &cp->ctx_tbl[csk->l5_cid];
  2661. union l5cm_specific_data l5_data;
  2662. u32 cmd = 0;
  2663. int close_complete = 0;
  2664. switch (opcode) {
  2665. case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
  2666. case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
  2667. case L4_KCQE_OPCODE_VALUE_RESET_COMP:
  2668. if (cnic_ready_to_close(csk, opcode))
  2669. cmd = L5CM_RAMROD_CMD_ID_SEARCHER_DELETE;
  2670. break;
  2671. case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
  2672. cmd = L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD;
  2673. break;
  2674. case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
  2675. close_complete = 1;
  2676. break;
  2677. }
  2678. if (cmd) {
  2679. memset(&l5_data, 0, sizeof(l5_data));
  2680. cnic_submit_kwqe_16(dev, cmd, csk->cid, ISCSI_CONNECTION_TYPE,
  2681. &l5_data);
  2682. } else if (close_complete) {
  2683. ctx->timestamp = jiffies;
  2684. cnic_close_conn(csk);
  2685. cnic_cm_upcall(cp, csk, csk->state);
  2686. }
  2687. }
  2688. static void cnic_cm_stop_bnx2x_hw(struct cnic_dev *dev)
  2689. {
  2690. }
  2691. static int cnic_cm_init_bnx2x_hw(struct cnic_dev *dev)
  2692. {
  2693. struct cnic_local *cp = dev->cnic_priv;
  2694. int func = CNIC_FUNC(cp);
  2695. cnic_init_bnx2x_mac(dev);
  2696. cnic_bnx2x_set_tcp_timestamp(dev, 1);
  2697. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  2698. XSTORM_ISCSI_LOCAL_VLAN_OFFSET(func), 0);
  2699. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  2700. XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(func), 1);
  2701. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  2702. XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(func),
  2703. DEF_MAX_DA_COUNT);
  2704. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  2705. XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(func), DEF_TTL);
  2706. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  2707. XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(func), DEF_TOS);
  2708. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  2709. XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(func), 2);
  2710. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  2711. XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(func), DEF_SWS_TIMER);
  2712. CNIC_WR(dev, BAR_TSTRORM_INTMEM + TSTORM_TCP_MAX_CWND_OFFSET(func),
  2713. DEF_MAX_CWND);
  2714. return 0;
  2715. }
  2716. static int cnic_cm_open(struct cnic_dev *dev)
  2717. {
  2718. struct cnic_local *cp = dev->cnic_priv;
  2719. int err;
  2720. err = cnic_cm_alloc_mem(dev);
  2721. if (err)
  2722. return err;
  2723. err = cp->start_cm(dev);
  2724. if (err)
  2725. goto err_out;
  2726. dev->cm_create = cnic_cm_create;
  2727. dev->cm_destroy = cnic_cm_destroy;
  2728. dev->cm_connect = cnic_cm_connect;
  2729. dev->cm_abort = cnic_cm_abort;
  2730. dev->cm_close = cnic_cm_close;
  2731. dev->cm_select_dev = cnic_cm_select_dev;
  2732. cp->ulp_handle[CNIC_ULP_L4] = dev;
  2733. rcu_assign_pointer(cp->ulp_ops[CNIC_ULP_L4], &cm_ulp_ops);
  2734. return 0;
  2735. err_out:
  2736. cnic_cm_free_mem(dev);
  2737. return err;
  2738. }
  2739. static int cnic_cm_shutdown(struct cnic_dev *dev)
  2740. {
  2741. struct cnic_local *cp = dev->cnic_priv;
  2742. int i;
  2743. cp->stop_cm(dev);
  2744. if (!cp->csk_tbl)
  2745. return 0;
  2746. for (i = 0; i < MAX_CM_SK_TBL_SZ; i++) {
  2747. struct cnic_sock *csk = &cp->csk_tbl[i];
  2748. clear_bit(SK_F_INUSE, &csk->flags);
  2749. cnic_cm_cleanup(csk);
  2750. }
  2751. cnic_cm_free_mem(dev);
  2752. return 0;
  2753. }
  2754. static void cnic_init_context(struct cnic_dev *dev, u32 cid)
  2755. {
  2756. struct cnic_local *cp = dev->cnic_priv;
  2757. u32 cid_addr;
  2758. int i;
  2759. if (CHIP_NUM(cp) == CHIP_NUM_5709)
  2760. return;
  2761. cid_addr = GET_CID_ADDR(cid);
  2762. for (i = 0; i < CTX_SIZE; i += 4)
  2763. cnic_ctx_wr(dev, cid_addr, i, 0);
  2764. }
  2765. static int cnic_setup_5709_context(struct cnic_dev *dev, int valid)
  2766. {
  2767. struct cnic_local *cp = dev->cnic_priv;
  2768. int ret = 0, i;
  2769. u32 valid_bit = valid ? BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID : 0;
  2770. if (CHIP_NUM(cp) != CHIP_NUM_5709)
  2771. return 0;
  2772. for (i = 0; i < cp->ctx_blks; i++) {
  2773. int j;
  2774. u32 idx = cp->ctx_arr[i].cid / cp->cids_per_blk;
  2775. u32 val;
  2776. memset(cp->ctx_arr[i].ctx, 0, BCM_PAGE_SIZE);
  2777. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA0,
  2778. (cp->ctx_arr[i].mapping & 0xffffffff) | valid_bit);
  2779. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA1,
  2780. (u64) cp->ctx_arr[i].mapping >> 32);
  2781. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL, idx |
  2782. BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
  2783. for (j = 0; j < 10; j++) {
  2784. val = CNIC_RD(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL);
  2785. if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
  2786. break;
  2787. udelay(5);
  2788. }
  2789. if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
  2790. ret = -EBUSY;
  2791. break;
  2792. }
  2793. }
  2794. return ret;
  2795. }
  2796. static void cnic_free_irq(struct cnic_dev *dev)
  2797. {
  2798. struct cnic_local *cp = dev->cnic_priv;
  2799. struct cnic_eth_dev *ethdev = cp->ethdev;
  2800. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  2801. cp->disable_int_sync(dev);
  2802. tasklet_disable(&cp->cnic_irq_task);
  2803. free_irq(ethdev->irq_arr[0].vector, dev);
  2804. }
  2805. }
  2806. static int cnic_init_bnx2_irq(struct cnic_dev *dev)
  2807. {
  2808. struct cnic_local *cp = dev->cnic_priv;
  2809. struct cnic_eth_dev *ethdev = cp->ethdev;
  2810. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  2811. int err, i = 0;
  2812. int sblk_num = cp->status_blk_num;
  2813. u32 base = ((sblk_num - 1) * BNX2_HC_SB_CONFIG_SIZE) +
  2814. BNX2_HC_SB_CONFIG_1;
  2815. CNIC_WR(dev, base, BNX2_HC_SB_CONFIG_1_ONE_SHOT);
  2816. CNIC_WR(dev, base + BNX2_HC_COMP_PROD_TRIP_OFF, (2 << 16) | 8);
  2817. CNIC_WR(dev, base + BNX2_HC_COM_TICKS_OFF, (64 << 16) | 220);
  2818. CNIC_WR(dev, base + BNX2_HC_CMD_TICKS_OFF, (64 << 16) | 220);
  2819. cp->bnx2_status_blk = cp->status_blk;
  2820. cp->last_status_idx = cp->bnx2_status_blk->status_idx;
  2821. tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2_msix,
  2822. (unsigned long) dev);
  2823. err = request_irq(ethdev->irq_arr[0].vector, cnic_irq, 0,
  2824. "cnic", dev);
  2825. if (err) {
  2826. tasklet_disable(&cp->cnic_irq_task);
  2827. return err;
  2828. }
  2829. while (cp->bnx2_status_blk->status_completion_producer_index &&
  2830. i < 10) {
  2831. CNIC_WR(dev, BNX2_HC_COALESCE_NOW,
  2832. 1 << (11 + sblk_num));
  2833. udelay(10);
  2834. i++;
  2835. barrier();
  2836. }
  2837. if (cp->bnx2_status_blk->status_completion_producer_index) {
  2838. cnic_free_irq(dev);
  2839. goto failed;
  2840. }
  2841. } else {
  2842. struct status_block *sblk = cp->status_blk;
  2843. u32 hc_cmd = CNIC_RD(dev, BNX2_HC_COMMAND);
  2844. int i = 0;
  2845. while (sblk->status_completion_producer_index && i < 10) {
  2846. CNIC_WR(dev, BNX2_HC_COMMAND,
  2847. hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
  2848. udelay(10);
  2849. i++;
  2850. barrier();
  2851. }
  2852. if (sblk->status_completion_producer_index)
  2853. goto failed;
  2854. }
  2855. return 0;
  2856. failed:
  2857. netdev_err(dev->netdev, "KCQ index not resetting to 0\n");
  2858. return -EBUSY;
  2859. }
  2860. static void cnic_enable_bnx2_int(struct cnic_dev *dev)
  2861. {
  2862. struct cnic_local *cp = dev->cnic_priv;
  2863. struct cnic_eth_dev *ethdev = cp->ethdev;
  2864. if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  2865. return;
  2866. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  2867. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
  2868. }
  2869. static void cnic_disable_bnx2_int_sync(struct cnic_dev *dev)
  2870. {
  2871. struct cnic_local *cp = dev->cnic_priv;
  2872. struct cnic_eth_dev *ethdev = cp->ethdev;
  2873. if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  2874. return;
  2875. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  2876. BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
  2877. CNIC_RD(dev, BNX2_PCICFG_INT_ACK_CMD);
  2878. synchronize_irq(ethdev->irq_arr[0].vector);
  2879. }
  2880. static void cnic_init_bnx2_tx_ring(struct cnic_dev *dev)
  2881. {
  2882. struct cnic_local *cp = dev->cnic_priv;
  2883. struct cnic_eth_dev *ethdev = cp->ethdev;
  2884. u32 cid_addr, tx_cid, sb_id;
  2885. u32 val, offset0, offset1, offset2, offset3;
  2886. int i;
  2887. struct tx_bd *txbd;
  2888. dma_addr_t buf_map;
  2889. struct status_block *s_blk = cp->status_blk;
  2890. sb_id = cp->status_blk_num;
  2891. tx_cid = 20;
  2892. cnic_init_context(dev, tx_cid);
  2893. cnic_init_context(dev, tx_cid + 1);
  2894. cp->tx_cons_ptr = &s_blk->status_tx_quick_consumer_index2;
  2895. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  2896. struct status_block_msix *sblk = cp->status_blk;
  2897. tx_cid = TX_TSS_CID + sb_id - 1;
  2898. cnic_init_context(dev, tx_cid);
  2899. CNIC_WR(dev, BNX2_TSCH_TSS_CFG, (sb_id << 24) |
  2900. (TX_TSS_CID << 7));
  2901. cp->tx_cons_ptr = &sblk->status_tx_quick_consumer_index;
  2902. }
  2903. cp->tx_cons = *cp->tx_cons_ptr;
  2904. cid_addr = GET_CID_ADDR(tx_cid);
  2905. if (CHIP_NUM(cp) == CHIP_NUM_5709) {
  2906. u32 cid_addr2 = GET_CID_ADDR(tx_cid + 4) + 0x40;
  2907. for (i = 0; i < PHY_CTX_SIZE; i += 4)
  2908. cnic_ctx_wr(dev, cid_addr2, i, 0);
  2909. offset0 = BNX2_L2CTX_TYPE_XI;
  2910. offset1 = BNX2_L2CTX_CMD_TYPE_XI;
  2911. offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
  2912. offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
  2913. } else {
  2914. offset0 = BNX2_L2CTX_TYPE;
  2915. offset1 = BNX2_L2CTX_CMD_TYPE;
  2916. offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
  2917. offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
  2918. }
  2919. val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
  2920. cnic_ctx_wr(dev, cid_addr, offset0, val);
  2921. val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
  2922. cnic_ctx_wr(dev, cid_addr, offset1, val);
  2923. txbd = (struct tx_bd *) cp->l2_ring;
  2924. buf_map = cp->l2_buf_map;
  2925. for (i = 0; i < MAX_TX_DESC_CNT; i++, txbd++) {
  2926. txbd->tx_bd_haddr_hi = (u64) buf_map >> 32;
  2927. txbd->tx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
  2928. }
  2929. val = (u64) cp->l2_ring_map >> 32;
  2930. cnic_ctx_wr(dev, cid_addr, offset2, val);
  2931. txbd->tx_bd_haddr_hi = val;
  2932. val = (u64) cp->l2_ring_map & 0xffffffff;
  2933. cnic_ctx_wr(dev, cid_addr, offset3, val);
  2934. txbd->tx_bd_haddr_lo = val;
  2935. }
  2936. static void cnic_init_bnx2_rx_ring(struct cnic_dev *dev)
  2937. {
  2938. struct cnic_local *cp = dev->cnic_priv;
  2939. struct cnic_eth_dev *ethdev = cp->ethdev;
  2940. u32 cid_addr, sb_id, val, coal_reg, coal_val;
  2941. int i;
  2942. struct rx_bd *rxbd;
  2943. struct status_block *s_blk = cp->status_blk;
  2944. sb_id = cp->status_blk_num;
  2945. cnic_init_context(dev, 2);
  2946. cp->rx_cons_ptr = &s_blk->status_rx_quick_consumer_index2;
  2947. coal_reg = BNX2_HC_COMMAND;
  2948. coal_val = CNIC_RD(dev, coal_reg);
  2949. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  2950. struct status_block_msix *sblk = cp->status_blk;
  2951. cp->rx_cons_ptr = &sblk->status_rx_quick_consumer_index;
  2952. coal_reg = BNX2_HC_COALESCE_NOW;
  2953. coal_val = 1 << (11 + sb_id);
  2954. }
  2955. i = 0;
  2956. while (!(*cp->rx_cons_ptr != 0) && i < 10) {
  2957. CNIC_WR(dev, coal_reg, coal_val);
  2958. udelay(10);
  2959. i++;
  2960. barrier();
  2961. }
  2962. cp->rx_cons = *cp->rx_cons_ptr;
  2963. cid_addr = GET_CID_ADDR(2);
  2964. val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE |
  2965. BNX2_L2CTX_CTX_TYPE_SIZE_L2 | (0x02 << 8);
  2966. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_CTX_TYPE, val);
  2967. if (sb_id == 0)
  2968. val = 2 << BNX2_L2CTX_L2_STATUSB_NUM_SHIFT;
  2969. else
  2970. val = BNX2_L2CTX_L2_STATUSB_NUM(sb_id);
  2971. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_HOST_BDIDX, val);
  2972. rxbd = (struct rx_bd *) (cp->l2_ring + BCM_PAGE_SIZE);
  2973. for (i = 0; i < MAX_RX_DESC_CNT; i++, rxbd++) {
  2974. dma_addr_t buf_map;
  2975. int n = (i % cp->l2_rx_ring_size) + 1;
  2976. buf_map = cp->l2_buf_map + (n * cp->l2_single_buf_size);
  2977. rxbd->rx_bd_len = cp->l2_single_buf_size;
  2978. rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
  2979. rxbd->rx_bd_haddr_hi = (u64) buf_map >> 32;
  2980. rxbd->rx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
  2981. }
  2982. val = (u64) (cp->l2_ring_map + BCM_PAGE_SIZE) >> 32;
  2983. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
  2984. rxbd->rx_bd_haddr_hi = val;
  2985. val = (u64) (cp->l2_ring_map + BCM_PAGE_SIZE) & 0xffffffff;
  2986. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
  2987. rxbd->rx_bd_haddr_lo = val;
  2988. val = cnic_reg_rd_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD);
  2989. cnic_reg_wr_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD, val | (1 << 2));
  2990. }
  2991. static void cnic_shutdown_bnx2_rx_ring(struct cnic_dev *dev)
  2992. {
  2993. struct kwqe *wqes[1], l2kwqe;
  2994. memset(&l2kwqe, 0, sizeof(l2kwqe));
  2995. wqes[0] = &l2kwqe;
  2996. l2kwqe.kwqe_op_flag = (L2_LAYER_CODE << KWQE_FLAGS_LAYER_SHIFT) |
  2997. (L2_KWQE_OPCODE_VALUE_FLUSH <<
  2998. KWQE_OPCODE_SHIFT) | 2;
  2999. dev->submit_kwqes(dev, wqes, 1);
  3000. }
  3001. static void cnic_set_bnx2_mac(struct cnic_dev *dev)
  3002. {
  3003. struct cnic_local *cp = dev->cnic_priv;
  3004. u32 val;
  3005. val = cp->func << 2;
  3006. cp->shmem_base = cnic_reg_rd_ind(dev, BNX2_SHM_HDR_ADDR_0 + val);
  3007. val = cnic_reg_rd_ind(dev, cp->shmem_base +
  3008. BNX2_PORT_HW_CFG_ISCSI_MAC_UPPER);
  3009. dev->mac_addr[0] = (u8) (val >> 8);
  3010. dev->mac_addr[1] = (u8) val;
  3011. CNIC_WR(dev, BNX2_EMAC_MAC_MATCH4, val);
  3012. val = cnic_reg_rd_ind(dev, cp->shmem_base +
  3013. BNX2_PORT_HW_CFG_ISCSI_MAC_LOWER);
  3014. dev->mac_addr[2] = (u8) (val >> 24);
  3015. dev->mac_addr[3] = (u8) (val >> 16);
  3016. dev->mac_addr[4] = (u8) (val >> 8);
  3017. dev->mac_addr[5] = (u8) val;
  3018. CNIC_WR(dev, BNX2_EMAC_MAC_MATCH5, val);
  3019. val = 4 | BNX2_RPM_SORT_USER2_BC_EN;
  3020. if (CHIP_NUM(cp) != CHIP_NUM_5709)
  3021. val |= BNX2_RPM_SORT_USER2_PROM_VLAN;
  3022. CNIC_WR(dev, BNX2_RPM_SORT_USER2, 0x0);
  3023. CNIC_WR(dev, BNX2_RPM_SORT_USER2, val);
  3024. CNIC_WR(dev, BNX2_RPM_SORT_USER2, val | BNX2_RPM_SORT_USER2_ENA);
  3025. }
  3026. static int cnic_start_bnx2_hw(struct cnic_dev *dev)
  3027. {
  3028. struct cnic_local *cp = dev->cnic_priv;
  3029. struct cnic_eth_dev *ethdev = cp->ethdev;
  3030. struct status_block *sblk = cp->status_blk;
  3031. u32 val;
  3032. int err;
  3033. cnic_set_bnx2_mac(dev);
  3034. val = CNIC_RD(dev, BNX2_MQ_CONFIG);
  3035. val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
  3036. if (BCM_PAGE_BITS > 12)
  3037. val |= (12 - 8) << 4;
  3038. else
  3039. val |= (BCM_PAGE_BITS - 8) << 4;
  3040. CNIC_WR(dev, BNX2_MQ_CONFIG, val);
  3041. CNIC_WR(dev, BNX2_HC_COMP_PROD_TRIP, (2 << 16) | 8);
  3042. CNIC_WR(dev, BNX2_HC_COM_TICKS, (64 << 16) | 220);
  3043. CNIC_WR(dev, BNX2_HC_CMD_TICKS, (64 << 16) | 220);
  3044. err = cnic_setup_5709_context(dev, 1);
  3045. if (err)
  3046. return err;
  3047. cnic_init_context(dev, KWQ_CID);
  3048. cnic_init_context(dev, KCQ_CID);
  3049. cp->kwq_cid_addr = GET_CID_ADDR(KWQ_CID);
  3050. cp->kwq_io_addr = MB_GET_CID_ADDR(KWQ_CID) + L5_KRNLQ_HOST_QIDX;
  3051. cp->max_kwq_idx = MAX_KWQ_IDX;
  3052. cp->kwq_prod_idx = 0;
  3053. cp->kwq_con_idx = 0;
  3054. cp->cnic_local_flags |= CNIC_LCL_FL_KWQ_INIT;
  3055. if (CHIP_NUM(cp) == CHIP_NUM_5706 || CHIP_NUM(cp) == CHIP_NUM_5708)
  3056. cp->kwq_con_idx_ptr = &sblk->status_rx_quick_consumer_index15;
  3057. else
  3058. cp->kwq_con_idx_ptr = &sblk->status_cmd_consumer_index;
  3059. /* Initialize the kernel work queue context. */
  3060. val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
  3061. (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
  3062. cnic_ctx_wr(dev, cp->kwq_cid_addr, L5_KRNLQ_TYPE, val);
  3063. val = (BCM_PAGE_SIZE / sizeof(struct kwqe) - 1) << 16;
  3064. cnic_ctx_wr(dev, cp->kwq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
  3065. val = ((BCM_PAGE_SIZE / sizeof(struct kwqe)) << 16) | KWQ_PAGE_CNT;
  3066. cnic_ctx_wr(dev, cp->kwq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
  3067. val = (u32) ((u64) cp->kwq_info.pgtbl_map >> 32);
  3068. cnic_ctx_wr(dev, cp->kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
  3069. val = (u32) cp->kwq_info.pgtbl_map;
  3070. cnic_ctx_wr(dev, cp->kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
  3071. cp->kcq_cid_addr = GET_CID_ADDR(KCQ_CID);
  3072. cp->kcq_io_addr = MB_GET_CID_ADDR(KCQ_CID) + L5_KRNLQ_HOST_QIDX;
  3073. cp->kcq_prod_idx = 0;
  3074. /* Initialize the kernel complete queue context. */
  3075. val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
  3076. (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
  3077. cnic_ctx_wr(dev, cp->kcq_cid_addr, L5_KRNLQ_TYPE, val);
  3078. val = (BCM_PAGE_SIZE / sizeof(struct kcqe) - 1) << 16;
  3079. cnic_ctx_wr(dev, cp->kcq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
  3080. val = ((BCM_PAGE_SIZE / sizeof(struct kcqe)) << 16) | KCQ_PAGE_CNT;
  3081. cnic_ctx_wr(dev, cp->kcq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
  3082. val = (u32) ((u64) cp->kcq_info.pgtbl_map >> 32);
  3083. cnic_ctx_wr(dev, cp->kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
  3084. val = (u32) cp->kcq_info.pgtbl_map;
  3085. cnic_ctx_wr(dev, cp->kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
  3086. cp->int_num = 0;
  3087. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3088. u32 sb_id = cp->status_blk_num;
  3089. u32 sb = BNX2_L2CTX_L5_STATUSB_NUM(sb_id);
  3090. cp->int_num = sb_id << BNX2_PCICFG_INT_ACK_CMD_INT_NUM_SHIFT;
  3091. cnic_ctx_wr(dev, cp->kwq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
  3092. cnic_ctx_wr(dev, cp->kcq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
  3093. }
  3094. /* Enable Commnad Scheduler notification when we write to the
  3095. * host producer index of the kernel contexts. */
  3096. CNIC_WR(dev, BNX2_MQ_KNL_CMD_MASK1, 2);
  3097. /* Enable Command Scheduler notification when we write to either
  3098. * the Send Queue or Receive Queue producer indexes of the kernel
  3099. * bypass contexts. */
  3100. CNIC_WR(dev, BNX2_MQ_KNL_BYP_CMD_MASK1, 7);
  3101. CNIC_WR(dev, BNX2_MQ_KNL_BYP_WRITE_MASK1, 7);
  3102. /* Notify COM when the driver post an application buffer. */
  3103. CNIC_WR(dev, BNX2_MQ_KNL_RX_V2P_MASK2, 0x2000);
  3104. /* Set the CP and COM doorbells. These two processors polls the
  3105. * doorbell for a non zero value before running. This must be done
  3106. * after setting up the kernel queue contexts. */
  3107. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 1);
  3108. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 1);
  3109. cnic_init_bnx2_tx_ring(dev);
  3110. cnic_init_bnx2_rx_ring(dev);
  3111. err = cnic_init_bnx2_irq(dev);
  3112. if (err) {
  3113. netdev_err(dev->netdev, "cnic_init_irq failed\n");
  3114. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
  3115. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
  3116. return err;
  3117. }
  3118. return 0;
  3119. }
  3120. static void cnic_setup_bnx2x_context(struct cnic_dev *dev)
  3121. {
  3122. struct cnic_local *cp = dev->cnic_priv;
  3123. struct cnic_eth_dev *ethdev = cp->ethdev;
  3124. u32 start_offset = ethdev->ctx_tbl_offset;
  3125. int i;
  3126. for (i = 0; i < cp->ctx_blks; i++) {
  3127. struct cnic_ctx *ctx = &cp->ctx_arr[i];
  3128. dma_addr_t map = ctx->mapping;
  3129. if (cp->ctx_align) {
  3130. unsigned long mask = cp->ctx_align - 1;
  3131. map = (map + mask) & ~mask;
  3132. }
  3133. cnic_ctx_tbl_wr(dev, start_offset + i, map);
  3134. }
  3135. }
  3136. static int cnic_init_bnx2x_irq(struct cnic_dev *dev)
  3137. {
  3138. struct cnic_local *cp = dev->cnic_priv;
  3139. struct cnic_eth_dev *ethdev = cp->ethdev;
  3140. int err = 0;
  3141. tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2x_bh,
  3142. (unsigned long) dev);
  3143. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3144. err = request_irq(ethdev->irq_arr[0].vector, cnic_irq, 0,
  3145. "cnic", dev);
  3146. if (err)
  3147. tasklet_disable(&cp->cnic_irq_task);
  3148. }
  3149. return err;
  3150. }
  3151. static void cnic_enable_bnx2x_int(struct cnic_dev *dev)
  3152. {
  3153. struct cnic_local *cp = dev->cnic_priv;
  3154. u8 sb_id = cp->status_blk_num;
  3155. int port = CNIC_PORT(cp);
  3156. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  3157. CSTORM_SB_HC_TIMEOUT_C_OFFSET(port, sb_id,
  3158. HC_INDEX_C_ISCSI_EQ_CONS),
  3159. 64 / 12);
  3160. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  3161. CSTORM_SB_HC_DISABLE_C_OFFSET(port, sb_id,
  3162. HC_INDEX_C_ISCSI_EQ_CONS), 0);
  3163. }
  3164. static void cnic_disable_bnx2x_int_sync(struct cnic_dev *dev)
  3165. {
  3166. }
  3167. static void cnic_init_bnx2x_tx_ring(struct cnic_dev *dev)
  3168. {
  3169. struct cnic_local *cp = dev->cnic_priv;
  3170. union eth_tx_bd_types *txbd = (union eth_tx_bd_types *) cp->l2_ring;
  3171. struct eth_context *context;
  3172. struct regpair context_addr;
  3173. dma_addr_t buf_map;
  3174. int func = CNIC_FUNC(cp);
  3175. int port = CNIC_PORT(cp);
  3176. int i;
  3177. int cli = BNX2X_ISCSI_CL_ID(CNIC_E1HVN(cp));
  3178. u32 val;
  3179. memset(txbd, 0, BCM_PAGE_SIZE);
  3180. buf_map = cp->l2_buf_map;
  3181. for (i = 0; i < MAX_TX_DESC_CNT; i += 3, txbd += 3) {
  3182. struct eth_tx_start_bd *start_bd = &txbd->start_bd;
  3183. struct eth_tx_bd *reg_bd = &((txbd + 2)->reg_bd);
  3184. start_bd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
  3185. start_bd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
  3186. reg_bd->addr_hi = start_bd->addr_hi;
  3187. reg_bd->addr_lo = start_bd->addr_lo + 0x10;
  3188. start_bd->nbytes = cpu_to_le16(0x10);
  3189. start_bd->nbd = cpu_to_le16(3);
  3190. start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
  3191. start_bd->general_data = (UNICAST_ADDRESS <<
  3192. ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT);
  3193. start_bd->general_data |= (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
  3194. }
  3195. context = cnic_get_bnx2x_ctx(dev, BNX2X_ISCSI_L2_CID, 1, &context_addr);
  3196. val = (u64) cp->l2_ring_map >> 32;
  3197. txbd->next_bd.addr_hi = cpu_to_le32(val);
  3198. context->xstorm_st_context.tx_bd_page_base_hi = val;
  3199. val = (u64) cp->l2_ring_map & 0xffffffff;
  3200. txbd->next_bd.addr_lo = cpu_to_le32(val);
  3201. context->xstorm_st_context.tx_bd_page_base_lo = val;
  3202. context->cstorm_st_context.sb_index_number =
  3203. HC_INDEX_DEF_C_ETH_ISCSI_CQ_CONS;
  3204. context->cstorm_st_context.status_block_id = BNX2X_DEF_SB_ID;
  3205. context->xstorm_st_context.statistics_data = (cli |
  3206. XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE);
  3207. context->xstorm_ag_context.cdu_reserved =
  3208. CDU_RSRVD_VALUE_TYPE_A(BNX2X_HW_CID(BNX2X_ISCSI_L2_CID, func),
  3209. CDU_REGION_NUMBER_XCM_AG,
  3210. ETH_CONNECTION_TYPE);
  3211. /* reset xstorm per client statistics */
  3212. val = BAR_XSTRORM_INTMEM +
  3213. XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, cli);
  3214. for (i = 0; i < sizeof(struct xstorm_per_client_stats) / 4; i++)
  3215. CNIC_WR(dev, val + i * 4, 0);
  3216. cp->tx_cons_ptr =
  3217. &cp->bnx2x_def_status_blk->c_def_status_block.index_values[
  3218. HC_INDEX_DEF_C_ETH_ISCSI_CQ_CONS];
  3219. }
  3220. static void cnic_init_bnx2x_rx_ring(struct cnic_dev *dev)
  3221. {
  3222. struct cnic_local *cp = dev->cnic_priv;
  3223. struct eth_rx_bd *rxbd = (struct eth_rx_bd *) (cp->l2_ring +
  3224. BCM_PAGE_SIZE);
  3225. struct eth_rx_cqe_next_page *rxcqe = (struct eth_rx_cqe_next_page *)
  3226. (cp->l2_ring + (2 * BCM_PAGE_SIZE));
  3227. struct eth_context *context;
  3228. struct regpair context_addr;
  3229. int i;
  3230. int port = CNIC_PORT(cp);
  3231. int func = CNIC_FUNC(cp);
  3232. int cli = BNX2X_ISCSI_CL_ID(CNIC_E1HVN(cp));
  3233. u32 val;
  3234. struct tstorm_eth_client_config tstorm_client = {0};
  3235. for (i = 0; i < BNX2X_MAX_RX_DESC_CNT; i++, rxbd++) {
  3236. dma_addr_t buf_map;
  3237. int n = (i % cp->l2_rx_ring_size) + 1;
  3238. buf_map = cp->l2_buf_map + (n * cp->l2_single_buf_size);
  3239. rxbd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
  3240. rxbd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
  3241. }
  3242. context = cnic_get_bnx2x_ctx(dev, BNX2X_ISCSI_L2_CID, 0, &context_addr);
  3243. val = (u64) (cp->l2_ring_map + BCM_PAGE_SIZE) >> 32;
  3244. rxbd->addr_hi = cpu_to_le32(val);
  3245. context->ustorm_st_context.common.bd_page_base_hi = val;
  3246. val = (u64) (cp->l2_ring_map + BCM_PAGE_SIZE) & 0xffffffff;
  3247. rxbd->addr_lo = cpu_to_le32(val);
  3248. context->ustorm_st_context.common.bd_page_base_lo = val;
  3249. context->ustorm_st_context.common.sb_index_numbers =
  3250. BNX2X_ISCSI_RX_SB_INDEX_NUM;
  3251. context->ustorm_st_context.common.clientId = cli;
  3252. context->ustorm_st_context.common.status_block_id = BNX2X_DEF_SB_ID;
  3253. context->ustorm_st_context.common.flags =
  3254. USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS;
  3255. context->ustorm_st_context.common.statistics_counter_id = cli;
  3256. context->ustorm_st_context.common.mc_alignment_log_size = 0;
  3257. context->ustorm_st_context.common.bd_buff_size =
  3258. cp->l2_single_buf_size;
  3259. context->ustorm_ag_context.cdu_usage =
  3260. CDU_RSRVD_VALUE_TYPE_A(BNX2X_HW_CID(BNX2X_ISCSI_L2_CID, func),
  3261. CDU_REGION_NUMBER_UCM_AG,
  3262. ETH_CONNECTION_TYPE);
  3263. rxcqe += BNX2X_MAX_RCQ_DESC_CNT;
  3264. val = (u64) (cp->l2_ring_map + (2 * BCM_PAGE_SIZE)) >> 32;
  3265. rxcqe->addr_hi = cpu_to_le32(val);
  3266. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  3267. USTORM_CQE_PAGE_BASE_OFFSET(port, cli) + 4, val);
  3268. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  3269. USTORM_CQE_PAGE_NEXT_OFFSET(port, cli) + 4, val);
  3270. val = (u64) (cp->l2_ring_map + (2 * BCM_PAGE_SIZE)) & 0xffffffff;
  3271. rxcqe->addr_lo = cpu_to_le32(val);
  3272. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  3273. USTORM_CQE_PAGE_BASE_OFFSET(port, cli), val);
  3274. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  3275. USTORM_CQE_PAGE_NEXT_OFFSET(port, cli), val);
  3276. /* client tstorm info */
  3277. tstorm_client.mtu = cp->l2_single_buf_size - 14;
  3278. tstorm_client.config_flags =
  3279. (TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE |
  3280. TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE);
  3281. tstorm_client.statistics_counter_id = cli;
  3282. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  3283. TSTORM_CLIENT_CONFIG_OFFSET(port, cli),
  3284. ((u32 *)&tstorm_client)[0]);
  3285. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  3286. TSTORM_CLIENT_CONFIG_OFFSET(port, cli) + 4,
  3287. ((u32 *)&tstorm_client)[1]);
  3288. /* reset tstorm per client statistics */
  3289. val = BAR_TSTRORM_INTMEM +
  3290. TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, cli);
  3291. for (i = 0; i < sizeof(struct tstorm_per_client_stats) / 4; i++)
  3292. CNIC_WR(dev, val + i * 4, 0);
  3293. /* reset ustorm per client statistics */
  3294. val = BAR_USTRORM_INTMEM +
  3295. USTORM_PER_COUNTER_ID_STATS_OFFSET(port, cli);
  3296. for (i = 0; i < sizeof(struct ustorm_per_client_stats) / 4; i++)
  3297. CNIC_WR(dev, val + i * 4, 0);
  3298. cp->rx_cons_ptr =
  3299. &cp->bnx2x_def_status_blk->u_def_status_block.index_values[
  3300. HC_INDEX_DEF_U_ETH_ISCSI_RX_CQ_CONS];
  3301. }
  3302. static void cnic_get_bnx2x_iscsi_info(struct cnic_dev *dev)
  3303. {
  3304. struct cnic_local *cp = dev->cnic_priv;
  3305. u32 base, addr, val;
  3306. int port = CNIC_PORT(cp);
  3307. dev->max_iscsi_conn = 0;
  3308. base = CNIC_RD(dev, MISC_REG_SHARED_MEM_ADDR);
  3309. if (base < 0xa0000 || base >= 0xc0000)
  3310. return;
  3311. addr = BNX2X_SHMEM_ADDR(base,
  3312. dev_info.port_hw_config[port].iscsi_mac_upper);
  3313. val = CNIC_RD(dev, addr);
  3314. dev->mac_addr[0] = (u8) (val >> 8);
  3315. dev->mac_addr[1] = (u8) val;
  3316. addr = BNX2X_SHMEM_ADDR(base,
  3317. dev_info.port_hw_config[port].iscsi_mac_lower);
  3318. val = CNIC_RD(dev, addr);
  3319. dev->mac_addr[2] = (u8) (val >> 24);
  3320. dev->mac_addr[3] = (u8) (val >> 16);
  3321. dev->mac_addr[4] = (u8) (val >> 8);
  3322. dev->mac_addr[5] = (u8) val;
  3323. addr = BNX2X_SHMEM_ADDR(base, validity_map[port]);
  3324. val = CNIC_RD(dev, addr);
  3325. if (!(val & SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT)) {
  3326. u16 val16;
  3327. addr = BNX2X_SHMEM_ADDR(base,
  3328. drv_lic_key[port].max_iscsi_init_conn);
  3329. val16 = CNIC_RD16(dev, addr);
  3330. if (val16)
  3331. val16 ^= 0x1e1e;
  3332. dev->max_iscsi_conn = val16;
  3333. }
  3334. if (BNX2X_CHIP_IS_E1H(cp->chip_id)) {
  3335. int func = CNIC_FUNC(cp);
  3336. addr = BNX2X_SHMEM_ADDR(base,
  3337. mf_cfg.func_mf_config[func].e1hov_tag);
  3338. val = CNIC_RD(dev, addr);
  3339. val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
  3340. if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
  3341. addr = BNX2X_SHMEM_ADDR(base,
  3342. mf_cfg.func_mf_config[func].config);
  3343. val = CNIC_RD(dev, addr);
  3344. val &= FUNC_MF_CFG_PROTOCOL_MASK;
  3345. if (val != FUNC_MF_CFG_PROTOCOL_ISCSI)
  3346. dev->max_iscsi_conn = 0;
  3347. }
  3348. }
  3349. }
  3350. static int cnic_start_bnx2x_hw(struct cnic_dev *dev)
  3351. {
  3352. struct cnic_local *cp = dev->cnic_priv;
  3353. int func = CNIC_FUNC(cp), ret, i;
  3354. int port = CNIC_PORT(cp);
  3355. u16 eq_idx;
  3356. u8 sb_id = cp->status_blk_num;
  3357. ret = cnic_init_id_tbl(&cp->cid_tbl, MAX_ISCSI_TBL_SZ,
  3358. BNX2X_ISCSI_START_CID);
  3359. if (ret)
  3360. return -ENOMEM;
  3361. cp->kcq_io_addr = BAR_CSTRORM_INTMEM +
  3362. CSTORM_ISCSI_EQ_PROD_OFFSET(func, 0);
  3363. cp->kcq_prod_idx = 0;
  3364. cnic_get_bnx2x_iscsi_info(dev);
  3365. /* Only 1 EQ */
  3366. CNIC_WR16(dev, cp->kcq_io_addr, MAX_KCQ_IDX);
  3367. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  3368. CSTORM_ISCSI_EQ_CONS_OFFSET(func, 0), 0);
  3369. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  3370. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(func, 0),
  3371. cp->kcq_info.pg_map_arr[1] & 0xffffffff);
  3372. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  3373. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(func, 0) + 4,
  3374. (u64) cp->kcq_info.pg_map_arr[1] >> 32);
  3375. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  3376. CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(func, 0),
  3377. cp->kcq_info.pg_map_arr[0] & 0xffffffff);
  3378. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  3379. CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(func, 0) + 4,
  3380. (u64) cp->kcq_info.pg_map_arr[0] >> 32);
  3381. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  3382. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(func, 0), 1);
  3383. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  3384. CSTORM_ISCSI_EQ_SB_NUM_OFFSET(func, 0), cp->status_blk_num);
  3385. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  3386. CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(func, 0),
  3387. HC_INDEX_C_ISCSI_EQ_CONS);
  3388. for (i = 0; i < cp->conn_buf_info.num_pages; i++) {
  3389. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  3390. TSTORM_ISCSI_CONN_BUF_PBL_OFFSET(func, i),
  3391. cp->conn_buf_info.pgtbl[2 * i]);
  3392. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  3393. TSTORM_ISCSI_CONN_BUF_PBL_OFFSET(func, i) + 4,
  3394. cp->conn_buf_info.pgtbl[(2 * i) + 1]);
  3395. }
  3396. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  3397. USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(func),
  3398. cp->gbl_buf_info.pg_map_arr[0] & 0xffffffff);
  3399. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  3400. USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(func) + 4,
  3401. (u64) cp->gbl_buf_info.pg_map_arr[0] >> 32);
  3402. cnic_setup_bnx2x_context(dev);
  3403. eq_idx = CNIC_RD16(dev, BAR_CSTRORM_INTMEM +
  3404. CSTORM_SB_HOST_STATUS_BLOCK_C_OFFSET(port, sb_id) +
  3405. offsetof(struct cstorm_status_block_c,
  3406. index_values[HC_INDEX_C_ISCSI_EQ_CONS]));
  3407. if (eq_idx != 0) {
  3408. netdev_err(dev->netdev, "EQ cons index %x != 0\n", eq_idx);
  3409. return -EBUSY;
  3410. }
  3411. ret = cnic_init_bnx2x_irq(dev);
  3412. if (ret)
  3413. return ret;
  3414. cnic_init_bnx2x_tx_ring(dev);
  3415. cnic_init_bnx2x_rx_ring(dev);
  3416. return 0;
  3417. }
  3418. static void cnic_init_rings(struct cnic_dev *dev)
  3419. {
  3420. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  3421. cnic_init_bnx2_tx_ring(dev);
  3422. cnic_init_bnx2_rx_ring(dev);
  3423. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  3424. struct cnic_local *cp = dev->cnic_priv;
  3425. u32 cli = BNX2X_ISCSI_CL_ID(CNIC_E1HVN(cp));
  3426. union l5cm_specific_data l5_data;
  3427. struct ustorm_eth_rx_producers rx_prods = {0};
  3428. u32 off, i;
  3429. rx_prods.bd_prod = 0;
  3430. rx_prods.cqe_prod = BNX2X_MAX_RCQ_DESC_CNT;
  3431. barrier();
  3432. off = BAR_USTRORM_INTMEM +
  3433. USTORM_RX_PRODS_OFFSET(CNIC_PORT(cp), cli);
  3434. for (i = 0; i < sizeof(struct ustorm_eth_rx_producers) / 4; i++)
  3435. CNIC_WR(dev, off + i * 4, ((u32 *) &rx_prods)[i]);
  3436. cnic_init_bnx2x_tx_ring(dev);
  3437. cnic_init_bnx2x_rx_ring(dev);
  3438. l5_data.phy_address.lo = cli;
  3439. l5_data.phy_address.hi = 0;
  3440. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_CLIENT_SETUP,
  3441. BNX2X_ISCSI_L2_CID, ETH_CONNECTION_TYPE, &l5_data);
  3442. cnic_ring_ctl(dev, BNX2X_ISCSI_L2_CID, cli, 1);
  3443. }
  3444. }
  3445. static void cnic_shutdown_rings(struct cnic_dev *dev)
  3446. {
  3447. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  3448. cnic_shutdown_bnx2_rx_ring(dev);
  3449. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  3450. struct cnic_local *cp = dev->cnic_priv;
  3451. u32 cli = BNX2X_ISCSI_CL_ID(CNIC_E1HVN(cp));
  3452. union l5cm_specific_data l5_data;
  3453. cnic_ring_ctl(dev, BNX2X_ISCSI_L2_CID, cli, 0);
  3454. l5_data.phy_address.lo = cli;
  3455. l5_data.phy_address.hi = 0;
  3456. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_HALT,
  3457. BNX2X_ISCSI_L2_CID, ETH_CONNECTION_TYPE, &l5_data);
  3458. msleep(10);
  3459. memset(&l5_data, 0, sizeof(l5_data));
  3460. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_CFC_DEL,
  3461. BNX2X_ISCSI_L2_CID, ETH_CONNECTION_TYPE |
  3462. (1 << SPE_HDR_COMMON_RAMROD_SHIFT), &l5_data);
  3463. msleep(10);
  3464. }
  3465. }
  3466. static int cnic_register_netdev(struct cnic_dev *dev)
  3467. {
  3468. struct cnic_local *cp = dev->cnic_priv;
  3469. struct cnic_eth_dev *ethdev = cp->ethdev;
  3470. int err;
  3471. if (!ethdev)
  3472. return -ENODEV;
  3473. if (ethdev->drv_state & CNIC_DRV_STATE_REGD)
  3474. return 0;
  3475. err = ethdev->drv_register_cnic(dev->netdev, cp->cnic_ops, dev);
  3476. if (err)
  3477. netdev_err(dev->netdev, "register_cnic failed\n");
  3478. return err;
  3479. }
  3480. static void cnic_unregister_netdev(struct cnic_dev *dev)
  3481. {
  3482. struct cnic_local *cp = dev->cnic_priv;
  3483. struct cnic_eth_dev *ethdev = cp->ethdev;
  3484. if (!ethdev)
  3485. return;
  3486. ethdev->drv_unregister_cnic(dev->netdev);
  3487. }
  3488. static int cnic_start_hw(struct cnic_dev *dev)
  3489. {
  3490. struct cnic_local *cp = dev->cnic_priv;
  3491. struct cnic_eth_dev *ethdev = cp->ethdev;
  3492. int err;
  3493. if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
  3494. return -EALREADY;
  3495. dev->regview = ethdev->io_base;
  3496. cp->chip_id = ethdev->chip_id;
  3497. pci_dev_get(dev->pcidev);
  3498. cp->func = PCI_FUNC(dev->pcidev->devfn);
  3499. cp->status_blk = ethdev->irq_arr[0].status_blk;
  3500. cp->status_blk_num = ethdev->irq_arr[0].status_blk_num;
  3501. err = cp->alloc_resc(dev);
  3502. if (err) {
  3503. netdev_err(dev->netdev, "allocate resource failure\n");
  3504. goto err1;
  3505. }
  3506. err = cp->start_hw(dev);
  3507. if (err)
  3508. goto err1;
  3509. err = cnic_cm_open(dev);
  3510. if (err)
  3511. goto err1;
  3512. set_bit(CNIC_F_CNIC_UP, &dev->flags);
  3513. cp->enable_int(dev);
  3514. return 0;
  3515. err1:
  3516. cp->free_resc(dev);
  3517. pci_dev_put(dev->pcidev);
  3518. return err;
  3519. }
  3520. static void cnic_stop_bnx2_hw(struct cnic_dev *dev)
  3521. {
  3522. cnic_disable_bnx2_int_sync(dev);
  3523. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
  3524. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
  3525. cnic_init_context(dev, KWQ_CID);
  3526. cnic_init_context(dev, KCQ_CID);
  3527. cnic_setup_5709_context(dev, 0);
  3528. cnic_free_irq(dev);
  3529. cnic_free_resc(dev);
  3530. }
  3531. static void cnic_stop_bnx2x_hw(struct cnic_dev *dev)
  3532. {
  3533. struct cnic_local *cp = dev->cnic_priv;
  3534. u8 sb_id = cp->status_blk_num;
  3535. int port = CNIC_PORT(cp);
  3536. cnic_free_irq(dev);
  3537. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  3538. CSTORM_SB_HOST_STATUS_BLOCK_C_OFFSET(port, sb_id) +
  3539. offsetof(struct cstorm_status_block_c,
  3540. index_values[HC_INDEX_C_ISCSI_EQ_CONS]),
  3541. 0);
  3542. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  3543. CSTORM_ISCSI_EQ_CONS_OFFSET(cp->func, 0), 0);
  3544. CNIC_WR16(dev, cp->kcq_io_addr, 0);
  3545. cnic_free_resc(dev);
  3546. }
  3547. static void cnic_stop_hw(struct cnic_dev *dev)
  3548. {
  3549. if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  3550. struct cnic_local *cp = dev->cnic_priv;
  3551. clear_bit(CNIC_F_CNIC_UP, &dev->flags);
  3552. rcu_assign_pointer(cp->ulp_ops[CNIC_ULP_L4], NULL);
  3553. synchronize_rcu();
  3554. cnic_cm_shutdown(dev);
  3555. cp->stop_hw(dev);
  3556. pci_dev_put(dev->pcidev);
  3557. }
  3558. }
  3559. static void cnic_free_dev(struct cnic_dev *dev)
  3560. {
  3561. int i = 0;
  3562. while ((atomic_read(&dev->ref_count) != 0) && i < 10) {
  3563. msleep(100);
  3564. i++;
  3565. }
  3566. if (atomic_read(&dev->ref_count) != 0)
  3567. netdev_err(dev->netdev, "Failed waiting for ref count to go to zero\n");
  3568. netdev_info(dev->netdev, "Removed CNIC device\n");
  3569. dev_put(dev->netdev);
  3570. kfree(dev);
  3571. }
  3572. static struct cnic_dev *cnic_alloc_dev(struct net_device *dev,
  3573. struct pci_dev *pdev)
  3574. {
  3575. struct cnic_dev *cdev;
  3576. struct cnic_local *cp;
  3577. int alloc_size;
  3578. alloc_size = sizeof(struct cnic_dev) + sizeof(struct cnic_local);
  3579. cdev = kzalloc(alloc_size , GFP_KERNEL);
  3580. if (cdev == NULL) {
  3581. netdev_err(dev, "allocate dev struct failure\n");
  3582. return NULL;
  3583. }
  3584. cdev->netdev = dev;
  3585. cdev->cnic_priv = (char *)cdev + sizeof(struct cnic_dev);
  3586. cdev->register_device = cnic_register_device;
  3587. cdev->unregister_device = cnic_unregister_device;
  3588. cdev->iscsi_nl_msg_recv = cnic_iscsi_nl_msg_recv;
  3589. cp = cdev->cnic_priv;
  3590. cp->dev = cdev;
  3591. cp->uio_dev = -1;
  3592. cp->l2_single_buf_size = 0x400;
  3593. cp->l2_rx_ring_size = 3;
  3594. spin_lock_init(&cp->cnic_ulp_lock);
  3595. netdev_info(dev, "Added CNIC device\n");
  3596. return cdev;
  3597. }
  3598. static struct cnic_dev *init_bnx2_cnic(struct net_device *dev)
  3599. {
  3600. struct pci_dev *pdev;
  3601. struct cnic_dev *cdev;
  3602. struct cnic_local *cp;
  3603. struct cnic_eth_dev *ethdev = NULL;
  3604. struct cnic_eth_dev *(*probe)(struct net_device *) = NULL;
  3605. probe = symbol_get(bnx2_cnic_probe);
  3606. if (probe) {
  3607. ethdev = (*probe)(dev);
  3608. symbol_put(bnx2_cnic_probe);
  3609. }
  3610. if (!ethdev)
  3611. return NULL;
  3612. pdev = ethdev->pdev;
  3613. if (!pdev)
  3614. return NULL;
  3615. dev_hold(dev);
  3616. pci_dev_get(pdev);
  3617. if (pdev->device == PCI_DEVICE_ID_NX2_5709 ||
  3618. pdev->device == PCI_DEVICE_ID_NX2_5709S) {
  3619. u8 rev;
  3620. pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
  3621. if (rev < 0x10) {
  3622. pci_dev_put(pdev);
  3623. goto cnic_err;
  3624. }
  3625. }
  3626. pci_dev_put(pdev);
  3627. cdev = cnic_alloc_dev(dev, pdev);
  3628. if (cdev == NULL)
  3629. goto cnic_err;
  3630. set_bit(CNIC_F_BNX2_CLASS, &cdev->flags);
  3631. cdev->submit_kwqes = cnic_submit_bnx2_kwqes;
  3632. cp = cdev->cnic_priv;
  3633. cp->ethdev = ethdev;
  3634. cdev->pcidev = pdev;
  3635. cp->cnic_ops = &cnic_bnx2_ops;
  3636. cp->start_hw = cnic_start_bnx2_hw;
  3637. cp->stop_hw = cnic_stop_bnx2_hw;
  3638. cp->setup_pgtbl = cnic_setup_page_tbl;
  3639. cp->alloc_resc = cnic_alloc_bnx2_resc;
  3640. cp->free_resc = cnic_free_resc;
  3641. cp->start_cm = cnic_cm_init_bnx2_hw;
  3642. cp->stop_cm = cnic_cm_stop_bnx2_hw;
  3643. cp->enable_int = cnic_enable_bnx2_int;
  3644. cp->disable_int_sync = cnic_disable_bnx2_int_sync;
  3645. cp->close_conn = cnic_close_bnx2_conn;
  3646. cp->next_idx = cnic_bnx2_next_idx;
  3647. cp->hw_idx = cnic_bnx2_hw_idx;
  3648. return cdev;
  3649. cnic_err:
  3650. dev_put(dev);
  3651. return NULL;
  3652. }
  3653. static struct cnic_dev *init_bnx2x_cnic(struct net_device *dev)
  3654. {
  3655. struct pci_dev *pdev;
  3656. struct cnic_dev *cdev;
  3657. struct cnic_local *cp;
  3658. struct cnic_eth_dev *ethdev = NULL;
  3659. struct cnic_eth_dev *(*probe)(struct net_device *) = NULL;
  3660. probe = symbol_get(bnx2x_cnic_probe);
  3661. if (probe) {
  3662. ethdev = (*probe)(dev);
  3663. symbol_put(bnx2x_cnic_probe);
  3664. }
  3665. if (!ethdev)
  3666. return NULL;
  3667. pdev = ethdev->pdev;
  3668. if (!pdev)
  3669. return NULL;
  3670. dev_hold(dev);
  3671. cdev = cnic_alloc_dev(dev, pdev);
  3672. if (cdev == NULL) {
  3673. dev_put(dev);
  3674. return NULL;
  3675. }
  3676. set_bit(CNIC_F_BNX2X_CLASS, &cdev->flags);
  3677. cdev->submit_kwqes = cnic_submit_bnx2x_kwqes;
  3678. cp = cdev->cnic_priv;
  3679. cp->ethdev = ethdev;
  3680. cdev->pcidev = pdev;
  3681. cp->cnic_ops = &cnic_bnx2x_ops;
  3682. cp->start_hw = cnic_start_bnx2x_hw;
  3683. cp->stop_hw = cnic_stop_bnx2x_hw;
  3684. cp->setup_pgtbl = cnic_setup_page_tbl_le;
  3685. cp->alloc_resc = cnic_alloc_bnx2x_resc;
  3686. cp->free_resc = cnic_free_resc;
  3687. cp->start_cm = cnic_cm_init_bnx2x_hw;
  3688. cp->stop_cm = cnic_cm_stop_bnx2x_hw;
  3689. cp->enable_int = cnic_enable_bnx2x_int;
  3690. cp->disable_int_sync = cnic_disable_bnx2x_int_sync;
  3691. cp->ack_int = cnic_ack_bnx2x_msix;
  3692. cp->close_conn = cnic_close_bnx2x_conn;
  3693. cp->next_idx = cnic_bnx2x_next_idx;
  3694. cp->hw_idx = cnic_bnx2x_hw_idx;
  3695. return cdev;
  3696. }
  3697. static struct cnic_dev *is_cnic_dev(struct net_device *dev)
  3698. {
  3699. struct ethtool_drvinfo drvinfo;
  3700. struct cnic_dev *cdev = NULL;
  3701. if (dev->ethtool_ops && dev->ethtool_ops->get_drvinfo) {
  3702. memset(&drvinfo, 0, sizeof(drvinfo));
  3703. dev->ethtool_ops->get_drvinfo(dev, &drvinfo);
  3704. if (!strcmp(drvinfo.driver, "bnx2"))
  3705. cdev = init_bnx2_cnic(dev);
  3706. if (!strcmp(drvinfo.driver, "bnx2x"))
  3707. cdev = init_bnx2x_cnic(dev);
  3708. if (cdev) {
  3709. write_lock(&cnic_dev_lock);
  3710. list_add(&cdev->list, &cnic_dev_list);
  3711. write_unlock(&cnic_dev_lock);
  3712. }
  3713. }
  3714. return cdev;
  3715. }
  3716. /**
  3717. * netdev event handler
  3718. */
  3719. static int cnic_netdev_event(struct notifier_block *this, unsigned long event,
  3720. void *ptr)
  3721. {
  3722. struct net_device *netdev = ptr;
  3723. struct cnic_dev *dev;
  3724. int if_type;
  3725. int new_dev = 0;
  3726. dev = cnic_from_netdev(netdev);
  3727. if (!dev && (event == NETDEV_REGISTER || event == NETDEV_UP)) {
  3728. /* Check for the hot-plug device */
  3729. dev = is_cnic_dev(netdev);
  3730. if (dev) {
  3731. new_dev = 1;
  3732. cnic_hold(dev);
  3733. }
  3734. }
  3735. if (dev) {
  3736. struct cnic_local *cp = dev->cnic_priv;
  3737. if (new_dev)
  3738. cnic_ulp_init(dev);
  3739. else if (event == NETDEV_UNREGISTER)
  3740. cnic_ulp_exit(dev);
  3741. if (event == NETDEV_UP) {
  3742. if (cnic_register_netdev(dev) != 0) {
  3743. cnic_put(dev);
  3744. goto done;
  3745. }
  3746. if (!cnic_start_hw(dev))
  3747. cnic_ulp_start(dev);
  3748. }
  3749. rcu_read_lock();
  3750. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  3751. struct cnic_ulp_ops *ulp_ops;
  3752. void *ctx;
  3753. ulp_ops = rcu_dereference(cp->ulp_ops[if_type]);
  3754. if (!ulp_ops || !ulp_ops->indicate_netevent)
  3755. continue;
  3756. ctx = cp->ulp_handle[if_type];
  3757. ulp_ops->indicate_netevent(ctx, event);
  3758. }
  3759. rcu_read_unlock();
  3760. if (event == NETDEV_GOING_DOWN) {
  3761. cnic_ulp_stop(dev);
  3762. cnic_stop_hw(dev);
  3763. cnic_unregister_netdev(dev);
  3764. } else if (event == NETDEV_UNREGISTER) {
  3765. write_lock(&cnic_dev_lock);
  3766. list_del_init(&dev->list);
  3767. write_unlock(&cnic_dev_lock);
  3768. cnic_put(dev);
  3769. cnic_free_dev(dev);
  3770. goto done;
  3771. }
  3772. cnic_put(dev);
  3773. }
  3774. done:
  3775. return NOTIFY_DONE;
  3776. }
  3777. static struct notifier_block cnic_netdev_notifier = {
  3778. .notifier_call = cnic_netdev_event
  3779. };
  3780. static void cnic_release(void)
  3781. {
  3782. struct cnic_dev *dev;
  3783. while (!list_empty(&cnic_dev_list)) {
  3784. dev = list_entry(cnic_dev_list.next, struct cnic_dev, list);
  3785. if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  3786. cnic_ulp_stop(dev);
  3787. cnic_stop_hw(dev);
  3788. }
  3789. cnic_ulp_exit(dev);
  3790. cnic_unregister_netdev(dev);
  3791. list_del_init(&dev->list);
  3792. cnic_free_dev(dev);
  3793. }
  3794. }
  3795. static int __init cnic_init(void)
  3796. {
  3797. int rc = 0;
  3798. pr_info("%s", version);
  3799. rc = register_netdevice_notifier(&cnic_netdev_notifier);
  3800. if (rc) {
  3801. cnic_release();
  3802. return rc;
  3803. }
  3804. return 0;
  3805. }
  3806. static void __exit cnic_exit(void)
  3807. {
  3808. unregister_netdevice_notifier(&cnic_netdev_notifier);
  3809. cnic_release();
  3810. return;
  3811. }
  3812. module_init(cnic_init);
  3813. module_exit(cnic_exit);