controlfb.c 27 KB

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  1. /*
  2. * controlfb.c -- frame buffer device for the PowerMac 'control' display
  3. *
  4. * Created 12 July 1998 by Dan Jacobowitz <dan@debian.org>
  5. * Copyright (C) 1998 Dan Jacobowitz
  6. * Copyright (C) 2001 Takashi Oe
  7. *
  8. * Mmap code by Michel Lanners <mlan@cpu.lu>
  9. *
  10. * Frame buffer structure from:
  11. * drivers/video/chipsfb.c -- frame buffer device for
  12. * Chips & Technologies 65550 chip.
  13. *
  14. * Copyright (C) 1998 Paul Mackerras
  15. *
  16. * This file is derived from the Powermac "chips" driver:
  17. * Copyright (C) 1997 Fabio Riccardi.
  18. * And from the frame buffer device for Open Firmware-initialized devices:
  19. * Copyright (C) 1997 Geert Uytterhoeven.
  20. *
  21. * Hardware information from:
  22. * control.c: Console support for PowerMac "control" display adaptor.
  23. * Copyright (C) 1996 Paul Mackerras
  24. *
  25. * Updated to 2.5 framebuffer API by Ben Herrenschmidt
  26. * <benh@kernel.crashing.org>, Paul Mackerras <paulus@samba.org>,
  27. * and James Simmons <jsimmons@infradead.org>.
  28. *
  29. * This file is subject to the terms and conditions of the GNU General Public
  30. * License. See the file COPYING in the main directory of this archive for
  31. * more details.
  32. */
  33. #include <linux/module.h>
  34. #include <linux/kernel.h>
  35. #include <linux/errno.h>
  36. #include <linux/string.h>
  37. #include <linux/mm.h>
  38. #include <linux/tty.h>
  39. #include <linux/slab.h>
  40. #include <linux/vmalloc.h>
  41. #include <linux/delay.h>
  42. #include <linux/interrupt.h>
  43. #include <linux/fb.h>
  44. #include <linux/init.h>
  45. #include <linux/pci.h>
  46. #include <linux/nvram.h>
  47. #include <linux/adb.h>
  48. #include <linux/cuda.h>
  49. #include <asm/io.h>
  50. #include <asm/prom.h>
  51. #include <asm/pgtable.h>
  52. #include <asm/btext.h>
  53. #include "macmodes.h"
  54. #include "controlfb.h"
  55. struct fb_par_control {
  56. int vmode, cmode;
  57. int xres, yres;
  58. int vxres, vyres;
  59. int xoffset, yoffset;
  60. int pitch;
  61. struct control_regvals regvals;
  62. unsigned long sync;
  63. unsigned char ctrl;
  64. };
  65. #define DIRTY(z) ((x)->z != (y)->z)
  66. #define DIRTY_CMAP(z) (memcmp(&((x)->z), &((y)->z), sizeof((y)->z)))
  67. static inline int PAR_EQUAL(struct fb_par_control *x, struct fb_par_control *y)
  68. {
  69. int i, results;
  70. results = 1;
  71. for (i = 0; i < 3; i++)
  72. results &= !DIRTY(regvals.clock_params[i]);
  73. if (!results)
  74. return 0;
  75. for (i = 0; i < 16; i++)
  76. results &= !DIRTY(regvals.regs[i]);
  77. if (!results)
  78. return 0;
  79. return (!DIRTY(cmode) && !DIRTY(xres) && !DIRTY(yres)
  80. && !DIRTY(vxres) && !DIRTY(vyres));
  81. }
  82. static inline int VAR_MATCH(struct fb_var_screeninfo *x, struct fb_var_screeninfo *y)
  83. {
  84. return (!DIRTY(bits_per_pixel) && !DIRTY(xres)
  85. && !DIRTY(yres) && !DIRTY(xres_virtual)
  86. && !DIRTY(yres_virtual)
  87. && !DIRTY_CMAP(red) && !DIRTY_CMAP(green) && !DIRTY_CMAP(blue));
  88. }
  89. struct fb_info_control {
  90. struct fb_info info;
  91. struct fb_par_control par;
  92. u32 pseudo_palette[17];
  93. struct cmap_regs __iomem *cmap_regs;
  94. unsigned long cmap_regs_phys;
  95. struct control_regs __iomem *control_regs;
  96. unsigned long control_regs_phys;
  97. unsigned long control_regs_size;
  98. __u8 __iomem *frame_buffer;
  99. unsigned long frame_buffer_phys;
  100. unsigned long fb_orig_base;
  101. unsigned long fb_orig_size;
  102. int control_use_bank2;
  103. unsigned long total_vram;
  104. unsigned char vram_attr;
  105. };
  106. /* control register access macro */
  107. #define CNTRL_REG(INFO,REG) (&(((INFO)->control_regs->REG).r))
  108. /******************** Prototypes for exported functions ********************/
  109. /*
  110. * struct fb_ops
  111. */
  112. static int controlfb_pan_display(struct fb_var_screeninfo *var,
  113. struct fb_info *info);
  114. static int controlfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
  115. u_int transp, struct fb_info *info);
  116. static int controlfb_blank(int blank_mode, struct fb_info *info);
  117. static int controlfb_mmap(struct fb_info *info,
  118. struct vm_area_struct *vma);
  119. static int controlfb_set_par (struct fb_info *info);
  120. static int controlfb_check_var (struct fb_var_screeninfo *var, struct fb_info *info);
  121. /******************** Prototypes for internal functions **********************/
  122. static void set_control_clock(unsigned char *params);
  123. static int init_control(struct fb_info_control *p);
  124. static void control_set_hardware(struct fb_info_control *p,
  125. struct fb_par_control *par);
  126. static int control_of_init(struct device_node *dp);
  127. static void find_vram_size(struct fb_info_control *p);
  128. static int read_control_sense(struct fb_info_control *p);
  129. static int calc_clock_params(unsigned long clk, unsigned char *param);
  130. static int control_var_to_par(struct fb_var_screeninfo *var,
  131. struct fb_par_control *par, const struct fb_info *fb_info);
  132. static inline void control_par_to_var(struct fb_par_control *par,
  133. struct fb_var_screeninfo *var);
  134. static void control_init_info(struct fb_info *info, struct fb_info_control *p);
  135. static void control_cleanup(void);
  136. /************************** Internal variables *******************************/
  137. static struct fb_info_control *control_fb;
  138. static int default_vmode __initdata = VMODE_NVRAM;
  139. static int default_cmode __initdata = CMODE_NVRAM;
  140. static struct fb_ops controlfb_ops = {
  141. .owner = THIS_MODULE,
  142. .fb_check_var = controlfb_check_var,
  143. .fb_set_par = controlfb_set_par,
  144. .fb_setcolreg = controlfb_setcolreg,
  145. .fb_pan_display = controlfb_pan_display,
  146. .fb_blank = controlfb_blank,
  147. .fb_mmap = controlfb_mmap,
  148. .fb_fillrect = cfb_fillrect,
  149. .fb_copyarea = cfb_copyarea,
  150. .fb_imageblit = cfb_imageblit,
  151. };
  152. /******************** The functions for controlfb_ops ********************/
  153. #ifdef MODULE
  154. MODULE_LICENSE("GPL");
  155. int init_module(void)
  156. {
  157. struct device_node *dp;
  158. dp = find_devices("control");
  159. if (dp != 0 && !control_of_init(dp))
  160. return 0;
  161. return -ENXIO;
  162. }
  163. void cleanup_module(void)
  164. {
  165. control_cleanup();
  166. }
  167. #endif
  168. /*
  169. * Checks a var structure
  170. */
  171. static int controlfb_check_var (struct fb_var_screeninfo *var, struct fb_info *info)
  172. {
  173. struct fb_par_control par;
  174. int err;
  175. err = control_var_to_par(var, &par, info);
  176. if (err)
  177. return err;
  178. control_par_to_var(&par, var);
  179. return 0;
  180. }
  181. /*
  182. * Applies current var to display
  183. */
  184. static int controlfb_set_par (struct fb_info *info)
  185. {
  186. struct fb_info_control *p = (struct fb_info_control *) info;
  187. struct fb_par_control par;
  188. int err;
  189. if((err = control_var_to_par(&info->var, &par, info))) {
  190. printk (KERN_ERR "controlfb_set_par: error calling"
  191. " control_var_to_par: %d.\n", err);
  192. return err;
  193. }
  194. control_set_hardware(p, &par);
  195. info->fix.visual = (p->par.cmode == CMODE_8) ?
  196. FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
  197. info->fix.line_length = p->par.pitch;
  198. info->fix.xpanstep = 32 >> p->par.cmode;
  199. info->fix.ypanstep = 1;
  200. return 0;
  201. }
  202. /*
  203. * Set screen start address according to var offset values
  204. */
  205. static inline void set_screen_start(int xoffset, int yoffset,
  206. struct fb_info_control *p)
  207. {
  208. struct fb_par_control *par = &p->par;
  209. par->xoffset = xoffset;
  210. par->yoffset = yoffset;
  211. out_le32(CNTRL_REG(p,start_addr),
  212. par->yoffset * par->pitch + (par->xoffset << par->cmode));
  213. }
  214. static int controlfb_pan_display(struct fb_var_screeninfo *var,
  215. struct fb_info *info)
  216. {
  217. unsigned int xoffset, hstep;
  218. struct fb_info_control *p = (struct fb_info_control *)info;
  219. struct fb_par_control *par = &p->par;
  220. /*
  221. * make sure start addr will be 32-byte aligned
  222. */
  223. hstep = 0x1f >> par->cmode;
  224. xoffset = (var->xoffset + hstep) & ~hstep;
  225. if (xoffset+par->xres > par->vxres ||
  226. var->yoffset+par->yres > par->vyres)
  227. return -EINVAL;
  228. set_screen_start(xoffset, var->yoffset, p);
  229. return 0;
  230. }
  231. /*
  232. * Private mmap since we want to have a different caching on the framebuffer
  233. * for controlfb.
  234. * Note there's no locking in here; it's done in fb_mmap() in fbmem.c.
  235. */
  236. static int controlfb_mmap(struct fb_info *info,
  237. struct vm_area_struct *vma)
  238. {
  239. unsigned long off, start;
  240. u32 len;
  241. off = vma->vm_pgoff << PAGE_SHIFT;
  242. /* frame buffer memory */
  243. start = info->fix.smem_start;
  244. len = PAGE_ALIGN((start & ~PAGE_MASK)+info->fix.smem_len);
  245. if (off >= len) {
  246. /* memory mapped io */
  247. off -= len;
  248. if (info->var.accel_flags)
  249. return -EINVAL;
  250. start = info->fix.mmio_start;
  251. len = PAGE_ALIGN((start & ~PAGE_MASK)+info->fix.mmio_len);
  252. pgprot_val(vma->vm_page_prot) |= _PAGE_NO_CACHE|_PAGE_GUARDED;
  253. } else {
  254. /* framebuffer */
  255. pgprot_val(vma->vm_page_prot) |= _PAGE_WRITETHRU;
  256. }
  257. start &= PAGE_MASK;
  258. if ((vma->vm_end - vma->vm_start + off) > len)
  259. return -EINVAL;
  260. off += start;
  261. vma->vm_pgoff = off >> PAGE_SHIFT;
  262. if (io_remap_pfn_range(vma, vma->vm_start, off >> PAGE_SHIFT,
  263. vma->vm_end - vma->vm_start, vma->vm_page_prot))
  264. return -EAGAIN;
  265. return 0;
  266. }
  267. static int controlfb_blank(int blank_mode, struct fb_info *info)
  268. {
  269. struct fb_info_control *p = (struct fb_info_control *) info;
  270. unsigned ctrl;
  271. ctrl = ld_le32(CNTRL_REG(p,ctrl));
  272. if (blank_mode > 0)
  273. switch (blank_mode) {
  274. case FB_BLANK_VSYNC_SUSPEND:
  275. ctrl &= ~3;
  276. break;
  277. case FB_BLANK_HSYNC_SUSPEND:
  278. ctrl &= ~0x30;
  279. break;
  280. case FB_BLANK_POWERDOWN:
  281. ctrl &= ~0x33;
  282. /* fall through */
  283. case FB_BLANK_NORMAL:
  284. ctrl |= 0x400;
  285. break;
  286. default:
  287. break;
  288. }
  289. else {
  290. ctrl &= ~0x400;
  291. ctrl |= 0x33;
  292. }
  293. out_le32(CNTRL_REG(p,ctrl), ctrl);
  294. return 0;
  295. }
  296. static int controlfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
  297. u_int transp, struct fb_info *info)
  298. {
  299. struct fb_info_control *p = (struct fb_info_control *) info;
  300. __u8 r, g, b;
  301. if (regno > 255)
  302. return 1;
  303. r = red >> 8;
  304. g = green >> 8;
  305. b = blue >> 8;
  306. out_8(&p->cmap_regs->addr, regno); /* tell clut what addr to fill */
  307. out_8(&p->cmap_regs->lut, r); /* send one color channel at */
  308. out_8(&p->cmap_regs->lut, g); /* a time... */
  309. out_8(&p->cmap_regs->lut, b);
  310. if (regno < 16) {
  311. int i;
  312. switch (p->par.cmode) {
  313. case CMODE_16:
  314. p->pseudo_palette[regno] =
  315. (regno << 10) | (regno << 5) | regno;
  316. break;
  317. case CMODE_32:
  318. i = (regno << 8) | regno;
  319. p->pseudo_palette[regno] = (i << 16) | i;
  320. break;
  321. }
  322. }
  323. return 0;
  324. }
  325. /******************** End of controlfb_ops implementation ******************/
  326. static void set_control_clock(unsigned char *params)
  327. {
  328. #ifdef CONFIG_ADB_CUDA
  329. struct adb_request req;
  330. int i;
  331. for (i = 0; i < 3; ++i) {
  332. cuda_request(&req, NULL, 5, CUDA_PACKET, CUDA_GET_SET_IIC,
  333. 0x50, i + 1, params[i]);
  334. while (!req.complete)
  335. cuda_poll();
  336. }
  337. #endif
  338. }
  339. /*
  340. * finish off the driver initialization and register
  341. */
  342. static int __init init_control(struct fb_info_control *p)
  343. {
  344. int full, sense, vmode, cmode, vyres;
  345. struct fb_var_screeninfo var;
  346. int rc;
  347. printk(KERN_INFO "controlfb: ");
  348. full = p->total_vram == 0x400000;
  349. /* Try to pick a video mode out of NVRAM if we have one. */
  350. if (default_cmode == CMODE_NVRAM){
  351. cmode = nvram_read_byte(NV_CMODE);
  352. if(cmode < CMODE_8 || cmode > CMODE_32)
  353. cmode = CMODE_8;
  354. } else
  355. cmode=default_cmode;
  356. if (default_vmode == VMODE_NVRAM) {
  357. vmode = nvram_read_byte(NV_VMODE);
  358. if (vmode < 1 || vmode > VMODE_MAX ||
  359. control_mac_modes[vmode - 1].m[full] < cmode) {
  360. sense = read_control_sense(p);
  361. printk("Monitor sense value = 0x%x, ", sense);
  362. vmode = mac_map_monitor_sense(sense);
  363. if (control_mac_modes[vmode - 1].m[full] < cmode)
  364. vmode = VMODE_640_480_60;
  365. }
  366. } else {
  367. vmode=default_vmode;
  368. if (control_mac_modes[vmode - 1].m[full] < cmode) {
  369. if (cmode > CMODE_8)
  370. cmode--;
  371. else
  372. vmode = VMODE_640_480_60;
  373. }
  374. }
  375. /* Initialize info structure */
  376. control_init_info(&p->info, p);
  377. /* Setup default var */
  378. if (mac_vmode_to_var(vmode, cmode, &var) < 0) {
  379. /* This shouldn't happen! */
  380. printk("mac_vmode_to_var(%d, %d,) failed\n", vmode, cmode);
  381. try_again:
  382. vmode = VMODE_640_480_60;
  383. cmode = CMODE_8;
  384. if (mac_vmode_to_var(vmode, cmode, &var) < 0) {
  385. printk(KERN_ERR "controlfb: mac_vmode_to_var() failed\n");
  386. return -ENXIO;
  387. }
  388. printk(KERN_INFO "controlfb: ");
  389. }
  390. printk("using video mode %d and color mode %d.\n", vmode, cmode);
  391. vyres = (p->total_vram - CTRLFB_OFF) / (var.xres << cmode);
  392. if (vyres > var.yres)
  393. var.yres_virtual = vyres;
  394. /* Apply default var */
  395. var.activate = FB_ACTIVATE_NOW;
  396. rc = fb_set_var(&p->info, &var);
  397. if (rc && (vmode != VMODE_640_480_60 || cmode != CMODE_8))
  398. goto try_again;
  399. /* Register with fbdev layer */
  400. if (register_framebuffer(&p->info) < 0)
  401. return -ENXIO;
  402. printk(KERN_INFO "fb%d: control display adapter\n", p->info.node);
  403. return 0;
  404. }
  405. #define RADACAL_WRITE(a,d) \
  406. out_8(&p->cmap_regs->addr, (a)); \
  407. out_8(&p->cmap_regs->dat, (d))
  408. /* Now how about actually saying, Make it so! */
  409. /* Some things in here probably don't need to be done each time. */
  410. static void control_set_hardware(struct fb_info_control *p, struct fb_par_control *par)
  411. {
  412. struct control_regvals *r;
  413. volatile struct preg __iomem *rp;
  414. int i, cmode;
  415. if (PAR_EQUAL(&p->par, par)) {
  416. /*
  417. * check if only xoffset or yoffset differs.
  418. * this prevents flickers in typical VT switch case.
  419. */
  420. if (p->par.xoffset != par->xoffset ||
  421. p->par.yoffset != par->yoffset)
  422. set_screen_start(par->xoffset, par->yoffset, p);
  423. return;
  424. }
  425. p->par = *par;
  426. cmode = p->par.cmode;
  427. r = &par->regvals;
  428. /* Turn off display */
  429. out_le32(CNTRL_REG(p,ctrl), 0x400 | par->ctrl);
  430. set_control_clock(r->clock_params);
  431. RADACAL_WRITE(0x20, r->radacal_ctrl);
  432. RADACAL_WRITE(0x21, p->control_use_bank2 ? 0 : 1);
  433. RADACAL_WRITE(0x10, 0);
  434. RADACAL_WRITE(0x11, 0);
  435. rp = &p->control_regs->vswin;
  436. for (i = 0; i < 16; ++i, ++rp)
  437. out_le32(&rp->r, r->regs[i]);
  438. out_le32(CNTRL_REG(p,pitch), par->pitch);
  439. out_le32(CNTRL_REG(p,mode), r->mode);
  440. out_le32(CNTRL_REG(p,vram_attr), p->vram_attr);
  441. out_le32(CNTRL_REG(p,start_addr), par->yoffset * par->pitch
  442. + (par->xoffset << cmode));
  443. out_le32(CNTRL_REG(p,rfrcnt), 0x1e5);
  444. out_le32(CNTRL_REG(p,intr_ena), 0);
  445. /* Turn on display */
  446. out_le32(CNTRL_REG(p,ctrl), par->ctrl);
  447. #ifdef CONFIG_BOOTX_TEXT
  448. btext_update_display(p->frame_buffer_phys + CTRLFB_OFF,
  449. p->par.xres, p->par.yres,
  450. (cmode == CMODE_32? 32: cmode == CMODE_16? 16: 8),
  451. p->par.pitch);
  452. #endif /* CONFIG_BOOTX_TEXT */
  453. }
  454. /*
  455. * Parse user speficied options (`video=controlfb:')
  456. */
  457. static void __init control_setup(char *options)
  458. {
  459. char *this_opt;
  460. if (!options || !*options)
  461. return;
  462. while ((this_opt = strsep(&options, ",")) != NULL) {
  463. if (!strncmp(this_opt, "vmode:", 6)) {
  464. int vmode = simple_strtoul(this_opt+6, NULL, 0);
  465. if (vmode > 0 && vmode <= VMODE_MAX &&
  466. control_mac_modes[vmode - 1].m[1] >= 0)
  467. default_vmode = vmode;
  468. } else if (!strncmp(this_opt, "cmode:", 6)) {
  469. int depth = simple_strtoul(this_opt+6, NULL, 0);
  470. switch (depth) {
  471. case CMODE_8:
  472. case CMODE_16:
  473. case CMODE_32:
  474. default_cmode = depth;
  475. break;
  476. case 8:
  477. default_cmode = CMODE_8;
  478. break;
  479. case 15:
  480. case 16:
  481. default_cmode = CMODE_16;
  482. break;
  483. case 24:
  484. case 32:
  485. default_cmode = CMODE_32;
  486. break;
  487. }
  488. }
  489. }
  490. }
  491. static int __init control_init(void)
  492. {
  493. struct device_node *dp;
  494. char *option = NULL;
  495. if (fb_get_options("controlfb", &option))
  496. return -ENODEV;
  497. control_setup(option);
  498. dp = find_devices("control");
  499. if (dp != 0 && !control_of_init(dp))
  500. return 0;
  501. return -ENXIO;
  502. }
  503. module_init(control_init);
  504. /* Work out which banks of VRAM we have installed. */
  505. /* danj: I guess the card just ignores writes to nonexistant VRAM... */
  506. static void __init find_vram_size(struct fb_info_control *p)
  507. {
  508. int bank1, bank2;
  509. /*
  510. * Set VRAM in 2MB (bank 1) mode
  511. * VRAM Bank 2 will be accessible through offset 0x600000 if present
  512. * and VRAM Bank 1 will not respond at that offset even if present
  513. */
  514. out_le32(CNTRL_REG(p,vram_attr), 0x31);
  515. out_8(&p->frame_buffer[0x600000], 0xb3);
  516. out_8(&p->frame_buffer[0x600001], 0x71);
  517. asm volatile("eieio; dcbf 0,%0" : : "r" (&p->frame_buffer[0x600000])
  518. : "memory" );
  519. mb();
  520. asm volatile("eieio; dcbi 0,%0" : : "r" (&p->frame_buffer[0x600000])
  521. : "memory" );
  522. mb();
  523. bank2 = (in_8(&p->frame_buffer[0x600000]) == 0xb3)
  524. && (in_8(&p->frame_buffer[0x600001]) == 0x71);
  525. /*
  526. * Set VRAM in 2MB (bank 2) mode
  527. * VRAM Bank 1 will be accessible through offset 0x000000 if present
  528. * and VRAM Bank 2 will not respond at that offset even if present
  529. */
  530. out_le32(CNTRL_REG(p,vram_attr), 0x39);
  531. out_8(&p->frame_buffer[0], 0x5a);
  532. out_8(&p->frame_buffer[1], 0xc7);
  533. asm volatile("eieio; dcbf 0,%0" : : "r" (&p->frame_buffer[0])
  534. : "memory" );
  535. mb();
  536. asm volatile("eieio; dcbi 0,%0" : : "r" (&p->frame_buffer[0])
  537. : "memory" );
  538. mb();
  539. bank1 = (in_8(&p->frame_buffer[0]) == 0x5a)
  540. && (in_8(&p->frame_buffer[1]) == 0xc7);
  541. if (bank2) {
  542. if (!bank1) {
  543. /*
  544. * vram bank 2 only
  545. */
  546. p->control_use_bank2 = 1;
  547. p->vram_attr = 0x39;
  548. p->frame_buffer += 0x600000;
  549. p->frame_buffer_phys += 0x600000;
  550. } else {
  551. /*
  552. * 4 MB vram
  553. */
  554. p->vram_attr = 0x51;
  555. }
  556. } else {
  557. /*
  558. * vram bank 1 only
  559. */
  560. p->vram_attr = 0x31;
  561. }
  562. p->total_vram = (bank1 + bank2) * 0x200000;
  563. printk(KERN_INFO "controlfb: VRAM Total = %dMB "
  564. "(%dMB @ bank 1, %dMB @ bank 2)\n",
  565. (bank1 + bank2) << 1, bank1 << 1, bank2 << 1);
  566. }
  567. /*
  568. * find "control" and initialize
  569. */
  570. static int __init control_of_init(struct device_node *dp)
  571. {
  572. struct fb_info_control *p;
  573. struct resource fb_res, reg_res;
  574. if (control_fb) {
  575. printk(KERN_ERR "controlfb: only one control is supported\n");
  576. return -ENXIO;
  577. }
  578. if (of_pci_address_to_resource(dp, 2, &fb_res) ||
  579. of_pci_address_to_resource(dp, 1, &reg_res)) {
  580. printk(KERN_ERR "can't get 2 addresses for control\n");
  581. return -ENXIO;
  582. }
  583. p = kmalloc(sizeof(*p), GFP_KERNEL);
  584. if (p == 0)
  585. return -ENXIO;
  586. control_fb = p; /* save it for cleanups */
  587. memset(p, 0, sizeof(*p));
  588. /* Map in frame buffer and registers */
  589. p->fb_orig_base = fb_res.start;
  590. p->fb_orig_size = fb_res.end - fb_res.start + 1;
  591. /* use the big-endian aperture (??) */
  592. p->frame_buffer_phys = fb_res.start + 0x800000;
  593. p->control_regs_phys = reg_res.start;
  594. p->control_regs_size = reg_res.end - reg_res.start + 1;
  595. if (!p->fb_orig_base ||
  596. !request_mem_region(p->fb_orig_base,p->fb_orig_size,"controlfb")) {
  597. p->fb_orig_base = 0;
  598. goto error_out;
  599. }
  600. /* map at most 8MB for the frame buffer */
  601. p->frame_buffer = __ioremap(p->frame_buffer_phys, 0x800000,
  602. _PAGE_WRITETHRU);
  603. if (!p->control_regs_phys ||
  604. !request_mem_region(p->control_regs_phys, p->control_regs_size,
  605. "controlfb regs")) {
  606. p->control_regs_phys = 0;
  607. goto error_out;
  608. }
  609. p->control_regs = ioremap(p->control_regs_phys, p->control_regs_size);
  610. p->cmap_regs_phys = 0xf301b000; /* XXX not in prom? */
  611. if (!request_mem_region(p->cmap_regs_phys, 0x1000, "controlfb cmap")) {
  612. p->cmap_regs_phys = 0;
  613. goto error_out;
  614. }
  615. p->cmap_regs = ioremap(p->cmap_regs_phys, 0x1000);
  616. if (!p->cmap_regs || !p->control_regs || !p->frame_buffer)
  617. goto error_out;
  618. find_vram_size(p);
  619. if (!p->total_vram)
  620. goto error_out;
  621. if (init_control(p) < 0)
  622. goto error_out;
  623. return 0;
  624. error_out:
  625. control_cleanup();
  626. return -ENXIO;
  627. }
  628. /*
  629. * Get the monitor sense value.
  630. * Note that this can be called before calibrate_delay,
  631. * so we can't use udelay.
  632. */
  633. static int read_control_sense(struct fb_info_control *p)
  634. {
  635. int sense;
  636. out_le32(CNTRL_REG(p,mon_sense), 7); /* drive all lines high */
  637. __delay(200);
  638. out_le32(CNTRL_REG(p,mon_sense), 077); /* turn off drivers */
  639. __delay(2000);
  640. sense = (in_le32(CNTRL_REG(p,mon_sense)) & 0x1c0) << 2;
  641. /* drive each sense line low in turn and collect the other 2 */
  642. out_le32(CNTRL_REG(p,mon_sense), 033); /* drive A low */
  643. __delay(2000);
  644. sense |= (in_le32(CNTRL_REG(p,mon_sense)) & 0xc0) >> 2;
  645. out_le32(CNTRL_REG(p,mon_sense), 055); /* drive B low */
  646. __delay(2000);
  647. sense |= ((in_le32(CNTRL_REG(p,mon_sense)) & 0x100) >> 5)
  648. | ((in_le32(CNTRL_REG(p,mon_sense)) & 0x40) >> 4);
  649. out_le32(CNTRL_REG(p,mon_sense), 066); /* drive C low */
  650. __delay(2000);
  651. sense |= (in_le32(CNTRL_REG(p,mon_sense)) & 0x180) >> 7;
  652. out_le32(CNTRL_REG(p,mon_sense), 077); /* turn off drivers */
  653. return sense;
  654. }
  655. /********************** Various translation functions **********************/
  656. #define CONTROL_PIXCLOCK_BASE 256016
  657. #define CONTROL_PIXCLOCK_MIN 5000 /* ~ 200 MHz dot clock */
  658. /*
  659. * calculate the clock paramaters to be sent to CUDA according to given
  660. * pixclock in pico second.
  661. */
  662. static int calc_clock_params(unsigned long clk, unsigned char *param)
  663. {
  664. unsigned long p0, p1, p2, k, l, m, n, min;
  665. if (clk > (CONTROL_PIXCLOCK_BASE << 3))
  666. return 1;
  667. p2 = ((clk << 4) < CONTROL_PIXCLOCK_BASE)? 3: 2;
  668. l = clk << p2;
  669. p0 = 0;
  670. p1 = 0;
  671. for (k = 1, min = l; k < 32; k++) {
  672. unsigned long rem;
  673. m = CONTROL_PIXCLOCK_BASE * k;
  674. n = m / l;
  675. rem = m % l;
  676. if (n && (n < 128) && rem < min) {
  677. p0 = k;
  678. p1 = n;
  679. min = rem;
  680. }
  681. }
  682. if (!p0 || !p1)
  683. return 1;
  684. param[0] = p0;
  685. param[1] = p1;
  686. param[2] = p2;
  687. return 0;
  688. }
  689. /*
  690. * This routine takes a user-supplied var, and picks the best vmode/cmode
  691. * from it.
  692. */
  693. static int control_var_to_par(struct fb_var_screeninfo *var,
  694. struct fb_par_control *par, const struct fb_info *fb_info)
  695. {
  696. int cmode, piped_diff, hstep;
  697. unsigned hperiod, hssync, hsblank, hesync, heblank, piped, heq, hlfln,
  698. hserr, vperiod, vssync, vesync, veblank, vsblank, vswin, vewin;
  699. unsigned long pixclock;
  700. struct fb_info_control *p = (struct fb_info_control *) fb_info;
  701. struct control_regvals *r = &par->regvals;
  702. switch (var->bits_per_pixel) {
  703. case 8:
  704. par->cmode = CMODE_8;
  705. if (p->total_vram > 0x200000) {
  706. r->mode = 3;
  707. r->radacal_ctrl = 0x20;
  708. piped_diff = 13;
  709. } else {
  710. r->mode = 2;
  711. r->radacal_ctrl = 0x10;
  712. piped_diff = 9;
  713. }
  714. break;
  715. case 15:
  716. case 16:
  717. par->cmode = CMODE_16;
  718. if (p->total_vram > 0x200000) {
  719. r->mode = 2;
  720. r->radacal_ctrl = 0x24;
  721. piped_diff = 5;
  722. } else {
  723. r->mode = 1;
  724. r->radacal_ctrl = 0x14;
  725. piped_diff = 3;
  726. }
  727. break;
  728. case 32:
  729. par->cmode = CMODE_32;
  730. if (p->total_vram > 0x200000) {
  731. r->mode = 1;
  732. r->radacal_ctrl = 0x28;
  733. } else {
  734. r->mode = 0;
  735. r->radacal_ctrl = 0x18;
  736. }
  737. piped_diff = 1;
  738. break;
  739. default:
  740. return -EINVAL;
  741. }
  742. /*
  743. * adjust xres and vxres so that the corresponding memory widths are
  744. * 32-byte aligned
  745. */
  746. hstep = 31 >> par->cmode;
  747. par->xres = (var->xres + hstep) & ~hstep;
  748. par->vxres = (var->xres_virtual + hstep) & ~hstep;
  749. par->xoffset = (var->xoffset + hstep) & ~hstep;
  750. if (par->vxres < par->xres)
  751. par->vxres = par->xres;
  752. par->pitch = par->vxres << par->cmode;
  753. par->yres = var->yres;
  754. par->vyres = var->yres_virtual;
  755. par->yoffset = var->yoffset;
  756. if (par->vyres < par->yres)
  757. par->vyres = par->yres;
  758. par->sync = var->sync;
  759. if (par->pitch * par->vyres + CTRLFB_OFF > p->total_vram)
  760. return -EINVAL;
  761. if (par->xoffset + par->xres > par->vxres)
  762. par->xoffset = par->vxres - par->xres;
  763. if (par->yoffset + par->yres > par->vyres)
  764. par->yoffset = par->vyres - par->yres;
  765. pixclock = (var->pixclock < CONTROL_PIXCLOCK_MIN)? CONTROL_PIXCLOCK_MIN:
  766. var->pixclock;
  767. if (calc_clock_params(pixclock, r->clock_params))
  768. return -EINVAL;
  769. hperiod = ((var->left_margin + par->xres + var->right_margin
  770. + var->hsync_len) >> 1) - 2;
  771. hssync = hperiod + 1;
  772. hsblank = hssync - (var->right_margin >> 1);
  773. hesync = (var->hsync_len >> 1) - 1;
  774. heblank = (var->left_margin >> 1) + hesync;
  775. piped = heblank - piped_diff;
  776. heq = var->hsync_len >> 2;
  777. hlfln = (hperiod+2) >> 1;
  778. hserr = hssync-hesync;
  779. vperiod = (var->vsync_len + var->lower_margin + par->yres
  780. + var->upper_margin) << 1;
  781. vssync = vperiod - 2;
  782. vesync = (var->vsync_len << 1) - vperiod + vssync;
  783. veblank = (var->upper_margin << 1) + vesync;
  784. vsblank = vssync - (var->lower_margin << 1);
  785. vswin = (vsblank+vssync) >> 1;
  786. vewin = (vesync+veblank) >> 1;
  787. r->regs[0] = vswin;
  788. r->regs[1] = vsblank;
  789. r->regs[2] = veblank;
  790. r->regs[3] = vewin;
  791. r->regs[4] = vesync;
  792. r->regs[5] = vssync;
  793. r->regs[6] = vperiod;
  794. r->regs[7] = piped;
  795. r->regs[8] = hperiod;
  796. r->regs[9] = hsblank;
  797. r->regs[10] = heblank;
  798. r->regs[11] = hesync;
  799. r->regs[12] = hssync;
  800. r->regs[13] = heq;
  801. r->regs[14] = hlfln;
  802. r->regs[15] = hserr;
  803. if (par->xres >= 1280 && par->cmode >= CMODE_16)
  804. par->ctrl = 0x7f;
  805. else
  806. par->ctrl = 0x3b;
  807. if (mac_var_to_vmode(var, &par->vmode, &cmode))
  808. par->vmode = 0;
  809. return 0;
  810. }
  811. /*
  812. * Convert hardware data in par to an fb_var_screeninfo
  813. */
  814. static void control_par_to_var(struct fb_par_control *par, struct fb_var_screeninfo *var)
  815. {
  816. struct control_regints *rv;
  817. rv = (struct control_regints *) par->regvals.regs;
  818. memset(var, 0, sizeof(*var));
  819. var->xres = par->xres;
  820. var->yres = par->yres;
  821. var->xres_virtual = par->vxres;
  822. var->yres_virtual = par->vyres;
  823. var->xoffset = par->xoffset;
  824. var->yoffset = par->yoffset;
  825. switch(par->cmode) {
  826. default:
  827. case CMODE_8:
  828. var->bits_per_pixel = 8;
  829. var->red.length = 8;
  830. var->green.length = 8;
  831. var->blue.length = 8;
  832. break;
  833. case CMODE_16: /* RGB 555 */
  834. var->bits_per_pixel = 16;
  835. var->red.offset = 10;
  836. var->red.length = 5;
  837. var->green.offset = 5;
  838. var->green.length = 5;
  839. var->blue.length = 5;
  840. break;
  841. case CMODE_32: /* RGB 888 */
  842. var->bits_per_pixel = 32;
  843. var->red.offset = 16;
  844. var->red.length = 8;
  845. var->green.offset = 8;
  846. var->green.length = 8;
  847. var->blue.length = 8;
  848. var->transp.offset = 24;
  849. var->transp.length = 8;
  850. break;
  851. }
  852. var->height = -1;
  853. var->width = -1;
  854. var->vmode = FB_VMODE_NONINTERLACED;
  855. var->left_margin = (rv->heblank - rv->hesync) << 1;
  856. var->right_margin = (rv->hssync - rv->hsblank) << 1;
  857. var->hsync_len = (rv->hperiod + 2 - rv->hssync + rv->hesync) << 1;
  858. var->upper_margin = (rv->veblank - rv->vesync) >> 1;
  859. var->lower_margin = (rv->vssync - rv->vsblank) >> 1;
  860. var->vsync_len = (rv->vperiod - rv->vssync + rv->vesync) >> 1;
  861. var->sync = par->sync;
  862. /*
  863. * 10^12 * clock_params[0] / (3906400 * clock_params[1]
  864. * * 2^clock_params[2])
  865. * (10^12 * clock_params[0] / (3906400 * clock_params[1]))
  866. * >> clock_params[2]
  867. */
  868. /* (255990.17 * clock_params[0] / clock_params[1]) >> clock_params[2] */
  869. var->pixclock = CONTROL_PIXCLOCK_BASE * par->regvals.clock_params[0];
  870. var->pixclock /= par->regvals.clock_params[1];
  871. var->pixclock >>= par->regvals.clock_params[2];
  872. }
  873. /*
  874. * Set misc info vars for this driver
  875. */
  876. static void __init control_init_info(struct fb_info *info, struct fb_info_control *p)
  877. {
  878. /* Fill fb_info */
  879. info->par = &p->par;
  880. info->fbops = &controlfb_ops;
  881. info->pseudo_palette = p->pseudo_palette;
  882. info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
  883. info->screen_base = p->frame_buffer + CTRLFB_OFF;
  884. fb_alloc_cmap(&info->cmap, 256, 0);
  885. /* Fill fix common fields */
  886. strcpy(info->fix.id, "control");
  887. info->fix.mmio_start = p->control_regs_phys;
  888. info->fix.mmio_len = sizeof(struct control_regs);
  889. info->fix.type = FB_TYPE_PACKED_PIXELS;
  890. info->fix.smem_start = p->frame_buffer_phys + CTRLFB_OFF;
  891. info->fix.smem_len = p->total_vram - CTRLFB_OFF;
  892. info->fix.ywrapstep = 0;
  893. info->fix.type_aux = 0;
  894. info->fix.accel = FB_ACCEL_NONE;
  895. }
  896. static void control_cleanup(void)
  897. {
  898. struct fb_info_control *p = control_fb;
  899. if (!p)
  900. return;
  901. if (p->cmap_regs)
  902. iounmap(p->cmap_regs);
  903. if (p->control_regs)
  904. iounmap(p->control_regs);
  905. if (p->frame_buffer) {
  906. if (p->control_use_bank2)
  907. p->frame_buffer -= 0x600000;
  908. iounmap(p->frame_buffer);
  909. }
  910. if (p->cmap_regs_phys)
  911. release_mem_region(p->cmap_regs_phys, 0x1000);
  912. if (p->control_regs_phys)
  913. release_mem_region(p->control_regs_phys, p->control_regs_size);
  914. if (p->fb_orig_base)
  915. release_mem_region(p->fb_orig_base, p->fb_orig_size);
  916. kfree(p);
  917. }