asiliantfb.c 16 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610
  1. /*
  2. * drivers/video/asiliantfb.c
  3. * frame buffer driver for Asiliant 69000 chip
  4. * Copyright (C) 2001-2003 Saito.K & Jeanne
  5. *
  6. * from driver/video/chipsfb.c and,
  7. *
  8. * drivers/video/asiliantfb.c -- frame buffer device for
  9. * Asiliant 69030 chip (formerly Intel, formerly Chips & Technologies)
  10. * Author: apc@agelectronics.co.uk
  11. * Copyright (C) 2000 AG Electronics
  12. * Note: the data sheets don't seem to be available from Asiliant.
  13. * They are available by searching developer.intel.com, but are not otherwise
  14. * linked to.
  15. *
  16. * This driver should be portable with minimal effort to the 69000 display
  17. * chip, and to the twin-display mode of the 69030.
  18. * Contains code from Thomas Hhenleitner <th@visuelle-maschinen.de> (thanks)
  19. *
  20. * Derived from the CT65550 driver chipsfb.c:
  21. * Copyright (C) 1998 Paul Mackerras
  22. * ...which was derived from the Powermac "chips" driver:
  23. * Copyright (C) 1997 Fabio Riccardi.
  24. * And from the frame buffer device for Open Firmware-initialized devices:
  25. * Copyright (C) 1997 Geert Uytterhoeven.
  26. *
  27. * This file is subject to the terms and conditions of the GNU General Public
  28. * License. See the file COPYING in the main directory of this archive for
  29. * more details.
  30. */
  31. #include <linux/module.h>
  32. #include <linux/kernel.h>
  33. #include <linux/errno.h>
  34. #include <linux/string.h>
  35. #include <linux/mm.h>
  36. #include <linux/tty.h>
  37. #include <linux/slab.h>
  38. #include <linux/vmalloc.h>
  39. #include <linux/delay.h>
  40. #include <linux/interrupt.h>
  41. #include <linux/fb.h>
  42. #include <linux/init.h>
  43. #include <linux/pci.h>
  44. #include <asm/io.h>
  45. /* Built in clock of the 69030 */
  46. static const unsigned Fref = 14318180;
  47. #define mmio_base (p->screen_base + 0x400000)
  48. #define mm_write_ind(num, val, ap, dp) do { \
  49. writeb((num), mmio_base + (ap)); writeb((val), mmio_base + (dp)); \
  50. } while (0)
  51. static void mm_write_xr(struct fb_info *p, u8 reg, u8 data)
  52. {
  53. mm_write_ind(reg, data, 0x7ac, 0x7ad);
  54. }
  55. #define write_xr(num, val) mm_write_xr(p, num, val)
  56. static void mm_write_fr(struct fb_info *p, u8 reg, u8 data)
  57. {
  58. mm_write_ind(reg, data, 0x7a0, 0x7a1);
  59. }
  60. #define write_fr(num, val) mm_write_fr(p, num, val)
  61. static void mm_write_cr(struct fb_info *p, u8 reg, u8 data)
  62. {
  63. mm_write_ind(reg, data, 0x7a8, 0x7a9);
  64. }
  65. #define write_cr(num, val) mm_write_cr(p, num, val)
  66. static void mm_write_gr(struct fb_info *p, u8 reg, u8 data)
  67. {
  68. mm_write_ind(reg, data, 0x79c, 0x79d);
  69. }
  70. #define write_gr(num, val) mm_write_gr(p, num, val)
  71. static void mm_write_sr(struct fb_info *p, u8 reg, u8 data)
  72. {
  73. mm_write_ind(reg, data, 0x788, 0x789);
  74. }
  75. #define write_sr(num, val) mm_write_sr(p, num, val)
  76. static void mm_write_ar(struct fb_info *p, u8 reg, u8 data)
  77. {
  78. readb(mmio_base + 0x7b4);
  79. mm_write_ind(reg, data, 0x780, 0x780);
  80. }
  81. #define write_ar(num, val) mm_write_ar(p, num, val)
  82. static int asiliantfb_pci_init(struct pci_dev *dp, const struct pci_device_id *);
  83. static int asiliantfb_check_var(struct fb_var_screeninfo *var,
  84. struct fb_info *info);
  85. static int asiliantfb_set_par(struct fb_info *info);
  86. static int asiliantfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
  87. u_int transp, struct fb_info *info);
  88. static struct fb_ops asiliantfb_ops = {
  89. .owner = THIS_MODULE,
  90. .fb_check_var = asiliantfb_check_var,
  91. .fb_set_par = asiliantfb_set_par,
  92. .fb_setcolreg = asiliantfb_setcolreg,
  93. .fb_fillrect = cfb_fillrect,
  94. .fb_copyarea = cfb_copyarea,
  95. .fb_imageblit = cfb_imageblit,
  96. };
  97. /* Calculate the ratios for the dot clocks without using a single long long
  98. * value */
  99. static void asiliant_calc_dclk2(u32 *ppixclock, u8 *dclk2_m, u8 *dclk2_n, u8 *dclk2_div)
  100. {
  101. unsigned pixclock = *ppixclock;
  102. unsigned Ftarget = 1000000 * (1000000 / pixclock);
  103. unsigned n;
  104. unsigned best_error = 0xffffffff;
  105. unsigned best_m = 0xffffffff,
  106. best_n = 0xffffffff;
  107. unsigned ratio;
  108. unsigned remainder;
  109. unsigned char divisor = 0;
  110. /* Calculate the frequency required. This is hard enough. */
  111. ratio = 1000000 / pixclock;
  112. remainder = 1000000 % pixclock;
  113. Ftarget = 1000000 * ratio + (1000000 * remainder) / pixclock;
  114. while (Ftarget < 100000000) {
  115. divisor += 0x10;
  116. Ftarget <<= 1;
  117. }
  118. ratio = Ftarget / Fref;
  119. remainder = Ftarget % Fref;
  120. /* This expresses the constraint that 150kHz <= Fref/n <= 5Mhz,
  121. * together with 3 <= n <= 257. */
  122. for (n = 3; n <= 257; n++) {
  123. unsigned m = n * ratio + (n * remainder) / Fref;
  124. /* 3 <= m <= 257 */
  125. if (m >= 3 && m <= 257) {
  126. unsigned new_error = ((Ftarget * n) - (Fref * m)) >= 0 ?
  127. ((Ftarget * n) - (Fref * m)) : ((Fref * m) - (Ftarget * n));
  128. if (new_error < best_error) {
  129. best_n = n;
  130. best_m = m;
  131. best_error = new_error;
  132. }
  133. }
  134. /* But if VLD = 4, then 4m <= 1028 */
  135. else if (m <= 1028) {
  136. /* remember there are still only 8-bits of precision in m, so
  137. * avoid over-optimistic error calculations */
  138. unsigned new_error = ((Ftarget * n) - (Fref * (m & ~3))) >= 0 ?
  139. ((Ftarget * n) - (Fref * (m & ~3))) : ((Fref * (m & ~3)) - (Ftarget * n));
  140. if (new_error < best_error) {
  141. best_n = n;
  142. best_m = m;
  143. best_error = new_error;
  144. }
  145. }
  146. }
  147. if (best_m > 257)
  148. best_m >>= 2; /* divide m by 4, and leave VCO loop divide at 4 */
  149. else
  150. divisor |= 4; /* or set VCO loop divide to 1 */
  151. *dclk2_m = best_m - 2;
  152. *dclk2_n = best_n - 2;
  153. *dclk2_div = divisor;
  154. *ppixclock = pixclock;
  155. return;
  156. }
  157. static void asiliant_set_timing(struct fb_info *p)
  158. {
  159. unsigned hd = p->var.xres / 8;
  160. unsigned hs = (p->var.xres + p->var.right_margin) / 8;
  161. unsigned he = (p->var.xres + p->var.right_margin + p->var.hsync_len) / 8;
  162. unsigned ht = (p->var.left_margin + p->var.xres + p->var.right_margin + p->var.hsync_len) / 8;
  163. unsigned vd = p->var.yres;
  164. unsigned vs = p->var.yres + p->var.lower_margin;
  165. unsigned ve = p->var.yres + p->var.lower_margin + p->var.vsync_len;
  166. unsigned vt = p->var.upper_margin + p->var.yres + p->var.lower_margin + p->var.vsync_len;
  167. unsigned wd = (p->var.xres_virtual * ((p->var.bits_per_pixel+7)/8)) / 8;
  168. if ((p->var.xres == 640) && (p->var.yres == 480) && (p->var.pixclock == 39722)) {
  169. write_fr(0x01, 0x02); /* LCD */
  170. } else {
  171. write_fr(0x01, 0x01); /* CRT */
  172. }
  173. write_cr(0x11, (ve - 1) & 0x0f);
  174. write_cr(0x00, (ht - 5) & 0xff);
  175. write_cr(0x01, hd - 1);
  176. write_cr(0x02, hd);
  177. write_cr(0x03, ((ht - 1) & 0x1f) | 0x80);
  178. write_cr(0x04, hs);
  179. write_cr(0x05, (((ht - 1) & 0x20) <<2) | (he & 0x1f));
  180. write_cr(0x3c, (ht - 1) & 0xc0);
  181. write_cr(0x06, (vt - 2) & 0xff);
  182. write_cr(0x30, (vt - 2) >> 8);
  183. write_cr(0x07, 0x00);
  184. write_cr(0x08, 0x00);
  185. write_cr(0x09, 0x00);
  186. write_cr(0x10, (vs - 1) & 0xff);
  187. write_cr(0x32, ((vs - 1) >> 8) & 0xf);
  188. write_cr(0x11, ((ve - 1) & 0x0f) | 0x80);
  189. write_cr(0x12, (vd - 1) & 0xff);
  190. write_cr(0x31, ((vd - 1) & 0xf00) >> 8);
  191. write_cr(0x13, wd & 0xff);
  192. write_cr(0x41, (wd & 0xf00) >> 8);
  193. write_cr(0x15, (vs - 1) & 0xff);
  194. write_cr(0x33, ((vs - 1) >> 8) & 0xf);
  195. write_cr(0x38, ((ht - 5) & 0x100) >> 8);
  196. write_cr(0x16, (vt - 1) & 0xff);
  197. write_cr(0x18, 0x00);
  198. if (p->var.xres == 640) {
  199. writeb(0xc7, mmio_base + 0x784); /* set misc output reg */
  200. } else {
  201. writeb(0x07, mmio_base + 0x784); /* set misc output reg */
  202. }
  203. }
  204. static int asiliantfb_check_var(struct fb_var_screeninfo *var,
  205. struct fb_info *p)
  206. {
  207. unsigned long Ftarget, ratio, remainder;
  208. ratio = 1000000 / var->pixclock;
  209. remainder = 1000000 % var->pixclock;
  210. Ftarget = 1000000 * ratio + (1000000 * remainder) / var->pixclock;
  211. /* First check the constraint that the maximum post-VCO divisor is 32,
  212. * and the maximum Fvco is 220MHz */
  213. if (Ftarget > 220000000 || Ftarget < 3125000) {
  214. printk(KERN_ERR "asiliantfb dotclock must be between 3.125 and 220MHz\n");
  215. return -ENXIO;
  216. }
  217. var->xres_virtual = var->xres;
  218. var->yres_virtual = var->yres;
  219. if (var->bits_per_pixel == 24) {
  220. var->red.offset = 16;
  221. var->green.offset = 8;
  222. var->blue.offset = 0;
  223. var->red.length = var->blue.length = var->green.length = 8;
  224. } else if (var->bits_per_pixel == 16) {
  225. switch (var->red.offset) {
  226. case 11:
  227. var->green.length = 6;
  228. break;
  229. case 10:
  230. var->green.length = 5;
  231. break;
  232. default:
  233. return -EINVAL;
  234. }
  235. var->green.offset = 5;
  236. var->blue.offset = 0;
  237. var->red.length = var->blue.length = 5;
  238. } else if (var->bits_per_pixel == 8) {
  239. var->red.offset = var->green.offset = var->blue.offset = 0;
  240. var->red.length = var->green.length = var->blue.length = 8;
  241. }
  242. return 0;
  243. }
  244. static int asiliantfb_set_par(struct fb_info *p)
  245. {
  246. u8 dclk2_m; /* Holds m-2 value for register */
  247. u8 dclk2_n; /* Holds n-2 value for register */
  248. u8 dclk2_div; /* Holds divisor bitmask */
  249. /* Set pixclock */
  250. asiliant_calc_dclk2(&p->var.pixclock, &dclk2_m, &dclk2_n, &dclk2_div);
  251. /* Set color depth */
  252. if (p->var.bits_per_pixel == 24) {
  253. write_xr(0x81, 0x16); /* 24 bit packed color mode */
  254. write_xr(0x82, 0x00); /* Disable palettes */
  255. write_xr(0x20, 0x20); /* 24 bit blitter mode */
  256. } else if (p->var.bits_per_pixel == 16) {
  257. if (p->var.red.offset == 11)
  258. write_xr(0x81, 0x15); /* 16 bit color mode */
  259. else
  260. write_xr(0x81, 0x14); /* 15 bit color mode */
  261. write_xr(0x82, 0x00); /* Disable palettes */
  262. write_xr(0x20, 0x10); /* 16 bit blitter mode */
  263. } else if (p->var.bits_per_pixel == 8) {
  264. write_xr(0x0a, 0x02); /* Linear */
  265. write_xr(0x81, 0x12); /* 8 bit color mode */
  266. write_xr(0x82, 0x00); /* Graphics gamma enable */
  267. write_xr(0x20, 0x00); /* 8 bit blitter mode */
  268. }
  269. p->fix.line_length = p->var.xres * (p->var.bits_per_pixel >> 3);
  270. p->fix.visual = (p->var.bits_per_pixel == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
  271. write_xr(0xc4, dclk2_m);
  272. write_xr(0xc5, dclk2_n);
  273. write_xr(0xc7, dclk2_div);
  274. /* Set up the CR registers */
  275. asiliant_set_timing(p);
  276. return 0;
  277. }
  278. static int asiliantfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
  279. u_int transp, struct fb_info *p)
  280. {
  281. if (regno > 255)
  282. return 1;
  283. red >>= 8;
  284. green >>= 8;
  285. blue >>= 8;
  286. /* Set hardware palete */
  287. writeb(regno, mmio_base + 0x790);
  288. udelay(1);
  289. writeb(red, mmio_base + 0x791);
  290. writeb(green, mmio_base + 0x791);
  291. writeb(blue, mmio_base + 0x791);
  292. if (regno < 16) {
  293. switch(p->var.red.offset) {
  294. case 10: /* RGB 555 */
  295. ((u32 *)(p->pseudo_palette))[regno] =
  296. ((red & 0xf8) << 7) |
  297. ((green & 0xf8) << 2) |
  298. ((blue & 0xf8) >> 3);
  299. break;
  300. case 11: /* RGB 565 */
  301. ((u32 *)(p->pseudo_palette))[regno] =
  302. ((red & 0xf8) << 8) |
  303. ((green & 0xfc) << 3) |
  304. ((blue & 0xf8) >> 3);
  305. break;
  306. case 16: /* RGB 888 */
  307. ((u32 *)(p->pseudo_palette))[regno] =
  308. (red << 16) |
  309. (green << 8) |
  310. (blue);
  311. break;
  312. }
  313. }
  314. return 0;
  315. }
  316. struct chips_init_reg {
  317. unsigned char addr;
  318. unsigned char data;
  319. };
  320. static struct chips_init_reg chips_init_sr[] =
  321. {
  322. {0x00, 0x03}, /* Reset register */
  323. {0x01, 0x01}, /* Clocking mode */
  324. {0x02, 0x0f}, /* Plane mask */
  325. {0x04, 0x0e} /* Memory mode */
  326. };
  327. static struct chips_init_reg chips_init_gr[] =
  328. {
  329. {0x03, 0x00}, /* Data rotate */
  330. {0x05, 0x00}, /* Graphics mode */
  331. {0x06, 0x01}, /* Miscellaneous */
  332. {0x08, 0x00} /* Bit mask */
  333. };
  334. static struct chips_init_reg chips_init_ar[] =
  335. {
  336. {0x10, 0x01}, /* Mode control */
  337. {0x11, 0x00}, /* Overscan */
  338. {0x12, 0x0f}, /* Memory plane enable */
  339. {0x13, 0x00} /* Horizontal pixel panning */
  340. };
  341. static struct chips_init_reg chips_init_cr[] =
  342. {
  343. {0x0c, 0x00}, /* Start address high */
  344. {0x0d, 0x00}, /* Start address low */
  345. {0x40, 0x00}, /* Extended Start Address */
  346. {0x41, 0x00}, /* Extended Start Address */
  347. {0x14, 0x00}, /* Underline location */
  348. {0x17, 0xe3}, /* CRT mode control */
  349. {0x70, 0x00} /* Interlace control */
  350. };
  351. static struct chips_init_reg chips_init_fr[] =
  352. {
  353. {0x01, 0x02},
  354. {0x03, 0x08},
  355. {0x08, 0xcc},
  356. {0x0a, 0x08},
  357. {0x18, 0x00},
  358. {0x1e, 0x80},
  359. {0x40, 0x83},
  360. {0x41, 0x00},
  361. {0x48, 0x13},
  362. {0x4d, 0x60},
  363. {0x4e, 0x0f},
  364. {0x0b, 0x01},
  365. {0x21, 0x51},
  366. {0x22, 0x1d},
  367. {0x23, 0x5f},
  368. {0x20, 0x4f},
  369. {0x34, 0x00},
  370. {0x24, 0x51},
  371. {0x25, 0x00},
  372. {0x27, 0x0b},
  373. {0x26, 0x00},
  374. {0x37, 0x80},
  375. {0x33, 0x0b},
  376. {0x35, 0x11},
  377. {0x36, 0x02},
  378. {0x31, 0xea},
  379. {0x32, 0x0c},
  380. {0x30, 0xdf},
  381. {0x10, 0x0c},
  382. {0x11, 0xe0},
  383. {0x12, 0x50},
  384. {0x13, 0x00},
  385. {0x16, 0x03},
  386. {0x17, 0xbd},
  387. {0x1a, 0x00},
  388. };
  389. static struct chips_init_reg chips_init_xr[] =
  390. {
  391. {0xce, 0x00}, /* set default memory clock */
  392. {0xcc, 200 }, /* MCLK ratio M */
  393. {0xcd, 18 }, /* MCLK ratio N */
  394. {0xce, 0x90}, /* MCLK divisor = 2 */
  395. {0xc4, 209 },
  396. {0xc5, 118 },
  397. {0xc7, 32 },
  398. {0xcf, 0x06},
  399. {0x09, 0x01}, /* IO Control - CRT controller extensions */
  400. {0x0a, 0x02}, /* Frame buffer mapping */
  401. {0x0b, 0x01}, /* PCI burst write */
  402. {0x40, 0x03}, /* Memory access control */
  403. {0x80, 0x82}, /* Pixel pipeline configuration 0 */
  404. {0x81, 0x12}, /* Pixel pipeline configuration 1 */
  405. {0x82, 0x08}, /* Pixel pipeline configuration 2 */
  406. {0xd0, 0x0f},
  407. {0xd1, 0x01},
  408. };
  409. static void __devinit chips_hw_init(struct fb_info *p)
  410. {
  411. int i;
  412. for (i = 0; i < ARRAY_SIZE(chips_init_xr); ++i)
  413. write_xr(chips_init_xr[i].addr, chips_init_xr[i].data);
  414. write_xr(0x81, 0x12);
  415. write_xr(0x82, 0x08);
  416. write_xr(0x20, 0x00);
  417. for (i = 0; i < ARRAY_SIZE(chips_init_sr); ++i)
  418. write_sr(chips_init_sr[i].addr, chips_init_sr[i].data);
  419. for (i = 0; i < ARRAY_SIZE(chips_init_gr); ++i)
  420. write_gr(chips_init_gr[i].addr, chips_init_gr[i].data);
  421. for (i = 0; i < ARRAY_SIZE(chips_init_ar); ++i)
  422. write_ar(chips_init_ar[i].addr, chips_init_ar[i].data);
  423. /* Enable video output in attribute index register */
  424. writeb(0x20, mmio_base + 0x780);
  425. for (i = 0; i < ARRAY_SIZE(chips_init_cr); ++i)
  426. write_cr(chips_init_cr[i].addr, chips_init_cr[i].data);
  427. for (i = 0; i < ARRAY_SIZE(chips_init_fr); ++i)
  428. write_fr(chips_init_fr[i].addr, chips_init_fr[i].data);
  429. }
  430. static struct fb_fix_screeninfo asiliantfb_fix __devinitdata = {
  431. .id = "Asiliant 69000",
  432. .type = FB_TYPE_PACKED_PIXELS,
  433. .visual = FB_VISUAL_PSEUDOCOLOR,
  434. .accel = FB_ACCEL_NONE,
  435. .line_length = 640,
  436. .smem_len = 0x200000, /* 2MB */
  437. };
  438. static struct fb_var_screeninfo asiliantfb_var __devinitdata = {
  439. .xres = 640,
  440. .yres = 480,
  441. .xres_virtual = 640,
  442. .yres_virtual = 480,
  443. .bits_per_pixel = 8,
  444. .red = { .length = 8 },
  445. .green = { .length = 8 },
  446. .blue = { .length = 8 },
  447. .height = -1,
  448. .width = -1,
  449. .vmode = FB_VMODE_NONINTERLACED,
  450. .pixclock = 39722,
  451. .left_margin = 48,
  452. .right_margin = 16,
  453. .upper_margin = 33,
  454. .lower_margin = 10,
  455. .hsync_len = 96,
  456. .vsync_len = 2,
  457. };
  458. static void __devinit init_asiliant(struct fb_info *p, unsigned long addr)
  459. {
  460. p->fix = asiliantfb_fix;
  461. p->fix.smem_start = addr;
  462. p->var = asiliantfb_var;
  463. p->fbops = &asiliantfb_ops;
  464. p->flags = FBINFO_DEFAULT;
  465. fb_alloc_cmap(&p->cmap, 256, 0);
  466. if (register_framebuffer(p) < 0) {
  467. printk(KERN_ERR "C&T 69000 framebuffer failed to register\n");
  468. return;
  469. }
  470. printk(KERN_INFO "fb%d: Asiliant 69000 frame buffer (%dK RAM detected)\n",
  471. p->node, p->fix.smem_len / 1024);
  472. writeb(0xff, mmio_base + 0x78c);
  473. chips_hw_init(p);
  474. }
  475. static int __devinit
  476. asiliantfb_pci_init(struct pci_dev *dp, const struct pci_device_id *ent)
  477. {
  478. unsigned long addr, size;
  479. struct fb_info *p;
  480. if ((dp->resource[0].flags & IORESOURCE_MEM) == 0)
  481. return -ENODEV;
  482. addr = pci_resource_start(dp, 0);
  483. size = pci_resource_len(dp, 0);
  484. if (addr == 0)
  485. return -ENODEV;
  486. if (!request_mem_region(addr, size, "asiliantfb"))
  487. return -EBUSY;
  488. p = framebuffer_alloc(sizeof(u32) * 16, &dp->dev);
  489. if (!p) {
  490. release_mem_region(addr, size);
  491. return -ENOMEM;
  492. }
  493. p->pseudo_palette = p->par;
  494. p->par = NULL;
  495. p->screen_base = ioremap(addr, 0x800000);
  496. if (p->screen_base == NULL) {
  497. release_mem_region(addr, size);
  498. framebuffer_release(p);
  499. return -ENOMEM;
  500. }
  501. pci_write_config_dword(dp, 4, 0x02800083);
  502. writeb(3, p->screen_base + 0x400784);
  503. init_asiliant(p, addr);
  504. pci_set_drvdata(dp, p);
  505. return 0;
  506. }
  507. static void __devexit asiliantfb_remove(struct pci_dev *dp)
  508. {
  509. struct fb_info *p = pci_get_drvdata(dp);
  510. unregister_framebuffer(p);
  511. iounmap(p->screen_base);
  512. release_mem_region(pci_resource_start(dp, 0), pci_resource_len(dp, 0));
  513. pci_set_drvdata(dp, NULL);
  514. framebuffer_release(p);
  515. }
  516. static struct pci_device_id asiliantfb_pci_tbl[] __devinitdata = {
  517. { PCI_VENDOR_ID_CT, PCI_DEVICE_ID_CT_69000, PCI_ANY_ID, PCI_ANY_ID },
  518. { 0 }
  519. };
  520. MODULE_DEVICE_TABLE(pci, asiliantfb_pci_tbl);
  521. static struct pci_driver asiliantfb_driver = {
  522. .name = "asiliantfb",
  523. .id_table = asiliantfb_pci_tbl,
  524. .probe = asiliantfb_pci_init,
  525. .remove = __devexit_p(asiliantfb_remove),
  526. };
  527. static int __init asiliantfb_init(void)
  528. {
  529. if (fb_get_options("asiliantfb", NULL))
  530. return -ENODEV;
  531. return pci_register_driver(&asiliantfb_driver);
  532. }
  533. module_init(asiliantfb_init);
  534. static void __exit asiliantfb_exit(void)
  535. {
  536. pci_unregister_driver(&asiliantfb_driver);
  537. }
  538. MODULE_LICENSE("GPL");