sata_promise.c 20 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837
  1. /*
  2. * sata_promise.c - Promise SATA
  3. *
  4. * Maintained by: Jeff Garzik <jgarzik@pobox.com>
  5. * Please ALWAYS copy linux-ide@vger.kernel.org
  6. * on emails.
  7. *
  8. * Copyright 2003-2004 Red Hat, Inc.
  9. *
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License as published by
  13. * the Free Software Foundation; either version 2, or (at your option)
  14. * any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; see the file COPYING. If not, write to
  23. * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
  24. *
  25. *
  26. * libata documentation is available via 'make {ps|pdf}docs',
  27. * as Documentation/DocBook/libata.*
  28. *
  29. * Hardware information only available under NDA.
  30. *
  31. */
  32. #include <linux/kernel.h>
  33. #include <linux/module.h>
  34. #include <linux/pci.h>
  35. #include <linux/init.h>
  36. #include <linux/blkdev.h>
  37. #include <linux/delay.h>
  38. #include <linux/interrupt.h>
  39. #include <linux/sched.h>
  40. #include <linux/device.h>
  41. #include <scsi/scsi_host.h>
  42. #include <scsi/scsi_cmnd.h>
  43. #include <linux/libata.h>
  44. #include <asm/io.h>
  45. #include "sata_promise.h"
  46. #define DRV_NAME "sata_promise"
  47. #define DRV_VERSION "1.04"
  48. enum {
  49. PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
  50. PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
  51. PDC_TBG_MODE = 0x41, /* TBG mode */
  52. PDC_FLASH_CTL = 0x44, /* Flash control register */
  53. PDC_PCI_CTL = 0x48, /* PCI control and status register */
  54. PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */
  55. PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */
  56. PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */
  57. PDC2_SATA_PLUG_CSR = 0x60, /* SATAII Plug control/status reg */
  58. PDC_SLEW_CTL = 0x470, /* slew rate control reg */
  59. PDC_ERR_MASK = (1<<19) | (1<<20) | (1<<21) | (1<<22) |
  60. (1<<8) | (1<<9) | (1<<10),
  61. board_2037x = 0, /* FastTrak S150 TX2plus */
  62. board_20319 = 1, /* FastTrak S150 TX4 */
  63. board_20619 = 2, /* FastTrak TX4000 */
  64. board_20771 = 3, /* FastTrak TX2300 */
  65. board_2057x = 4, /* SATAII150 Tx2plus */
  66. board_40518 = 5, /* SATAII150 Tx4 */
  67. PDC_HAS_PATA = (1 << 1), /* PDC20375/20575 has PATA */
  68. PDC_RESET = (1 << 11), /* HDMA reset */
  69. PDC_COMMON_FLAGS = ATA_FLAG_NO_LEGACY | ATA_FLAG_SRST |
  70. ATA_FLAG_MMIO | ATA_FLAG_NO_ATAPI |
  71. ATA_FLAG_PIO_POLLING,
  72. };
  73. struct pdc_port_priv {
  74. u8 *pkt;
  75. dma_addr_t pkt_dma;
  76. };
  77. struct pdc_host_priv {
  78. int hotplug_offset;
  79. };
  80. static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg);
  81. static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
  82. static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
  83. static irqreturn_t pdc_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
  84. static void pdc_eng_timeout(struct ata_port *ap);
  85. static int pdc_port_start(struct ata_port *ap);
  86. static void pdc_port_stop(struct ata_port *ap);
  87. static void pdc_pata_phy_reset(struct ata_port *ap);
  88. static void pdc_sata_phy_reset(struct ata_port *ap);
  89. static void pdc_qc_prep(struct ata_queued_cmd *qc);
  90. static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
  91. static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
  92. static void pdc_irq_clear(struct ata_port *ap);
  93. static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc);
  94. static void pdc_host_stop(struct ata_host_set *host_set);
  95. static struct scsi_host_template pdc_ata_sht = {
  96. .module = THIS_MODULE,
  97. .name = DRV_NAME,
  98. .ioctl = ata_scsi_ioctl,
  99. .queuecommand = ata_scsi_queuecmd,
  100. .can_queue = ATA_DEF_QUEUE,
  101. .this_id = ATA_SHT_THIS_ID,
  102. .sg_tablesize = LIBATA_MAX_PRD,
  103. .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
  104. .emulated = ATA_SHT_EMULATED,
  105. .use_clustering = ATA_SHT_USE_CLUSTERING,
  106. .proc_name = DRV_NAME,
  107. .dma_boundary = ATA_DMA_BOUNDARY,
  108. .slave_configure = ata_scsi_slave_config,
  109. .slave_destroy = ata_scsi_slave_destroy,
  110. .bios_param = ata_std_bios_param,
  111. };
  112. static const struct ata_port_operations pdc_sata_ops = {
  113. .port_disable = ata_port_disable,
  114. .tf_load = pdc_tf_load_mmio,
  115. .tf_read = ata_tf_read,
  116. .check_status = ata_check_status,
  117. .exec_command = pdc_exec_command_mmio,
  118. .dev_select = ata_std_dev_select,
  119. .phy_reset = pdc_sata_phy_reset,
  120. .qc_prep = pdc_qc_prep,
  121. .qc_issue = pdc_qc_issue_prot,
  122. .eng_timeout = pdc_eng_timeout,
  123. .data_xfer = ata_mmio_data_xfer,
  124. .irq_handler = pdc_interrupt,
  125. .irq_clear = pdc_irq_clear,
  126. .scr_read = pdc_sata_scr_read,
  127. .scr_write = pdc_sata_scr_write,
  128. .port_start = pdc_port_start,
  129. .port_stop = pdc_port_stop,
  130. .host_stop = pdc_host_stop,
  131. };
  132. static const struct ata_port_operations pdc_pata_ops = {
  133. .port_disable = ata_port_disable,
  134. .tf_load = pdc_tf_load_mmio,
  135. .tf_read = ata_tf_read,
  136. .check_status = ata_check_status,
  137. .exec_command = pdc_exec_command_mmio,
  138. .dev_select = ata_std_dev_select,
  139. .phy_reset = pdc_pata_phy_reset,
  140. .qc_prep = pdc_qc_prep,
  141. .qc_issue = pdc_qc_issue_prot,
  142. .data_xfer = ata_mmio_data_xfer,
  143. .eng_timeout = pdc_eng_timeout,
  144. .irq_handler = pdc_interrupt,
  145. .irq_clear = pdc_irq_clear,
  146. .port_start = pdc_port_start,
  147. .port_stop = pdc_port_stop,
  148. .host_stop = pdc_host_stop,
  149. };
  150. static const struct ata_port_info pdc_port_info[] = {
  151. /* board_2037x */
  152. {
  153. .sht = &pdc_ata_sht,
  154. .host_flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
  155. .pio_mask = 0x1f, /* pio0-4 */
  156. .mwdma_mask = 0x07, /* mwdma0-2 */
  157. .udma_mask = 0x7f, /* udma0-6 ; FIXME */
  158. .port_ops = &pdc_sata_ops,
  159. },
  160. /* board_20319 */
  161. {
  162. .sht = &pdc_ata_sht,
  163. .host_flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
  164. .pio_mask = 0x1f, /* pio0-4 */
  165. .mwdma_mask = 0x07, /* mwdma0-2 */
  166. .udma_mask = 0x7f, /* udma0-6 ; FIXME */
  167. .port_ops = &pdc_sata_ops,
  168. },
  169. /* board_20619 */
  170. {
  171. .sht = &pdc_ata_sht,
  172. .host_flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS,
  173. .pio_mask = 0x1f, /* pio0-4 */
  174. .mwdma_mask = 0x07, /* mwdma0-2 */
  175. .udma_mask = 0x7f, /* udma0-6 ; FIXME */
  176. .port_ops = &pdc_pata_ops,
  177. },
  178. /* board_20771 */
  179. {
  180. .sht = &pdc_ata_sht,
  181. .host_flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
  182. .pio_mask = 0x1f, /* pio0-4 */
  183. .mwdma_mask = 0x07, /* mwdma0-2 */
  184. .udma_mask = 0x7f, /* udma0-6 ; FIXME */
  185. .port_ops = &pdc_sata_ops,
  186. },
  187. /* board_2057x */
  188. {
  189. .sht = &pdc_ata_sht,
  190. .host_flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
  191. .pio_mask = 0x1f, /* pio0-4 */
  192. .mwdma_mask = 0x07, /* mwdma0-2 */
  193. .udma_mask = 0x7f, /* udma0-6 ; FIXME */
  194. .port_ops = &pdc_sata_ops,
  195. },
  196. /* board_40518 */
  197. {
  198. .sht = &pdc_ata_sht,
  199. .host_flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
  200. .pio_mask = 0x1f, /* pio0-4 */
  201. .mwdma_mask = 0x07, /* mwdma0-2 */
  202. .udma_mask = 0x7f, /* udma0-6 ; FIXME */
  203. .port_ops = &pdc_sata_ops,
  204. },
  205. };
  206. static const struct pci_device_id pdc_ata_pci_tbl[] = {
  207. { PCI_VENDOR_ID_PROMISE, 0x3371, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  208. board_2037x },
  209. { PCI_VENDOR_ID_PROMISE, 0x3570, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  210. board_2037x },
  211. { PCI_VENDOR_ID_PROMISE, 0x3571, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  212. board_2037x },
  213. { PCI_VENDOR_ID_PROMISE, 0x3373, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  214. board_2037x },
  215. { PCI_VENDOR_ID_PROMISE, 0x3375, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  216. board_2037x },
  217. { PCI_VENDOR_ID_PROMISE, 0x3376, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  218. board_2037x },
  219. { PCI_VENDOR_ID_PROMISE, 0x3574, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  220. board_2057x },
  221. { PCI_VENDOR_ID_PROMISE, 0x3d75, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  222. board_2057x },
  223. { PCI_VENDOR_ID_PROMISE, 0x3d73, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  224. board_2037x },
  225. { PCI_VENDOR_ID_PROMISE, 0x3318, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  226. board_20319 },
  227. { PCI_VENDOR_ID_PROMISE, 0x3319, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  228. board_20319 },
  229. { PCI_VENDOR_ID_PROMISE, 0x3515, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  230. board_20319 },
  231. { PCI_VENDOR_ID_PROMISE, 0x3519, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  232. board_20319 },
  233. { PCI_VENDOR_ID_PROMISE, 0x3d17, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  234. board_20319 },
  235. { PCI_VENDOR_ID_PROMISE, 0x3d18, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  236. board_40518 },
  237. { PCI_VENDOR_ID_PROMISE, 0x6629, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  238. board_20619 },
  239. { PCI_VENDOR_ID_PROMISE, 0x3570, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  240. board_20771 },
  241. { } /* terminate list */
  242. };
  243. static struct pci_driver pdc_ata_pci_driver = {
  244. .name = DRV_NAME,
  245. .id_table = pdc_ata_pci_tbl,
  246. .probe = pdc_ata_init_one,
  247. .remove = ata_pci_remove_one,
  248. };
  249. static int pdc_port_start(struct ata_port *ap)
  250. {
  251. struct device *dev = ap->host_set->dev;
  252. struct pdc_port_priv *pp;
  253. int rc;
  254. rc = ata_port_start(ap);
  255. if (rc)
  256. return rc;
  257. pp = kzalloc(sizeof(*pp), GFP_KERNEL);
  258. if (!pp) {
  259. rc = -ENOMEM;
  260. goto err_out;
  261. }
  262. pp->pkt = dma_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
  263. if (!pp->pkt) {
  264. rc = -ENOMEM;
  265. goto err_out_kfree;
  266. }
  267. ap->private_data = pp;
  268. return 0;
  269. err_out_kfree:
  270. kfree(pp);
  271. err_out:
  272. ata_port_stop(ap);
  273. return rc;
  274. }
  275. static void pdc_port_stop(struct ata_port *ap)
  276. {
  277. struct device *dev = ap->host_set->dev;
  278. struct pdc_port_priv *pp = ap->private_data;
  279. ap->private_data = NULL;
  280. dma_free_coherent(dev, 128, pp->pkt, pp->pkt_dma);
  281. kfree(pp);
  282. ata_port_stop(ap);
  283. }
  284. static void pdc_host_stop(struct ata_host_set *host_set)
  285. {
  286. struct pdc_host_priv *hp = host_set->private_data;
  287. ata_pci_host_stop(host_set);
  288. kfree(hp);
  289. }
  290. static void pdc_reset_port(struct ata_port *ap)
  291. {
  292. void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_CTLSTAT;
  293. unsigned int i;
  294. u32 tmp;
  295. for (i = 11; i > 0; i--) {
  296. tmp = readl(mmio);
  297. if (tmp & PDC_RESET)
  298. break;
  299. udelay(100);
  300. tmp |= PDC_RESET;
  301. writel(tmp, mmio);
  302. }
  303. tmp &= ~PDC_RESET;
  304. writel(tmp, mmio);
  305. readl(mmio); /* flush */
  306. }
  307. static void pdc_sata_phy_reset(struct ata_port *ap)
  308. {
  309. pdc_reset_port(ap);
  310. sata_phy_reset(ap);
  311. }
  312. static void pdc_pata_cbl_detect(struct ata_port *ap)
  313. {
  314. u8 tmp;
  315. void __iomem *mmio = (void *) ap->ioaddr.cmd_addr + PDC_CTLSTAT + 0x03;
  316. tmp = readb(mmio);
  317. if (tmp & 0x01) {
  318. ap->cbl = ATA_CBL_PATA40;
  319. ap->udma_mask &= ATA_UDMA_MASK_40C;
  320. } else
  321. ap->cbl = ATA_CBL_PATA80;
  322. }
  323. static void pdc_pata_phy_reset(struct ata_port *ap)
  324. {
  325. pdc_pata_cbl_detect(ap);
  326. pdc_reset_port(ap);
  327. ata_port_probe(ap);
  328. ata_bus_reset(ap);
  329. }
  330. static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg)
  331. {
  332. if (sc_reg > SCR_CONTROL)
  333. return 0xffffffffU;
  334. return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
  335. }
  336. static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg,
  337. u32 val)
  338. {
  339. if (sc_reg > SCR_CONTROL)
  340. return;
  341. writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
  342. }
  343. static void pdc_qc_prep(struct ata_queued_cmd *qc)
  344. {
  345. struct pdc_port_priv *pp = qc->ap->private_data;
  346. unsigned int i;
  347. VPRINTK("ENTER\n");
  348. switch (qc->tf.protocol) {
  349. case ATA_PROT_DMA:
  350. ata_qc_prep(qc);
  351. /* fall through */
  352. case ATA_PROT_NODATA:
  353. i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma,
  354. qc->dev->devno, pp->pkt);
  355. if (qc->tf.flags & ATA_TFLAG_LBA48)
  356. i = pdc_prep_lba48(&qc->tf, pp->pkt, i);
  357. else
  358. i = pdc_prep_lba28(&qc->tf, pp->pkt, i);
  359. pdc_pkt_footer(&qc->tf, pp->pkt, i);
  360. break;
  361. default:
  362. break;
  363. }
  364. }
  365. static void pdc_eng_timeout(struct ata_port *ap)
  366. {
  367. struct ata_host_set *host_set = ap->host_set;
  368. u8 drv_stat;
  369. struct ata_queued_cmd *qc;
  370. unsigned long flags;
  371. DPRINTK("ENTER\n");
  372. spin_lock_irqsave(&host_set->lock, flags);
  373. qc = ata_qc_from_tag(ap, ap->active_tag);
  374. switch (qc->tf.protocol) {
  375. case ATA_PROT_DMA:
  376. case ATA_PROT_NODATA:
  377. ata_port_printk(ap, KERN_ERR, "command timeout\n");
  378. drv_stat = ata_wait_idle(ap);
  379. qc->err_mask |= __ac_err_mask(drv_stat);
  380. break;
  381. default:
  382. drv_stat = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
  383. ata_port_printk(ap, KERN_ERR,
  384. "unknown timeout, cmd 0x%x stat 0x%x\n",
  385. qc->tf.command, drv_stat);
  386. qc->err_mask |= ac_err_mask(drv_stat);
  387. break;
  388. }
  389. spin_unlock_irqrestore(&host_set->lock, flags);
  390. ata_eh_qc_complete(qc);
  391. DPRINTK("EXIT\n");
  392. }
  393. static inline unsigned int pdc_host_intr( struct ata_port *ap,
  394. struct ata_queued_cmd *qc)
  395. {
  396. unsigned int handled = 0;
  397. u32 tmp;
  398. void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_GLOBAL_CTL;
  399. tmp = readl(mmio);
  400. if (tmp & PDC_ERR_MASK) {
  401. qc->err_mask |= AC_ERR_DEV;
  402. pdc_reset_port(ap);
  403. }
  404. switch (qc->tf.protocol) {
  405. case ATA_PROT_DMA:
  406. case ATA_PROT_NODATA:
  407. qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
  408. ata_qc_complete(qc);
  409. handled = 1;
  410. break;
  411. default:
  412. ap->stats.idle_irq++;
  413. break;
  414. }
  415. return handled;
  416. }
  417. static void pdc_irq_clear(struct ata_port *ap)
  418. {
  419. struct ata_host_set *host_set = ap->host_set;
  420. void __iomem *mmio = host_set->mmio_base;
  421. readl(mmio + PDC_INT_SEQMASK);
  422. }
  423. static irqreturn_t pdc_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
  424. {
  425. struct ata_host_set *host_set = dev_instance;
  426. struct ata_port *ap;
  427. u32 mask = 0;
  428. unsigned int i, tmp;
  429. unsigned int handled = 0;
  430. void __iomem *mmio_base;
  431. VPRINTK("ENTER\n");
  432. if (!host_set || !host_set->mmio_base) {
  433. VPRINTK("QUICK EXIT\n");
  434. return IRQ_NONE;
  435. }
  436. mmio_base = host_set->mmio_base;
  437. /* reading should also clear interrupts */
  438. mask = readl(mmio_base + PDC_INT_SEQMASK);
  439. if (mask == 0xffffffff) {
  440. VPRINTK("QUICK EXIT 2\n");
  441. return IRQ_NONE;
  442. }
  443. spin_lock(&host_set->lock);
  444. mask &= 0xffff; /* only 16 tags possible */
  445. if (!mask) {
  446. VPRINTK("QUICK EXIT 3\n");
  447. goto done_irq;
  448. }
  449. writel(mask, mmio_base + PDC_INT_SEQMASK);
  450. for (i = 0; i < host_set->n_ports; i++) {
  451. VPRINTK("port %u\n", i);
  452. ap = host_set->ports[i];
  453. tmp = mask & (1 << (i + 1));
  454. if (tmp && ap &&
  455. !(ap->flags & ATA_FLAG_DISABLED)) {
  456. struct ata_queued_cmd *qc;
  457. qc = ata_qc_from_tag(ap, ap->active_tag);
  458. if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
  459. handled += pdc_host_intr(ap, qc);
  460. }
  461. }
  462. VPRINTK("EXIT\n");
  463. done_irq:
  464. spin_unlock(&host_set->lock);
  465. return IRQ_RETVAL(handled);
  466. }
  467. static inline void pdc_packet_start(struct ata_queued_cmd *qc)
  468. {
  469. struct ata_port *ap = qc->ap;
  470. struct pdc_port_priv *pp = ap->private_data;
  471. unsigned int port_no = ap->port_no;
  472. u8 seq = (u8) (port_no + 1);
  473. VPRINTK("ENTER, ap %p\n", ap);
  474. writel(0x00000001, ap->host_set->mmio_base + (seq * 4));
  475. readl(ap->host_set->mmio_base + (seq * 4)); /* flush */
  476. pp->pkt[2] = seq;
  477. wmb(); /* flush PRD, pkt writes */
  478. writel(pp->pkt_dma, (void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
  479. readl((void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); /* flush */
  480. }
  481. static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc)
  482. {
  483. switch (qc->tf.protocol) {
  484. case ATA_PROT_DMA:
  485. case ATA_PROT_NODATA:
  486. pdc_packet_start(qc);
  487. return 0;
  488. case ATA_PROT_ATAPI_DMA:
  489. BUG();
  490. break;
  491. default:
  492. break;
  493. }
  494. return ata_qc_issue_prot(qc);
  495. }
  496. static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
  497. {
  498. WARN_ON (tf->protocol == ATA_PROT_DMA ||
  499. tf->protocol == ATA_PROT_NODATA);
  500. ata_tf_load(ap, tf);
  501. }
  502. static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
  503. {
  504. WARN_ON (tf->protocol == ATA_PROT_DMA ||
  505. tf->protocol == ATA_PROT_NODATA);
  506. ata_exec_command(ap, tf);
  507. }
  508. static void pdc_ata_setup_port(struct ata_ioports *port, unsigned long base)
  509. {
  510. port->cmd_addr = base;
  511. port->data_addr = base;
  512. port->feature_addr =
  513. port->error_addr = base + 0x4;
  514. port->nsect_addr = base + 0x8;
  515. port->lbal_addr = base + 0xc;
  516. port->lbam_addr = base + 0x10;
  517. port->lbah_addr = base + 0x14;
  518. port->device_addr = base + 0x18;
  519. port->command_addr =
  520. port->status_addr = base + 0x1c;
  521. port->altstatus_addr =
  522. port->ctl_addr = base + 0x38;
  523. }
  524. static void pdc_host_init(unsigned int chip_id, struct ata_probe_ent *pe)
  525. {
  526. void __iomem *mmio = pe->mmio_base;
  527. struct pdc_host_priv *hp = pe->private_data;
  528. int hotplug_offset = hp->hotplug_offset;
  529. u32 tmp;
  530. /*
  531. * Except for the hotplug stuff, this is voodoo from the
  532. * Promise driver. Label this entire section
  533. * "TODO: figure out why we do this"
  534. */
  535. /* change FIFO_SHD to 8 dwords, enable BMR_BURST */
  536. tmp = readl(mmio + PDC_FLASH_CTL);
  537. tmp |= 0x12000; /* bit 16 (fifo 8 dw) and 13 (bmr burst?) */
  538. writel(tmp, mmio + PDC_FLASH_CTL);
  539. /* clear plug/unplug flags for all ports */
  540. tmp = readl(mmio + hotplug_offset);
  541. writel(tmp | 0xff, mmio + hotplug_offset);
  542. /* mask plug/unplug ints */
  543. tmp = readl(mmio + hotplug_offset);
  544. writel(tmp | 0xff0000, mmio + hotplug_offset);
  545. /* reduce TBG clock to 133 Mhz. */
  546. tmp = readl(mmio + PDC_TBG_MODE);
  547. tmp &= ~0x30000; /* clear bit 17, 16*/
  548. tmp |= 0x10000; /* set bit 17:16 = 0:1 */
  549. writel(tmp, mmio + PDC_TBG_MODE);
  550. readl(mmio + PDC_TBG_MODE); /* flush */
  551. msleep(10);
  552. /* adjust slew rate control register. */
  553. tmp = readl(mmio + PDC_SLEW_CTL);
  554. tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */
  555. tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */
  556. writel(tmp, mmio + PDC_SLEW_CTL);
  557. }
  558. static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
  559. {
  560. static int printed_version;
  561. struct ata_probe_ent *probe_ent = NULL;
  562. struct pdc_host_priv *hp;
  563. unsigned long base;
  564. void __iomem *mmio_base;
  565. unsigned int board_idx = (unsigned int) ent->driver_data;
  566. int pci_dev_busy = 0;
  567. int rc;
  568. if (!printed_version++)
  569. dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
  570. rc = pci_enable_device(pdev);
  571. if (rc)
  572. return rc;
  573. rc = pci_request_regions(pdev, DRV_NAME);
  574. if (rc) {
  575. pci_dev_busy = 1;
  576. goto err_out;
  577. }
  578. rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
  579. if (rc)
  580. goto err_out_regions;
  581. rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
  582. if (rc)
  583. goto err_out_regions;
  584. probe_ent = kzalloc(sizeof(*probe_ent), GFP_KERNEL);
  585. if (probe_ent == NULL) {
  586. rc = -ENOMEM;
  587. goto err_out_regions;
  588. }
  589. probe_ent->dev = pci_dev_to_dev(pdev);
  590. INIT_LIST_HEAD(&probe_ent->node);
  591. mmio_base = pci_iomap(pdev, 3, 0);
  592. if (mmio_base == NULL) {
  593. rc = -ENOMEM;
  594. goto err_out_free_ent;
  595. }
  596. base = (unsigned long) mmio_base;
  597. hp = kzalloc(sizeof(*hp), GFP_KERNEL);
  598. if (hp == NULL) {
  599. rc = -ENOMEM;
  600. goto err_out_free_ent;
  601. }
  602. /* Set default hotplug offset */
  603. hp->hotplug_offset = PDC_SATA_PLUG_CSR;
  604. probe_ent->private_data = hp;
  605. probe_ent->sht = pdc_port_info[board_idx].sht;
  606. probe_ent->host_flags = pdc_port_info[board_idx].host_flags;
  607. probe_ent->pio_mask = pdc_port_info[board_idx].pio_mask;
  608. probe_ent->mwdma_mask = pdc_port_info[board_idx].mwdma_mask;
  609. probe_ent->udma_mask = pdc_port_info[board_idx].udma_mask;
  610. probe_ent->port_ops = pdc_port_info[board_idx].port_ops;
  611. probe_ent->irq = pdev->irq;
  612. probe_ent->irq_flags = IRQF_SHARED;
  613. probe_ent->mmio_base = mmio_base;
  614. pdc_ata_setup_port(&probe_ent->port[0], base + 0x200);
  615. pdc_ata_setup_port(&probe_ent->port[1], base + 0x280);
  616. probe_ent->port[0].scr_addr = base + 0x400;
  617. probe_ent->port[1].scr_addr = base + 0x500;
  618. /* notice 4-port boards */
  619. switch (board_idx) {
  620. case board_40518:
  621. /* Override hotplug offset for SATAII150 */
  622. hp->hotplug_offset = PDC2_SATA_PLUG_CSR;
  623. /* Fall through */
  624. case board_20319:
  625. probe_ent->n_ports = 4;
  626. pdc_ata_setup_port(&probe_ent->port[2], base + 0x300);
  627. pdc_ata_setup_port(&probe_ent->port[3], base + 0x380);
  628. probe_ent->port[2].scr_addr = base + 0x600;
  629. probe_ent->port[3].scr_addr = base + 0x700;
  630. break;
  631. case board_2057x:
  632. /* Override hotplug offset for SATAII150 */
  633. hp->hotplug_offset = PDC2_SATA_PLUG_CSR;
  634. /* Fall through */
  635. case board_2037x:
  636. probe_ent->n_ports = 2;
  637. break;
  638. case board_20771:
  639. probe_ent->n_ports = 2;
  640. break;
  641. case board_20619:
  642. probe_ent->n_ports = 4;
  643. pdc_ata_setup_port(&probe_ent->port[2], base + 0x300);
  644. pdc_ata_setup_port(&probe_ent->port[3], base + 0x380);
  645. probe_ent->port[2].scr_addr = base + 0x600;
  646. probe_ent->port[3].scr_addr = base + 0x700;
  647. break;
  648. default:
  649. BUG();
  650. break;
  651. }
  652. pci_set_master(pdev);
  653. /* initialize adapter */
  654. pdc_host_init(board_idx, probe_ent);
  655. /* FIXME: Need any other frees than hp? */
  656. if (!ata_device_add(probe_ent))
  657. kfree(hp);
  658. kfree(probe_ent);
  659. return 0;
  660. err_out_free_ent:
  661. kfree(probe_ent);
  662. err_out_regions:
  663. pci_release_regions(pdev);
  664. err_out:
  665. if (!pci_dev_busy)
  666. pci_disable_device(pdev);
  667. return rc;
  668. }
  669. static int __init pdc_ata_init(void)
  670. {
  671. return pci_module_init(&pdc_ata_pci_driver);
  672. }
  673. static void __exit pdc_ata_exit(void)
  674. {
  675. pci_unregister_driver(&pdc_ata_pci_driver);
  676. }
  677. MODULE_AUTHOR("Jeff Garzik");
  678. MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver");
  679. MODULE_LICENSE("GPL");
  680. MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl);
  681. MODULE_VERSION(DRV_VERSION);
  682. module_init(pdc_ata_init);
  683. module_exit(pdc_ata_exit);