zd_rf_al2230.c 8.3 KB

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  1. /* zd_rf_al2230.c: Functions for the AL2230 RF controller
  2. *
  3. * This program is free software; you can redistribute it and/or modify
  4. * it under the terms of the GNU General Public License as published by
  5. * the Free Software Foundation; either version 2 of the License, or
  6. * (at your option) any later version.
  7. *
  8. * This program is distributed in the hope that it will be useful,
  9. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. * GNU General Public License for more details.
  12. *
  13. * You should have received a copy of the GNU General Public License
  14. * along with this program; if not, write to the Free Software
  15. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  16. */
  17. #include <linux/kernel.h>
  18. #include "zd_rf.h"
  19. #include "zd_usb.h"
  20. #include "zd_chip.h"
  21. static const u32 al2230_table[][3] = {
  22. RF_CHANNEL( 1) = { 0x03f790, 0x033331, 0x00000d, },
  23. RF_CHANNEL( 2) = { 0x03f790, 0x0b3331, 0x00000d, },
  24. RF_CHANNEL( 3) = { 0x03e790, 0x033331, 0x00000d, },
  25. RF_CHANNEL( 4) = { 0x03e790, 0x0b3331, 0x00000d, },
  26. RF_CHANNEL( 5) = { 0x03f7a0, 0x033331, 0x00000d, },
  27. RF_CHANNEL( 6) = { 0x03f7a0, 0x0b3331, 0x00000d, },
  28. RF_CHANNEL( 7) = { 0x03e7a0, 0x033331, 0x00000d, },
  29. RF_CHANNEL( 8) = { 0x03e7a0, 0x0b3331, 0x00000d, },
  30. RF_CHANNEL( 9) = { 0x03f7b0, 0x033331, 0x00000d, },
  31. RF_CHANNEL(10) = { 0x03f7b0, 0x0b3331, 0x00000d, },
  32. RF_CHANNEL(11) = { 0x03e7b0, 0x033331, 0x00000d, },
  33. RF_CHANNEL(12) = { 0x03e7b0, 0x0b3331, 0x00000d, },
  34. RF_CHANNEL(13) = { 0x03f7c0, 0x033331, 0x00000d, },
  35. RF_CHANNEL(14) = { 0x03e7c0, 0x066661, 0x00000d, },
  36. };
  37. static int zd1211_al2230_init_hw(struct zd_rf *rf)
  38. {
  39. int r;
  40. struct zd_chip *chip = zd_rf_to_chip(rf);
  41. static const struct zd_ioreq16 ioreqs[] = {
  42. { CR15, 0x20 }, { CR23, 0x40 }, { CR24, 0x20 },
  43. { CR26, 0x11 }, { CR28, 0x3e }, { CR29, 0x00 },
  44. { CR44, 0x33 }, { CR106, 0x2a }, { CR107, 0x1a },
  45. { CR109, 0x09 }, { CR110, 0x27 }, { CR111, 0x2b },
  46. { CR112, 0x2b }, { CR119, 0x0a }, { CR10, 0x89 },
  47. /* for newest (3rd cut) AL2300 */
  48. { CR17, 0x28 },
  49. { CR26, 0x93 }, { CR34, 0x30 },
  50. /* for newest (3rd cut) AL2300 */
  51. { CR35, 0x3e },
  52. { CR41, 0x24 }, { CR44, 0x32 },
  53. /* for newest (3rd cut) AL2300 */
  54. { CR46, 0x96 },
  55. { CR47, 0x1e }, { CR79, 0x58 }, { CR80, 0x30 },
  56. { CR81, 0x30 }, { CR87, 0x0a }, { CR89, 0x04 },
  57. { CR92, 0x0a }, { CR99, 0x28 }, { CR100, 0x00 },
  58. { CR101, 0x13 }, { CR102, 0x27 }, { CR106, 0x24 },
  59. { CR107, 0x2a }, { CR109, 0x09 }, { CR110, 0x13 },
  60. { CR111, 0x1f }, { CR112, 0x1f }, { CR113, 0x27 },
  61. { CR114, 0x27 },
  62. /* for newest (3rd cut) AL2300 */
  63. { CR115, 0x24 },
  64. { CR116, 0x24 }, { CR117, 0xf4 }, { CR118, 0xfc },
  65. { CR119, 0x10 }, { CR120, 0x4f }, { CR121, 0x77 },
  66. { CR122, 0xe0 }, { CR137, 0x88 }, { CR252, 0xff },
  67. { CR253, 0xff },
  68. /* These following happen separately in the vendor driver */
  69. { },
  70. /* shdnb(PLL_ON)=0 */
  71. { CR251, 0x2f },
  72. /* shdnb(PLL_ON)=1 */
  73. { CR251, 0x3f },
  74. { CR138, 0x28 }, { CR203, 0x06 },
  75. };
  76. static const u32 rv[] = {
  77. /* Channel 1 */
  78. 0x03f790,
  79. 0x033331,
  80. 0x00000d,
  81. 0x0b3331,
  82. 0x03b812,
  83. 0x00fff3,
  84. 0x000da4,
  85. 0x0f4dc5, /* fix freq shift, 0x04edc5 */
  86. 0x0805b6,
  87. 0x011687,
  88. 0x000688,
  89. 0x0403b9, /* external control TX power (CR31) */
  90. 0x00dbba,
  91. 0x00099b,
  92. 0x0bdffc,
  93. 0x00000d,
  94. 0x00500f,
  95. /* These writes happen separately in the vendor driver */
  96. 0x00d00f,
  97. 0x004c0f,
  98. 0x00540f,
  99. 0x00700f,
  100. 0x00500f,
  101. };
  102. r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
  103. if (r)
  104. return r;
  105. r = zd_rfwritev_locked(chip, rv, ARRAY_SIZE(rv), RF_RV_BITS);
  106. if (r)
  107. return r;
  108. return 0;
  109. }
  110. static int zd1211b_al2230_init_hw(struct zd_rf *rf)
  111. {
  112. int r;
  113. struct zd_chip *chip = zd_rf_to_chip(rf);
  114. static const struct zd_ioreq16 ioreqs1[] = {
  115. { CR10, 0x89 }, { CR15, 0x20 },
  116. { CR17, 0x2B }, /* for newest(3rd cut) AL2230 */
  117. { CR23, 0x40 }, { CR24, 0x20 }, { CR26, 0x93 },
  118. { CR28, 0x3e }, { CR29, 0x00 },
  119. { CR33, 0x28 }, /* 5621 */
  120. { CR34, 0x30 },
  121. { CR35, 0x3e }, /* for newest(3rd cut) AL2230 */
  122. { CR41, 0x24 }, { CR44, 0x32 },
  123. { CR46, 0x99 }, /* for newest(3rd cut) AL2230 */
  124. { CR47, 0x1e },
  125. /* ZD1211B 05.06.10 */
  126. { CR48, 0x00 }, { CR49, 0x00 }, { CR51, 0x01 },
  127. { CR52, 0x80 }, { CR53, 0x7e }, { CR65, 0x00 },
  128. { CR66, 0x00 }, { CR67, 0x00 }, { CR68, 0x00 },
  129. { CR69, 0x28 },
  130. { CR79, 0x58 }, { CR80, 0x30 }, { CR81, 0x30 },
  131. { CR87, 0x0a }, { CR89, 0x04 },
  132. { CR91, 0x00 }, /* 5621 */
  133. { CR92, 0x0a },
  134. { CR98, 0x8d }, /* 4804, for 1212 new algorithm */
  135. { CR99, 0x00 }, /* 5621 */
  136. { CR101, 0x13 }, { CR102, 0x27 },
  137. { CR106, 0x24 }, /* for newest(3rd cut) AL2230 */
  138. { CR107, 0x2a },
  139. { CR109, 0x13 }, /* 4804, for 1212 new algorithm */
  140. { CR110, 0x1f }, /* 4804, for 1212 new algorithm */
  141. { CR111, 0x1f }, { CR112, 0x1f }, { CR113, 0x27 },
  142. { CR114, 0x27 },
  143. { CR115, 0x26 }, /* 24->26 at 4902 for newest(3rd cut) AL2230 */
  144. { CR116, 0x24 },
  145. { CR117, 0xfa }, /* for 1211b */
  146. { CR118, 0xfa }, /* for 1211b */
  147. { CR119, 0x10 },
  148. { CR120, 0x4f },
  149. { CR121, 0x6c }, /* for 1211b */
  150. { CR122, 0xfc }, /* E0->FC at 4902 */
  151. { CR123, 0x57 }, /* 5623 */
  152. { CR125, 0xad }, /* 4804, for 1212 new algorithm */
  153. { CR126, 0x6c }, /* 5614 */
  154. { CR127, 0x03 }, /* 4804, for 1212 new algorithm */
  155. { CR137, 0x50 }, /* 5614 */
  156. { CR138, 0xa8 },
  157. { CR144, 0xac }, /* 5621 */
  158. { CR150, 0x0d }, { CR252, 0x00 }, { CR253, 0x00 },
  159. };
  160. static const u32 rv1[] = {
  161. /* channel 1 */
  162. 0x03f790,
  163. 0x033331,
  164. 0x00000d,
  165. 0x0b3331,
  166. 0x03b812,
  167. 0x00fff3,
  168. 0x0005a4,
  169. 0x0f4dc5, /* fix freq shift 0x044dc5 */
  170. 0x0805b6,
  171. 0x0146c7,
  172. 0x000688,
  173. 0x0403b9, /* External control TX power (CR31) */
  174. 0x00dbba,
  175. 0x00099b,
  176. 0x0bdffc,
  177. 0x00000d,
  178. 0x00580f,
  179. };
  180. static const struct zd_ioreq16 ioreqs2[] = {
  181. { CR47, 0x1e }, { CR_RFCFG, 0x03 },
  182. };
  183. static const u32 rv2[] = {
  184. 0x00880f,
  185. 0x00080f,
  186. };
  187. static const struct zd_ioreq16 ioreqs3[] = {
  188. { CR_RFCFG, 0x00 }, { CR47, 0x1e }, { CR251, 0x7f },
  189. };
  190. static const u32 rv3[] = {
  191. 0x00d80f,
  192. 0x00780f,
  193. 0x00580f,
  194. };
  195. static const struct zd_ioreq16 ioreqs4[] = {
  196. { CR138, 0x28 }, { CR203, 0x06 },
  197. };
  198. r = zd_iowrite16a_locked(chip, ioreqs1, ARRAY_SIZE(ioreqs1));
  199. if (r)
  200. return r;
  201. r = zd_rfwritev_locked(chip, rv1, ARRAY_SIZE(rv1), RF_RV_BITS);
  202. if (r)
  203. return r;
  204. r = zd_iowrite16a_locked(chip, ioreqs2, ARRAY_SIZE(ioreqs2));
  205. if (r)
  206. return r;
  207. r = zd_rfwritev_locked(chip, rv2, ARRAY_SIZE(rv2), RF_RV_BITS);
  208. if (r)
  209. return r;
  210. r = zd_iowrite16a_locked(chip, ioreqs3, ARRAY_SIZE(ioreqs3));
  211. if (r)
  212. return r;
  213. r = zd_rfwritev_locked(chip, rv3, ARRAY_SIZE(rv3), RF_RV_BITS);
  214. if (r)
  215. return r;
  216. return zd_iowrite16a_locked(chip, ioreqs4, ARRAY_SIZE(ioreqs4));
  217. }
  218. static int al2230_set_channel(struct zd_rf *rf, u8 channel)
  219. {
  220. int r;
  221. const u32 *rv = al2230_table[channel-1];
  222. struct zd_chip *chip = zd_rf_to_chip(rf);
  223. static const struct zd_ioreq16 ioreqs[] = {
  224. { CR138, 0x28 },
  225. { CR203, 0x06 },
  226. };
  227. r = zd_rfwritev_locked(chip, rv, 3, RF_RV_BITS);
  228. if (r)
  229. return r;
  230. return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
  231. }
  232. static int zd1211_al2230_switch_radio_on(struct zd_rf *rf)
  233. {
  234. struct zd_chip *chip = zd_rf_to_chip(rf);
  235. static const struct zd_ioreq16 ioreqs[] = {
  236. { CR11, 0x00 },
  237. { CR251, 0x3f },
  238. };
  239. return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
  240. }
  241. static int zd1211b_al2230_switch_radio_on(struct zd_rf *rf)
  242. {
  243. struct zd_chip *chip = zd_rf_to_chip(rf);
  244. static const struct zd_ioreq16 ioreqs[] = {
  245. { CR11, 0x00 },
  246. { CR251, 0x7f },
  247. };
  248. return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
  249. }
  250. static int al2230_switch_radio_off(struct zd_rf *rf)
  251. {
  252. struct zd_chip *chip = zd_rf_to_chip(rf);
  253. static const struct zd_ioreq16 ioreqs[] = {
  254. { CR11, 0x04 },
  255. { CR251, 0x2f },
  256. };
  257. return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
  258. }
  259. int zd_rf_init_al2230(struct zd_rf *rf)
  260. {
  261. struct zd_chip *chip = zd_rf_to_chip(rf);
  262. rf->set_channel = al2230_set_channel;
  263. rf->switch_radio_off = al2230_switch_radio_off;
  264. if (chip->is_zd1211b) {
  265. rf->init_hw = zd1211b_al2230_init_hw;
  266. rf->switch_radio_on = zd1211b_al2230_switch_radio_on;
  267. } else {
  268. rf->init_hw = zd1211_al2230_init_hw;
  269. rf->switch_radio_on = zd1211_al2230_switch_radio_on;
  270. }
  271. rf->patch_6m_band_edge = 1;
  272. return 0;
  273. }