mac-fec.c 15 KB

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  1. /*
  2. * Freescale Ethernet controllers
  3. *
  4. * Copyright (c) 2005 Intracom S.A.
  5. * by Pantelis Antoniou <panto@intracom.gr>
  6. *
  7. * 2005 (c) MontaVista Software, Inc.
  8. * Vitaly Bordug <vbordug@ru.mvista.com>
  9. *
  10. * This file is licensed under the terms of the GNU General Public License
  11. * version 2. This program is licensed "as is" without any warranty of any
  12. * kind, whether express or implied.
  13. */
  14. #include <linux/module.h>
  15. #include <linux/kernel.h>
  16. #include <linux/types.h>
  17. #include <linux/sched.h>
  18. #include <linux/string.h>
  19. #include <linux/ptrace.h>
  20. #include <linux/errno.h>
  21. #include <linux/ioport.h>
  22. #include <linux/slab.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/pci.h>
  25. #include <linux/init.h>
  26. #include <linux/delay.h>
  27. #include <linux/netdevice.h>
  28. #include <linux/etherdevice.h>
  29. #include <linux/skbuff.h>
  30. #include <linux/spinlock.h>
  31. #include <linux/mii.h>
  32. #include <linux/ethtool.h>
  33. #include <linux/bitops.h>
  34. #include <linux/fs.h>
  35. #include <linux/platform_device.h>
  36. #include <asm/irq.h>
  37. #include <asm/uaccess.h>
  38. #ifdef CONFIG_8xx
  39. #include <asm/8xx_immap.h>
  40. #include <asm/pgtable.h>
  41. #include <asm/mpc8xx.h>
  42. #include <asm/commproc.h>
  43. #endif
  44. #include "fs_enet.h"
  45. /*************************************************/
  46. #if defined(CONFIG_CPM1)
  47. /* for a CPM1 __raw_xxx's are sufficient */
  48. #define __fs_out32(addr, x) __raw_writel(x, addr)
  49. #define __fs_out16(addr, x) __raw_writew(x, addr)
  50. #define __fs_in32(addr) __raw_readl(addr)
  51. #define __fs_in16(addr) __raw_readw(addr)
  52. #else
  53. /* for others play it safe */
  54. #define __fs_out32(addr, x) out_be32(addr, x)
  55. #define __fs_out16(addr, x) out_be16(addr, x)
  56. #define __fs_in32(addr) in_be32(addr)
  57. #define __fs_in16(addr) in_be16(addr)
  58. #endif
  59. /* write */
  60. #define FW(_fecp, _reg, _v) __fs_out32(&(_fecp)->fec_ ## _reg, (_v))
  61. /* read */
  62. #define FR(_fecp, _reg) __fs_in32(&(_fecp)->fec_ ## _reg)
  63. /* set bits */
  64. #define FS(_fecp, _reg, _v) FW(_fecp, _reg, FR(_fecp, _reg) | (_v))
  65. /* clear bits */
  66. #define FC(_fecp, _reg, _v) FW(_fecp, _reg, FR(_fecp, _reg) & ~(_v))
  67. /* CRC polynomium used by the FEC for the multicast group filtering */
  68. #define FEC_CRC_POLY 0x04C11DB7
  69. #define FEC_MAX_MULTICAST_ADDRS 64
  70. /* Interrupt events/masks.
  71. */
  72. #define FEC_ENET_HBERR 0x80000000U /* Heartbeat error */
  73. #define FEC_ENET_BABR 0x40000000U /* Babbling receiver */
  74. #define FEC_ENET_BABT 0x20000000U /* Babbling transmitter */
  75. #define FEC_ENET_GRA 0x10000000U /* Graceful stop complete */
  76. #define FEC_ENET_TXF 0x08000000U /* Full frame transmitted */
  77. #define FEC_ENET_TXB 0x04000000U /* A buffer was transmitted */
  78. #define FEC_ENET_RXF 0x02000000U /* Full frame received */
  79. #define FEC_ENET_RXB 0x01000000U /* A buffer was received */
  80. #define FEC_ENET_MII 0x00800000U /* MII interrupt */
  81. #define FEC_ENET_EBERR 0x00400000U /* SDMA bus error */
  82. #define FEC_ECNTRL_PINMUX 0x00000004
  83. #define FEC_ECNTRL_ETHER_EN 0x00000002
  84. #define FEC_ECNTRL_RESET 0x00000001
  85. #define FEC_RCNTRL_BC_REJ 0x00000010
  86. #define FEC_RCNTRL_PROM 0x00000008
  87. #define FEC_RCNTRL_MII_MODE 0x00000004
  88. #define FEC_RCNTRL_DRT 0x00000002
  89. #define FEC_RCNTRL_LOOP 0x00000001
  90. #define FEC_TCNTRL_FDEN 0x00000004
  91. #define FEC_TCNTRL_HBC 0x00000002
  92. #define FEC_TCNTRL_GTS 0x00000001
  93. /* Make MII read/write commands for the FEC.
  94. */
  95. #define mk_mii_read(REG) (0x60020000 | ((REG & 0x1f) << 18))
  96. #define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | (VAL & 0xffff))
  97. #define mk_mii_end 0
  98. #define FEC_MII_LOOPS 10000
  99. /*
  100. * Delay to wait for FEC reset command to complete (in us)
  101. */
  102. #define FEC_RESET_DELAY 50
  103. static int whack_reset(fec_t * fecp)
  104. {
  105. int i;
  106. FW(fecp, ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET);
  107. for (i = 0; i < FEC_RESET_DELAY; i++) {
  108. if ((FR(fecp, ecntrl) & FEC_ECNTRL_RESET) == 0)
  109. return 0; /* OK */
  110. udelay(1);
  111. }
  112. return -1;
  113. }
  114. static int do_pd_setup(struct fs_enet_private *fep)
  115. {
  116. struct platform_device *pdev = to_platform_device(fep->dev);
  117. struct resource *r;
  118. /* Fill out IRQ field */
  119. fep->interrupt = platform_get_irq_byname(pdev,"interrupt");
  120. if (fep->interrupt < 0)
  121. return -EINVAL;
  122. r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
  123. fep->fec.fecp =(void*)r->start;
  124. if(fep->fec.fecp == NULL)
  125. return -EINVAL;
  126. return 0;
  127. }
  128. #define FEC_NAPI_RX_EVENT_MSK (FEC_ENET_RXF | FEC_ENET_RXB)
  129. #define FEC_RX_EVENT (FEC_ENET_RXF)
  130. #define FEC_TX_EVENT (FEC_ENET_TXF)
  131. #define FEC_ERR_EVENT_MSK (FEC_ENET_HBERR | FEC_ENET_BABR | \
  132. FEC_ENET_BABT | FEC_ENET_EBERR)
  133. static int setup_data(struct net_device *dev)
  134. {
  135. struct fs_enet_private *fep = netdev_priv(dev);
  136. if (do_pd_setup(fep) != 0)
  137. return -EINVAL;
  138. fep->fec.hthi = 0;
  139. fep->fec.htlo = 0;
  140. fep->ev_napi_rx = FEC_NAPI_RX_EVENT_MSK;
  141. fep->ev_rx = FEC_RX_EVENT;
  142. fep->ev_tx = FEC_TX_EVENT;
  143. fep->ev_err = FEC_ERR_EVENT_MSK;
  144. return 0;
  145. }
  146. static int allocate_bd(struct net_device *dev)
  147. {
  148. struct fs_enet_private *fep = netdev_priv(dev);
  149. const struct fs_platform_info *fpi = fep->fpi;
  150. fep->ring_base = dma_alloc_coherent(fep->dev,
  151. (fpi->tx_ring + fpi->rx_ring) *
  152. sizeof(cbd_t), &fep->ring_mem_addr,
  153. GFP_KERNEL);
  154. if (fep->ring_base == NULL)
  155. return -ENOMEM;
  156. return 0;
  157. }
  158. static void free_bd(struct net_device *dev)
  159. {
  160. struct fs_enet_private *fep = netdev_priv(dev);
  161. const struct fs_platform_info *fpi = fep->fpi;
  162. if(fep->ring_base)
  163. dma_free_coherent(fep->dev, (fpi->tx_ring + fpi->rx_ring)
  164. * sizeof(cbd_t),
  165. fep->ring_base,
  166. fep->ring_mem_addr);
  167. }
  168. static void cleanup_data(struct net_device *dev)
  169. {
  170. /* nothing */
  171. }
  172. static void set_promiscuous_mode(struct net_device *dev)
  173. {
  174. struct fs_enet_private *fep = netdev_priv(dev);
  175. fec_t *fecp = fep->fec.fecp;
  176. FS(fecp, r_cntrl, FEC_RCNTRL_PROM);
  177. }
  178. static void set_multicast_start(struct net_device *dev)
  179. {
  180. struct fs_enet_private *fep = netdev_priv(dev);
  181. fep->fec.hthi = 0;
  182. fep->fec.htlo = 0;
  183. }
  184. static void set_multicast_one(struct net_device *dev, const u8 *mac)
  185. {
  186. struct fs_enet_private *fep = netdev_priv(dev);
  187. int temp, hash_index, i, j;
  188. u32 crc, csrVal;
  189. u8 byte, msb;
  190. crc = 0xffffffff;
  191. for (i = 0; i < 6; i++) {
  192. byte = mac[i];
  193. for (j = 0; j < 8; j++) {
  194. msb = crc >> 31;
  195. crc <<= 1;
  196. if (msb ^ (byte & 0x1))
  197. crc ^= FEC_CRC_POLY;
  198. byte >>= 1;
  199. }
  200. }
  201. temp = (crc & 0x3f) >> 1;
  202. hash_index = ((temp & 0x01) << 4) |
  203. ((temp & 0x02) << 2) |
  204. ((temp & 0x04)) |
  205. ((temp & 0x08) >> 2) |
  206. ((temp & 0x10) >> 4);
  207. csrVal = 1 << hash_index;
  208. if (crc & 1)
  209. fep->fec.hthi |= csrVal;
  210. else
  211. fep->fec.htlo |= csrVal;
  212. }
  213. static void set_multicast_finish(struct net_device *dev)
  214. {
  215. struct fs_enet_private *fep = netdev_priv(dev);
  216. fec_t *fecp = fep->fec.fecp;
  217. /* if all multi or too many multicasts; just enable all */
  218. if ((dev->flags & IFF_ALLMULTI) != 0 ||
  219. dev->mc_count > FEC_MAX_MULTICAST_ADDRS) {
  220. fep->fec.hthi = 0xffffffffU;
  221. fep->fec.htlo = 0xffffffffU;
  222. }
  223. FC(fecp, r_cntrl, FEC_RCNTRL_PROM);
  224. FW(fecp, hash_table_high, fep->fec.hthi);
  225. FW(fecp, hash_table_low, fep->fec.htlo);
  226. }
  227. static void set_multicast_list(struct net_device *dev)
  228. {
  229. struct dev_mc_list *pmc;
  230. if ((dev->flags & IFF_PROMISC) == 0) {
  231. set_multicast_start(dev);
  232. for (pmc = dev->mc_list; pmc != NULL; pmc = pmc->next)
  233. set_multicast_one(dev, pmc->dmi_addr);
  234. set_multicast_finish(dev);
  235. } else
  236. set_promiscuous_mode(dev);
  237. }
  238. static void restart(struct net_device *dev)
  239. {
  240. #ifdef CONFIG_DUET
  241. immap_t *immap = fs_enet_immap;
  242. u32 cptr;
  243. #endif
  244. struct fs_enet_private *fep = netdev_priv(dev);
  245. fec_t *fecp = fep->fec.fecp;
  246. const struct fs_platform_info *fpi = fep->fpi;
  247. dma_addr_t rx_bd_base_phys, tx_bd_base_phys;
  248. int r;
  249. u32 addrhi, addrlo;
  250. r = whack_reset(fep->fec.fecp);
  251. if (r != 0)
  252. printk(KERN_ERR DRV_MODULE_NAME
  253. ": %s FEC Reset FAILED!\n", dev->name);
  254. /*
  255. * Set station address.
  256. */
  257. addrhi = ((u32) dev->dev_addr[0] << 24) |
  258. ((u32) dev->dev_addr[1] << 16) |
  259. ((u32) dev->dev_addr[2] << 8) |
  260. (u32) dev->dev_addr[3];
  261. addrlo = ((u32) dev->dev_addr[4] << 24) |
  262. ((u32) dev->dev_addr[5] << 16);
  263. FW(fecp, addr_low, addrhi);
  264. FW(fecp, addr_high, addrlo);
  265. /*
  266. * Reset all multicast.
  267. */
  268. FW(fecp, hash_table_high, fep->fec.hthi);
  269. FW(fecp, hash_table_low, fep->fec.htlo);
  270. /*
  271. * Set maximum receive buffer size.
  272. */
  273. FW(fecp, r_buff_size, PKT_MAXBLR_SIZE);
  274. FW(fecp, r_hash, PKT_MAXBUF_SIZE);
  275. /* get physical address */
  276. rx_bd_base_phys = fep->ring_mem_addr;
  277. tx_bd_base_phys = rx_bd_base_phys + sizeof(cbd_t) * fpi->rx_ring;
  278. /*
  279. * Set receive and transmit descriptor base.
  280. */
  281. FW(fecp, r_des_start, rx_bd_base_phys);
  282. FW(fecp, x_des_start, tx_bd_base_phys);
  283. fs_init_bds(dev);
  284. /*
  285. * Enable big endian and don't care about SDMA FC.
  286. */
  287. FW(fecp, fun_code, 0x78000000);
  288. /*
  289. * Set MII speed.
  290. */
  291. FW(fecp, mii_speed, fep->mii_bus->fec.mii_speed);
  292. /*
  293. * Clear any outstanding interrupt.
  294. */
  295. FW(fecp, ievent, 0xffc0);
  296. FW(fecp, ivec, (fep->interrupt / 2) << 29);
  297. /*
  298. * adjust to speed (only for DUET & RMII)
  299. */
  300. #ifdef CONFIG_DUET
  301. if (fpi->use_rmii) {
  302. cptr = in_be32(&immap->im_cpm.cp_cptr);
  303. switch (fs_get_fec_index(fpi->fs_no)) {
  304. case 0:
  305. cptr |= 0x100;
  306. if (fep->speed == 10)
  307. cptr |= 0x0000010;
  308. else if (fep->speed == 100)
  309. cptr &= ~0x0000010;
  310. break;
  311. case 1:
  312. cptr |= 0x80;
  313. if (fep->speed == 10)
  314. cptr |= 0x0000008;
  315. else if (fep->speed == 100)
  316. cptr &= ~0x0000008;
  317. break;
  318. default:
  319. BUG(); /* should never happen */
  320. break;
  321. }
  322. out_be32(&immap->im_cpm.cp_cptr, cptr);
  323. }
  324. #endif
  325. FW(fecp, r_cntrl, FEC_RCNTRL_MII_MODE); /* MII enable */
  326. /*
  327. * adjust to duplex mode
  328. */
  329. if (fep->duplex) {
  330. FC(fecp, r_cntrl, FEC_RCNTRL_DRT);
  331. FS(fecp, x_cntrl, FEC_TCNTRL_FDEN); /* FD enable */
  332. } else {
  333. FS(fecp, r_cntrl, FEC_RCNTRL_DRT);
  334. FC(fecp, x_cntrl, FEC_TCNTRL_FDEN); /* FD disable */
  335. }
  336. /*
  337. * Enable interrupts we wish to service.
  338. */
  339. FW(fecp, imask, FEC_ENET_TXF | FEC_ENET_TXB |
  340. FEC_ENET_RXF | FEC_ENET_RXB);
  341. /*
  342. * And last, enable the transmit and receive processing.
  343. */
  344. FW(fecp, ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN);
  345. FW(fecp, r_des_active, 0x01000000);
  346. }
  347. static void stop(struct net_device *dev)
  348. {
  349. struct fs_enet_private *fep = netdev_priv(dev);
  350. fec_t *fecp = fep->fec.fecp;
  351. struct fs_enet_mii_bus *bus = fep->mii_bus;
  352. const struct fs_mii_bus_info *bi = bus->bus_info;
  353. int i;
  354. if ((FR(fecp, ecntrl) & FEC_ECNTRL_ETHER_EN) == 0)
  355. return; /* already down */
  356. FW(fecp, x_cntrl, 0x01); /* Graceful transmit stop */
  357. for (i = 0; ((FR(fecp, ievent) & 0x10000000) == 0) &&
  358. i < FEC_RESET_DELAY; i++)
  359. udelay(1);
  360. if (i == FEC_RESET_DELAY)
  361. printk(KERN_WARNING DRV_MODULE_NAME
  362. ": %s FEC timeout on graceful transmit stop\n",
  363. dev->name);
  364. /*
  365. * Disable FEC. Let only MII interrupts.
  366. */
  367. FW(fecp, imask, 0);
  368. FC(fecp, ecntrl, FEC_ECNTRL_ETHER_EN);
  369. fs_cleanup_bds(dev);
  370. /* shut down FEC1? that's where the mii bus is */
  371. if (fep->fec.idx == 0 && bus->refs > 1 && bi->method == fsmii_fec) {
  372. FS(fecp, r_cntrl, FEC_RCNTRL_MII_MODE); /* MII enable */
  373. FS(fecp, ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN);
  374. FW(fecp, ievent, FEC_ENET_MII);
  375. FW(fecp, mii_speed, bus->fec.mii_speed);
  376. }
  377. }
  378. static void pre_request_irq(struct net_device *dev, int irq)
  379. {
  380. immap_t *immap = fs_enet_immap;
  381. u32 siel;
  382. /* SIU interrupt */
  383. if (irq >= SIU_IRQ0 && irq < SIU_LEVEL7) {
  384. siel = in_be32(&immap->im_siu_conf.sc_siel);
  385. if ((irq & 1) == 0)
  386. siel |= (0x80000000 >> irq);
  387. else
  388. siel &= ~(0x80000000 >> (irq & ~1));
  389. out_be32(&immap->im_siu_conf.sc_siel, siel);
  390. }
  391. }
  392. static void post_free_irq(struct net_device *dev, int irq)
  393. {
  394. /* nothing */
  395. }
  396. static void napi_clear_rx_event(struct net_device *dev)
  397. {
  398. struct fs_enet_private *fep = netdev_priv(dev);
  399. fec_t *fecp = fep->fec.fecp;
  400. FW(fecp, ievent, FEC_NAPI_RX_EVENT_MSK);
  401. }
  402. static void napi_enable_rx(struct net_device *dev)
  403. {
  404. struct fs_enet_private *fep = netdev_priv(dev);
  405. fec_t *fecp = fep->fec.fecp;
  406. FS(fecp, imask, FEC_NAPI_RX_EVENT_MSK);
  407. }
  408. static void napi_disable_rx(struct net_device *dev)
  409. {
  410. struct fs_enet_private *fep = netdev_priv(dev);
  411. fec_t *fecp = fep->fec.fecp;
  412. FC(fecp, imask, FEC_NAPI_RX_EVENT_MSK);
  413. }
  414. static void rx_bd_done(struct net_device *dev)
  415. {
  416. struct fs_enet_private *fep = netdev_priv(dev);
  417. fec_t *fecp = fep->fec.fecp;
  418. FW(fecp, r_des_active, 0x01000000);
  419. }
  420. static void tx_kickstart(struct net_device *dev)
  421. {
  422. struct fs_enet_private *fep = netdev_priv(dev);
  423. fec_t *fecp = fep->fec.fecp;
  424. FW(fecp, x_des_active, 0x01000000);
  425. }
  426. static u32 get_int_events(struct net_device *dev)
  427. {
  428. struct fs_enet_private *fep = netdev_priv(dev);
  429. fec_t *fecp = fep->fec.fecp;
  430. return FR(fecp, ievent) & FR(fecp, imask);
  431. }
  432. static void clear_int_events(struct net_device *dev, u32 int_events)
  433. {
  434. struct fs_enet_private *fep = netdev_priv(dev);
  435. fec_t *fecp = fep->fec.fecp;
  436. FW(fecp, ievent, int_events);
  437. }
  438. static void ev_error(struct net_device *dev, u32 int_events)
  439. {
  440. printk(KERN_WARNING DRV_MODULE_NAME
  441. ": %s FEC ERROR(s) 0x%x\n", dev->name, int_events);
  442. }
  443. int get_regs(struct net_device *dev, void *p, int *sizep)
  444. {
  445. struct fs_enet_private *fep = netdev_priv(dev);
  446. if (*sizep < sizeof(fec_t))
  447. return -EINVAL;
  448. memcpy_fromio(p, fep->fec.fecp, sizeof(fec_t));
  449. return 0;
  450. }
  451. int get_regs_len(struct net_device *dev)
  452. {
  453. return sizeof(fec_t);
  454. }
  455. void tx_restart(struct net_device *dev)
  456. {
  457. /* nothing */
  458. }
  459. /*************************************************************************/
  460. const struct fs_ops fs_fec_ops = {
  461. .setup_data = setup_data,
  462. .cleanup_data = cleanup_data,
  463. .set_multicast_list = set_multicast_list,
  464. .restart = restart,
  465. .stop = stop,
  466. .pre_request_irq = pre_request_irq,
  467. .post_free_irq = post_free_irq,
  468. .napi_clear_rx_event = napi_clear_rx_event,
  469. .napi_enable_rx = napi_enable_rx,
  470. .napi_disable_rx = napi_disable_rx,
  471. .rx_bd_done = rx_bd_done,
  472. .tx_kickstart = tx_kickstart,
  473. .get_int_events = get_int_events,
  474. .clear_int_events = clear_int_events,
  475. .ev_error = ev_error,
  476. .get_regs = get_regs,
  477. .get_regs_len = get_regs_len,
  478. .tx_restart = tx_restart,
  479. .allocate_bd = allocate_bd,
  480. .free_bd = free_bd,
  481. };
  482. /***********************************************************************/
  483. static int mii_read(struct fs_enet_mii_bus *bus, int phy_id, int location)
  484. {
  485. fec_t *fecp = bus->fec.fecp;
  486. int i, ret = -1;
  487. if ((FR(fecp, r_cntrl) & FEC_RCNTRL_MII_MODE) == 0)
  488. BUG();
  489. /* Add PHY address to register command. */
  490. FW(fecp, mii_data, (phy_id << 23) | mk_mii_read(location));
  491. for (i = 0; i < FEC_MII_LOOPS; i++)
  492. if ((FR(fecp, ievent) & FEC_ENET_MII) != 0)
  493. break;
  494. if (i < FEC_MII_LOOPS) {
  495. FW(fecp, ievent, FEC_ENET_MII);
  496. ret = FR(fecp, mii_data) & 0xffff;
  497. }
  498. return ret;
  499. }
  500. static void mii_write(struct fs_enet_mii_bus *bus, int phy_id, int location, int value)
  501. {
  502. fec_t *fecp = bus->fec.fecp;
  503. int i;
  504. /* this must never happen */
  505. if ((FR(fecp, r_cntrl) & FEC_RCNTRL_MII_MODE) == 0)
  506. BUG();
  507. /* Add PHY address to register command. */
  508. FW(fecp, mii_data, (phy_id << 23) | mk_mii_write(location, value));
  509. for (i = 0; i < FEC_MII_LOOPS; i++)
  510. if ((FR(fecp, ievent) & FEC_ENET_MII) != 0)
  511. break;
  512. if (i < FEC_MII_LOOPS)
  513. FW(fecp, ievent, FEC_ENET_MII);
  514. }
  515. int fs_mii_fec_init(struct fs_enet_mii_bus *bus)
  516. {
  517. bd_t *bd = (bd_t *)__res;
  518. const struct fs_mii_bus_info *bi = bus->bus_info;
  519. fec_t *fecp;
  520. if (bi->id != 0)
  521. return -1;
  522. bus->fec.fecp = &((immap_t *)fs_enet_immap)->im_cpm.cp_fec;
  523. bus->fec.mii_speed = ((((bd->bi_intfreq + 4999999) / 2500000) / 2)
  524. & 0x3F) << 1;
  525. fecp = bus->fec.fecp;
  526. FS(fecp, r_cntrl, FEC_RCNTRL_MII_MODE); /* MII enable */
  527. FS(fecp, ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN);
  528. FW(fecp, ievent, FEC_ENET_MII);
  529. FW(fecp, mii_speed, bus->fec.mii_speed);
  530. bus->mii_read = mii_read;
  531. bus->mii_write = mii_write;
  532. return 0;
  533. }