lpd270.c 11 KB

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  1. /*
  2. * linux/arch/arm/mach-pxa/lpd270.c
  3. *
  4. * Support for the LogicPD PXA270 Card Engine.
  5. * Derived from the mainstone code, which carries these notices:
  6. *
  7. * Author: Nicolas Pitre
  8. * Created: Nov 05, 2002
  9. * Copyright: MontaVista Software Inc.
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License version 2 as
  13. * published by the Free Software Foundation.
  14. */
  15. #include <linux/init.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/sysdev.h>
  18. #include <linux/interrupt.h>
  19. #include <linux/sched.h>
  20. #include <linux/bitops.h>
  21. #include <linux/fb.h>
  22. #include <linux/ioport.h>
  23. #include <linux/mtd/mtd.h>
  24. #include <linux/mtd/partitions.h>
  25. #include <asm/types.h>
  26. #include <asm/setup.h>
  27. #include <asm/memory.h>
  28. #include <asm/mach-types.h>
  29. #include <asm/hardware.h>
  30. #include <asm/irq.h>
  31. #include <asm/sizes.h>
  32. #include <asm/mach/arch.h>
  33. #include <asm/mach/map.h>
  34. #include <asm/mach/irq.h>
  35. #include <asm/mach/flash.h>
  36. #include <asm/arch/pxa-regs.h>
  37. #include <asm/arch/lpd270.h>
  38. #include <asm/arch/audio.h>
  39. #include <asm/arch/pxafb.h>
  40. #include <asm/arch/mmc.h>
  41. #include <asm/arch/irda.h>
  42. #include <asm/arch/ohci.h>
  43. #include "generic.h"
  44. static unsigned int lpd270_irq_enabled;
  45. static void lpd270_mask_irq(unsigned int irq)
  46. {
  47. int lpd270_irq = irq - LPD270_IRQ(0);
  48. __raw_writew(~(1 << lpd270_irq), LPD270_INT_STATUS);
  49. lpd270_irq_enabled &= ~(1 << lpd270_irq);
  50. __raw_writew(lpd270_irq_enabled, LPD270_INT_MASK);
  51. }
  52. static void lpd270_unmask_irq(unsigned int irq)
  53. {
  54. int lpd270_irq = irq - LPD270_IRQ(0);
  55. lpd270_irq_enabled |= 1 << lpd270_irq;
  56. __raw_writew(lpd270_irq_enabled, LPD270_INT_MASK);
  57. }
  58. static struct irqchip lpd270_irq_chip = {
  59. .ack = lpd270_mask_irq,
  60. .mask = lpd270_mask_irq,
  61. .unmask = lpd270_unmask_irq,
  62. };
  63. static void lpd270_irq_handler(unsigned int irq, struct irqdesc *desc,
  64. struct pt_regs *regs)
  65. {
  66. unsigned long pending;
  67. pending = __raw_readw(LPD270_INT_STATUS) & lpd270_irq_enabled;
  68. do {
  69. GEDR(0) = GPIO_bit(0); /* clear useless edge notification */
  70. if (likely(pending)) {
  71. irq = LPD270_IRQ(0) + __ffs(pending);
  72. desc = irq_desc + irq;
  73. desc_handle_irq(irq, desc, regs);
  74. pending = __raw_readw(LPD270_INT_STATUS) &
  75. lpd270_irq_enabled;
  76. }
  77. } while (pending);
  78. }
  79. static void __init lpd270_init_irq(void)
  80. {
  81. int irq;
  82. pxa_init_irq();
  83. __raw_writew(0, LPD270_INT_MASK);
  84. __raw_writew(0, LPD270_INT_STATUS);
  85. /* setup extra LogicPD PXA270 irqs */
  86. for (irq = LPD270_IRQ(2); irq <= LPD270_IRQ(4); irq++) {
  87. set_irq_chip(irq, &lpd270_irq_chip);
  88. set_irq_handler(irq, do_level_IRQ);
  89. set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
  90. }
  91. set_irq_chained_handler(IRQ_GPIO(0), lpd270_irq_handler);
  92. set_irq_type(IRQ_GPIO(0), IRQT_FALLING);
  93. }
  94. #ifdef CONFIG_PM
  95. static int lpd270_irq_resume(struct sys_device *dev)
  96. {
  97. __raw_writew(lpd270_irq_enabled, LPD270_INT_MASK);
  98. return 0;
  99. }
  100. static struct sysdev_class lpd270_irq_sysclass = {
  101. set_kset_name("cpld_irq"),
  102. .resume = lpd270_irq_resume,
  103. };
  104. static struct sys_device lpd270_irq_device = {
  105. .cls = &lpd270_irq_sysclass,
  106. };
  107. static int __init lpd270_irq_device_init(void)
  108. {
  109. int ret = sysdev_class_register(&lpd270_irq_sysclass);
  110. if (ret == 0)
  111. ret = sysdev_register(&lpd270_irq_device);
  112. return ret;
  113. }
  114. device_initcall(lpd270_irq_device_init);
  115. #endif
  116. static struct resource smc91x_resources[] = {
  117. [0] = {
  118. .start = LPD270_ETH_PHYS,
  119. .end = (LPD270_ETH_PHYS + 0xfffff),
  120. .flags = IORESOURCE_MEM,
  121. },
  122. [1] = {
  123. .start = LPD270_ETHERNET_IRQ,
  124. .end = LPD270_ETHERNET_IRQ,
  125. .flags = IORESOURCE_IRQ,
  126. },
  127. };
  128. static struct platform_device smc91x_device = {
  129. .name = "smc91x",
  130. .id = 0,
  131. .num_resources = ARRAY_SIZE(smc91x_resources),
  132. .resource = smc91x_resources,
  133. };
  134. static struct platform_device lpd270_audio_device = {
  135. .name = "pxa2xx-ac97",
  136. .id = -1,
  137. };
  138. static struct resource lpd270_flash_resources[] = {
  139. [0] = {
  140. .start = PXA_CS0_PHYS,
  141. .end = PXA_CS0_PHYS + SZ_64M - 1,
  142. .flags = IORESOURCE_MEM,
  143. },
  144. [1] = {
  145. .start = PXA_CS1_PHYS,
  146. .end = PXA_CS1_PHYS + SZ_64M - 1,
  147. .flags = IORESOURCE_MEM,
  148. },
  149. };
  150. static struct mtd_partition lpd270_flash0_partitions[] = {
  151. {
  152. .name = "Bootloader",
  153. .size = 0x00040000,
  154. .offset = 0,
  155. .mask_flags = MTD_WRITEABLE /* force read-only */
  156. }, {
  157. .name = "Kernel",
  158. .size = 0x00400000,
  159. .offset = 0x00040000,
  160. }, {
  161. .name = "Filesystem",
  162. .size = MTDPART_SIZ_FULL,
  163. .offset = 0x00440000
  164. },
  165. };
  166. static struct flash_platform_data lpd270_flash_data[2] = {
  167. {
  168. .name = "processor-flash",
  169. .map_name = "cfi_probe",
  170. .parts = lpd270_flash0_partitions,
  171. .nr_parts = ARRAY_SIZE(lpd270_flash0_partitions),
  172. }, {
  173. .name = "mainboard-flash",
  174. .map_name = "cfi_probe",
  175. .parts = NULL,
  176. .nr_parts = 0,
  177. }
  178. };
  179. static struct platform_device lpd270_flash_device[2] = {
  180. {
  181. .name = "pxa2xx-flash",
  182. .id = 0,
  183. .dev = {
  184. .platform_data = &lpd270_flash_data[0],
  185. },
  186. .resource = &lpd270_flash_resources[0],
  187. .num_resources = 1,
  188. }, {
  189. .name = "pxa2xx-flash",
  190. .id = 1,
  191. .dev = {
  192. .platform_data = &lpd270_flash_data[1],
  193. },
  194. .resource = &lpd270_flash_resources[1],
  195. .num_resources = 1,
  196. },
  197. };
  198. static void lpd270_backlight_power(int on)
  199. {
  200. if (on) {
  201. pxa_gpio_mode(GPIO16_PWM0_MD);
  202. pxa_set_cken(CKEN0_PWM0, 1);
  203. PWM_CTRL0 = 0;
  204. PWM_PWDUTY0 = 0x3ff;
  205. PWM_PERVAL0 = 0x3ff;
  206. } else {
  207. PWM_CTRL0 = 0;
  208. PWM_PWDUTY0 = 0x0;
  209. PWM_PERVAL0 = 0x3FF;
  210. pxa_set_cken(CKEN0_PWM0, 0);
  211. }
  212. }
  213. /* 5.7" TFT QVGA (LoLo display number 1) */
  214. static struct pxafb_mach_info sharp_lq057q3dc02 __initdata = {
  215. .pixclock = 150000,
  216. .xres = 320,
  217. .yres = 240,
  218. .bpp = 16,
  219. .hsync_len = 0x14,
  220. .left_margin = 0x28,
  221. .right_margin = 0x0a,
  222. .vsync_len = 0x02,
  223. .upper_margin = 0x08,
  224. .lower_margin = 0x14,
  225. .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
  226. .lccr0 = 0x07800080,
  227. .lccr3 = 0x00400000,
  228. .pxafb_backlight_power = lpd270_backlight_power,
  229. };
  230. /* 12.1" TFT SVGA (LoLo display number 2) */
  231. static struct pxafb_mach_info sharp_lq121s1dg31 __initdata = {
  232. .pixclock = 50000,
  233. .xres = 800,
  234. .yres = 600,
  235. .bpp = 16,
  236. .hsync_len = 0x05,
  237. .left_margin = 0x52,
  238. .right_margin = 0x05,
  239. .vsync_len = 0x04,
  240. .upper_margin = 0x14,
  241. .lower_margin = 0x0a,
  242. .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
  243. .lccr0 = 0x07800080,
  244. .lccr3 = 0x00400000,
  245. .pxafb_backlight_power = lpd270_backlight_power,
  246. };
  247. /* 3.6" TFT QVGA (LoLo display number 3) */
  248. static struct pxafb_mach_info sharp_lq036q1da01 __initdata = {
  249. .pixclock = 150000,
  250. .xres = 320,
  251. .yres = 240,
  252. .bpp = 16,
  253. .hsync_len = 0x0e,
  254. .left_margin = 0x04,
  255. .right_margin = 0x0a,
  256. .vsync_len = 0x03,
  257. .upper_margin = 0x03,
  258. .lower_margin = 0x03,
  259. .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
  260. .lccr0 = 0x07800080,
  261. .lccr3 = 0x00400000,
  262. .pxafb_backlight_power = lpd270_backlight_power,
  263. };
  264. /* 6.4" TFT VGA (LoLo display number 5) */
  265. static struct pxafb_mach_info sharp_lq64d343 __initdata = {
  266. .pixclock = 25000,
  267. .xres = 640,
  268. .yres = 480,
  269. .bpp = 16,
  270. .hsync_len = 0x31,
  271. .left_margin = 0x89,
  272. .right_margin = 0x19,
  273. .vsync_len = 0x12,
  274. .upper_margin = 0x22,
  275. .lower_margin = 0x00,
  276. .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
  277. .lccr0 = 0x07800080,
  278. .lccr3 = 0x00400000,
  279. .pxafb_backlight_power = lpd270_backlight_power,
  280. };
  281. /* 10.4" TFT VGA (LoLo display number 7) */
  282. static struct pxafb_mach_info sharp_lq10d368 __initdata = {
  283. .pixclock = 25000,
  284. .xres = 640,
  285. .yres = 480,
  286. .bpp = 16,
  287. .hsync_len = 0x31,
  288. .left_margin = 0x89,
  289. .right_margin = 0x19,
  290. .vsync_len = 0x12,
  291. .upper_margin = 0x22,
  292. .lower_margin = 0x00,
  293. .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
  294. .lccr0 = 0x07800080,
  295. .lccr3 = 0x00400000,
  296. .pxafb_backlight_power = lpd270_backlight_power,
  297. };
  298. /* 3.5" TFT QVGA (LoLo display number 8) */
  299. static struct pxafb_mach_info sharp_lq035q7db02_20 __initdata = {
  300. .pixclock = 150000,
  301. .xres = 240,
  302. .yres = 320,
  303. .bpp = 16,
  304. .hsync_len = 0x0e,
  305. .left_margin = 0x0a,
  306. .right_margin = 0x0a,
  307. .vsync_len = 0x03,
  308. .upper_margin = 0x05,
  309. .lower_margin = 0x14,
  310. .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
  311. .lccr0 = 0x07800080,
  312. .lccr3 = 0x00400000,
  313. .pxafb_backlight_power = lpd270_backlight_power,
  314. };
  315. static struct pxafb_mach_info *lpd270_lcd_to_use;
  316. static int __init lpd270_set_lcd(char *str)
  317. {
  318. if (!strnicmp(str, "lq057q3dc02", 11)) {
  319. lpd270_lcd_to_use = &sharp_lq057q3dc02;
  320. } else if (!strnicmp(str, "lq121s1dg31", 11)) {
  321. lpd270_lcd_to_use = &sharp_lq121s1dg31;
  322. } else if (!strnicmp(str, "lq036q1da01", 11)) {
  323. lpd270_lcd_to_use = &sharp_lq036q1da01;
  324. } else if (!strnicmp(str, "lq64d343", 8)) {
  325. lpd270_lcd_to_use = &sharp_lq64d343;
  326. } else if (!strnicmp(str, "lq10d368", 8)) {
  327. lpd270_lcd_to_use = &sharp_lq10d368;
  328. } else if (!strnicmp(str, "lq035q7db02-20", 14)) {
  329. lpd270_lcd_to_use = &sharp_lq035q7db02_20;
  330. } else {
  331. printk(KERN_INFO "lpd270: unknown lcd panel [%s]\n", str);
  332. }
  333. return 1;
  334. }
  335. __setup("lcd=", lpd270_set_lcd);
  336. static struct platform_device *platform_devices[] __initdata = {
  337. &smc91x_device,
  338. &lpd270_audio_device,
  339. &lpd270_flash_device[0],
  340. &lpd270_flash_device[1],
  341. };
  342. static int lpd270_ohci_init(struct device *dev)
  343. {
  344. /* setup Port1 GPIO pin. */
  345. pxa_gpio_mode(88 | GPIO_ALT_FN_1_IN); /* USBHPWR1 */
  346. pxa_gpio_mode(89 | GPIO_ALT_FN_2_OUT); /* USBHPEN1 */
  347. /* Set the Power Control Polarity Low and Power Sense
  348. Polarity Low to active low. */
  349. UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
  350. ~(UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSEP3 | UHCHR_SSE);
  351. return 0;
  352. }
  353. static struct pxaohci_platform_data lpd270_ohci_platform_data = {
  354. .port_mode = PMM_PERPORT_MODE,
  355. .init = lpd270_ohci_init,
  356. };
  357. static void __init lpd270_init(void)
  358. {
  359. lpd270_flash_data[0].width = (BOOT_DEF & 1) ? 2 : 4;
  360. lpd270_flash_data[1].width = 4;
  361. /*
  362. * System bus arbiter setting:
  363. * - Core_Park
  364. * - LCD_wt:DMA_wt:CORE_Wt = 2:3:4
  365. */
  366. ARB_CNTRL = ARB_CORE_PARK | 0x234;
  367. /*
  368. * On LogicPD PXA270, we route AC97_SYSCLK via GPIO45.
  369. */
  370. pxa_gpio_mode(GPIO45_SYSCLK_AC97_MD);
  371. platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
  372. if (lpd270_lcd_to_use != NULL)
  373. set_pxa_fb_info(lpd270_lcd_to_use);
  374. pxa_set_ohci_info(&lpd270_ohci_platform_data);
  375. }
  376. static struct map_desc lpd270_io_desc[] __initdata = {
  377. {
  378. .virtual = LPD270_CPLD_VIRT,
  379. .pfn = __phys_to_pfn(LPD270_CPLD_PHYS),
  380. .length = LPD270_CPLD_SIZE,
  381. .type = MT_DEVICE,
  382. },
  383. };
  384. static void __init lpd270_map_io(void)
  385. {
  386. pxa_map_io();
  387. iotable_init(lpd270_io_desc, ARRAY_SIZE(lpd270_io_desc));
  388. /* initialize sleep mode regs (wake-up sources, etc) */
  389. PGSR0 = 0x00008800;
  390. PGSR1 = 0x00000002;
  391. PGSR2 = 0x0001FC00;
  392. PGSR3 = 0x00001F81;
  393. PWER = 0xC0000002;
  394. PRER = 0x00000002;
  395. PFER = 0x00000002;
  396. /* for use I SRAM as framebuffer. */
  397. PSLR |= 0x00000F04;
  398. PCFR = 0x00000066;
  399. }
  400. MACHINE_START(LOGICPD_PXA270, "LogicPD PXA270 Card Engine")
  401. /* Maintainer: Peter Barada */
  402. .phys_io = 0x40000000,
  403. .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
  404. .boot_params = 0xa0000100,
  405. .map_io = lpd270_map_io,
  406. .init_irq = lpd270_init_irq,
  407. .timer = &pxa_timer,
  408. .init_machine = lpd270_init,
  409. MACHINE_END