i915_debugfs.c 33 KB

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  1. /*
  2. * Copyright © 2008 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21. * IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Eric Anholt <eric@anholt.net>
  25. * Keith Packard <keithp@keithp.com>
  26. *
  27. */
  28. #include <linux/seq_file.h>
  29. #include <linux/debugfs.h>
  30. #include <linux/slab.h>
  31. #include "drmP.h"
  32. #include "drm.h"
  33. #include "intel_drv.h"
  34. #include "intel_ringbuffer.h"
  35. #include "i915_drm.h"
  36. #include "i915_drv.h"
  37. #define DRM_I915_RING_DEBUG 1
  38. #if defined(CONFIG_DEBUG_FS)
  39. enum {
  40. ACTIVE_LIST,
  41. FLUSHING_LIST,
  42. INACTIVE_LIST,
  43. PINNED_LIST,
  44. DEFERRED_FREE_LIST,
  45. };
  46. static const char *yesno(int v)
  47. {
  48. return v ? "yes" : "no";
  49. }
  50. static int i915_capabilities(struct seq_file *m, void *data)
  51. {
  52. struct drm_info_node *node = (struct drm_info_node *) m->private;
  53. struct drm_device *dev = node->minor->dev;
  54. const struct intel_device_info *info = INTEL_INFO(dev);
  55. seq_printf(m, "gen: %d\n", info->gen);
  56. #define B(x) seq_printf(m, #x ": %s\n", yesno(info->x))
  57. B(is_mobile);
  58. B(is_i85x);
  59. B(is_i915g);
  60. B(is_i945gm);
  61. B(is_g33);
  62. B(need_gfx_hws);
  63. B(is_g4x);
  64. B(is_pineview);
  65. B(is_broadwater);
  66. B(is_crestline);
  67. B(has_fbc);
  68. B(has_rc6);
  69. B(has_pipe_cxsr);
  70. B(has_hotplug);
  71. B(cursor_needs_physical);
  72. B(has_overlay);
  73. B(overlay_needs_physical);
  74. B(supports_tv);
  75. B(has_bsd_ring);
  76. B(has_blt_ring);
  77. #undef B
  78. return 0;
  79. }
  80. static const char *get_pin_flag(struct drm_i915_gem_object *obj_priv)
  81. {
  82. if (obj_priv->user_pin_count > 0)
  83. return "P";
  84. else if (obj_priv->pin_count > 0)
  85. return "p";
  86. else
  87. return " ";
  88. }
  89. static const char *get_tiling_flag(struct drm_i915_gem_object *obj_priv)
  90. {
  91. switch (obj_priv->tiling_mode) {
  92. default:
  93. case I915_TILING_NONE: return " ";
  94. case I915_TILING_X: return "X";
  95. case I915_TILING_Y: return "Y";
  96. }
  97. }
  98. static void
  99. describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
  100. {
  101. seq_printf(m, "%p: %s%s %8zd %08x %08x %d%s%s",
  102. &obj->base,
  103. get_pin_flag(obj),
  104. get_tiling_flag(obj),
  105. obj->base.size,
  106. obj->base.read_domains,
  107. obj->base.write_domain,
  108. obj->last_rendering_seqno,
  109. obj->dirty ? " dirty" : "",
  110. obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
  111. if (obj->base.name)
  112. seq_printf(m, " (name: %d)", obj->base.name);
  113. if (obj->fence_reg != I915_FENCE_REG_NONE)
  114. seq_printf(m, " (fence: %d)", obj->fence_reg);
  115. if (obj->gtt_space != NULL)
  116. seq_printf(m, " (gtt offset: %08x, size: %08x)",
  117. obj->gtt_offset, (unsigned int)obj->gtt_space->size);
  118. if (obj->pin_mappable || obj->fault_mappable)
  119. seq_printf(m, " (mappable)");
  120. if (obj->ring != NULL)
  121. seq_printf(m, " (%s)", obj->ring->name);
  122. }
  123. static int i915_gem_object_list_info(struct seq_file *m, void *data)
  124. {
  125. struct drm_info_node *node = (struct drm_info_node *) m->private;
  126. uintptr_t list = (uintptr_t) node->info_ent->data;
  127. struct list_head *head;
  128. struct drm_device *dev = node->minor->dev;
  129. drm_i915_private_t *dev_priv = dev->dev_private;
  130. struct drm_i915_gem_object *obj_priv;
  131. size_t total_obj_size, total_gtt_size;
  132. int count, ret;
  133. ret = mutex_lock_interruptible(&dev->struct_mutex);
  134. if (ret)
  135. return ret;
  136. switch (list) {
  137. case ACTIVE_LIST:
  138. seq_printf(m, "Active:\n");
  139. head = &dev_priv->mm.active_list;
  140. break;
  141. case INACTIVE_LIST:
  142. seq_printf(m, "Inactive:\n");
  143. head = &dev_priv->mm.inactive_list;
  144. break;
  145. case PINNED_LIST:
  146. seq_printf(m, "Pinned:\n");
  147. head = &dev_priv->mm.pinned_list;
  148. break;
  149. case FLUSHING_LIST:
  150. seq_printf(m, "Flushing:\n");
  151. head = &dev_priv->mm.flushing_list;
  152. break;
  153. case DEFERRED_FREE_LIST:
  154. seq_printf(m, "Deferred free:\n");
  155. head = &dev_priv->mm.deferred_free_list;
  156. break;
  157. default:
  158. mutex_unlock(&dev->struct_mutex);
  159. return -EINVAL;
  160. }
  161. total_obj_size = total_gtt_size = count = 0;
  162. list_for_each_entry(obj_priv, head, mm_list) {
  163. seq_printf(m, " ");
  164. describe_obj(m, obj_priv);
  165. seq_printf(m, "\n");
  166. total_obj_size += obj_priv->base.size;
  167. total_gtt_size += obj_priv->gtt_space->size;
  168. count++;
  169. }
  170. mutex_unlock(&dev->struct_mutex);
  171. seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
  172. count, total_obj_size, total_gtt_size);
  173. return 0;
  174. }
  175. static int i915_gem_object_info(struct seq_file *m, void* data)
  176. {
  177. struct drm_info_node *node = (struct drm_info_node *) m->private;
  178. struct drm_device *dev = node->minor->dev;
  179. struct drm_i915_private *dev_priv = dev->dev_private;
  180. int ret;
  181. ret = mutex_lock_interruptible(&dev->struct_mutex);
  182. if (ret)
  183. return ret;
  184. seq_printf(m, "%u objects\n", dev_priv->mm.object_count);
  185. seq_printf(m, "%zu object bytes\n", dev_priv->mm.object_memory);
  186. seq_printf(m, "%u pinned\n", dev_priv->mm.pin_count);
  187. seq_printf(m, "%zu pin bytes\n", dev_priv->mm.pin_memory);
  188. seq_printf(m, "%u mappable objects in gtt\n", dev_priv->mm.gtt_mappable_count);
  189. seq_printf(m, "%zu mappable gtt bytes\n", dev_priv->mm.gtt_mappable_memory);
  190. seq_printf(m, "%zu mappable gtt used bytes\n", dev_priv->mm.mappable_gtt_used);
  191. seq_printf(m, "%zu mappable gtt total\n", dev_priv->mm.mappable_gtt_total);
  192. seq_printf(m, "%u objects in gtt\n", dev_priv->mm.gtt_count);
  193. seq_printf(m, "%zu gtt bytes\n", dev_priv->mm.gtt_memory);
  194. seq_printf(m, "%zu gtt total\n", dev_priv->mm.gtt_total);
  195. mutex_unlock(&dev->struct_mutex);
  196. return 0;
  197. }
  198. static int i915_gem_pageflip_info(struct seq_file *m, void *data)
  199. {
  200. struct drm_info_node *node = (struct drm_info_node *) m->private;
  201. struct drm_device *dev = node->minor->dev;
  202. unsigned long flags;
  203. struct intel_crtc *crtc;
  204. list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
  205. const char *pipe = crtc->pipe ? "B" : "A";
  206. const char *plane = crtc->plane ? "B" : "A";
  207. struct intel_unpin_work *work;
  208. spin_lock_irqsave(&dev->event_lock, flags);
  209. work = crtc->unpin_work;
  210. if (work == NULL) {
  211. seq_printf(m, "No flip due on pipe %s (plane %s)\n",
  212. pipe, plane);
  213. } else {
  214. if (!work->pending) {
  215. seq_printf(m, "Flip queued on pipe %s (plane %s)\n",
  216. pipe, plane);
  217. } else {
  218. seq_printf(m, "Flip pending (waiting for vsync) on pipe %s (plane %s)\n",
  219. pipe, plane);
  220. }
  221. if (work->enable_stall_check)
  222. seq_printf(m, "Stall check enabled, ");
  223. else
  224. seq_printf(m, "Stall check waiting for page flip ioctl, ");
  225. seq_printf(m, "%d prepares\n", work->pending);
  226. if (work->old_fb_obj) {
  227. struct drm_i915_gem_object *obj_priv = to_intel_bo(work->old_fb_obj);
  228. if(obj_priv)
  229. seq_printf(m, "Old framebuffer gtt_offset 0x%08x\n", obj_priv->gtt_offset );
  230. }
  231. if (work->pending_flip_obj) {
  232. struct drm_i915_gem_object *obj_priv = to_intel_bo(work->pending_flip_obj);
  233. if(obj_priv)
  234. seq_printf(m, "New framebuffer gtt_offset 0x%08x\n", obj_priv->gtt_offset );
  235. }
  236. }
  237. spin_unlock_irqrestore(&dev->event_lock, flags);
  238. }
  239. return 0;
  240. }
  241. static int i915_gem_request_info(struct seq_file *m, void *data)
  242. {
  243. struct drm_info_node *node = (struct drm_info_node *) m->private;
  244. struct drm_device *dev = node->minor->dev;
  245. drm_i915_private_t *dev_priv = dev->dev_private;
  246. struct drm_i915_gem_request *gem_request;
  247. int ret, count;
  248. ret = mutex_lock_interruptible(&dev->struct_mutex);
  249. if (ret)
  250. return ret;
  251. count = 0;
  252. if (!list_empty(&dev_priv->render_ring.request_list)) {
  253. seq_printf(m, "Render requests:\n");
  254. list_for_each_entry(gem_request,
  255. &dev_priv->render_ring.request_list,
  256. list) {
  257. seq_printf(m, " %d @ %d\n",
  258. gem_request->seqno,
  259. (int) (jiffies - gem_request->emitted_jiffies));
  260. }
  261. count++;
  262. }
  263. if (!list_empty(&dev_priv->bsd_ring.request_list)) {
  264. seq_printf(m, "BSD requests:\n");
  265. list_for_each_entry(gem_request,
  266. &dev_priv->bsd_ring.request_list,
  267. list) {
  268. seq_printf(m, " %d @ %d\n",
  269. gem_request->seqno,
  270. (int) (jiffies - gem_request->emitted_jiffies));
  271. }
  272. count++;
  273. }
  274. if (!list_empty(&dev_priv->blt_ring.request_list)) {
  275. seq_printf(m, "BLT requests:\n");
  276. list_for_each_entry(gem_request,
  277. &dev_priv->blt_ring.request_list,
  278. list) {
  279. seq_printf(m, " %d @ %d\n",
  280. gem_request->seqno,
  281. (int) (jiffies - gem_request->emitted_jiffies));
  282. }
  283. count++;
  284. }
  285. mutex_unlock(&dev->struct_mutex);
  286. if (count == 0)
  287. seq_printf(m, "No requests\n");
  288. return 0;
  289. }
  290. static void i915_ring_seqno_info(struct seq_file *m,
  291. struct intel_ring_buffer *ring)
  292. {
  293. if (ring->get_seqno) {
  294. seq_printf(m, "Current sequence (%s): %d\n",
  295. ring->name, ring->get_seqno(ring));
  296. seq_printf(m, "Waiter sequence (%s): %d\n",
  297. ring->name, ring->waiting_seqno);
  298. seq_printf(m, "IRQ sequence (%s): %d\n",
  299. ring->name, ring->irq_seqno);
  300. }
  301. }
  302. static int i915_gem_seqno_info(struct seq_file *m, void *data)
  303. {
  304. struct drm_info_node *node = (struct drm_info_node *) m->private;
  305. struct drm_device *dev = node->minor->dev;
  306. drm_i915_private_t *dev_priv = dev->dev_private;
  307. int ret;
  308. ret = mutex_lock_interruptible(&dev->struct_mutex);
  309. if (ret)
  310. return ret;
  311. i915_ring_seqno_info(m, &dev_priv->render_ring);
  312. i915_ring_seqno_info(m, &dev_priv->bsd_ring);
  313. i915_ring_seqno_info(m, &dev_priv->blt_ring);
  314. mutex_unlock(&dev->struct_mutex);
  315. return 0;
  316. }
  317. static int i915_interrupt_info(struct seq_file *m, void *data)
  318. {
  319. struct drm_info_node *node = (struct drm_info_node *) m->private;
  320. struct drm_device *dev = node->minor->dev;
  321. drm_i915_private_t *dev_priv = dev->dev_private;
  322. int ret;
  323. ret = mutex_lock_interruptible(&dev->struct_mutex);
  324. if (ret)
  325. return ret;
  326. if (!HAS_PCH_SPLIT(dev)) {
  327. seq_printf(m, "Interrupt enable: %08x\n",
  328. I915_READ(IER));
  329. seq_printf(m, "Interrupt identity: %08x\n",
  330. I915_READ(IIR));
  331. seq_printf(m, "Interrupt mask: %08x\n",
  332. I915_READ(IMR));
  333. seq_printf(m, "Pipe A stat: %08x\n",
  334. I915_READ(PIPEASTAT));
  335. seq_printf(m, "Pipe B stat: %08x\n",
  336. I915_READ(PIPEBSTAT));
  337. } else {
  338. seq_printf(m, "North Display Interrupt enable: %08x\n",
  339. I915_READ(DEIER));
  340. seq_printf(m, "North Display Interrupt identity: %08x\n",
  341. I915_READ(DEIIR));
  342. seq_printf(m, "North Display Interrupt mask: %08x\n",
  343. I915_READ(DEIMR));
  344. seq_printf(m, "South Display Interrupt enable: %08x\n",
  345. I915_READ(SDEIER));
  346. seq_printf(m, "South Display Interrupt identity: %08x\n",
  347. I915_READ(SDEIIR));
  348. seq_printf(m, "South Display Interrupt mask: %08x\n",
  349. I915_READ(SDEIMR));
  350. seq_printf(m, "Graphics Interrupt enable: %08x\n",
  351. I915_READ(GTIER));
  352. seq_printf(m, "Graphics Interrupt identity: %08x\n",
  353. I915_READ(GTIIR));
  354. seq_printf(m, "Graphics Interrupt mask: %08x\n",
  355. I915_READ(GTIMR));
  356. }
  357. seq_printf(m, "Interrupts received: %d\n",
  358. atomic_read(&dev_priv->irq_received));
  359. i915_ring_seqno_info(m, &dev_priv->render_ring);
  360. i915_ring_seqno_info(m, &dev_priv->bsd_ring);
  361. i915_ring_seqno_info(m, &dev_priv->blt_ring);
  362. mutex_unlock(&dev->struct_mutex);
  363. return 0;
  364. }
  365. static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
  366. {
  367. struct drm_info_node *node = (struct drm_info_node *) m->private;
  368. struct drm_device *dev = node->minor->dev;
  369. drm_i915_private_t *dev_priv = dev->dev_private;
  370. int i, ret;
  371. ret = mutex_lock_interruptible(&dev->struct_mutex);
  372. if (ret)
  373. return ret;
  374. seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
  375. seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
  376. for (i = 0; i < dev_priv->num_fence_regs; i++) {
  377. struct drm_gem_object *obj = dev_priv->fence_regs[i].obj;
  378. seq_printf(m, "Fenced object[%2d] = ", i);
  379. if (obj == NULL)
  380. seq_printf(m, "unused");
  381. else
  382. describe_obj(m, to_intel_bo(obj));
  383. seq_printf(m, "\n");
  384. }
  385. mutex_unlock(&dev->struct_mutex);
  386. return 0;
  387. }
  388. static int i915_hws_info(struct seq_file *m, void *data)
  389. {
  390. struct drm_info_node *node = (struct drm_info_node *) m->private;
  391. struct drm_device *dev = node->minor->dev;
  392. drm_i915_private_t *dev_priv = dev->dev_private;
  393. struct intel_ring_buffer *ring;
  394. volatile u32 *hws;
  395. int i;
  396. switch ((uintptr_t)node->info_ent->data) {
  397. case RING_RENDER: ring = &dev_priv->render_ring; break;
  398. case RING_BSD: ring = &dev_priv->bsd_ring; break;
  399. case RING_BLT: ring = &dev_priv->blt_ring; break;
  400. default: return -EINVAL;
  401. }
  402. hws = (volatile u32 *)ring->status_page.page_addr;
  403. if (hws == NULL)
  404. return 0;
  405. for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
  406. seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
  407. i * 4,
  408. hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
  409. }
  410. return 0;
  411. }
  412. static void i915_dump_object(struct seq_file *m,
  413. struct io_mapping *mapping,
  414. struct drm_i915_gem_object *obj_priv)
  415. {
  416. int page, page_count, i;
  417. page_count = obj_priv->base.size / PAGE_SIZE;
  418. for (page = 0; page < page_count; page++) {
  419. u32 *mem = io_mapping_map_wc(mapping,
  420. obj_priv->gtt_offset + page * PAGE_SIZE);
  421. for (i = 0; i < PAGE_SIZE; i += 4)
  422. seq_printf(m, "%08x : %08x\n", i, mem[i / 4]);
  423. io_mapping_unmap(mem);
  424. }
  425. }
  426. static int i915_batchbuffer_info(struct seq_file *m, void *data)
  427. {
  428. struct drm_info_node *node = (struct drm_info_node *) m->private;
  429. struct drm_device *dev = node->minor->dev;
  430. drm_i915_private_t *dev_priv = dev->dev_private;
  431. struct drm_gem_object *obj;
  432. struct drm_i915_gem_object *obj_priv;
  433. int ret;
  434. ret = mutex_lock_interruptible(&dev->struct_mutex);
  435. if (ret)
  436. return ret;
  437. list_for_each_entry(obj_priv, &dev_priv->mm.active_list, mm_list) {
  438. obj = &obj_priv->base;
  439. if (obj->read_domains & I915_GEM_DOMAIN_COMMAND) {
  440. seq_printf(m, "--- gtt_offset = 0x%08x\n",
  441. obj_priv->gtt_offset);
  442. i915_dump_object(m, dev_priv->mm.gtt_mapping, obj_priv);
  443. }
  444. }
  445. mutex_unlock(&dev->struct_mutex);
  446. return 0;
  447. }
  448. static int i915_ringbuffer_data(struct seq_file *m, void *data)
  449. {
  450. struct drm_info_node *node = (struct drm_info_node *) m->private;
  451. struct drm_device *dev = node->minor->dev;
  452. drm_i915_private_t *dev_priv = dev->dev_private;
  453. struct intel_ring_buffer *ring;
  454. int ret;
  455. switch ((uintptr_t)node->info_ent->data) {
  456. case RING_RENDER: ring = &dev_priv->render_ring; break;
  457. case RING_BSD: ring = &dev_priv->bsd_ring; break;
  458. case RING_BLT: ring = &dev_priv->blt_ring; break;
  459. default: return -EINVAL;
  460. }
  461. ret = mutex_lock_interruptible(&dev->struct_mutex);
  462. if (ret)
  463. return ret;
  464. if (!ring->gem_object) {
  465. seq_printf(m, "No ringbuffer setup\n");
  466. } else {
  467. u8 *virt = ring->virtual_start;
  468. uint32_t off;
  469. for (off = 0; off < ring->size; off += 4) {
  470. uint32_t *ptr = (uint32_t *)(virt + off);
  471. seq_printf(m, "%08x : %08x\n", off, *ptr);
  472. }
  473. }
  474. mutex_unlock(&dev->struct_mutex);
  475. return 0;
  476. }
  477. static int i915_ringbuffer_info(struct seq_file *m, void *data)
  478. {
  479. struct drm_info_node *node = (struct drm_info_node *) m->private;
  480. struct drm_device *dev = node->minor->dev;
  481. drm_i915_private_t *dev_priv = dev->dev_private;
  482. struct intel_ring_buffer *ring;
  483. switch ((uintptr_t)node->info_ent->data) {
  484. case RING_RENDER: ring = &dev_priv->render_ring; break;
  485. case RING_BSD: ring = &dev_priv->bsd_ring; break;
  486. case RING_BLT: ring = &dev_priv->blt_ring; break;
  487. default: return -EINVAL;
  488. }
  489. if (ring->size == 0)
  490. return 0;
  491. seq_printf(m, "Ring %s:\n", ring->name);
  492. seq_printf(m, " Head : %08x\n", I915_READ_HEAD(ring) & HEAD_ADDR);
  493. seq_printf(m, " Tail : %08x\n", I915_READ_TAIL(ring) & TAIL_ADDR);
  494. seq_printf(m, " Size : %08x\n", ring->size);
  495. seq_printf(m, " Active : %08x\n", intel_ring_get_active_head(ring));
  496. seq_printf(m, " Control : %08x\n", I915_READ_CTL(ring));
  497. seq_printf(m, " Start : %08x\n", I915_READ_START(ring));
  498. return 0;
  499. }
  500. static const char *ring_str(int ring)
  501. {
  502. switch (ring) {
  503. case RING_RENDER: return "render";
  504. case RING_BSD: return "bsd";
  505. case RING_BLT: return "blt";
  506. default: return "";
  507. }
  508. }
  509. static const char *pin_flag(int pinned)
  510. {
  511. if (pinned > 0)
  512. return " P";
  513. else if (pinned < 0)
  514. return " p";
  515. else
  516. return "";
  517. }
  518. static const char *tiling_flag(int tiling)
  519. {
  520. switch (tiling) {
  521. default:
  522. case I915_TILING_NONE: return "";
  523. case I915_TILING_X: return " X";
  524. case I915_TILING_Y: return " Y";
  525. }
  526. }
  527. static const char *dirty_flag(int dirty)
  528. {
  529. return dirty ? " dirty" : "";
  530. }
  531. static const char *purgeable_flag(int purgeable)
  532. {
  533. return purgeable ? " purgeable" : "";
  534. }
  535. static void print_error_buffers(struct seq_file *m,
  536. const char *name,
  537. struct drm_i915_error_buffer *err,
  538. int count)
  539. {
  540. seq_printf(m, "%s [%d]:\n", name, count);
  541. while (count--) {
  542. seq_printf(m, " %08x %8zd %04x %04x %08x%s%s%s%s%s",
  543. err->gtt_offset,
  544. err->size,
  545. err->read_domains,
  546. err->write_domain,
  547. err->seqno,
  548. pin_flag(err->pinned),
  549. tiling_flag(err->tiling),
  550. dirty_flag(err->dirty),
  551. purgeable_flag(err->purgeable),
  552. ring_str(err->ring));
  553. if (err->name)
  554. seq_printf(m, " (name: %d)", err->name);
  555. if (err->fence_reg != I915_FENCE_REG_NONE)
  556. seq_printf(m, " (fence: %d)", err->fence_reg);
  557. seq_printf(m, "\n");
  558. err++;
  559. }
  560. }
  561. static int i915_error_state(struct seq_file *m, void *unused)
  562. {
  563. struct drm_info_node *node = (struct drm_info_node *) m->private;
  564. struct drm_device *dev = node->minor->dev;
  565. drm_i915_private_t *dev_priv = dev->dev_private;
  566. struct drm_i915_error_state *error;
  567. unsigned long flags;
  568. int i, page, offset, elt;
  569. spin_lock_irqsave(&dev_priv->error_lock, flags);
  570. if (!dev_priv->first_error) {
  571. seq_printf(m, "no error state collected\n");
  572. goto out;
  573. }
  574. error = dev_priv->first_error;
  575. seq_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,
  576. error->time.tv_usec);
  577. seq_printf(m, "PCI ID: 0x%04x\n", dev->pci_device);
  578. seq_printf(m, "EIR: 0x%08x\n", error->eir);
  579. seq_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
  580. if (INTEL_INFO(dev)->gen >= 6) {
  581. seq_printf(m, "ERROR: 0x%08x\n", error->error);
  582. seq_printf(m, "Blitter command stream:\n");
  583. seq_printf(m, " ACTHD: 0x%08x\n", error->bcs_acthd);
  584. seq_printf(m, " IPEIR: 0x%08x\n", error->bcs_ipeir);
  585. seq_printf(m, " IPEHR: 0x%08x\n", error->bcs_ipehr);
  586. seq_printf(m, " INSTDONE: 0x%08x\n", error->bcs_instdone);
  587. seq_printf(m, " seqno: 0x%08x\n", error->bcs_seqno);
  588. seq_printf(m, "Video (BSD) command stream:\n");
  589. seq_printf(m, " ACTHD: 0x%08x\n", error->vcs_acthd);
  590. seq_printf(m, " IPEIR: 0x%08x\n", error->vcs_ipeir);
  591. seq_printf(m, " IPEHR: 0x%08x\n", error->vcs_ipehr);
  592. seq_printf(m, " INSTDONE: 0x%08x\n", error->vcs_instdone);
  593. seq_printf(m, " seqno: 0x%08x\n", error->vcs_seqno);
  594. }
  595. seq_printf(m, "Render command stream:\n");
  596. seq_printf(m, " ACTHD: 0x%08x\n", error->acthd);
  597. seq_printf(m, " IPEIR: 0x%08x\n", error->ipeir);
  598. seq_printf(m, " IPEHR: 0x%08x\n", error->ipehr);
  599. seq_printf(m, " INSTDONE: 0x%08x\n", error->instdone);
  600. if (INTEL_INFO(dev)->gen >= 4) {
  601. seq_printf(m, " INSTDONE1: 0x%08x\n", error->instdone1);
  602. seq_printf(m, " INSTPS: 0x%08x\n", error->instps);
  603. }
  604. seq_printf(m, " INSTPM: 0x%08x\n", error->instpm);
  605. seq_printf(m, " seqno: 0x%08x\n", error->seqno);
  606. if (error->active_bo)
  607. print_error_buffers(m, "Active",
  608. error->active_bo,
  609. error->active_bo_count);
  610. if (error->pinned_bo)
  611. print_error_buffers(m, "Pinned",
  612. error->pinned_bo,
  613. error->pinned_bo_count);
  614. for (i = 0; i < ARRAY_SIZE(error->batchbuffer); i++) {
  615. if (error->batchbuffer[i]) {
  616. struct drm_i915_error_object *obj = error->batchbuffer[i];
  617. seq_printf(m, "--- gtt_offset = 0x%08x\n", obj->gtt_offset);
  618. offset = 0;
  619. for (page = 0; page < obj->page_count; page++) {
  620. for (elt = 0; elt < PAGE_SIZE/4; elt++) {
  621. seq_printf(m, "%08x : %08x\n", offset, obj->pages[page][elt]);
  622. offset += 4;
  623. }
  624. }
  625. }
  626. }
  627. if (error->ringbuffer) {
  628. struct drm_i915_error_object *obj = error->ringbuffer;
  629. seq_printf(m, "--- ringbuffer = 0x%08x\n", obj->gtt_offset);
  630. offset = 0;
  631. for (page = 0; page < obj->page_count; page++) {
  632. for (elt = 0; elt < PAGE_SIZE/4; elt++) {
  633. seq_printf(m, "%08x : %08x\n", offset, obj->pages[page][elt]);
  634. offset += 4;
  635. }
  636. }
  637. }
  638. if (error->overlay)
  639. intel_overlay_print_error_state(m, error->overlay);
  640. if (error->display)
  641. intel_display_print_error_state(m, dev, error->display);
  642. out:
  643. spin_unlock_irqrestore(&dev_priv->error_lock, flags);
  644. return 0;
  645. }
  646. static int i915_rstdby_delays(struct seq_file *m, void *unused)
  647. {
  648. struct drm_info_node *node = (struct drm_info_node *) m->private;
  649. struct drm_device *dev = node->minor->dev;
  650. drm_i915_private_t *dev_priv = dev->dev_private;
  651. u16 crstanddelay = I915_READ16(CRSTANDVID);
  652. seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f));
  653. return 0;
  654. }
  655. static int i915_cur_delayinfo(struct seq_file *m, void *unused)
  656. {
  657. struct drm_info_node *node = (struct drm_info_node *) m->private;
  658. struct drm_device *dev = node->minor->dev;
  659. drm_i915_private_t *dev_priv = dev->dev_private;
  660. u16 rgvswctl = I915_READ16(MEMSWCTL);
  661. u16 rgvstat = I915_READ16(MEMSTAT_ILK);
  662. seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
  663. seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
  664. seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
  665. MEMSTAT_VID_SHIFT);
  666. seq_printf(m, "Current P-state: %d\n",
  667. (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
  668. return 0;
  669. }
  670. static int i915_delayfreq_table(struct seq_file *m, void *unused)
  671. {
  672. struct drm_info_node *node = (struct drm_info_node *) m->private;
  673. struct drm_device *dev = node->minor->dev;
  674. drm_i915_private_t *dev_priv = dev->dev_private;
  675. u32 delayfreq;
  676. int i;
  677. for (i = 0; i < 16; i++) {
  678. delayfreq = I915_READ(PXVFREQ_BASE + i * 4);
  679. seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq,
  680. (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT);
  681. }
  682. return 0;
  683. }
  684. static inline int MAP_TO_MV(int map)
  685. {
  686. return 1250 - (map * 25);
  687. }
  688. static int i915_inttoext_table(struct seq_file *m, void *unused)
  689. {
  690. struct drm_info_node *node = (struct drm_info_node *) m->private;
  691. struct drm_device *dev = node->minor->dev;
  692. drm_i915_private_t *dev_priv = dev->dev_private;
  693. u32 inttoext;
  694. int i;
  695. for (i = 1; i <= 32; i++) {
  696. inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4);
  697. seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext);
  698. }
  699. return 0;
  700. }
  701. static int i915_drpc_info(struct seq_file *m, void *unused)
  702. {
  703. struct drm_info_node *node = (struct drm_info_node *) m->private;
  704. struct drm_device *dev = node->minor->dev;
  705. drm_i915_private_t *dev_priv = dev->dev_private;
  706. u32 rgvmodectl = I915_READ(MEMMODECTL);
  707. u32 rstdbyctl = I915_READ(MCHBAR_RENDER_STANDBY);
  708. u16 crstandvid = I915_READ16(CRSTANDVID);
  709. seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
  710. "yes" : "no");
  711. seq_printf(m, "Boost freq: %d\n",
  712. (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
  713. MEMMODE_BOOST_FREQ_SHIFT);
  714. seq_printf(m, "HW control enabled: %s\n",
  715. rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
  716. seq_printf(m, "SW control enabled: %s\n",
  717. rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
  718. seq_printf(m, "Gated voltage change: %s\n",
  719. rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
  720. seq_printf(m, "Starting frequency: P%d\n",
  721. (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
  722. seq_printf(m, "Max P-state: P%d\n",
  723. (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
  724. seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
  725. seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
  726. seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
  727. seq_printf(m, "Render standby enabled: %s\n",
  728. (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
  729. return 0;
  730. }
  731. static int i915_fbc_status(struct seq_file *m, void *unused)
  732. {
  733. struct drm_info_node *node = (struct drm_info_node *) m->private;
  734. struct drm_device *dev = node->minor->dev;
  735. drm_i915_private_t *dev_priv = dev->dev_private;
  736. if (!I915_HAS_FBC(dev)) {
  737. seq_printf(m, "FBC unsupported on this chipset\n");
  738. return 0;
  739. }
  740. if (intel_fbc_enabled(dev)) {
  741. seq_printf(m, "FBC enabled\n");
  742. } else {
  743. seq_printf(m, "FBC disabled: ");
  744. switch (dev_priv->no_fbc_reason) {
  745. case FBC_NO_OUTPUT:
  746. seq_printf(m, "no outputs");
  747. break;
  748. case FBC_STOLEN_TOO_SMALL:
  749. seq_printf(m, "not enough stolen memory");
  750. break;
  751. case FBC_UNSUPPORTED_MODE:
  752. seq_printf(m, "mode not supported");
  753. break;
  754. case FBC_MODE_TOO_LARGE:
  755. seq_printf(m, "mode too large");
  756. break;
  757. case FBC_BAD_PLANE:
  758. seq_printf(m, "FBC unsupported on plane");
  759. break;
  760. case FBC_NOT_TILED:
  761. seq_printf(m, "scanout buffer not tiled");
  762. break;
  763. case FBC_MULTIPLE_PIPES:
  764. seq_printf(m, "multiple pipes are enabled");
  765. break;
  766. default:
  767. seq_printf(m, "unknown reason");
  768. }
  769. seq_printf(m, "\n");
  770. }
  771. return 0;
  772. }
  773. static int i915_sr_status(struct seq_file *m, void *unused)
  774. {
  775. struct drm_info_node *node = (struct drm_info_node *) m->private;
  776. struct drm_device *dev = node->minor->dev;
  777. drm_i915_private_t *dev_priv = dev->dev_private;
  778. bool sr_enabled = false;
  779. if (IS_GEN5(dev))
  780. sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
  781. else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
  782. sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
  783. else if (IS_I915GM(dev))
  784. sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
  785. else if (IS_PINEVIEW(dev))
  786. sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
  787. seq_printf(m, "self-refresh: %s\n",
  788. sr_enabled ? "enabled" : "disabled");
  789. return 0;
  790. }
  791. static int i915_emon_status(struct seq_file *m, void *unused)
  792. {
  793. struct drm_info_node *node = (struct drm_info_node *) m->private;
  794. struct drm_device *dev = node->minor->dev;
  795. drm_i915_private_t *dev_priv = dev->dev_private;
  796. unsigned long temp, chipset, gfx;
  797. int ret;
  798. ret = mutex_lock_interruptible(&dev->struct_mutex);
  799. if (ret)
  800. return ret;
  801. temp = i915_mch_val(dev_priv);
  802. chipset = i915_chipset_val(dev_priv);
  803. gfx = i915_gfx_val(dev_priv);
  804. mutex_unlock(&dev->struct_mutex);
  805. seq_printf(m, "GMCH temp: %ld\n", temp);
  806. seq_printf(m, "Chipset power: %ld\n", chipset);
  807. seq_printf(m, "GFX power: %ld\n", gfx);
  808. seq_printf(m, "Total power: %ld\n", chipset + gfx);
  809. return 0;
  810. }
  811. static int i915_gfxec(struct seq_file *m, void *unused)
  812. {
  813. struct drm_info_node *node = (struct drm_info_node *) m->private;
  814. struct drm_device *dev = node->minor->dev;
  815. drm_i915_private_t *dev_priv = dev->dev_private;
  816. seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4));
  817. return 0;
  818. }
  819. static int i915_opregion(struct seq_file *m, void *unused)
  820. {
  821. struct drm_info_node *node = (struct drm_info_node *) m->private;
  822. struct drm_device *dev = node->minor->dev;
  823. drm_i915_private_t *dev_priv = dev->dev_private;
  824. struct intel_opregion *opregion = &dev_priv->opregion;
  825. int ret;
  826. ret = mutex_lock_interruptible(&dev->struct_mutex);
  827. if (ret)
  828. return ret;
  829. if (opregion->header)
  830. seq_write(m, opregion->header, OPREGION_SIZE);
  831. mutex_unlock(&dev->struct_mutex);
  832. return 0;
  833. }
  834. static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
  835. {
  836. struct drm_info_node *node = (struct drm_info_node *) m->private;
  837. struct drm_device *dev = node->minor->dev;
  838. drm_i915_private_t *dev_priv = dev->dev_private;
  839. struct intel_fbdev *ifbdev;
  840. struct intel_framebuffer *fb;
  841. int ret;
  842. ret = mutex_lock_interruptible(&dev->mode_config.mutex);
  843. if (ret)
  844. return ret;
  845. ifbdev = dev_priv->fbdev;
  846. fb = to_intel_framebuffer(ifbdev->helper.fb);
  847. seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, obj ",
  848. fb->base.width,
  849. fb->base.height,
  850. fb->base.depth,
  851. fb->base.bits_per_pixel);
  852. describe_obj(m, to_intel_bo(fb->obj));
  853. seq_printf(m, "\n");
  854. list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
  855. if (&fb->base == ifbdev->helper.fb)
  856. continue;
  857. seq_printf(m, "user size: %d x %d, depth %d, %d bpp, obj ",
  858. fb->base.width,
  859. fb->base.height,
  860. fb->base.depth,
  861. fb->base.bits_per_pixel);
  862. describe_obj(m, to_intel_bo(fb->obj));
  863. seq_printf(m, "\n");
  864. }
  865. mutex_unlock(&dev->mode_config.mutex);
  866. return 0;
  867. }
  868. static int
  869. i915_wedged_open(struct inode *inode,
  870. struct file *filp)
  871. {
  872. filp->private_data = inode->i_private;
  873. return 0;
  874. }
  875. static ssize_t
  876. i915_wedged_read(struct file *filp,
  877. char __user *ubuf,
  878. size_t max,
  879. loff_t *ppos)
  880. {
  881. struct drm_device *dev = filp->private_data;
  882. drm_i915_private_t *dev_priv = dev->dev_private;
  883. char buf[80];
  884. int len;
  885. len = snprintf(buf, sizeof (buf),
  886. "wedged : %d\n",
  887. atomic_read(&dev_priv->mm.wedged));
  888. if (len > sizeof (buf))
  889. len = sizeof (buf);
  890. return simple_read_from_buffer(ubuf, max, ppos, buf, len);
  891. }
  892. static ssize_t
  893. i915_wedged_write(struct file *filp,
  894. const char __user *ubuf,
  895. size_t cnt,
  896. loff_t *ppos)
  897. {
  898. struct drm_device *dev = filp->private_data;
  899. char buf[20];
  900. int val = 1;
  901. if (cnt > 0) {
  902. if (cnt > sizeof (buf) - 1)
  903. return -EINVAL;
  904. if (copy_from_user(buf, ubuf, cnt))
  905. return -EFAULT;
  906. buf[cnt] = 0;
  907. val = simple_strtoul(buf, NULL, 0);
  908. }
  909. DRM_INFO("Manually setting wedged to %d\n", val);
  910. i915_handle_error(dev, val);
  911. return cnt;
  912. }
  913. static const struct file_operations i915_wedged_fops = {
  914. .owner = THIS_MODULE,
  915. .open = i915_wedged_open,
  916. .read = i915_wedged_read,
  917. .write = i915_wedged_write,
  918. .llseek = default_llseek,
  919. };
  920. /* As the drm_debugfs_init() routines are called before dev->dev_private is
  921. * allocated we need to hook into the minor for release. */
  922. static int
  923. drm_add_fake_info_node(struct drm_minor *minor,
  924. struct dentry *ent,
  925. const void *key)
  926. {
  927. struct drm_info_node *node;
  928. node = kmalloc(sizeof(struct drm_info_node), GFP_KERNEL);
  929. if (node == NULL) {
  930. debugfs_remove(ent);
  931. return -ENOMEM;
  932. }
  933. node->minor = minor;
  934. node->dent = ent;
  935. node->info_ent = (void *) key;
  936. list_add(&node->list, &minor->debugfs_nodes.list);
  937. return 0;
  938. }
  939. static int i915_wedged_create(struct dentry *root, struct drm_minor *minor)
  940. {
  941. struct drm_device *dev = minor->dev;
  942. struct dentry *ent;
  943. ent = debugfs_create_file("i915_wedged",
  944. S_IRUGO | S_IWUSR,
  945. root, dev,
  946. &i915_wedged_fops);
  947. if (IS_ERR(ent))
  948. return PTR_ERR(ent);
  949. return drm_add_fake_info_node(minor, ent, &i915_wedged_fops);
  950. }
  951. static struct drm_info_list i915_debugfs_list[] = {
  952. {"i915_capabilities", i915_capabilities, 0, 0},
  953. {"i915_gem_objects", i915_gem_object_info, 0},
  954. {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
  955. {"i915_gem_flushing", i915_gem_object_list_info, 0, (void *) FLUSHING_LIST},
  956. {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
  957. {"i915_gem_pinned", i915_gem_object_list_info, 0, (void *) PINNED_LIST},
  958. {"i915_gem_deferred_free", i915_gem_object_list_info, 0, (void *) DEFERRED_FREE_LIST},
  959. {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
  960. {"i915_gem_request", i915_gem_request_info, 0},
  961. {"i915_gem_seqno", i915_gem_seqno_info, 0},
  962. {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
  963. {"i915_gem_interrupt", i915_interrupt_info, 0},
  964. {"i915_gem_hws", i915_hws_info, 0, (void *)RING_RENDER},
  965. {"i915_gem_hws_blt", i915_hws_info, 0, (void *)RING_BLT},
  966. {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)RING_BSD},
  967. {"i915_ringbuffer_data", i915_ringbuffer_data, 0, (void *)RING_RENDER},
  968. {"i915_ringbuffer_info", i915_ringbuffer_info, 0, (void *)RING_RENDER},
  969. {"i915_bsd_ringbuffer_data", i915_ringbuffer_data, 0, (void *)RING_BSD},
  970. {"i915_bsd_ringbuffer_info", i915_ringbuffer_info, 0, (void *)RING_BSD},
  971. {"i915_blt_ringbuffer_data", i915_ringbuffer_data, 0, (void *)RING_BLT},
  972. {"i915_blt_ringbuffer_info", i915_ringbuffer_info, 0, (void *)RING_BLT},
  973. {"i915_batchbuffers", i915_batchbuffer_info, 0},
  974. {"i915_error_state", i915_error_state, 0},
  975. {"i915_rstdby_delays", i915_rstdby_delays, 0},
  976. {"i915_cur_delayinfo", i915_cur_delayinfo, 0},
  977. {"i915_delayfreq_table", i915_delayfreq_table, 0},
  978. {"i915_inttoext_table", i915_inttoext_table, 0},
  979. {"i915_drpc_info", i915_drpc_info, 0},
  980. {"i915_emon_status", i915_emon_status, 0},
  981. {"i915_gfxec", i915_gfxec, 0},
  982. {"i915_fbc_status", i915_fbc_status, 0},
  983. {"i915_sr_status", i915_sr_status, 0},
  984. {"i915_opregion", i915_opregion, 0},
  985. {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
  986. };
  987. #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
  988. int i915_debugfs_init(struct drm_minor *minor)
  989. {
  990. int ret;
  991. ret = i915_wedged_create(minor->debugfs_root, minor);
  992. if (ret)
  993. return ret;
  994. return drm_debugfs_create_files(i915_debugfs_list,
  995. I915_DEBUGFS_ENTRIES,
  996. minor->debugfs_root, minor);
  997. }
  998. void i915_debugfs_cleanup(struct drm_minor *minor)
  999. {
  1000. drm_debugfs_remove_files(i915_debugfs_list,
  1001. I915_DEBUGFS_ENTRIES, minor);
  1002. drm_debugfs_remove_files((struct drm_info_list *) &i915_wedged_fops,
  1003. 1, minor);
  1004. }
  1005. #endif /* CONFIG_DEBUG_FS */